An apparatus and method for performing multitask convolutional neural network prediction
By optimizing the hardware architecture and utilizing memory and accelerator units, the problems of slow processing speed and low memory bandwidth utilization in multi-task convolutional neural networks were solved, achieving efficient multi-task convolutional neural network prediction, reducing hardware costs and improving applicability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- TIANJIN IRISTAR TECH LTD
- Filing Date
- 2021-04-12
- Publication Date
- 2026-06-05
Smart Images
Figure CN113065643B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the fields of computers and image processing, and more specifically, to an apparatus and method for performing multi-task convolutional neural network predictions. Background Technology
[0002] In recent years, computer technology and artificial intelligence technology have developed rapidly. With Moore's Law nearing its end and no major breakthroughs in new chip physical materials, the computing performance of conventional processors is also approaching its limit. When AlexNet ignited this wave of deep learning in 2012, the network had only 8 layers, but even with only 8 layers, a large amount of computation was required. The 153-layer ResNet of 2016, and more recently, network structures with thousands of layers, require even more powerful computing resources to support network training. However, with the booming development of cloud computing, big data, mobile internet, artificial intelligence, and 5G, especially the high demands on image processing capabilities in computer vision applications, the computing power requirements for processors are increasing. Therefore, the contradiction between these two is inevitable and urgently needs to be resolved. At the same time, as image processing algorithms become increasingly complex, some algorithms (programs) simultaneously possess one or more of the following capabilities: general-purpose computing, parallel computing, and convolutional computing. However, there is currently no universal hardware architecture that can simultaneously accelerate the complex algorithms described above without increasing the scale of the hardware architecture. With the increasing complexity of algorithms in artificial intelligence, intelligent recognition, and supercomputing, the requirement to simultaneously accelerate general-purpose computing, parallel computing, and convolutional computing is becoming increasingly urgent.
[0003] Neural networks and deep learning currently offer the best solutions for many problems in image recognition. Image detection technology based on multi-task convolutional neural networks (MTCNN) can solve the drawbacks of traditional algorithms, such as high environmental requirements, high face accuracy requirements, and high detection time. However, it still requires hardware to provide high computing power and memory bandwidth. In existing technologies, hardware based on FPGA platforms and RIS-V processors can achieve miniaturized modules and a certain degree of acceleration. However, for the image convolution calculation process, there are still problems such as slow multi-task processing speed, low memory bandwidth utilization efficiency, poor external data compatibility, and slow convolution operation speed. Summary of the Invention
[0004] To address the aforementioned technical problems, this invention proposes an apparatus and method for performing multi-task convolutional neural network prediction. Through hardware architecture optimization, it accelerates multi-task convolutional neural network prediction by optimizing the processor's handling of complex computations such as convolution kernel calculation and pooling operations for each level of the multi-task convolutional neural network. Based on miniaturized, highly compatible, and highly integrated hardware, it alleviates the overall computing power requirements of the processor and effectively utilizes the maximum bandwidth of memory, thereby making the training process of multi-task convolutional neural networks smoother and faster.
[0005] To achieve the objectives of this invention, the technical solution adopted is as follows:
[0006] An apparatus and method for performing predictions in a multi-task convolutional neural network, characterized in that the apparatus comprises: a control interface, a memory unit, a bus multiplexer, and an accelerator unit; the control interface is used to receive instruction input and send it to the accelerator unit; the memory unit is used to store data information, convolutional layer parameters, and activation functions; the bus multiplexer is used to connect the various units and transmit data and instruction information; the accelerator unit includes a data buffer, a convolutional kernel buffer, a convolutional kernel controller, a convolutional scheduler, and several sets of multiply-accumulate arrays; the accelerator unit is used to allocate and process various tasks during the execution of the multi-task convolutional neural network, through... The bus multiplexer accesses the data and instruction information stored in the memory unit. The convolution scheduler retrieves and allocates convolution control instructions through the bus multiplexer. The data buffer performs data prefetching and storage according to the convolution control instructions. The convolution kernel buffer performs convolution kernel prefetching and storage according to the convolution control instructions. The convolution kernel controller accesses and reads the corresponding data information in the data buffer and the convolution kernel buffer respectively according to the convolution control instructions, and sends the data information to the multiply-accumulate array to complete the convolution kernel operation. After the operation is completed, the result is input into the corresponding address of the memory unit through quantization write-back via the bus multiplexer.
[0007] This invention, based on the complex computational characteristics of multi-task convolutional neural network (CNN) prediction processes, executes memory access instructions and convolution operation instructions independently. This optimizes the utilization of memory access bandwidth and effectively reduces the time consumed in the CNN prediction process. It simplifies the CNN prediction process and allows for the targeted configuration of the number of multiply-accumulate arrays based on the computational load of the convolution kernels, effectively improving the execution efficiency and applicability of existing neural network prediction methods.
[0008] This invention proposes an apparatus and method for performing multi-task convolutional neural network prediction. The apparatus and method described in this invention are of great significance for improving the efficiency of multi-task convolutional neural network prediction, and their beneficial effects are specifically reflected in the following aspects:
[0009] 1. The memory and operation instruction allocation of the present invention enables the buffer to prefetch data segment by segment and execute convolution operation simultaneously, thereby simplifying the time-consuming processing process in the traditional method that requires reading all image data first and then completing the convolution calculation.
[0010] 2. This invention pre-processes the data in memory units by address segmentation, facilitating orderly and continuous access, reading, and caching of data by the cache. This enables efficient utilization of memory bandwidth, thereby reducing concentrated memory bandwidth occupation and idle memory bandwidth. Simultaneously, this method can write convolution results in real time, maximizing memory bandwidth utilization and reducing training time.
[0011] 3. The multiply-accumulate array of the present invention can be configured in a more reasonable manner according to the specific computing scale. While ensuring computing power, it can save the internal space and hardware materials of the device to the greatest extent, reduce costs, and further improve the energy consumption optimization in detail.
[0012] 4. The apparatus and method of the present invention also have strong integration capabilities and can be widely applied to mobile devices, smart terminals, various artificial intelligence devices, etc.
[0013] Thanks to the above advantages, this invention can accelerate the prediction of multi-task convolutional neural networks, which not only reduces the time consumption but also greatly reduces the hardware cost of artificial intelligence devices. It can effectively improve the execution efficiency and applicability of existing neural network prediction and can be extended to various multi-task neural network prediction or image recognition systems based on multi-task neural networks. Attached Figure Description
[0014] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments of the present invention will be briefly described below. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.
[0015] Figure 1 A schematic diagram of the structure of an apparatus for performing multi-task convolutional neural network prediction provided in an embodiment of the present invention;
[0016] Figure 2 A schematic diagram of the hardware architecture of an apparatus for performing multi-task convolutional neural network prediction, provided in an embodiment of the present invention;
[0017] Figure 3 A flowchart of a method for performing multi-task convolutional neural network prediction is provided in an embodiment of the present invention;
[0018] Figure 4This is a schematic diagram of a segmented memory data storage mode provided in an embodiment of the present invention;
[0019] Figure 5 This is a schematic diagram of the hardware architecture of a combined acceleration unit provided in an embodiment of the present invention. Detailed Implementation
[0020] Embodiments of the invention are described below. However, it should be understood that the disclosed embodiments are merely examples, and other embodiments may take various alternative forms. The drawings are not necessarily drawn to scale; certain functions may be exaggerated or minimized to show details of specific components. Therefore, the specific structural and functional details disclosed herein should not be construed as limiting, but merely as a representative basis for teaching those skilled in the art to use the invention in various ways. As will be understood by those skilled in the art, various features shown and described with reference to any of the drawings may be combined with features shown in one or more other drawings to produce embodiments not explicitly shown or described. The combinations of features shown provide representative embodiments for typical applications. However, various combinations and modifications of features consistent with the teachings of the invention may be desired for certain particular applications or implementations.
[0021] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to specific examples and the accompanying drawings.
[0022] To achieve the above objectives, embodiments of the present invention provide an apparatus for performing multi-task convolutional neural network prediction. Figure 1 Figure 1 shows a schematic diagram of a device structure for performing multi-task convolutional neural network prediction, which is provided as a real-time example of the present invention. The device includes a control interface, a memory unit, a bus multiplexer, and an accelerator unit.
[0023] The control interface is used for inputting instructions and sending them to and storing them at the corresponding data address in the storage unit.
[0024] The memory unit is used to store data information, convolutional layer parameters, and activation functions.
[0025] Specifically, the memory unit is a Double Data Rate (DDR) synchronous dynamic random access memory, and the memory unit adopts a segmented storage mode, such as... Figure 4 As shown, the image data to be tested is an M*N feature matrix. It is segmented once every certain length of step, so that the image data to be tested has several segmented labels.
[0026] The bus multiplexer is used to connect the various units and transmit data and instruction information.
[0027] The accelerator unit is used to accelerate convolution operations during training and includes: a data buffer, a convolution kernel buffer, a convolution kernel controller, a convolution scheduler, and several sets of multiply-accumulate arrays.
[0028] Specifically, the convolution scheduler retrieves and distributes convolution control instructions through the bus multiplexer, including: data prefetch instructions, convolution kernel prefetch instructions, and convolution computation instructions. The data prefetch instructions drive the data buffer to access memory units through the bus multiplexer to prefetch and cache the data required for convolution computation; the convolution kernel prefetch instructions drive the convolution kernel buffer to access memory units through the bus multiplexer to prefetch and cache the convolution kernels; the convolution computation instructions include, but are not limited to: convolutional layer computation (convolutional layer), pooling computation (pooling layer), activation functions (activation layer), etc.
[0029] Specifically, the data buffer performs data prefetching and storage driven by convolution control instructions.
[0030] Specifically, the convolution kernel buffer is driven by convolution control instructions to prefetch and store convolution kernels.
[0031] Specifically, the multiply-accumulate array is driven by the convolution control instruction to complete the convolution kernel operation. After the operation is completed, the result is written back to the bus multiplexer and input to the corresponding address of the memory unit.
[0032] In some embodiments, the apparatus for performing multi-task convolutional neural network prediction is an FPGA. Figure 2 A hardware architecture diagram of an apparatus for performing multi-task convolutional neural network prediction is provided in an embodiment of the present invention, as shown below. Figure 2 As shown, the memory unit belongs to the FPGA chip. Developers set up control interfaces based on the resource characteristics of the FPGA chip, forming different hardware architectures within the FPGA chip. Based on the FPGA platform and RISC-V processor, a highly configurable hardware acceleration architecture is formed, relying on different levels of RISC-V processor cores to create a three-level acceleration structure: a general-purpose level (high-performance, large-area RISC-V), a parallel level (lower-performance, small-area single-core RISC-V), and a dedicated level (convolutional computation). Accelerator units can be flexibly configured according to different application scenarios, forming a hardware architecture capable of supporting multi-task convolutional neural network prediction, avoiding the drawbacks of previously requiring different hardware platforms for different application scenarios. This demonstrates the flexibility of FPGAs.
[0033] Figure 3The flowchart of a method for performing multi-task convolutional neural network prediction provided by an embodiment of the present invention is shown in the figure. The process includes: pre-storing data information, convolutional layer parameters, activation functions and thresholds for performing multi-task convolutional neural network prediction in the memory unit; inputting a series of instructions for performing multi-task convolutional neural network prediction to the convolution caller through the control interface; the convolution caller sending a data prefetch instruction to prefetch data and convolutional kernels, and storing them in a data buffer and a convolutional kernel buffer, respectively; the convolution controller calling the convolutional data in the two buffers through the convolution control instruction issued by the convolution scheduler, and performing data calculation through the multiply-accumulate array, and writing back to the storage through quantization.
[0034] Specifically, image data, convolution kernels, activation functions, and thresholds are pre-stored in memory units (DDR). When convolution control instructions are input through the control interface, the convolution scheduler obtains the convolution control instructions through the bus multiplexer and decomposes the convolution control instructions into data prefetch instructions and convolution calculation instructions.
[0035] The data prefetch instruction drives the data buffer and the convolution kernel buffer to perform image data prefetching and convolution kernel prefetching. The data buffer accesses the memory unit and reads the feature map to be convolved through the bus multiplexer, and the convolution kernel buffer accesses the memory unit and reads the convolution kernel information through the bus multiplexer.
[0036] Because the memory units employ a segmented storage mode, the prefetching process is interrupted whenever the cache reaches the end of a segment. This interruption signal activates the convolution controller to execute convolution calculation instructions. These instructions drive the multiply-accumulate array to begin convolution multiplication-accumulation operations, while the cache continues to prefetch the next segment. After the multiply-accumulate array completes its operation, the convolution result is written back to the memory unit via a bus multiplexer for use by the next network layer. In this embodiment, the calculation of the convolution result for each convolution kernel and the determination of the target convolution result are existing technologies and will not be elaborated upon further.
[0037] It should be noted that developers can adjust the length of each data segment in the memory cell according to the specific requirements of the training task to obtain the best training acceleration effect. For example, if the device cannot load a sufficient number of multiply-accumulate arrays, the computational load in the process can be reduced by decreasing the length of the memory cell data segments, while maximizing the utilization of the memory cell access bandwidth. If the device can load a sufficient number of multiply-accumulate arrays, the length of the memory cell data segments can be set according to the maximum access bandwidth of the memory cell. Based on the prefetching time required for this segment length, the multiply-accumulate array group that can complete the corresponding convolution operation within the same time is the optimized configuration. This can also save hardware materials and optimize device size within the given conditions.
[0038] Figure 5The figure shows a hardware architecture diagram of a combined acceleration unit provided in an embodiment of the present invention. Multiple accelerator units can be loaded simultaneously in parallel to enhance the acceleration effect of the device in the process of multi-task neural network prediction. At the same time, multiple data source inputs can be realized through external interfaces such as USB / PCIE.
[0039] Specifically, the prediction process of a multi-task neural network mainly consists of three parts: face binary classification, bounding box regression, and label localization.
[0040] In existing technologies, a common approach is to first obtain the regression vectors of candidate windows and bounding boxes for the face region using a fully convolutional neural network (Proposal Network, P-Net), and then use these bounding boxes for regression to calibrate the candidate windows. Next, Non-Maximum Suppression (NMS) is used to merge highly overlapping candidate boxes. To better suppress false-positive effects, an optimization network (RefineNet, R-Net) with one more layer than P-Net is used to remove false-positive regions. Finally, an output network (Output Network, O-Net) with one more layer than R-Net outputs refined results and region-supervised label localization. Connecting these three networks in series completes the training of the multi-task neural network.
[0041] Based on the characteristic of multi-task neural networks, where R-Net has one more layer than P-Net, and O-Net has one more layer than R-Net, this invention provides a hardware architecture for a combined acceleration unit that achieves a more significant acceleration effect: when executing P-Net, the first, second, and third acceleration units are used to complete the computation; when executing R-Net, the first, second, third, and fourth acceleration units are used; and when executing O-Net, the first, second, third, fourth, and fifth acceleration units are used. Compared to existing technologies, this invention can significantly improve memory bandwidth utilization, reduce computation time, thereby improving prediction efficiency, while also greatly optimizing device material costs.
[0042] The implementation of any embodiment of the apparatus and method for performing multi-task convolutional neural network prediction can achieve the same or similar effects as any of the aforementioned method embodiments.
[0043] Furthermore, the method according to embodiments of the present invention can also be implemented as a computer program executed by a CPU, which may be stored in a computer-readable storage medium. When the computer program is executed by the CPU, it performs the functions defined in the method of the embodiments of the present invention.
[0044] Furthermore, the above-described method steps and system units can also be implemented using a controller and a computer-readable storage medium for storing a computer program that enables the controller to perform the functions of the above-described steps or units.
[0045] Furthermore, it should be understood that the computer-readable storage medium (e.g., memory) described herein can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. By way of example, and not limitation, non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM), which can act as external cache memory. By way of example, and not limitation, RAM may be embodied in various forms, such as synchronous RAM (DRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct Rambus RAM (DRRAM). The storage devices disclosed herein are intended to include, but are not limited to, these and other suitable types of memory.
[0046] It should also be noted that those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The memory unit can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.
[0047] Furthermore, typically, the devices and equipment disclosed in the embodiments of this invention can be various electronic terminal devices, such as mobile phones, personal digital assistants (PDAs), tablet computers (PADs), smart wearable devices, etc., or they can be large terminal devices, such as servers. Therefore, the scope of protection of the embodiments of this invention should not be limited to a certain specific type of device or equipment. The client described in the embodiments of this invention can be applied to any of the above-mentioned electronic terminal devices in the form of electronic hardware, computer software, or a combination of both.
[0048] Those skilled in the art will also understand that the various exemplary logic blocks, modules, circuits, and algorithm steps described in conjunction with the disclosure herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, the functionality of the various illustrative components, blocks, modules, circuits, and steps has been generally described. Whether this functionality is implemented as software or as hardware depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art can implement the described functionality in various ways for each specific application, but such implementation decisions should not be construed as departing from the scope of the embodiments disclosed herein.
[0049] The steps of the methods or algorithms described herein can be directly incorporated into hardware, into a software module executed by a processor, or a combination of both. The software module can reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from or write information to the storage medium. In an alternative, the storage medium can be integrated with the processor. The processor and storage medium can reside in an ASIC. The ASIC can reside in a user terminal. In an alternative, the processor and storage medium can reside as discrete components in the user terminal. In one or more exemplary designs, the functionality can be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functionality can be stored as one or more instructions or code on or transmitted via a computer-readable medium. Computer-readable media includes computer storage media and communication media, which includes any medium that facilitates the transfer of a computer program from one location to another. The storage medium can be any available medium that can be accessed by a general-purpose or special-purpose computer. By way of example and not limitation, the computer-readable medium may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage devices, magnetic disk storage devices or other magnetic storage devices, or any other medium that can be used to carry or store the required program code in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor.
[0050] Furthermore, any connection can be appropriately referred to as a computer-readable medium. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the aforementioned coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are all included in the definition of medium. As used herein, disks and optical discs include compact discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, wherein disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers.
[0051] The combination of the above should also be included within the scope of computer-readable media.
[0052] It should be understood that, as used herein, the singular form “a” is intended to include the plural form as well, unless the context clearly supports an exception. It should also be understood that, as used herein, “and / or” refers to any and all possible combinations of one or more of the associated listed items.
[0053] The embodiment numbers disclosed in the above embodiments of the present invention are merely for description and do not represent the superiority or inferiority of the embodiments.
[0054] The above embodiments are possible examples of implementation methods and are provided merely for the purpose of clearly understanding the principles of the present invention. Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of the disclosed embodiments of the present invention is limited to these examples; within the framework of the present invention, technical features of the above embodiments or different embodiments can also be combined, and many other variations of different aspects of the present invention as described above exist, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. An apparatus for performing multi-task convolutional neural network prediction, characterized in that, The device includes: The system comprises a control interface, a memory unit, a bus multiplexer, and an accelerator unit. The control interface receives instruction input and sends it to the accelerator unit. The memory unit stores data, convolutional layer parameters, and activation functions. The bus multiplexer connects the control interface, memory unit, and accelerator unit, transmitting data and instruction information. The accelerator unit includes a data buffer, a convolutional kernel buffer, a convolutional kernel controller, a convolutional scheduler, and several sets of multiply-accumulate arrays. The accelerator unit allocates and processes various tasks during the execution of the multi-task convolutional neural network and accesses the memory unit through the bus multiplexer. The convolution scheduler retrieves and allocates convolution control instructions through the bus multiplexer. The data buffer performs data prefetching and storage according to the convolution control instructions. The convolution kernel buffer performs convolution kernel prefetching and storage according to the convolution control instructions. The convolution kernel controller accesses and reads the corresponding data information in the data buffer and the convolution kernel buffer respectively according to the convolution control instructions, and sends the data information to the multiply-accumulate array to complete the convolution kernel operation. After the operation is completed, the result is input into the corresponding address of the memory unit through quantization write-back and the bus multiplexer.
2. The apparatus for performing multi-task convolutional neural network prediction according to claim 1, characterized in that, The memory unit is one or more onboard memory chips; the accelerator unit consists of one or more sets of caches and controllers, as well as several sets of multiply-accelerate arrays; the multiply-accelerate array is composed of multiple sets of multipliers and adders in a specific combination.
3. The apparatus for performing multi-task convolutional neural network prediction according to claim 1, characterized in that, The data in the memory unit is pre-segmented into addresses and used to store data and instruction information for performing multi-task convolutional neural network predictions.
4. An apparatus for performing multi-task convolutional neural network prediction according to any one of claims 1-3, characterized in that, The device is used to obtain source code statements, data to be processed, and instruction information from other processing devices, execute specified machine learning operations, and transmit the execution results to other processing devices through a bus interface; When the apparatus for performing multi-task convolutional neural network prediction includes multiple accelerator units, the multiple accelerator units can be connected and transmit data through a specific structure; wherein, the multiple apparatuses for performing multi-task convolutional neural network prediction are interconnected and transmit data through a PCIe bus to support larger-scale machine learning operations. Multiple devices used to perform multi-task convolutional neural network prediction share the same processing system or have their own processing systems; multiple devices used to perform multi-task convolutional neural network prediction share memory or have their own memory; the interconnection of the devices used to perform multi-task convolutional neural network prediction is an arbitrary interconnection topology.
5. A method for performing multi-task convolutional neural network prediction, applied to the apparatus for performing multi-task convolutional neural network prediction as described in claims 1-4, characterized in that, The data information, convolutional layer parameters, activation functions, and thresholds used for multi-task convolutional neural network prediction are pre-stored in the memory unit. A series of instructions for performing multi-task convolutional neural network prediction are input to the convolution scheduler through the control interface. The convolution scheduler accesses the data and convolutional kernel addresses in the memory unit through a bus multiplexer, performs data and convolutional kernel prefetching, and stores them in the data buffer and convolutional kernel buffer, respectively. The convolution controller calls the convolutional data in the two buffers through the convolutional control instructions issued by the convolution scheduler, performs data calculation through the multiply-accumulate array, and writes back to the storage through quantization.
6. The method for performing multi-task convolutional neural network prediction according to claim 5, characterized in that, The convolution scheduler retrieves and distributes convolution control instructions through the bus multiplexer, including: data prefetch instructions, convolution kernel prefetch instructions, and convolution computation instructions. The data prefetch instructions drive the data buffer to access memory units through the bus multiplexer to prefetch and cache the data required for convolution computation. The convolution kernel prefetch instructions drive the convolution kernel buffer to access memory units through the bus multiplexer to prefetch and cache the convolution kernel. The convolution computation instructions include convolutional layer computation, pooling computation, and activation functions.
7. The method for performing multi-task convolutional neural network prediction according to claim 5, characterized in that, During the quantization write-back process, the final calculation result is output through inter-row pooling and activation functions.
8. The method for performing multi-task convolutional neural network prediction according to claim 5, characterized in that, The device includes: preprocessing received data to obtain data in an executable format and storing it at a corresponding data address; accessing the corresponding storage address and calling the corresponding data according to the convolutional layer instruction corresponding to the device, performing convolution kernel calculation on the corresponding data, obtaining the calculation result and storing it at the corresponding address.
9. A computer-readable storage medium having computer program instructions stored thereon, characterized in that, When the computer program instructions are executed by the processor, they implement the method described in any one of claims 5-8.
10. An electronic device, characterized in that, Used to perform the method according to any one of claims 5-8.