Device and method for parallel generation of syndromes in MPEG-2 sync byte decoder

Abstract

This invention relates to a device and method for parallel generation of synchronous bytecode in an MPEG-2 synchronous bytecode decoder, applicable to the ITU-T J.83 recommended digital multiprogramming system B, characterized in that the device mainly consists of 15 registers R0 to R100. 14 83 two-input XOR gates and 14 two-input selectors M0 to M1 13 Composition. The accompaniment generation device provided by the present invention takes 188 bytes of received data as input in 16-bit parallel mode and outputs 1 byte of accompaniment in 8-bit parallel mode. It can effectively reduce resource requirements while increasing the processing speed by 16 times, and has the advantages of fast operation and low resource consumption.

Description

Technical Field

[0001] The present invention relates to the field of cable digital television, and in particular to a parallel generation technology of a MPEG-2 sync byte decoder syndrome in a digital multi-program system B recommended by ITU-T J.83. Background Art

[0002] The MPEG-2 transport packet is 188 bytes long and consists of a 1-byte "sync" field, a 3-byte "header" field, and a 184-byte "payload" field. For ease of description, we will refer to the 3-byte "header" field and the 184-byte "payload" field as 187 bytes of information.

[0003] ITU-T J.83 recommends four digital multi-program systems for cable distribution of television, audio and data services, one of which is Digital Multi-Program System B. This system removes the "synchronization" field based on the MPEG-2 transmission packet format, and adds a 1-byte "checksum" field after the "payload" field to form a codeword with a length of 188 bytes. The checksum can be calculated by a FIR parity-check linear block code on 187 bytes of information, which can be used for synchronization and error detection to provide enhanced packet division functions and error detection capabilities independent of the FEC layer. If the transmitter uses serial transmission of codewords, the most significant bit (MSB) of the byte is transmitted first, and the least significant bit (LSB) is transmitted last. The receiver uses a syndrome generation device to determine whether the received data is a valid codeword.

[0004] Digital Multi-Program System B gives the circuit model of the companion generator of the MPEG-2 sync byte decoder, such as Figure 1 As shown. Figure 1 In the figure, n=1504, k=1496, nk=8. The circuit model consists of two functional modules: infinite impulse response (IIR) filter and finite impulse response (FIR) filter, including 1512 registers and 8 two-input XOR gates. In the device, all registers are initialized to '0'. The device serially inputs 188 bytes of received data and serially outputs 1 byte of syndrome after n clock cycles.

[0005] The syndrome generating device provided by the digital multi-program system B uses 1512 registers and 8 two-input XOR gates, which consumes a lot of resources. It takes 1504 clock cycles to calculate a syndrome, and the running speed is slow. Summary of the invention

[0006] Aiming at the shortcomings of high resource consumption and slow operation speed of the companion generation scheme given by ITU-T J.83 digital multi-program system B, the present invention provides a parallel companion generation scheme and provides a corresponding circuit model to reduce resource requirements and improve processing speed.

[0007] like Figure 3 As shown in FIG. 1 , the syndrome parallel generation device in the MPEG-2 sync byte decoder mainly consists of 15 registers R0 to R1. 14 , 83 two-input XOR gates and 14 two-input selectors M0~M 13 Each time the syndrome is calculated, the two-input selectors M0-M6 always select and output bits a0-a6 of the first data vector respectively, and the registers R0-R6 always load bits a0-a6 of the first data vector respectively and keep them until the calculation is completed. 13 Output '0' in the first n / 16-1 clock cycles, and select and output v in the last clock cycle. k+1 ~v n-1 Registers R7 to R 14 Used to save the intermediate results of iterative operations. 83 two-input XOR gates are used to calculate v k+1 ~v n-1 , z′0~z′7 and q n ~q n+7 The device inputs 188 bytes of received data in 16-bit parallel mode and outputs 1 byte of syndrome in 8-bit parallel mode. The syndrome calculation is completed in 14 steps: (1) Initialize j = 0, registers R7~R 14 are w0~w7 respectively; (2) Input bits a0~a1 of the first data segment vector 15 , registers R7 to R 14 The contents in are regarded as z0~z7 respectively; (3) selectors M7~M 13 All output '0', 83 two-input XOR gates calculate v k+1 ~v n-1 and z′0~z′7; (4) Selectors M0~M6 select a0~a6 respectively and send them to registers R0~R6, which store a0~a6 respectively, and registers R7~R 14 Save z′0~z′7 respectively to update z0~z7; (5) j increases by 1; (6) input bit a of the next data segment vector 16j ~a 16j+15 , registers R7 to R 14 The contents in are regarded as z0~z7 respectively; (7) selectors M7~M 13 All output '0', 83 two-input XOR gates calculate v k+1 ~v n-1and z'0 to z'7; (8) Selectors M0 to M6 respectively select the output values of registers R0 to R6 and send them to registers R0 to R6. Registers R0 to R6 respectively store a0 to a6, and registers R7 to R 14 respectively store z'0 to z'7 to update z0 to z7; (9) If j < n / 16 - 2, jump to step (5); otherwise, continue to the next step; (10) Increment j by 1; (11) Input the bits a 16j ~a 16j+15 of the last data segment vector. The contents in registers R7 to R 14 are respectively regarded as z0 to z7; (12) Selectors M7 to M 13 respectively select and output v k+1 ~v n-1 . 83 two-input exclusive-OR gates calculate v k+1 ~v n-1 and z'0 to z'7; (13) Selectors M0 to M6 respectively select the output values of registers R0 to R6 and send them to registers R0 to R6. Registers R0 to R6 respectively store a0 to a6, and registers R7 to R 14 respectively store z'0 to z'7 to update z0 to z7; (14) z'0 to z'7 are q n ~q n+7 , and the calculation of the syndrome for this time is completed.

[0008] The syndrome generation device provided by the present invention inputs the received data in parallel and outputs the syndrome in parallel, which can effectively reduce the resource requirements while greatly improving the processing speed.

[0009] The advantages and spirit of the present invention can be further understood through the following detailed description of the invention and the accompanying drawings. Brief Description of the Drawings

[0010] Figure 1 is the circuit model for generating the syndrome of the MPEG-2 synchronization byte decoder;

[0011] Figure 2 is the polynomial model for generating the syndrome of the MPEG-2 synchronization byte decoder;

[0012] Figure 3 is the circuit model for generating the syndrome in parallel of the MPEG-2 synchronization byte decoder. Detailed Embodiment

[0013] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, but it is not intended to limit the present invention.

[0014] For ITU-T J.83 digital multi-program system B, the transmitter sends a codeword sequence c i(0 ≤ i < n), which corresponds to the first n coefficients of the following codeword polynomial c(x)

[0015]

[0016] Among them, c i takes the value of '0' or '1'. c(x) consists of four parts:

[0017] c(x) = m(x) + r(x) + s(x) + x k+1 m(x)b(x) (2)

[0018] Among them, m(x) is the information polynomial, whose coefficients correspond to 187 bytes of information, r(x) is the remainder of m(x) divided by the generating polynomial g(x) modulo 2, s(x) is the bias polynomial, b(x) = 1 + x + x 3 + x 7 , g(x) = 1 + x + x 5 + x 6 + x 8 . m(x), r(x) and s(x) can be expressed in the following forms respectively:

[0019]

[0020] Among them, m i , r i and s i take the value of '0' or '1', s k ~s n-1 are '0', '1', '1', '0', '0', '1', '1' and '1' respectively. When combined into one byte, it is the hexadecimal number 0x67. mod represents the remainder of polynomial division modulo 2. m(x) + r(x) is divisible by g(x), that is

[0021]

[0022] [m(x) + r(x)] mod g(x) = 0 (7) Among them, f i takes the value of '0' or '1'. s(x) is not divisible by g(x), that is

[0023]

[0024] Among them, h i and p i take the value of '0' or '1', h k ~h n-1 are '0', '1', '0', '0', '0', '1', '1' and '1' respectively. When combined into one byte, it is the hexadecimal number 0x47, p n ~pn+7 They are '1', '1', '1', '0', '0', '0', '1' and '1', which combined into one byte is the hexadecimal number 0xE3.

[0025] exist Figure 1 In the example, the received data sequence and the output sequence are marked as a i and d i , their values ​​are '0' or '1', where 0≤i <n,d k ~d n-1 It constitutes a 1-byte syndrome.

[0026] Figure 1 The corresponding polynomial model is Figure 2 As shown in the figure, the IIR filter completes the division operation on the generating polynomial g(x), and the FIR filter completes the division operation on the polynomial [1+x k+1 b(x)]. Figure 2 In the example, the received data polynomial a(x) is the sum of the codeword polynomial c(x) and the error polynomial e(x), that is,

[0027] a(x)=c(x)+e(x) (10)

[0028] in,

[0029]

[0030] e i The value of is '0' or '1', which is determined by the channel transmission characteristics. From equations (10), (1) and (11), we can see that the number of terms in a(x) is the same as the number of terms in c(x).

[0031]

[0032] Among them, a i The value is '0' or '1', and the coefficient is a0~a n-1 and Figure 1 a0~a n-1 Exactly the same Figure 1 The extra coefficient a n ~a n+k-1 It will not affect the calculation of the syndrome. The output of the IIR filter has infinite terms, which may lead to the subsequent output polynomial d(x) also having infinite terms.

[0033]

[0034] Among them, d i The value of is '0' or '1', and the coefficients d0~d n-1 and Figure 1 d0~dn-1 Exactly the same Figure 1 The extra coefficients are insignificant, only d k ~d n-1 is the target to be sought. After two-stage filtering, a(x) becomes

[0035]

[0036] Substituting equations (10), (2), (6) and (8) into the above equation,

[0037]

[0038] On the right side of the last equal sign in the above formula, the first term is used to calculate d k ~d n-1 No effect, the second term has no effect on the calculation of d k ~d n-1 From equations (4) and (5), we can see that the third term [r(x)+s(x)+x k+1 m(x)b(x)]x k+1 The lowest power of b(x) / g(x) is x 2k+1 , 2k+1>n-1, indicating that this term is important for calculating d k ~d n-1 No effect. If e(x) = 0, then the fourth term e(x)[1+x k+1 b(x)] / g(x)=0, indicating that this term is not useful for calculating d k ~d n-1 No effect; otherwise, this term is usually not equal to 0, indicating that this term has no effect on the calculation of d k ~d n-1 It can be seen that if e(x) = 0, that is, no error occurs during the transmission process, then d k ~d n-1 are equal to h k ~h n-1 , that is, the syndrome is equal to 0x47; otherwise, the syndrome is usually not equal to 0x47.

[0039] From the above analysis, it can be seen that if the syndrome is equal to the hexadecimal number 0x47, the received data is considered to be a valid codeword; otherwise, the received data is considered to be erroneous.

[0040] In equation (14), dividing by g(x) is to find the quotient polynomial. This operation is changed to dividing g(x) modulo 2 to find the remainder q(x),

[0041]

[0042] Substituting equations (10), (2), (7) and (9) into the above equation,

[0043]

[0044] On the right side of the last equal sign in the above equation, the first term is useful for calculating q n ~q n+7 It has an influence. From equations (4) and (5), we can see that the second term [r(x)+s(x)+x k+1 m(x)b(x)]x k+1 The lowest power of b(x) mod g(x) is x 2k+2 , 2k+2>n+7, indicating that this term is important for calculating q n ~q n+7 No effect. If e(x) = 0, then the third term e(x)[1+x k+1 b(x)]mod g(x)=0, indicating that this term is useful for calculating q n ~q n+7 No effect; otherwise, this term is usually not equal to 0, indicating that this term has no effect on the calculation of q n ~q n+7 It can be seen that if e(x) = 0, that is, no error occurs during the transmission process, then q n ~q n+7 are equal to p n ~p n+7 , that is, when combined, they are exactly equal to 0xE3; otherwise, when combined, they are usually not equal to 0xE3. When no error occurs during the transmission process, in order to make q n ~q n+7 are equal to h k ~h n-1 , which is exactly equal to 0x47 when combined. Formula (16) needs to be modified as

[0045]

[0046] in,

[0047]

[0048] w0~w7 are '1', '1', '1', '0', '1', '1', '1' and '1' respectively, and combined into one byte is the hexadecimal number 0xEF. Using the modulo 2 division of g(x) shown in formula (9) to find the remainder of w(x), we get

[0049]

[0050] Among them, u n ~u n+7 They are '1', '0', '1', '0', '0', '1', '0' and '0', which are combined into one byte to get the hexadecimal number 0xA4. Substituting equations (10), (2), (7), (9) and (20) into equation (18), we get

[0051]

[0052] The above formula shows that if e(x) = 0, that is, no error occurs during the transmission process, then q n ~q n+7 are equal to h k ~h n-1 , that is, when combined, they are exactly equal to 0x47; otherwise, when combined, they are usually not equal to 0x47. This conclusion is exactly the same as that obtained by equation (15). Therefore, q in equation (18) can be replaced by n ~q n+7 Considered as accompanying.

[0053] make

[0054]

[0055] Substituting the above formula into formula (18),

[0056]

[0057] From the above formula, we can know that the coefficient q of q(x) is n ~q n+7 Involving x in a(x), v(x) and w(x) n-1 And the coefficients of lower powers, from equations (12), (19) and (22), we can see that the coefficients of a0~a n-1 , w0~w7 and v k+1 ~v n-1 Therefore, when calculating formula (22), only the coefficient v is required. k+1 ~v n-1 For the sake of convenience, we will use v k+1 ~v n-1 The vector [v n-1 v k+6 v k+5 v k+4 v k+3 v k+2 v k+1 ] is called the product head vector, and the vector [a6 a5 a4 a3 a2 a1 a0] consisting of the coefficients a0 to a6 of a(x) is called the data head vector. k+1 ~v n-1 , the following vector and matrix multiplication can be used:

[0058] [v n-1 v k+6 v k+5 v k+4 v k+3 v k+2 vk+1 = [a6 a5 a4 a3 a2 a1 a0]B (24)

[0059] where B is the following matrix constructed from the coefficients of b(x)

[0060]

[0061] Use equation (23) to find q n ~q n+7 A parallel iterative operation can be adopted. Divide the received data sequence a i (0 ≤ i < n) into segments of equal length, each segment being 16 bits, which form the data segment vector [a 16j+15 a 16j+14 a 16j+13 a 16j+12 a 16j+11 a 16j+10 a 16j+ 9a 16j+8 a 16j+7 a 16j+6 a 16j+5 a 16j+4 a 16j+3 a 16j+2 a 16j+1 a 16j (0 ≤ j < n / 16 = 94). The current intermediate operation result forms the present state vector [z7 z6 z5 z4 z3 z2 z1 z0] (its initial value is the vector [w7 w6 w5 w4 w3 w2 w1 w0] = [1 11 1 0 1 1 1]). After one multiplication of the vector by the matrix, the next state vector [z′7 z′6 z′5 z′4 z′3 z′2 z′1 z′0] is obtained as follows:

[0062]

[0063] where G is the following matrix constructed from the coefficients of g(x)

[0064]

[0065] Update the present state vector with the next state vector and repeat the above process. After n / 16 iterations, the next state vector is equal to the syndrome vector [q n+7 q n+6 q n+5 q n+4 q n+3 q n+2 q n+1 q n .

[0066] Based on the above analysis, we can get a circuit model of a companion parallel generator in an MPEG-2 sync byte decoder, as shown in Figure 3 The device inputs 188 bytes of received data in 16-bit parallel mode and outputs 1 byte of syndrome in 8-bit parallel mode. The device mainly consists of 15 registers R0~R 14 , 83 two-input XOR gates and 14 two-input selectors M0~M 13 Each time the syndrome is calculated, the two-input selectors M0-M6 always select and output bits a0-a6 of the first data vector respectively, and the registers R0-R6 always load bits a0-a6 of the first data vector respectively and keep them until the calculation is completed. 13 Output '0' in the first n / 16-1 clock cycles, and select and output v in the last clock cycle. k+1 ~v n-1 Registers R7 to R 14 Used to save the intermediate results of iterative operations. Their initial values ​​are w0~w7, their current states are z0~z7, and their next states are z′0~z′7. That is, they store z0~z7 in the current clock cycle and z′0~z′7 in the next clock cycle. 83 two-input XOR gates are used to calculate v k+1 ~v n-1 , z′0~z′7 and q n ~q n+7 Specifically, a portion of the two-input XOR gates calculate v according to equations (24) and (25). k+1 ~v n-1 , the remaining two-input XOR gates calculate z′0~z′7 according to equations (26) and (27), and the final z′0~z′7 is q n ~q n+7 .

[0067] Aiming at the digital multi-program system B recommended by ITU-T J.83, the present invention provides a method for parallel generation of syndromes in an MPEG-2 sync byte decoder. The steps of calculating a syndrome once are as follows:

[0068] (1) Initialize j = 0, registers R7 to R 14 They are w0~w7 respectively;

[0069] (2) Input bits a0 to a1 of the first data segment vector 15 , registers R7 to R 14 The contents in are regarded as z0~z 7 ;

[0070] (3) Selector M7~M 13All output '0', and 83 two - input exclusive - OR gates calculate v k+1 ~v n-1 and z′0 to z′7;

[0071] (4) Selectors M0 to M6 respectively select a0 to a6 and send them to registers R0 to R6. Registers R0 to R6 respectively store a0 to a6, and registers R7 to R 14 respectively store z′0 to z′7 to update z0 to z7;

[0072] (5) Increment j by 1;

[0073] (6) Input the bits a 16j ~a 16j+15 of the next data - segment vector. The contents in registers R7 to R 14 are respectively regarded as z0 to z7;

[0074] (7) Selectors M7 to M 13 All output '0', and 83 two - input exclusive - OR gates calculate v k+1 ~v n-1 and z′0 to z′7;

[0075] (8) Selectors M0 to M6 respectively select the output values of registers R0 to R6 and send them to registers R0 to R6. Registers R0 to R6 respectively store a0 to a6, and registers R7 to R 14 respectively store z′0 to z′7 to update z0 to z7;

[0076] (9) If j < n / 16 - 2, jump to step (5); otherwise, continue to the next step;

[0077] (10) Increment j by 1;

[0078] (11) Input the bits a 16j ~a 16j+15 of the last data - segment vector. The contents in registers R7 to R 14 are respectively regarded as z0 to z7;

[0079] (12) Selectors M7 to M 13 respectively select and output v k+1 ~v n-1 . 83 two - input exclusive - OR gates calculate v k+1 ~v n-1 and z′0 to z′7;

[0080] (13) Selectors M0 to M6 respectively select the output values of registers R0 to R6 and send them to registers R0 to R6. Registers R0 to R6 respectively store a0 to a6, and registers R7 to R 14 respectively store z′0 to z′7 to update z0 to z7;

[0081] (14) z′0~z′7 is q n ~q n+7 , this calculation is completed.

[0082] It should be noted that in step (2), j = 0, a 16j ~a 16j+15 It is a0~a 15 .

[0083] If the syndrome is equal to the hexadecimal number 0x47, the received data is considered to be a valid codeword; otherwise, the received data is considered to be erroneous.

[0084] The present invention requires 15 registers, 83 two-input XOR gates and 14 two-input selectors, and generates a syndrome result after 94 clock cycles. Compared with the syndrome generation device provided by ITU-T J.83 Digital Multi-Program System B, the processing speed of the present invention is increased by 16 times. Although 76 more two-input XOR gates and 14 two-input selectors are used, the consumption of registers is less than 1% of the former. In general, very few resources are consumed. In summary, it can be seen that compared with the syndrome generation device provided by ITU-T J.83 Digital Multi-Program System B, the present invention has the advantages of fast operation speed and less resource consumption.

[0085] The present invention has been described in detail above through specific implementation modes and examples. For those skilled in the art, several modifications and improvements may be made without departing from the principle of the present invention, which should also be regarded as within the protection scope of the present invention.

Claims

1. A device for generating a syndrome in a MPEG-2 sync byte decoder, suitable for the digital multi-program system B recommended by ITU-T J.83, which inputs 188 bytes of received data in a 16-bit parallel manner and outputs 1 byte of syndrome in an 8-bit parallel manner, and each 2 bytes of received data constitute a data segment vector [a 16j+15 a 16j+14 a 16j+13 a 16j+12 a 16j+11 a 16j+ 10 a 16j+9 a 16j+8 a 16j+7 a 16j+6 a 16j+5 a 16j+4 a 16j+3 a 16j+2 a 16j+1 a 16j ],in, 0 ≤ j < n / 16, n = 1504, and the 1-byte syndromes form the syndrome vector [q n+7 q n+6 q n+5 q n+4 q n+3 q n+2 q n+1 q n . The bits a0 to a6 of the first data segment vector form the data head vector [a6a5a4a3a2a1a0], and the data head vector is used to calculate the product head vector [v n-1 v k+6 v k+5 v k+4 v k+3 v k+2 v k+1 , where k = 1496, n - k = 8. The syndrome vector is calculated iteratively, involving the current state vector [z7z6z5z4z3z2z1z0] and the next state vector [z′7z′6z′5z′4z′3z′2z′1z′0]. The initial value of the current state vector is the vector [w7w6w5w4w3w2w1w0] = [1 1 1 1 0 1 1 1], and the next state vector is used to update the current state vector. After n / 16 iterations, the next state vector is equal to the syndrome vector. It is characterized in that the device comprises the following components: 14 two-input selectors M0~M 13 The two-input selectors M0-M6 always select and output bits a0-a6 of the first data vector respectively, and the two-input selectors M7-M 13 Output '0' in the first n / 16-1 clock cycles, and select and output v in the last clock cycle. k+1 ~v n-1 ; 15 registers R0~R 14 , registers R0 to R6 are always loaded with bits a0 to a6 of the first vector of data, and registers R7 to R 14 Used to save the intermediate results of iterative operations, their initial values ​​are w0~w7; 83 two-input XOR gates, which are used to calculate v k+1 ~v n-1 , z′0~z′7 and q n ~q n+7 ; Selector M i The two input terminals are connected to the receiving data a 16j+i and register R i The output terminal of register R i The input terminal and selector M i The output ends are connected, where 0≤i≤6; Two input terminals of the selector M7 are respectively connected to the constant '0' and the output terminal of the register R0; Selector M i The two input terminals of are connected to the constant '0' and the output terminal of the i+8th two-input XOR gate respectively, where 8≤i≤13; The input of the i-th two-input XOR gate is connected to the received data a 16j+i-1 and register R i+6 The output ends are connected, where 1≤i≤8; The input of the i-th two-input XOR gate is connected to the received data a 16j+i and selector M i-2 The output ends are connected, where 9≤i≤15; The input of the i-th two-input XOR gate is connected to the register R i-15 and R i-16 The output terminals are connected, wherein i=16 or 17; The i-th and i+4-th two-input XOR gates together realize the register R i-15 , R i-16 , R i-18 Modulo 2 addition of the output, where 18≤i≤21; The 26th to 31st two-input XOR gates together realize the reception of data a 16j+8 Add the outputs of the 4th, 6th, 12th to 15th two-input XOR gates modulo 2 and send the result to register R7; The 32nd to 38th two-input XOR gates together realize the reception of data a 16j+8 Add the outputs of the 1st, 4th to 7th, 9th and 12th two-input XOR gates modulo 2 and send the result to register R8; The 39th to 46th two-input exclusive-OR gates jointly implement modulo-2 addition of the outputs of the 1st, 2nd, 5th to 10th, and 13th two-input exclusive-OR gates, and send the result to the register R9; The 47th to 54th two-input XOR gates together realize the reception of data a 16j+8 Add the output modulo 2 of the 2nd, 3rd, 6th to 8th, 10th, 11th, and 14th two-input XOR gates, and send the result to register R 10 middle; The 55th to 62nd two-input XOR gates together realize the reception of data a 16j+8 Add the outputs of the 3rd, 4th, 7th to 9th, 11th, 12th, and 15th two-input XOR gates modulo 2, and send the result to register R 11 middle; The 63rd to 69th two-input XOR gates jointly implement the modulo-2 addition of the outputs of the 1st, 5th, 6th, 8th to 10th, 14th, and 15th two-input XOR gates, and send the results to register R 12 middle; The 70th to 76th two-input XOR gates together implement the modulo-2 addition of the outputs of the 2nd, 4th, 7th, 10th to 14th two-input XOR gates and send the results to register R 13 middle; The 77th to 83rd two-input XOR gates together implement the modulo-2 addition of the outputs of the 3rd, 5th, 8th, 11th to 15th two-input XOR gates, and send the results to register R 14 middle.

2. A method for generating a syndrome in parallel in an MPEG-2 sync byte decoder, applicable to the digital multi-program system B recommended by ITU-T J.83, wherein the apparatus for generating a syndrome in parallel in an MPEG-2 sync byte decoder as claimed in claim 1 inputs 188 bytes of received data in a 16-bit parallel manner, outputs 1 byte of syndrome in an 8-bit parallel manner, and each 2 bytes of received data constitute a data segment vector [a 16j+15 a 16j+14 a 16j+13 a 16j+12 a 16j+11 a 16j+10 a 16j+9 a 16j+8 a 16j+7 a 16j+6 a 16j+ 5a 16j+4 a 16j+3 a 16j+2 a 16j+1 a 16j ],in, 0 ≤ j < n / 16, n = 1504, 1-byte syndromes form a syndrome vector [q n+ 7q n+6 q n+5 q n+4 q n+3 q n+2 q n+1 q n , bits a0 to a6 of the first data segment vector form a data head vector [a6a5a4a3a2a1a0], and the data head vector is used to calculate a product head vector [v n-1 v k+6 v k+5 v k+4 v k+3 v k+2 v k+1 , where k = 1496, n - k = 8, the syndrome vector is calculated iteratively, involving a current state vector [z7z6z5z4z3z2z1z0] and a next state vector [z′7z′6z′5z′4z′3z′2z′1z′0]. The initial value of the current state vector is the vector [w7w6w5w4w3w2w1w0] = [1 1 1 1 0 11 1], and the next state vector is used to update the current state vector. After n / 16 iterations, the next state vector is equal to the syndrome vector. It is characterized in that the steps of calculating a syndrome once by the generating method are as follows: (1) Initialize j = 0, registers R7 to R 14 They are w0~w7 respectively; (2) Input bits a0 to a1 of the first data segment vector 15 , registers R7 to R 14 The contents in are regarded as z0~z7 respectively; (3) Selector M7~M 13 All output '0', 83 two-input XOR gates calculate v k+1 ~v n-1 and z′0~z′7; (4) Selectors M0 to M6 select a0 to a6 and send them to registers R0 to R6. Registers R0 to R6 store a0 to a6 respectively. Registers R7 to R8 store a0 to a6 respectively. 14 Save z′0~z′7 respectively to update z0~z7; (5) Increment j by 1; (6) Input bit a of the next data segment vector 16j ~a 16j+15 , registers R7 to R 14 The contents in are regarded as z0~z7 respectively; (7) Selector M7~M 13 All output '0', 83 two-input XOR gates calculate v k+1 ~v n-1 and z′0~z′7; (8) Selectors M0 to M6 select the output values ​​of registers R0 to R6 and send them to registers R0 to R6. Registers R0 to R6 store a0 to a6 respectively. Registers R7 to R8 store a1 to a2 respectively. 14 Save z′0~z′7 respectively to update z0~z7; (9) If j < n / 16 - 2, jump to step (5); otherwise, continue to the next step; (10) Increment j by 1; (11) Input bit a of the last data segment vector 16j ~a 16j+15 , registers R7 to R 14 The contents in are regarded as z0~z7 respectively; (12) Selector M7~M 13 Select and output v respectively k+1 ~v n-1 , 83 two-input XOR gates calculate v k+1 ~v n-1 and z′0~z′7; (13) Selectors M0 to M6 select the output values ​​of registers R0 to R6 and send them to registers R0 to R6. Registers R0 to R6 store a0 to a6 respectively. Registers R7 to R8 store a1 to a2 respectively. 14 Save z′0~z′7 respectively to update z0~z7; (14) z′0~z′7 is q n ~q n+7 , this calculation is completed.

3. A method for parallel generation of syndromes in an MPEG-2 sync byte decoder as claimed in claim 2, characterized in that: Calculate v k+1 ~v n-1 The multiplication of vectors and matrices follows: [v n-1 v k+6 v k+5 v k+4 v k+3 v k+2 v k+1 ]=[a6a5a4a3a2a1a0]B Wherein, 4. A method for parallel generation of syndromes in an MPEG-2 sync byte decoder as claimed in claim 2, characterized in that: Calculating z′0 to z′7 follows the multiplication of the following vector and matrix: Wherein,

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