Voltage tracking circuit

Abstract

This disclosure relates to a voltage tracking circuit. Various embodiments described herein relate to a device having an output pad configured to provide an output pad voltage. The device may include a tracking circuit configured to receive a first voltage, receive a second voltage different from the first voltage, receive the output pad voltage as a feedback voltage, and provide a first tracking voltage and a second tracking voltage based on the first voltage, the second voltage, and the feedback voltage. The device may include an output circuit configured to receive the first tracking voltage and the second tracking voltage from the tracking circuit, and provide the output pad voltage to the output pad based on the first tracking voltage and the second tracking voltage.

Description

Technical Field

[0001] This disclosure relates to a voltage tracking circuit. Background Technology

[0002] This section aims to provide information relevant to understanding the various techniques described herein. As the title of this section suggests, this is a discussion of related techniques and should in no way imply that they are prior art. Generally, related techniques may or may not be considered prior art. Therefore, it should be understood that any statements in this section should be interpreted in this context and should not be construed as any admission of prior art.

[0003] In some computing architectures, fail-safe operation refers to electronic circuitry designed to prevent controlled components from operating unsafely in the event of a failure of one or more internal circuit components. Therefore, fail-safe circuitry is designed to mitigate failures when they occur. Regarding control logic, safe circuit operation can involve safely performing tasks, and in electrical engineering, fail-safe devices are typically designed to implement functions or practices that respond to and mitigate specific types of failures, minimizing or even eliminating damage to internal circuit components. Summary of the Invention

[0004] According to one aspect of this disclosure, an apparatus is provided, comprising: an output pad configured to provide an output pad voltage; a tracking circuit configured to receive a first voltage, receive a second voltage different from the first voltage, receive the output pad voltage as a feedback voltage, and provide a first tracking voltage and a second tracking voltage based on the first voltage, the second voltage, and the feedback voltage; and an output circuit configured to receive the first tracking voltage and the second tracking voltage from the tracking circuit, and provide the output pad voltage to the output pad based on the first tracking voltage and the second tracking voltage.

[0005] According to another aspect of this disclosure, a voltage tracking circuit is provided, comprising: an output stage having an output transistor, the output stage being configured to receive a first tracking signal, receive a second tracking signal, and provide the output pad signal to an output pad based on the first tracking signal and the second tracking signal; a feedback stage being configured to receive the output pad signal from the output stage and provide the pad feedback signal based on the output pad signal; and a tracking stage being configured to receive a first signal, receive a second signal different from the first signal, receive the output pad signal from the output pad, receive the pad feedback signal from the feedback stage, and provide the first tracking signal and the second tracking signal to the output stage based on the first signal, the second signal, the output pad signal, and the pad feedback signal.

[0006] According to another aspect of this disclosure, a method is provided, comprising: manufacturing an output pad configured to provide an output pad voltage; manufacturing a tracking circuit configured to receive a first voltage, receive a second voltage different from the first voltage, receive the output pad voltage as a feedback voltage, and provide a first tracking voltage and a second tracking voltage based on the first voltage, the second voltage, and the feedback voltage; and manufacturing an output circuit configured to receive the first tracking voltage and the second tracking voltage from the tracking circuit, and provide the output pad voltage to the output pad based on the first tracking voltage and the second tracking voltage. Attached Figure Description

[0007] This document describes various embodiments of the techniques with reference to the accompanying drawings. However, it should be understood that the drawings only illustrate the various embodiments described herein and are not intended to limit the implementation of the various techniques described herein.

[0008] Figure 1 A diagram of a chip-level circuit according to various embodiments described herein is shown.

[0009] Figure 2 A diagram of an overdriven input / output circuit according to various embodiments described herein is shown.

[0010] Figures 3A to 3B A diagram of a voltage tracking circuit according to various embodiments described herein is shown.

[0011] Figure 4 A diagram of the first-stage circuit according to various embodiments described herein is shown.

[0012] Figure 5 A diagram of the second-stage circuit according to various embodiments described herein is shown.

[0013] Figures 6A to 6B Various diagrams of third-stage circuits according to the various embodiments described herein are shown.

[0014] Figure 7 A flowchart is shown of a method for providing a voltage tracking circuit according to various embodiments described herein. Detailed Implementation

[0015] The various embodiments described herein refer to voltage tracking schemes and techniques. For example, the various schemes and techniques described herein can provide overdrive fail-safe input / output (IO) PAD voltage tracking circuitry. In some scenarios, various circuits can operate with a supply voltage (DVDD) of approximately 3.3V under normal operating conditions, while in other cases, various circuits can operate with a supply voltage (DVDD) and an intermediate supply voltage (DVDDLO) of 0V under fail-safe operating conditions. In this case, when the supply (DVDD, DVDDLO) = 0 and the PAD is externally driven by various supply voltage levels (e.g., 3.3V or 1.8V), the IO circuitry should be in a Hi-Z state. Therefore, the various embodiments described herein provide gate / well voltage tracking under both normal and fail-safe operating conditions. Moreover, the various embodiments described herein provide a single tracking circuitry that uses various low-voltage devices (e.g., 1.8V devices) for overdrive circuitry that operates with power sequence-independent fail-safe support in different voltage level domains (e.g., 3.3V / 2.5V / 1.8V). The advantages of using the voltage tracking scheme and technology described herein can provide overdrive (3.3V / 2.5V / 1.8V) fault safety support when using 1.8V devices, multi-voltage domain fault safety support, power sequence independence, and high-speed fault safety support.

[0016] This article will refer to Figures 1 to 7 This document provides a detailed description of various implementation methods for voltage tracking schemes and technologies.

[0017] Figure 1 A top view of a chip-level circuit 100 according to various embodiments described herein is shown.

[0018] In various embodiments, the chip-level circuit 100 can be implemented as a system or device having various integrated circuit (IC) components arranged and coupled together as a collection or combination of parts providing physical circuit design and related structures. In some cases, a method of designing, providing, and constructing the chip-level circuit 100 as an integrated system or device may include using the various IC circuit components described herein to implement associated voltage tracking schemes and techniques. The chip-level circuit 100 can be integrated with computing circuitry and related components on a single chip, and the chip-level circuit 100 can be implemented in various embedded systems for electronic applications, mobile applications, and Internet of Things (IoT) applications, including sensor nodes.

[0019] like Figure 1 As shown, chip-level circuitry 100 may refer to a System-on-a-Chip (SoC), which may include a digital core 104, an analog core 106, and overdriven input / output (I / O) circuitry 120. In some embodiments, SoC refers to an integrated circuit (IC) that integrates various logic components on a single chip or substrate. Because some SoCs operate with lower power consumption and smaller area compared to other multi-chip designs with equivalent functionality, SoCs are advantageously implemented in mobile computing devices, edge computing devices, embedded devices, and / or Internet of Things (IoT) devices. Furthermore, in some embodiments, I / O circuitry 120 may be used for communication between various internal components (e.g., 104, 106) and external components. I / O circuitry 120 may include one or more I / O ports that receive input signals and / or provide output signals, thus enabling I / O circuitry 120 to perform various I / O operations. As further described herein, I / O circuitry 120 is configured with fail-safe circuitry for implementing fail-safe mode operating characteristics and behavior.

[0020] Figure 2 A diagram of an overdriven input / output (IO) circuit 120 according to various embodiments described herein is shown.

[0021] In various implementations, the overdrive I / O circuit 120 can be implemented as a system or device having various integrated circuit (IC) components arranged and coupled together as an assembly or combination of parts providing physical circuit design and related structures. In some cases, a method of designing, providing, and constructing the overdrive I / O circuit 120 as an integrated system or device may include using the various IC circuit components described herein to implement associated voltage tracking schemes and techniques. The overdrive I / O circuit 120 can be integrated with computing circuitry and related components on a single chip, and the overdrive I / O circuit 120 can be implemented in embedded systems for electronic applications, mobile applications, and Internet of Things (IoT) applications, including sensor nodes.

[0022] like Figure 2 As shown, the overdrive I / O circuit 120 may include a logic control circuit 208 having one or more I / O ports 204, wherein the one or more I / O ports 204 are configured to receive one or more I / O signals from internal sources and / or external sources. In some cases, internal sources may refer to, for example, Figure 1 The chip-level circuitry 102 shown is associated with on-chip devices, such as digital core 104 and / or analog core 106, and external sources can be pointed to. Figure 1 The chip-level circuitry 102 is an external device located outside the chip. In various cases, the logic control circuitry 208 can be coupled to a first voltage domain, for example, a core voltage domain configured to provide a core supply voltage (VDD) and a core ground supply voltage (VSS). Furthermore, in various cases, one or more components of the overdrive I / O circuitry 120 can be coupled to a second voltage domain, for example, an I / O voltage domain configured to provide an I / O supply voltage (DVDD) and an I / O ground supply voltage (DVSS).

[0023] The overdrive I / O circuit 120 may include input circuitry (210, 212, 214) configured to receive an I / O voltage (Vio), provide a first voltage (PG) based on the I / O voltage (Vio), and provide a second voltage (NG) based on an I / O voltage (Vio) different from the first voltage (PG). In some cases, the I / O voltage (Vio) may refer to an overdrive input / output (I / O) voltage, and the input circuitry (210, 212, 214) may include a level shifting circuitry 210 that receives the overdrive I / O voltage (Vio), provides the first voltage (PG) based on the overdrive I / O voltage (Vio), and provides the second voltage (NG) based on the overdrive I / O voltage (Vio). The logic control 208 can be configured to provide an IO voltage (Vio) in the voltage range of 0V to 0.75V, and the level shifting circuit 210 can include a level shifter configured to receive the IO voltage (Vio) and provide a first voltage (PG), a second voltage (NG), a first reference voltage (REFP), and a second reference voltage (REFN).

[0024] In the first operating mode, the first voltage (PG) can operate within a voltage range of 1.5V and 3.3V, the second voltage (NG) can operate within a voltage range of 0V and 1.8V, the first reference voltage (REFP) can be 1.5V, and the second reference voltage (REFN) can be 1.8V. In the second operating mode, the first voltage (PG) can operate within a voltage range of 0.7V and 2.5V, the second voltage (NG) can be maintained within a voltage range of 0V and 1.8V, the first reference voltage (REFP) can be 0.7V, and the second reference voltage (REFN) can be maintained at 1.8V. Furthermore, in the third operating mode, the first voltage (PG) can operate within a voltage range of 0V and 1.8V, the second voltage (NG) can be maintained within a voltage range of 0V and 1.8V, the first reference voltage (REFP) can be 0V, and the second reference voltage (REFN) can be maintained at 1.8V.

[0025] The input circuitry (210, 212, 214) may include a first device 212, such as a pre-driver PFET, configured to receive a first voltage (PG), receive a first reference voltage (REFP), and provide the first voltage (PG) to the voltage tracking circuitry 218 based on PG and REFP. Furthermore, the input circuitry (210, 212, 214) may include a second device 212, such as a pre-driver NFET, configured to receive a second voltage (NG), receive a second reference voltage (REFN), and provide the second voltage (NG) to the voltage tracking circuitry 218 based on NG and REFN. Additionally, in some cases, the reference voltage from the PREFGEN cell may be provided to both the first reference voltage (REFP) line and the second reference voltage (REFN) line.

[0026] In some implementations, the first voltage (PG) may refer to a first operating voltage within a first range, and the second voltage (NG) may refer to a second operating voltage within a second range different from the first range. In some cases, the first range may refer to the voltage range between a first intermediate voltage (e.g., 1.5V) and an upper boundary voltage (e.g., 3.3V), and the second range may refer to the voltage range between a lower boundary voltage (e.g., 0V) and a second intermediate voltage (1.8V). In some cases, the level shifting circuit 210 may be configured to provide a first reference voltage (refp) and a second reference voltage (refn) different from the first reference voltage (refp). In some cases, the first reference voltage (refp) may refer to a voltage level similar to the first intermediate voltage (e.g., 1.5V), and the second reference voltage (refn) may refer to another voltage level similar to the second intermediate voltage (e.g., 1.8V).

[0027] The overdrive I / O circuit 120 may include a voltage tracking circuit 218 configured to receive a first voltage (PG), receive a second voltage (NG), provide a first tracking signal (PG_track) based on the first voltage (PG), and provide a second tracking signal (NG) based on the second voltage (NG). The tracking circuit 218 may also receive a first reference voltage (refp) and provide a first reference tracking signal (refp_track) based on the first reference voltage (refp), and the tracking circuit 218 may also receive a second reference voltage (refn) and provide a second reference tracking signal (refn_track) based on the second reference voltage (refn).

[0028] In some cases, the voltage tracking circuit 218 may be referred to as a pad tracking logic for the well and gate net. Furthermore, in some cases, the first voltage (PG) may refer to a first operating voltage operating within a first intermediate voltage (e.g., 1.5V) and an upper boundary voltage (e.g., 3.3V). The second voltage (NG) may refer to a second operating voltage different from the first operating voltage, wherein the second operating voltage operates within a lower boundary voltage (e.g., 0V) and a second intermediate voltage (e.g., 1.8V). Additionally, the first voltage (PG) may be referred to as a first gate voltage, the first tracking voltage may be referred to as a first gate tracking voltage, and in this case, the second voltage (NG) may be referred to as a second gate voltage, and the second tracking voltage may be referred to as a second gate tracking voltage. In various cases, the upper boundary voltage may vary under different operating conditions; for example, in different operating modes, the upper boundary voltage may refer to a first voltage level (e.g., 3.3V), a second voltage level (e.g., 2.5V), or a third voltage level (e.g., 1.8V). In this case, the first reference voltage (refp) can also vary under different operating conditions; for example, at a first voltage level (e.g., 3.3V), the first reference voltage (refp) can refer to 1.5V; at a second voltage level (e.g., 2.5V), the first reference voltage (refp) can refer to 0.7V; and at a third voltage level (e.g., 1.8V), the first reference voltage (refp) can refer to 0V. Furthermore, the second reference voltage (refn) can be maintained at a second intermediate voltage (e.g., 1.8V).

[0029] The overdrive I / O circuit 120 may include a receiver (Rx) circuit 216, which may be coupled to the voltage tracking circuit 218 and Figure 1Between one or more components of the chip-level circuit 102. In some embodiments, the Rx circuit 216 can operate as a secondary protection circuit, and the Rx circuit 216 can provide a receiver (Rx) path for communication between the voltage tracking circuit 218 and the components of the chip-level circuit 102. For example, the voltage tracking circuit 218 can provide an Rx_In signal to the Rx circuit 216, and the Rx circuit 216 can receive the Rx_In signal, receive the core voltage (VDD), receive the IO voltage (DVDD), receive the ground voltage (VSS), and provide output control / data signals to... Figure 1 The chip-level circuit 102 includes a digital core 104 and / or an analog core 106. In some cases, the digital core circuit 104 and / or the analog core circuit 106 can change and / or modify their operating characteristics and / or behavior based on the output control / data signals from the Rx circuit 216.

[0030] The overdrive I / O circuit 120 may include an output circuit 220 having a switching structure (e.g., P0, P1, N0, N1) configured to receive a first tracking signal (PG_track), receive a second tracking signal (NG), and provide an output pad voltage (V_pad or V_output) to a node associated with an output pad based on the first tracking signal (PG_track) and the second tracking signal (NG). In some cases, the output circuit 220 may be coupled to a second voltage domain, such as the I / O voltage domain between a first supply voltage (DVDD) and a second supply voltage (DVSS). In some cases, the switching structure (e.g., P0, P1, N0, N1) may include a first transistor (P0), a second transistor (P1), a third transistor (N0), and a fourth transistor (N1) series coupled between the first supply voltage (DVDD) and the second supply voltage (DVSS). Additionally, the first supply voltage (DVDD) can refer to a power supply voltage (or IO supply voltage) of 3.3V, 2.5V, or 1.8V, and the second supply voltage (DVSS) can refer to a ground voltage of 0V (or IO ground supply voltage).

[0031] In some embodiments, a first transistor (P0) may be coupled between a first supply voltage (DVDD) and a second transistor (P1), and the second transistor (P1) may be coupled between the first transistor (P0) and an output pad (PAD). In some cases, when the first transistor (P0) and the second transistor (P1) are activated, the first supply voltage (DVDD) can be provided to the output pad (PAD) as the output pad voltage (Voutput). The tracking circuit 218 can provide a first tracking signal (PG_track) to the gate of the first transistor (P0), and when activated by the first tracking signal (PG_track), the first transistor (P0) can provide the first supply voltage (DVDD) to the second transistor (P1). Furthermore, in some cases, the tracking circuit 218 can provide a first reference tracking signal (refp_track) to the gate of the second transistor (P1), and when activated by the second reference tracking signal (refn), the second transistor (P1) can provide the first supply voltage (DVDD) to the output pad (PAD).

[0032] In some embodiments, a third transistor (N0) may be coupled between an output pad (PAD) and a fourth transistor (N1), and the fourth transistor (N1) may be coupled between the third transistor (N0) and a second supply voltage (DVSS). In some cases, when the third transistor (N0) and the fourth transistor (N1) are activated, the second supply voltage (DVSS) can be provided to the output pad (PAD) as the output pad voltage (V_output). The tracking circuit 218 can provide a second tracking signal (refn) to the gate of the fourth transistor (N1), and when activated by the second tracking signal (NG), the fourth transistor (N1) can provide the second supply voltage (DVSS) to the third transistor (N0). Furthermore, in some cases, the tracking circuit 218 can provide a second reference tracking signal (refn) to the gate of the third transistor (N0), and when activated by the second reference tracking signal (refn), the third transistor (N0) can provide the second supply voltage (DVSS) to the output pad (PAD).

[0033] In some implementations, such as Figure 2 As shown, the output pad (PAD) can be configured to provide an output pad voltage (V_pad or V_output), and the tracking circuit 218 can be configured to receive a first voltage (PG), a second voltage (NG), and the output pad voltage (V_pad or V_output) as a feedback voltage. Furthermore, the tracking circuit 218 can be configured to provide a first tracking voltage (PG_track) and a second tracking voltage (NG) based on the first voltage (PG), the second voltage (NG), and the feedback voltage (V_pad or V_output). Additionally, as... Figure 2 As shown, the output circuit 220 can be configured to receive a first tracking voltage (PG_track) and a second tracking voltage (NG) from the tracking circuit 218, and provide an output pad voltage (V_pad or V_output) to the output pad (PAD) based on the first tracking voltage (PG_track) and the second tracking voltage (NG).

[0034] In some implementations, voltage tracking circuit 218 may be configured to provide a well control signal (well_ctrl) that is applied as a bias voltage to the wells of various transistors in overdrive circuit 120, such as the first transistor (P0) and the second transistor (P1) of output circuit 220. As further described herein, the well control signal (well_ctrl) may be applied to other transistors for biasing purposes.

[0035] Under various conditions, the first supply voltage (DVDD) can vary under different operating conditions; for example, in different operating modes, the first supply voltage (DVDD) can refer to a first level (e.g., 3.3V), a second level (e.g., 2.5V), or a third level (e.g., 1.8V). Therefore, the first supply voltage can operate between an upper boundary voltage (3.3V, 2.5V, 1.8V) and a corresponding first intermediate voltage (1.5V, 0.7V, 0V), and the second supply voltage can operate between a lower boundary voltage (0V) and a second intermediate voltage (1.8V). In this case, the first reference voltage (refp) can be generated by subtracting the second reference voltage (refn) from the first supply voltage (DVDD), such that: REFP = DVDD - REFN. Furthermore, the second reference voltage (refn) can be generated based on the maximum value of the first supply voltage (DVDD), such that: REFN = max(DVDDLO, DVDD / 2), where DVDDLO can vary from 1.62V to 1.98V on the PVT. Therefore, the maximum voltage of REFN can be 1.98V.

[0036] In some cases, the overdrive I / O circuit 120 can operate under fail-safe conditions, wherein during fail-safe conditions, the first supply voltage (DVDD) is similar to the lower boundary voltage (0V), and the output pad voltage (Vpad or Voutput) refers to the upper boundary voltage (3.3V, 2.5V, 1.8V). Furthermore, as described herein, the overdrive I / O circuit 120 can operate under different operating conditions, for example, in different operating modes. For example, during a first operating mode, the first supply voltage (DVDD) is similar to the upper boundary voltage at a first level (e.g., 3.3V), the second reference voltage (refn) is similar to a second intermediate voltage (e.g., 1.8V), and the second supply voltage (DVSS) is similar to the lower boundary voltage (0V). Therefore, in this case, the first reference voltage (refp) can be similar to the upper boundary voltage at the first level (e.g., 3.3V) minus the second intermediate voltage (e.g., 1.8V), which is similar to the first intermediate voltage (1.5V).

[0037] In another scenario, during the second operating mode, the first supply voltage (DVDD) is analogous to an upper boundary voltage at a second level (e.g., 2.5V) that is less than the first level (e.g., 3.3V), the second reference voltage (refp) is analogous to a second intermediate voltage (e.g., 1.8V), and the second supply voltage is analogous to a lower boundary voltage (0V). Therefore, in this case, the first reference voltage (refp) can be analogous to the upper boundary voltage at the second level (e.g., 2.5V) minus the second intermediate voltage (e.g., 1.8V), which is (0.7V).

[0038] In another scenario, during the third operating mode, the first supply voltage (DVDD) is analogous to the upper boundary voltage at the third level (e.g., 1.8V), which is less than the second level (e.g., 2.5V). The second reference voltage (refn) is analogous to the second intermediate voltage (e.g., 1.8V), while the second supply voltage (DVSS) is analogous to the lower boundary voltage (0V). Therefore, in this case, the first reference voltage (refp) is analogous to the upper boundary voltage at the third level (e.g., 1.8V) minus the second intermediate voltage (e.g., 1.8V), which is the lower boundary voltage (0V).

[0039] Figures 3A to 3B A diagram of a voltage tracking circuit according to various embodiments described herein is shown. Specifically, Figure 3A A diagram 300A is shown of a voltage tracking circuit 302 with pad tracking logic circuit 218. Furthermore, Figure 3B A diagram 300B shows a multi-stage circuit 304 of pad tracking logic circuit 218, which will... Figures 4 to 6B This will be further described in the text. In some cases, Figures 3A to 3BThe pad tracking logic circuit 218 refers to Figure 2 The voltage tracking circuit 218 in the diagram can also be referred to as voltage tracking logic. The pad tracking logic circuit 218 can be configured to support 3.3V / 2.5V / 1.8V fail-safe operation using a 1.8V device, and the pad tracking logic circuit 218 can also be configured to support multi-mode 3.3V / 2.5V / 1.8V fail-safe operation.

[0040] like Figure 3A As shown, the voltage tracking circuit 302 may include an output stage (e.g., output circuit 220) having multiple output transistors (e.g., P0, P1, N0, N1), the output transistors being configured to receive a first tracking signal (PG_track), receive a second tracking signal (NG), and provide an output pad signal (V_pad / V_output) to an output pad (PAD) based on the first tracking signal (PG_track) and the second tracking signal (NG). The voltage tracking circuit 302 may include a pad tracking logic circuit 218 having a feedback stage (R1, R2, R3, N2), and a multi-stage circuit 304. In some cases, the feedback stage may be configured to receive the output pad signal (V_pad or V_output) from the output stage 220 and provide a pad feedback signal (padby2) based on the output pad signal (V_pad or V_output). Tracking stage 218 may include multi-stage circuitry 304 configured to receive a first signal (PG), a second signal (NG), an output pad signal (V pad / V output from R1 as padr) from an output pad (PAD), a pad feedback signal (padby2) from a feedback stage (R2, R3, N2), and to provide a first tracking signal (PG_track) and a second tracking signal (NG) to output stage 220 based on the first signal (PG), the second signal (NG), the output pad signal (padr), and the pad feedback signal (padby2). Furthermore, multi-stage circuitry 304 may be configured to provide a well control signal (well_ctrl) as a bias voltage to the wells of various transistors, such as the first transistor (P0) and the second transistor (P1) of output stage 220.

[0041] In some implementations, the first transistor (P0) and the second transistor (P1) can be implemented using P-type transistors, while the third transistor (N0) and the fourth transistor (N1) can be implemented using N-type transistors. However, in other cases, transistors (P0, P1) can be implemented using N-type transistors, while transistors (N0, N1) can be implemented using P-type transistors.

[0042] The feedback stage can be configured to receive an output pad signal (Vpad or Voutput) from the output stage 220 and provide a pad feedback signal (padby2) based on the output pad signal (Vpad or Voutput). The feedback stage may include a first resistor (R1 or R_sec) that receives the output pad signal (Vpad or Voutput) from the output stage 220 and provides the output pad signal (Vpad / Voutput as padr from R1) as an input padr voltage to the multistage circuit 304. In some cases, the first resistor R1 has a resistance value of 500Ω (500 ohms). In various other cases, the first resistor R1 may have various other resistance values.

[0043] The feedback stage may include a second resistor R2 that receives the output pad signal (Vpad or Voutput) from the output stage 220 and provides the pad feedback signal (padby2) as the input padby2 voltage to the multi-stage circuit 304. In some cases, the second resistor R2 has a resistance value of 400kΩ. In various other cases, the second resistor R2 may have a variety of other resistance values.

[0044] The feedback stage may include a third resistor R3 that receives the pad feedback signal (padby2) from the second resistor R2 and provides the pad feedback signal (padby2) to the transistor (N2). In some cases, the third resistor R3 may have a resistance value of 400kΩ. In various other cases, the third resistor R3 may have a variety of other resistance values.

[0045] The feedback stage may include a transistor (N2) coupled between a third resistor R3 and ground (VSS). In some cases, the multi-stage circuit 304 may provide a resistor control signal (Res_ctrl) to the gate of the transistor (N2). Furthermore, in some cases, the transistor (N2) is implemented as an N-type transistor; however, in other cases, the transistor (N2) may be implemented as a P-type transistor.

[0046] In some cases, the first signal (PG) may refer to a first operating voltage within a first range, and the second signal (NG) may refer to a second operating voltage within a second range different from the first range. The tracking circuit 218 may be configured to receive a first reference signal (refp), receive a second reference signal (refn), provide a first reference tracking signal (refp_track) based on the first reference signal (refp), and provide a second reference tracking signal (refn_track) based on the second reference signal (refn). The first reference signal (refp) may be related to the first operating voltage (PG), and the second reference signal (NG) may be related to the second operating voltage (NG).

[0047] In some cases, the output circuit 220 may include output transistors (P0, I, N0, N1) as switching structures, configured to receive a first tracking signal (PG_track) from the tracking circuit 218, receive a second tracking signal (NG) from the tracking circuit 218, and provide an output pad voltage (V_pad or V_output) to the output pad (PAD) based on the first tracking signal (PG_track) and the second tracking signal (NG). The output transistors may include a first transistor (P0), a second transistor (P1), a third transistor (N0), and a fourth transistor (N1).

[0048] A first transistor (P0) is coupled between a first supply voltage (DVDD) and a second transistor (P1), and the second transistor (P1) is coupled between the first transistor (P1) and the output pad (PAD). When the first transistor (P0) and the second transistor (P1) are activated, the first supply voltage (DVDD) is provided to the output pad (PAD) as the output pad voltage (V_pad or V_output). The tracking circuit 218 provides a first tracking signal (PG_track) to the gate of the first transistor (P0), and when activated by the first tracking signal (PG_track), the first transistor (P1) provides the first supply voltage (DVDD) to the second transistor (P1). Additionally, the tracking circuit 218 provides a first reference tracking signal (refp_track) to the gate of the second transistor (P1), and when activated by the second reference tracking signal (refn_track), the second transistor (P1) provides the first supply voltage (DVDD) to the output pad (OUT).

[0049] A third transistor (N0) is coupled between the output pad (PAD) and the fourth transistor (P1), and the fourth transistor (N1) is coupled between the third transistor (P0) and the second supply voltage (DVSS). When the third transistor (N0) and the fourth transistor (N1) are activated, the second supply voltage (DVSS) is provided to the output pad (PAD) as the output pad voltage (V_pad or V_output). The tracking circuit 218 provides a second tracking signal (NG) to the gate of the fourth transistor (N1), and when activated by the second tracking signal (NG), the fourth transistor (N1) provides the second supply voltage (DVSS) to the third transistor (N0). Furthermore, the tracking circuit 218 provides a second reference tracking signal (refn) to the gate of the third transistor (N0), and when activated by the second reference tracking signal (refn), the third transistor (N0) provides the second supply voltage (DVSS) to the output pad (PAD).

[0050] Voltage tracking circuit 302 may include Rx circuit 216, which may be coupled to Figure 1 One or more components of the chip-level circuit 102. In some cases, the Rx circuit 216 can operate as a secondary protection circuit and provide an Rx path for communication between the multi-level circuit 304 and components 104, 106 of the chip-level circuit 102. For example, the multi-level circuit 304 can provide an Rx_In signal to the Rx circuit 216, and as described above, the Rx circuit 216 can receive the Rx_In signal, receive multiple input voltages (VDD, DVDD, VSS), and then provide output control / data signals to the digital core 104 and / or analog core 106 of the chip-level circuit 102. In some cases, the digital core circuit 104 and / or analog core circuit 106 can change and / or modify operating characteristics and / or behavior based on the output control / data signals from the Rx circuit 216.

[0051] like Figure 3B As shown, the pad tracking logic circuit 218 (or voltage tracking circuit) may include a multi-stage circuit 304 having a first stage 310, a second stage 320, and a third stage 330 coupled together, arranged and configured for voltage tracking schemes and techniques as described herein. In some cases, the multi-stage circuits 310, 320, and 330 may be configured to operate as a tracking stage that receives input signals (e.g., PG, NG, refp, refn) and provides tracking signals (e.g., PG_track, NG, refp_track, refn_track). The input signals may include a first gate voltage signal (PG), a second gate voltage signal (NG), a first reference voltage signal (refp), and a second reference voltage signal (refn). The tracking signals may include a first gate tracking voltage signal (PG_track), a second gate tracking voltage signal (NG), a first reference tracking voltage signal (refp_track), and a second reference tracking voltage signal (refn_track). See reference... Figures 2 to 3A The tracking signals (PG_track, NG, refp_track, refn_track) can be provided to an output stage circuit 220 having multiple output transistors (switching structure: P0, P1, N0, N1), which can be configured to receive the tracking signals and provide output pad voltages (V pad or V output) based on the tracking signals.

[0052] Figure 4 A transistor-level diagram 400 of a first-stage circuit 310 according to various embodiments described herein is shown. (References herein) Figures 4 to 6BThe various embodiments described may provide a single tracking circuit that enables various low-voltage devices (e.g., devices based on 1.8V transistors) to operate with power sequence-independent fail-safe support in different voltage level domains (e.g., 3.3V / 2.5V / 1.8V) for overdrive circuitry.

[0053] like Figure 4 As shown, the first-stage circuit 310 includes multiple transistors of different types, such as P-type transistors (P10, P11, P12, P13, P14, P15, P16, P17, P18, P19, P20) and N-type transistors (N11), which are coupled together, arranged and configured to operate as the first-stage circuit 310.

[0054] For example, transistor P10 is coupled between the gates of DVDD and transistor N10 at node (t_n1), and transistor P10 is activated by the first reference tracking signal (refp). Transistors P11 and P12 are coupled in series at node (n1) between the padby2 voltage signal and transistor N10. Transistor P11 is activated by the first reference tracking signal (refp), while transistor P12 is activated by the node voltage at node (t_n1). Transistor N10 is coupled at node (n1) between the first reference tracking signal (refp) and transistor N12, and transistor N10 is activated by the node voltage at node (t_n1). Transistors P13 and P14 are coupled in series between node (n1) and the second reference voltage signal (refn). Transistor P13 is activated by the second reference voltage signal (refn), and transistor P14 is activated by the node voltage at node (n1). The max_n1_refn signal is obtained from the node located between transistors P13 and P14.

[0055] Furthermore, transistors P15 and P16 are series-coupled between the padby voltage signal and transistor N11. Transistor P15 is activated by the node voltage at node (n1), while transistor P16 is activated by the first reference voltage signal (refp). Transistor N11 is coupled between the ground voltage signal (Vss) and transistor P16, and transistor N11 is activated by the second reference voltage signal (refn). The Res_ctrl signal is obtained from the node located between transistors P16 and N11.

[0056] Furthermore, transistors P17 and P18 are series coupled between the padr voltage signal and transistor P20 at node (n1). Transistor P17 is activated by the node voltage at node (n1), while transistor P18 is activated by the padr voltage signal. The node voltage at node (n3) is obtained from the node located between transistors P17 and P18. Transistors P19 and P20 are series coupled between node (t_n1) and transistor P18 at node (n1). Transistor P19 is activated by the node voltage at node (n1), and transistor P20 is activated by the node voltage at node (t_n1). The node voltage at node (n2) is obtained from the node located between transistors P19 and P20.

[0057] Figure 5 A transistor-level diagram 500 of a second-stage circuit 320 according to various embodiments described herein is shown. The second-stage circuit 320 can refer to… Figures 1 to 2 The output stage circuit 220.

[0058] like Figure 5 As shown, the second-stage circuit 320 may include one or more types of transistors (e.g., N-type transistors (N20, N21, N22)) and one or more resistors (R1, R2, R3), said transistors and resistors being coupled together, arranged and configured to operate as the second-stage circuit 320. The resistors (N20, N21, N22) may be grounded to VSS via a substrate connection or similar means.

[0059] For example, resistor R1 (R_sec) is coupled between the output pad (PAD) and the node (padr), which provides the padr voltage signal. Transistor N20 is coupled between nodes (padr) and (padby2), operating as a diode. Resistor R2 is coupled between nodes (padr) and (padby2), and resistor R3 is coupled between resistor R2 at node (padr) and transistor N21. Transistors N21 and N22 are coupled between resistor R3 and ground (VSS). Transistor N21 is activated by the node voltage at node (n1), and transistor N22 is activated by the Res_ctrl voltage signal. In some cases, resistor R1 is 500Ω (500 ohms), resistor R2 is 400kΩ (400 kiloohms), and resistor R3 is 400kΩ (400 kiloohms).

[0060] Figures 6A to 6B A transistor-level diagram of the third-stage circuit 330 according to the embodiment described herein is shown. Specifically, Figure 6A The diagram shows the first transistor stage 600A of the first circuit portion of the third-stage circuit 330, and... Figure 6BA diagram 600A showing the second transistor stage of the second circuit portion of the third-stage circuit 330 is provided. The third-stage circuit 330... Figure 6A The first circuit section and Figure 6B The second circuit portion is coupled together in the manner described herein, arranged and configured to operate as a third-level circuit 330.

[0061] like Figure 6A As shown, the first circuit portion of the third-stage circuit 330 may include multiple transistors of different types, such as P-type transistors (P30, P31, P32, P33, P34, P35, P36) and N-type transistors (N30, N31, N32, N33, N34, N35, N36, N37, N38, N39), which are coupled together, arranged and configured to operate as the first circuit portion of the third-stage circuit 330.

[0062] For example, transistors P30 and N30 are coupled in series between the first tracking voltage signal (PG_track) and transistor P31. Transistor P30 is activated by the node voltage at node (n1), and transistor N30 is activated by the node voltage at node (t_n1). The first tracking voltage signal (PG_track) is coupled to a node located between transistors N30 and P31. Transistor P31 is coupled between node (n1) and transistor N30, and transistor P31 is activated by the node voltage at node (t_n1).

[0063] Furthermore, transistors N31 and N32 are series-coupled between the first reference voltage signal (refn) and transistor P32. Transistor N31 is activated by the node voltage at node (t_n1), and transistor N32 is activated by the node voltage at node (n2). A second reference tracking voltage signal (refn_track) is coupled to a node located between transistors N32 and P32. Transistor P32 is coupled between node (n1) and transistor N32, and transistor P32 is activated by the node voltage at node (t_n1).

[0064] Furthermore, transistors N33 and N34 are series-coupled between the first reference voltage signal (refp) and transistor P33. Transistor N33 is activated by the node voltage at node (t_n1), and transistor N34 is activated by the node voltage at node (n2). The rx_ctrl signal is coupled to the node located between transistors N33 and N34. Transistor P33 is coupled between node (n3) and transistor N34, and transistor P33 is activated by the node voltage at node (n2).

[0065] Furthermore, transistor P34 is coupled between the node for the rx_ctrl voltage signal and the node for the well_ctrl voltage signal, and transistor P34 is activated by the node voltage at node (n2). Transistors P35 and P36 are coupled in parallel between node (n2) and the node for the well_ctrl voltage signal. Transistor P35 is activated by the rx_ctrl voltage signal, while transistor P36 is activated by the well_ctrl voltage signal. Transistor N35 is coupled between the second voltage signal (NG) and the ground voltage (Dvss), and transistor N35 is activated by the Res_ctrl voltage signal.

[0066] Furthermore, transistor N36 is coupled between the padby2 voltage signal and the node used for the Rx_In voltage signal, and transistor N36 is activated by the rx_ctrl voltage signal. Transistors N37, N38, and N39 are coupled in parallel between the node (padr) and the node used for the rx_ctrl voltage signal. Transistor N37 is activated by the node voltage signal at node (n1), transistor N38 is activated by the max_n1_refn voltage signal, and transistor N39 is activated by the rx_ctrl voltage signal.

[0067] like Figure 6B As shown, the second circuit portion of the third-stage circuit 330 may include multiple transistors of different types, such as P-type transistors (P40, P41, P42, P43, P44, P45) and N-type transistors (N40, N41, N42, N43, N44, N45), which are coupled together, arranged and configured to operate as the second circuit portion of the third-stage circuit 330.

[0068] For example, transistors N40, N41, and N42 are coupled in series between the first reference voltage signal (refp) and the node used for the first reference tracking voltage signal (refp_track). Transistor N40 is activated by the node voltage at node (oe_p), transistor N41 is activated by the node voltage at node (t_n1), and transistor N42 is activated by the node voltage at node (n2). Transistor P40 is coupled between node (n3) and the node used for the first reference tracking voltage signal (refp_track), and transistor P40 is activated by the node voltage at node (n2). Transistor P41 is coupled between node (n1) and the node used for the first reference tracking voltage signal (refp_track), and transistor P41 is activated by the first reference tracking voltage signal (refp_track).

[0069] Furthermore, transistors P42 and N43 are series coupled between the voltage supply signal Dvdd and the node used for the first reference voltage signal (refp). Transistor P42 is activated by the oe_p voltage signal, and transistor N43 is activated by the oe_p voltage signal. Transistors P42 and N43 are coupled to operate as inverters and provide the oeb_p voltage signal as the inversion of the oe_p voltage signal. The node (oeb_p) is located between transistors P42 and N43, and transistor P43 is coupled between the node used for the oeb_p voltage signal and node (n4). Transistors N44 and P44 are coupled in parallel between node (n4) and node (n1). Transistor N44 is activated by the oe_p voltage signal, and transistor P44 is activated by the oeb_p voltage signal. Transistors N45 and P45 are coupled between the node used for the first reference tracking voltage signal (refp_track) and node (n3). Transistor N45 is activated by the node voltage at node (n4), while transistor P45 is activated by the node voltage at node (n1).

[0070] Figure 7 A process flowchart 700 for providing a voltage tracking circuit according to an embodiment described herein is shown.

[0071] It should be understood that even though method 700 specifies a particular order of operation execution, in some cases, the specific parts of the operation may be executed in a different order and on different systems. In other cases, additional operations and / or steps may be added to method 700 and / or omitted from method 700. Furthermore, method 700 may be implemented in hardware and / or software. If implemented in hardware, method 700 may be implemented using various components and / or circuits, as referenced herein. Figures 1 to 6B Furthermore, if implemented in software, method 700 can be implemented as a program and / or software instruction process configured to provide voltage tracking schemes and techniques, as described herein. Moreover, if implemented in software, the instructions relating to the implementation of method 700 can be stored in memory and / or a database. For example, a computer or various other types of computing devices having a processor and memory can be configured to execute method 700.

[0072] In various embodiments, method 700 can refer to a method of designing, providing, constructing, and / or manufacturing a voltage tracking circuit as an integrated system, device, and / or circuit. This method may include using various IC circuit components described herein to implement associated voltage tracking schemes and techniques. The voltage tracking circuit can be integrated with computing circuitry and related components on a single chip, and the voltage tracking circuit can be implemented in various embedded systems for various electronic applications, mobile applications, and Internet of Things (IoT) applications, including sensor nodes.

[0073] At block 710, method 700 can manufacture an output pad configured to provide an output pad voltage. At block 720, method 700 can manufacture a tracking circuit configured to receive a first voltage, receive a second voltage different from the first voltage, receive the output pad voltage as a feedback voltage, and provide a first tracking voltage and a second tracking voltage based on the first voltage, the second voltage, and the feedback voltage. Furthermore, at block 730, method 700 can manufacture an output circuit configured to receive the first tracking voltage and the second tracking voltage from the tracking circuit, and provide the output pad voltage to the output pad based on the first tracking voltage and the second tracking voltage.

[0074] In some embodiments, the first voltage may refer to a first operating voltage within a first range, and the second voltage may refer to a second operating voltage within a second range different from the first range. The tracking circuit may be configured to receive a first reference signal related to the first operating voltage, receive a second reference signal related to the second operating voltage, provide a first reference tracking voltage based on the first reference voltage, and provide a second reference tracking voltage based on the second reference voltage. The output circuit may include a plurality of switching structures configured to receive the first tracking voltage from the tracking circuit, receive the second tracking voltage from the tracking circuit, and provide an output pad voltage to the output pad based on the first and second tracking voltages. The switching structures include a first transistor and a second transistor, wherein the first transistor may be coupled between a first supply voltage and the second transistor, and the second transistor may be coupled between the first transistor and the output pad. Additionally, when the first and second transistors are activated, the first supply voltage can be provided to the output pad as the output pad voltage. The tracking circuit may provide a first tracking signal to the gate of the first transistor, and when activated by the first tracking signal, the first transistor may provide the first supply voltage to the second transistor. The tracking circuit provides a first reference tracking signal to the gate of the second transistor, and when activated by the second reference tracking signal, the second transistor provides a first supply voltage to the output pad.

[0075] In some cases, the switching structure includes a third transistor and a fourth transistor, wherein the third transistor can be coupled between the output pad and the fourth transistor, and the fourth transistor can be coupled between the third transistor and a second supply voltage. Additionally, when the third and fourth transistors are activated, the second supply voltage can be provided to the output pad as the output pad voltage. A tracking circuit can provide a second tracking signal to the gate of the fourth transistor, and when activated by the second tracking signal, the fourth transistor can provide the second supply voltage to the third transistor. The tracking circuit can also provide a second reference tracking signal to the gate of the third transistor, and when activated by the second reference tracking signal, the third transistor can provide the second supply voltage to the output pad.

[0076] In some cases, the first supply voltage can be between a first intermediate voltage (1.5V, 0.7V, 0V) and an upper boundary voltage (3.3V, 2.5V, 1.8V), and the second supply voltage can be between a lower boundary voltage (0V) and a second intermediate voltage (1.8V). During fail-safe conditions, the first supply voltage can refer to the lower boundary voltage (0V), and the output pad voltage can refer to the upper boundary voltage (3.3V). During the first operating mode, the first supply voltage can refer to the upper boundary voltage at the first level (3.3V), the second reference voltage can refer to the second intermediate voltage (1.8V), and the second supply voltage can refer to the lower boundary voltage (0V). Furthermore, in this case, the first reference voltage can refer to the upper boundary voltage at the first level (3.3V) minus the second intermediate voltage (1.8V), which is the first intermediate voltage (1.5V).

[0077] In some cases, during the second operating mode, the first supply voltage may refer to the upper boundary voltage of the second level (2.5V), which is less than the first level (3.3V), the second reference voltage may refer to the second intermediate voltage (1.8V), and the second supply voltage may refer to the lower boundary voltage (0V). Furthermore, in this case, the first reference voltage may refer to the upper boundary voltage of the second level (2.5V) minus the second intermediate voltage (1.8V), which is (0.7V).

[0078] In some cases, during the third operating mode, the first supply voltage may refer to the upper boundary voltage of the third level (1.8V), which is less than the second level of 2.5V; the second reference voltage may refer to the second intermediate voltage (1.8V); and the second supply voltage may refer to the lower boundary voltage (0V). Alternatively, in this case, the first reference voltage may refer to the upper boundary voltage of the third level (1.8V) minus the second intermediate voltage (1.8V), which is the lower boundary voltage (0V).

[0079] It should be understood that the subject matter of the claims is not limited to the embodiments and illustrations provided herein, but includes modifications of those embodiments, including portions of the embodiments claimed and combinations of elements of different embodiments. It should be recognized that in the development of any such embodiment, as in any engineering or design project, numerous implementation-specific decisions should be made to achieve the developer's specific objectives, such as complying with system-related and business-related constraints that may vary depending on the implementation. Furthermore, it should be recognized that such development efforts can be complex and time-consuming, but remain routine tasks of design, manufacture, and production for those skilled in the art who benefit from this disclosure.

[0080] This document describes various embodiments of the device. The device may include an output pad configured to provide an output pad voltage. The device may include a tracking circuit configured to receive a first voltage, receive a second voltage different from the first voltage, receive the output pad voltage as a feedback voltage, and provide a first tracking voltage and a second tracking voltage based on the first voltage, the second voltage, and the feedback voltage. The device may include an output circuit configured to receive the first tracking voltage and the second tracking voltage from the tracking circuit, and provide the output pad voltage to the output pad based on the first tracking voltage and the second tracking voltage.

[0081] This document describes various embodiments of a voltage tracking circuit. The voltage tracking circuit may include an output stage having an output transistor configured to receive a first tracking signal, receive a second tracking signal, and provide an output pad signal to an output pad based on the first and second tracking signals. The voltage tracking circuit may include a feedback stage configured to receive the output pad signal from the output stage and provide a pad feedback signal based on the output pad signal. The voltage tracking circuit may also include a tracking stage configured to receive a first signal, receive a second signal different from the first signal, receive an output pad signal from an output pad, receive a pad feedback signal from the feedback stage, and provide the first and second tracking signals to the output stage based on the first signal, the second signal, the output pad signal, and the pad feedback signal.

[0082] This document describes various embodiments of a method for manufacturing integrated circuits. The method may include manufacturing an output pad configured to provide an output pad voltage. The method may include manufacturing a tracking circuit configured to receive a first voltage, receive a second voltage different from the first voltage, receive the output pad voltage as a feedback voltage, and provide a first tracking voltage and a second tracking voltage based on the first voltage, the second voltage, and the feedback voltage. The method may include manufacturing an output circuit configured to receive the first tracking voltage and the second tracking voltage from the tracking circuit, and provide the output pad voltage to the output pad based on the first tracking voltage and the second tracking voltage.

[0083] Various embodiments have been described in detail, examples of which are illustrated in the accompanying drawings. Numerous specific details are set forth in the following detailed description to provide a thorough understanding of the disclosure provided herein. However, the disclosure provided herein can be practiced without these specific details. In some other instances, well-known methods, processes, components, circuits, and networks have not been described in detail to avoid unnecessarily obscuring the details of the embodiments.

[0084] It should also be understood that although the terms "first," "second," etc., may be used in this document to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. Both the first and second elements are elements, but they are not considered the same element.

[0085] The terminology used in the description of the disclosure provided herein is for the purpose of describing particular embodiments and is not intended to limit the disclosure provided herein. As used in the description of the disclosure provided herein and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. The term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items. When used in this specification, the terms “comprising,” “including,” “containing,” and / or “having” indicate the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0086] As used herein, the term "if" can be interpreted as meaning "when," "at," "in response to being determined," or "in response to being detected," depending on the context. Similarly, the phrase "if determined" or "if (the stated condition or event) is detected" can be interpreted as meaning "when... is determined," "in response to being determined," "when (the stated condition or event) is detected," or "in response to being detected," depending on the context. The terms "upper" and "lower," "upper part" and "lower part," "upward" and "downward," "below" and "above," and other similar terms indicating relative positions above or below a given point or element, can be used in conjunction with some implementations of the various techniques described herein.

[0087] While the foregoing describes various implementations of the technologies described herein, other and further implementations can be contemplated based on the disclosure herein, as may be determined by the appended claims.

[0088] Although the subject matter has been described in language specific to structural features and / or methodological actions, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are disclosed as exemplary forms of implementing the claims.

Claims

1. A voltage tracking device comprising: an output pad configured to provide an output pad voltage; an input circuit configured to include a first predriver and a second predriver, the first predriver to output a first voltage based on a first reference voltage, the second predriver to output a second voltage based on a second reference voltage; a tracking circuit configured to receive the first voltage from the first predriver, to receive the second voltage different from the first voltage from the second predriver, to receive the output pad voltage as a feedback voltage, and to provide a first tracking voltage and a second tracking voltage based on the first voltage, the second voltage, and the feedback voltage, wherein the tracking circuit is further configured to receive the first reference voltage, to provide a first reference tracking voltage based on the first reference voltage, to receive the second reference voltage, and to provide a second reference tracking voltage based on the second reference voltage; and an output circuit configured to receive the first tracking voltage and the second tracking voltage from the tracking circuit, and to provide the output pad voltage to the output pad based on the first tracking voltage and the second tracking voltage.

2. The device of claim 1, wherein the first voltage refers to a first operating voltage in a first range, and wherein the second voltage refers to a second operating voltage in a second range different from the first range.

3. The device of claim 1, wherein the output circuit includes a switch structure configured to receive the first tracking voltage from the tracking circuit, to receive the second tracking voltage from the tracking circuit, and to provide the output pad voltage to the output pad based on the first tracking voltage and the second tracking voltage.

4. The device of claim 3, wherein the switch structure includes a first transistor and a second transistor, wherein the first transistor is coupled between a first supply voltage and the second transistor, wherein the second transistor is coupled between the first transistor and output pad, and wherein the first supply voltage is provided to the output pad as the output pad voltage when the first transistor and the second transistor are activated.

5. The device of claim 4, wherein the tracking circuit provides the first tracking voltage to a gate of the first transistor, and wherein the first transistor provides the first supply voltage to the second transistor when activated by the first tracking voltage.

6. The device of claim 5, wherein the tracking circuit provides the first reference tracking voltage to a gate of the second transistor, and wherein the second transistor provides the first supply voltage to the output pad when activated by the second reference tracking voltage. ​ 7. The apparatus of claim 4, wherein the switch structure comprises a third transistor and a fourth transistor, wherein the third transistor is coupled between the output pad and the fourth transistor, wherein the fourth transistor is coupled between the third transistor and a second supply voltage, and wherein the second supply voltage is provided to the output pad as the output pad voltage when the third transistor and the fourth transistor are activated.

8. The apparatus of claim 7, wherein the tracking circuit provides the second tracking voltage to a gate of the fourth transistor, and wherein the fourth transistor provides the second supply voltage to the third transistor when activated by the second tracking voltage.

9. The apparatus of claim 8, wherein the tracking circuit provides the second reference tracking voltage to a gate of the third transistor, and wherein the third transistor provides the second supply voltage to the output pad when activated by the second reference tracking voltage.

10. The apparatus of claim 7, wherein the first supply voltage is between a first intermediate voltage and an upper boundary voltage, and wherein the second supply voltage is between a lower boundary voltage and a second intermediate voltage.

11. The apparatus of claim 10, wherein during a fail-safe condition, the first supply voltage refers to the lower boundary voltage and the output pad voltage refers to the upper boundary voltage.

12. The apparatus of claim 10, wherein during a first operating mode, the first supply voltage refers to the upper boundary voltage at a first level, the second reference voltage refers to the second intermediate voltage, and the second supply voltage refers to the lower boundary voltage, and wherein the first reference voltage refers to the upper boundary voltage at the first level minus the second intermediate voltage, the first reference voltage refers to the first intermediate voltage.

13. The apparatus of claim 12, wherein during a second operating mode, the first supply voltage refers to the upper boundary voltage at a second level less than the first level, the second reference voltage refers to the second intermediate voltage, and the second supply voltage refers to the lower boundary voltage, and wherein the first reference voltage refers to the upper boundary voltage at the second level minus the second intermediate voltage.

14. The apparatus of claim 13, wherein during a third operating mode, the first supply voltage refers to the upper boundary voltage at a third level less than the second level, the second reference voltage refers to the second intermediate voltage, and the second supply voltage refers to the lower boundary voltage, and wherein the first reference voltage refers to the upper boundary voltage at the third level minus the second intermediate voltage, the first reference voltage refers to the lower boundary voltage.

15. A voltage tracking circuit, comprising: an output stage having an output transistor configured to receive a first tracking signal, receive a second tracking signal, and provide an output pad signal to an output pad based on the first tracking signal and the second tracking signal; an input stage having a first predriver outputting a first signal based on a first reference voltage and a second predriver outputting a second signal based on a second reference voltage; a feedback stage configured to receive the output pad signal from the output stage and provide a pad feedback signal based on the output pad signal; and a tracking stage configured to receive the first signal, receive the second signal different from the first signal, receive the output pad signal from the output pad, receive the pad feedback signal from the feedback stage, receive the first reference voltage, receive the second reference voltage, and provide the first tracking signal and the second tracking signal to the output stage based on the first signal, the second signal, the first reference voltage, the second reference voltage, the output pad signal, and the pad feedback signal.

16. The circuit of claim 15, wherein: the tracking stage is configured to receive a first reference signal, receive a second reference signal different from the first reference signal, and provide a first reference tracking signal and a second reference tracking signal based on the first reference signal and the second reference signal, and the output transistor of the output stage is configured to receive the first reference tracking signal, receive the second reference tracking signal, and provide the output pad signal to the output pad based on the first tracking signal, the second tracking signal, the first reference tracking signal, and the second reference tracking signal.

17. The circuit of claim 16, wherein the output transistor of the output stage comprises a first transistor, a second transistor, a third transistor, and a fourth transistor, and wherein: the first transistor is coupled between a supply voltage and the second transistor, the second transistor is coupled between the first transistor and the output pad, the third transistor is coupled between the output pad and the fourth transistor, the fourth transistor is coupled between the third transistor and a ground voltage, the supply voltage is provided to the output pad as the output pad signal when the first transistor and the second transistor are activated, and the ground voltage is provided to the output pad as the output pad signal when the third transistor and the fourth transistor are activated.

18. The circuit of claim 17, wherein: the tracking stage provides the first tracking signal to a gate of the first transistor, and the first transistor provides the supply voltage to the second transistor when activated by the first tracking signal, the second transistor provides the output pad signal to the output pad when activated by the first tracking signal and the second tracking signal, the tracking stage provides the second tracking signal to a gate of the fourth transistor, and when activated by the second tracking signal, the fourth transistor provides the ground voltage to the third transistor, and the tracking stage provides the second tracking signal to a gate of the fourth transistor, and when activated by the second tracking signal, the fourth transistor provides the ground voltage to the third transistor, and the tracking stage provides the second tracking signal to a gate of the fourth transistor, and when activated by the second tracking signal, the fourth transistor provides the ground voltage to the third transistor, and 19. A voltage tracking method, comprising: manufacturing an output pad configured to provide an output pad voltage; manufacturing an input circuit including a first pre-driver and a second pre-driver, the first pre-driver outputting a first voltage based on a first reference voltage, the second pre-driver outputting a second voltage based on a second reference voltage; manufacturing a tracking circuit configured to receive the first voltage from the first pre-driver, receive the second voltage different from the first voltage from the second pre-driver, receive the output pad voltage as a feedback voltage, and provide a first tracking voltage and a second tracking voltage based on the first voltage, the second voltage, and the feedback voltage, wherein the tracking circuit is further configured to receive the first reference voltage, provide a first reference tracking voltage based on the first reference voltage, receive the second reference voltage, and provide a second reference tracking voltage based on the second reference voltage; and manufacturing an output circuit configured to receive the first tracking voltage and the second tracking voltage from the tracking circuit, and provide the output pad voltage to the output pad based on the first tracking voltage and the second tracking voltage.

19. A voltage tracking method, comprising: manufacturing an output pad configured to provide an output pad voltage; manufacturing an input circuit including a first pre-driver and a second pre-driver, the first pre-driver outputting a first voltage based on a first reference voltage, the second pre-driver outputting a second voltage based on a second reference voltage; manufacturing a tracking circuit configured to receive the first voltage from the first pre-driver, receive the second voltage different from the first voltage from the second pre-driver, receive the output pad voltage as a feedback voltage, and provide a first tracking voltage and a second tracking voltage based on the first voltage, the second voltage, and the feedback voltage, wherein the tracking circuit is further configured to receive the first reference voltage, provide a first reference tracking voltage based on the first reference voltage, receive the second reference voltage, and provide a second reference tracking voltage based on the second reference voltage; and manufacturing an output circuit configured to receive the first tracking voltage and the second tracking voltage from the tracking circuit, and provide the output pad voltage to the output pad based on the first tracking voltage and the second tracking voltage.

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