A data transmission circuit and communication module

Abstract

The application provides a data transmission circuit and a communication module, comprising: a current mode driving circuit and a voltage mode driving circuit; the current mode driving circuit is configured to be turned on when a first mode selection signal is received; the voltage mode driving circuit is configured to be turned off when a second mode selection signal is received; the current mode driving circuit comprises two groups of current mode semiconductor switching elements, and can control the first group of current mode semiconductor switching elements or the second group of current mode semiconductor switching elements to be opened according to different driving signals; the voltage mode driving circuit comprises two voltage mode semiconductor switching elements, and can control the first voltage mode semiconductor switching element or the second voltage mode semiconductor switching element to be opened according to different driving signals. The scheme can realize single-chip integrated voltage type TX and current type TX two driving modes, so that users can flexibly switch according to requirements.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and more particularly to a data transmission circuit and a communication module. Background Technology

[0002] To reduce costs, lithium battery monitoring chips in a BMS typically use a cascaded approach for data transmission, thereby enabling monitoring and protection of the battery pack's operating status. The MCU communicates with a relay chip via a four-wire SPI interface. The relay chip converts the four-wire SPI signal into a two-wire differential signal, which is then cascaded with other battery monitoring chips via twisted-pair cables for signal transmission. A common communication module includes three parts: RX (receiver), TX (transmitter), and Digital (digital processing). RX resolves the two-wire twisted-pair signal into +1 or -1 signals, which are then restored to a four-wire signal by the Digital module. TX converts the +1 or -1 signal back into a two-wire signal.

[0003] Among them, TX is divided into two types: voltage-type and current-type. The current-type TX outputs a differential AC current source with high output impedance, cleaner signal waveform, and more controllable edges; the voltage-type TX outputs a voltage signal with low output impedance and stronger driving capability. However, the existing current-type TX and voltage-type TX structures are independent of each other, and it is impossible to combine the advantages of both voltage-type and current-type TX in a single chip, which limits the application scenarios. Summary of the Invention

[0004] The purpose of this invention is to provide a data transmission circuit and communication module that integrates both voltage-type and current-type TX driving modes on a single chip, allowing users to switch flexibly according to their needs, thereby improving the applicability of the product.

[0005] The technical solution provided by this invention is as follows:

[0006] In a first aspect, this application provides a data transmission circuit, including: a current-mode driving circuit and a voltage-mode driving circuit; the current-mode driving circuit is configured to be turned on when receiving a first mode selection signal and turned off when receiving a second mode selection signal; the voltage-mode driving circuit is configured to be turned off when receiving the first mode selection signal and turned off when receiving the second mode selection signal.

[0007] The current-mode drive circuit includes two sets of current-mode semiconductor switching elements. When a +1 signal is generated by the drive, the first set of current-mode semiconductor switching elements is turned on by a first control signal, so that a first positive differential voltage is generated between the high-side positive terminal and the high-side inverting terminal. When a -1 signal is generated by the drive, the second set of current-mode semiconductor switching elements is turned on by a second control signal, so that a first negative differential voltage is generated between the high-side positive terminal and the high-side inverting terminal.

[0008] The voltage-mode driving circuit includes two voltage-mode semiconductor switching elements. When a +1 signal is generated by the driving circuit, the first voltage-mode semiconductor switching element is turned on by the first control signal, so that a second positive differential voltage is generated between the high-side positive terminal and the high-side inverting terminal. When a -1 signal is generated by the driving circuit, the second voltage-mode semiconductor switching element is turned on by the second control signal, so that a second negative differential voltage is generated between the high-side positive terminal and the high-side inverting terminal.

[0009] In some embodiments, the voltage-mode drive circuit includes a first PMOS switch, a second PMOS switch, a first NMOS switch, and a second NMOS switch;

[0010] The gate of the first PMOS switch receives the mode selection signal, and the gate of the second NMOS switch receives the mode selection signal through an NOT gate.

[0011] The second PMOS switch is the first voltage-mode semiconductor switching element, and the first NMOS switch is the second voltage-mode semiconductor switching element. The gates of the second PMOS switch and the first NMOS switch are used to receive the first control signal and the second control signal.

[0012] The source of the first PMOS switch is connected to the driving power supply, and the drain is connected to the source of the second PMOS switch; the drain of the second PMOS switch is connected to the drain of the first NMOS switch; the source of the first NMOS switch is connected to the drain of the second NMOS switch; the source of the second NMOS switch is grounded.

[0013] The high-side positive terminal and the high-side negative terminal are connected between the drain of the second PMOS switch and the drain of the first NMOS switch.

[0014] In some embodiments, the voltage-mode drive circuit further includes an OR gate and a first NOR gate;

[0015] The transmission terminals of the first control signal and the second control signal are connected to the first input terminal of the OR gate through a NOT gate, the second input terminal of the OR gate is used to receive the IDLE signal, and the output terminal of the OR gate is connected to the gate of the second PMOS switch.

[0016] The transmission terminals of the first control signal and the second control signal are also connected to the first input terminal of the first NOR gate, the second input terminal of the first NOR gate is used to receive the IDLE signal, and the output terminal of the first NOR gate is connected to the gate of the first NMOS switch.

[0017] The high-side positive terminal and the high-side inverting terminal are connected between the drain of the second PMOS switch and the drain of the first NMOS switch through a first transmission gate. The enable terminal and the inverting enable terminal of the first transmission gate are respectively used to receive the mode selection signal and the non-signal of the mode selection signal, so that the first transmission gate is closed when the mode selection signal is the first mode selection signal.

[0018] In some embodiments, the current-mode drive circuit includes a third PMOS switch, a fourth PMOS switch, a fifth PMOS switch, a third NMOS switch, a fourth NMOS switch, and a fifth NMOS switch;

[0019] The first group of current-mode semiconductor switching elements includes the fourth PMOS switch and the fifth NMOS switch. The transmission terminal of the first control signal is connected to the gate of the fourth PMOS switch through a NOT gate, and the transmission terminal of the first control signal is connected to the gate of the fifth NMOS switch.

[0020] The second group of current-mode semiconductor switching elements includes the fifth PMOS switch and the fourth NMOS switch. The transmission terminal of the second control signal is connected to the gate of the fifth PMOS switch through a NOT gate, and the transmission terminal of the second control signal is connected to the gate of the fourth NMOS switch.

[0021] The source of the fourth PMOS switch and the source of the fifth PMOS switch are connected to the driving power supply through the third PMOS switch; the drain of the fourth PMOS switch is connected to the drain of the fourth NMOS switch, and the drain of the fifth PMOS switch is connected to the drain of the fifth NMOS switch; the source of the fourth NMOS switch and the source of the fifth NMOS switch are grounded through the third NMOS switch.

[0022] The gate of the third PMOS switch receives the mode selection signal via a NOT gate, and the gate of the third NMOS switch receives the mode selection signal.

[0023] The high-side positive terminal is connected between the drain of the fourth PMOS switch and the drain of the fourth NMOS switch, and the high-side inverting terminal is connected between the drain of the fifth PMOS switch and the drain of the fifth NMOS switch.

[0024] In some embodiments, the high-side positive input is connected between the drain of the fourth PMOS switch and the drain of the fourth NMOS switch via a second transmission gate, and the high-side inverting input is connected between the drain of the fifth PMOS switch and the drain of the fifth NMOS switch via a third transmission gate.

[0025] The enable terminals of the second and third transmission gates receive the mode selection signal, and the inverting enable terminals of the second and third transmission gates receive the non-signal of the mode selection signal, so that the second and third transmission gates are closed when the mode selection signal is the second mode selection signal.

[0026] In some embodiments, the current-mode drive circuit further includes a sixth PMOS switch, a seventh PMOS switch, a sixth NMOS switch, a seventh NMOS switch, and an eighth NMOS switch.

[0027] The drain of the sixth PMOS switch is connected to the source of the third PMOS switch, the source of the sixth PMOS switch is connected to the driving power supply, and the gate of the sixth PMOS switch is connected to the gate of the seventh PMOS switch; the drain of the sixth NMOS switch is connected to the source of the third NMOS switch, the source of the sixth NMOS switch is grounded, and the gate of the sixth PMOS switch is connected to the gate of the seventh NMOS switch; the gate of the seventh PMOS switch is also connected to the drain of the seventh NMOS switch, the source of the seventh PMOS switch is connected to the driving power supply, and the source of the seventh NMOS switch is grounded;

[0028] The gate of the eighth NMOS switch is connected to the gate of the seventh NMOS switch, the drain of the eighth NMOS switch is connected to the driving power supply, and the source of the eighth NMOS switch is grounded.

[0029] In some embodiments, the current-mode drive circuit further includes a capacitive coupling circuit, which includes a second NOR gate and a third NOR gate.

[0030] The first input terminal of the second NOR gate is connected to the positive terminal of the circuit via an NOT gate, the second input terminal of the second NOR gate is connected to the negative terminal of the circuit, the output terminal of the second NOR gate is connected between the sixth PMOS switch and the seventh PMOS switch via a first circuit, and the output terminal of the second NOR gate is also connected between the sixth NMOS switch and the seventh NMOS switch via a second circuit; the first circuit includes two NOT gates connected in series and a capacitor, and the second circuit includes three NOT gates connected in series and a capacitor;

[0031] The first input terminal of the third NOR gate is connected to the positive terminal of the circuit, the second input terminal of the second NOR gate is connected to the negative terminal of the circuit through an NOT gate, the output terminal of the third NOR gate is connected between the sixth PMOS switch and the seventh PMOS switch through a third circuit, and the output terminal of the third NOR gate is also connected between the sixth NMOS switch and the seventh NMOS switch through a fourth circuit; the third circuit includes two NOT gates connected in series and a capacitor, and the fourth circuit includes three NOT gates connected in series and a capacitor.

[0032] In some implementations, some components of the current-mode drive circuit and the voltage-mode drive circuit are shared to form an integrated drive circuit;

[0033] The drive integration circuit includes a tenth PMOS switch, an eleventh PMOS switch, a twelfth PMOS switch, a tenth NMOS switch, an eleventh NMOS switch, and a twelfth NMOS switch;

[0034] The transmission terminal of the first control signal is connected to the gate of the eleventh PMOS switch through a NOT gate, and the transmission terminal of the first control signal is connected to the gate of the twelfth NMOS switch; the transmission terminal of the second control signal is connected to the gate of the twelfth PMOS switch through a NOT gate, and the transmission terminal of the second control signal is connected to the gate of the eleventh NMOS switch.

[0035] The source of the eleventh PMOS switch and the source of the twelfth PMOS switch are connected to the driving power supply through the tenth PMOS switch; the drain of the eleventh PMOS switch is connected to the drain of the eleventh NMOS switch, and the drain of the twelfth PMOS switch is connected to the drain of the twelfth NMOS switch; the source of the eleventh NMOS switch and the source of the twelfth NMOS switch are grounded through the tenth NMOS switch.

[0036] The gate of the tenth PMOS switch receives the mode selection signal, and the gate of the tenth NMOS switch receives the mode selection signal through the NOT gate.

[0037] The high-side positive terminal is connected between the drain of the eleventh PMOS switch and the drain of the eleventh NMOS switch, and the high-side inverting terminal is connected between the drain of the twelfth PMOS switch and the drain of the twelfth NMOS switch.

[0038] In some embodiments, the drive integration circuit further includes a thirteenth PMOS switch, a fourteenth PMOS switch, a fifteenth PMOS switch, a thirteenth NMOS switch, a fourteenth NMOS switch, a fifteenth NMOS switch, a sixteenth NMOS switch, and a seventeenth NMOS switch;

[0039] The source of the thirteenth PMOS switch is connected to the driving power supply; the drain of the thirteenth PMOS switch is connected to the sources of the eleventh PMOS switch and the twelfth PMOS switch; the gate of the thirteenth PMOS switch is connected to the gate of the fourteenth PMOS switch; the source of the fourteenth PMOS switch is connected to the driving power supply; and the drain of the fourteenth PMOS switch is connected to the drain of the fourteenth NMOS switch. The drain of the thirteenth NMOS switch is connected to the sources of the eleventh NMOS switch and the twelfth NMOS switch; the source of the thirteenth NMOS switch is grounded; and the gate of the thirteenth NMOS switch is connected to the gate of the fourteenth NMOS switch. The source of the fourteenth NMOS switch is grounded.

[0040] The gate of the fifteenth PMOS switch receives the mode selection signal, the source of the fifteenth PMOS switch is connected to the driving power supply, and the drain of the fifteenth PMOS switch is connected to the gates of the thirteenth PMOS switch and the fourteenth PMOS switch; the gate of the fifteenth NMOS switch receives the mode selection signal through a NOT gate, the source of the fifteenth NMOS switch is grounded, and the drain of the fifteenth NMOS switch is connected to the gates of the thirteenth NMOS switch and the fourteenth NMOS switch;

[0041] The gate of the sixteenth NMOS switch is connected to the gate of the fourteenth NMOS switch, the source of the sixteenth NMOS switch is grounded, the drain of the sixteenth NMOS switch is connected to the source of the seventeenth NMOS switch, the drain of the seventeenth NMOS switch is connected to the driving power supply, and the gate of the seventeenth NMOS switch receives a mode selection signal.

[0042] Secondly, this application provides a communication module, including the data transmission circuit described in the first aspect.

[0043] The data transmission circuit and communication module provided by the present invention have at least the following technical effects:

[0044] 1) This solution can integrate both voltage-type and current-type TX driving modes on a single chip, allowing users to switch flexibly according to their needs, thereby improving the applicability of the product;

[0045] 2) By adding a current limiting module, this solution can reduce the risk of internal components burning out due to abnormal short circuits in external hardware when using current-type drives;

[0046] 3) This solution, by adding a capacitive coupling circuit, can avoid the distortion of the two-wire signals caused by changes in the drive current, thereby reducing the impact of parasitic capacitance;

[0047] 4) This solution integrates the current-mode drive circuit and the voltage-mode drive circuit, and shares some components, which can reduce the size of the components and the area of ​​the module, making the chip applicable to more application scenarios. Attached Figure Description

[0048] The preferred embodiments will now be described in a clear and easy-to-understand manner, with reference to the accompanying drawings, to further explain the above-mentioned characteristics, technical features, advantages, and implementation methods of this solution.

[0049] Figure 1 This is a schematic diagram of the structure of a voltage-mode driving circuit according to an embodiment of the present invention;

[0050] Figure 2 This is a schematic diagram of the structure of a current-mode drive circuit according to an embodiment of the present invention;

[0051] Figure 3 This is a schematic diagram of the current-mode drive circuit according to another embodiment of the present invention;

[0052] Figure 4 This is a schematic diagram of the structure of a capacitive coupling circuit according to an embodiment of the present invention;

[0053] Figure 5 This is a schematic diagram of the structure of a drive integrated circuit according to an embodiment of the present invention. Detailed Implementation

[0054] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the specific implementation methods of the present invention will be described below with reference to the accompanying drawings. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings and other implementation methods can be obtained based on these drawings without any creative effort.

[0055] To keep the drawings concise, only the parts relevant to the invention are shown schematically in each figure, and they do not represent the actual structure of the product. Furthermore, for ease of understanding, in some figures, only one of components with the same structure or function is shown schematically, or only one is labeled. In this document, "one" can mean not only "only one" but also "more than one".

[0056] To reduce costs, lithium battery monitoring chips in a BMS typically use a cascaded approach for data transmission, thereby enabling monitoring and protection of the battery pack's operating status. The MCU communicates with a relay chip via a four-wire SPI interface. The relay chip converts the four-wire SPI signal into a two-wire differential signal, which is then cascaded with other battery monitoring chips via twisted-pair cables for signal transmission. A common communication module includes three parts: RX (receiver), TX (transmitter), and Digital (digital processing). RX resolves the two-wire twisted-pair signal into +1 or -1 signals, which are then restored to a four-wire signal by the Digital module. TX converts the +1 or -1 signal back into a two-wire signal.

[0057] The transmission signal (TX) is divided into two types: voltage-type and current-type. The current-type TX outputs a differential AC current source with high output impedance, a cleaner signal waveform, and more controllable edges. The voltage-type TX outputs a voltage signal with low output impedance and stronger driving capability. However, existing current-type and voltage-type TX structures are independent, making it impossible to combine the advantages of both on a single chip, thus limiting application scenarios. Therefore, this solution provides a data transmission circuit that integrates both voltage-type and current-type TX driver circuits, allowing users to switch between the two driving modes via registers. The following is a detailed description of this solution with reference to the accompanying drawings:

[0058] In one embodiment, this application provides a data transmission circuit, including a current-mode drive circuit and a voltage-mode drive circuit. The current-mode drive circuit is configured to turn on when receiving a first mode selection signal and turn off when receiving a second mode selection signal; the voltage-mode drive circuit is configured to turn off when receiving the first mode selection signal and turn off when receiving the second mode selection signal, thereby enabling the selection of the current-mode drive circuit and the voltage-mode drive circuit according to usage requirements. In this embodiment, the first mode selection signal is 1, and the second mode selection signal is 0. The switching between the first mode selection signal and the second mode selection signal can be implemented through a register.

[0059] The current-mode drive circuit includes two sets of current-mode semiconductor switching elements. When a +1 signal is generated, a first control signal controls the first set of current-mode semiconductor switching elements to open, generating a first positive differential voltage between the high-side positive and high-side inverting terminals. When a -1 signal is generated, a second control signal controls the second set of current-mode semiconductor switching elements to open, generating a first negative differential voltage between the high-side positive and high-side inverting terminals. The semiconductor switching elements include PMOS switches, NMOS switches, etc., and this application is not limited thereto.

[0060] The voltage-mode drive circuit includes two voltage-mode semiconductor switching elements. When the drive generates a +1 signal, the first voltage-mode semiconductor switching element is turned on by a first control signal, so that a second positive differential voltage is generated between the high-side positive terminal and the high-side inverting terminal. When the drive generates a -1 signal, the second voltage-mode semiconductor switching element is turned on by a second control signal, so that a second negative differential voltage is generated between the high-side positive terminal and the high-side inverting terminal.

[0061] In one embodiment, refer to the appendix to the specification. Figure 1 The voltage-mode drive circuit includes a first PMOS switch (PM1), a second PMOS switch (PM2), a first NMOS switch (NM1), and a second NMOS switch (NM2). The gate of the first PMOS switch (PM1) receives the mode selection signal MOD, and the gate of the second NMOS switch (NM2) receives the mode selection signal MOD via a NOT gate. The second PMOS switch (PM2) is the first voltage-mode semiconductor switching element, and the first NMOS switch (NM1) is the second voltage-mode semiconductor switching element. The gates of the second PMOS switch (PM2) and the first NMOS switch (NM1) are used to receive the first control signal CTR_P and the second control signal CTR_N. The source of the first PMOS switch (PM1) is connected to the drive power supply, and its drain is connected to the source of the second PMOS switch (PM2). The drain of the second PMOS switch (PM2) is connected to the drain of the first NMOS switch (NM1). The source of the first NMOS switch (NM1) is connected to the drain of the second NMOS switch (NM2). The source of the second NMOS switch (NM2) is grounded. The high-side positive terminal HP and the high-side negative terminal HN are connected between the drain of the second PMOS switch (PM2) and the drain of the first NMOS switch (NM1).

[0062] The voltage-mode drive circuit also includes an OR gate and a first NOR gate; the transmission terminals of the first control signal CTR_P and the second control signal CTR_N are connected to the first input terminal of the OR gate through the NOT gate, the second input terminal of the OR gate is used to receive the IDLE signal, and the output terminal of the OR gate is connected to the gate of the second PMOS switch (PM2). The transmission terminals of the first control signal CTR_P and the second control signal CTR_N are also connected to the first input terminal of the first NOR gate, the second input terminal of the first NOR gate is used to receive the IDLE signal, and the output terminal of the first NOR gate is connected to the gate of the first NMOS switch (NM1).

[0063] The high-side positive terminal HP and the high-side inverting terminal HN are connected between the drain of the second PMOS switch and the drain of the first NMOS switch through the first transmission gate. The enable terminal and the inverting enable terminal of the first transmission gate are used to receive the mode selection signal MOD and the non-signal MOD_B of the mode selection signal, respectively, so that the first transmission gate is closed when the mode selection signal is the first mode selection signal, thereby achieving voltage-mode isolation and preventing it from interfering with the current-mode drive circuit.

[0064] When the mode selection signal MOD is 1, corresponding to the first mode selection signal, the voltage mode section is turned off through PM1 and NM2, and the current mode drive circuit operates normally. When the mode selection signal MOD is 0, corresponding to the second mode selection signal, the voltage mode operating mode is selected. When IDLE is 1, PM2 and NM1 are turned off, and HP and HN are high impedance. When IDLE is 0 and the drive generates a +1 signal, HP is pulled up to the power supply VDD through PM1 and PM2, and HN is pulled down to GND through NM1 and NM2. The differential voltage between HP and HN is VDD; conversely, when -1 is generated, the differential voltage is -VDD.

[0065] In one embodiment, refer to the appendix to the specification. Figure 2 The current-mode drive circuit includes a third PMOS switch (PM3), a fourth PMOS switch (PM4), a fifth PMOS switch (PM5), a third NMOS switch (NM3), a fourth NMOS switch (NM4), and a fifth NMOS switch (NM5). The first group of current-mode semiconductor switching elements includes the fourth PMOS switch (PM4) and the fifth NMOS switch (NM5). The transmission terminal of the first control signal CTR_P is connected to the gate of the fourth PMOS switch (PM4) via a NOT gate, and the transmission terminal of the first control signal CTR_P is connected to the gate of the fifth NMOS switch (NM5). The second group of current-mode semiconductor switching elements includes the fifth PMOS switch (PM5) and the fourth NMOS switch (NM4). The transmission terminal of the second control signal CTR_N is connected to the gate of the fifth PMOS switch (PM5) via a NOT gate, and the transmission terminal of the second control signal CTR_N is connected to the gate of the fourth NMOS switch (NM4).

[0066] The source of the fourth PMOS switch (PM4) and the source of the fifth PMOS switch (PM5) are connected to the drive power supply through the third PMOS switch (PM3); the drain of the fourth PMOS switch (PM4) is connected to the drain of the fourth NMOS switch (NM4), and the drain of the fifth PMOS switch (PM5) is connected to the drain of the fifth NMOS switch (NM5); the source of the fourth NMOS switch (NM4) and the source of the fifth NMOS switch (NM5) are grounded through the third NMOS switch (NM3).

[0067] The gate of the third PMOS switch (PM3) receives the mode selection signal MOD through the NOT gate, and the gate of the third NMOS switch (NM3) receives the mode selection signal MOD through the NOT gate. This allows the current-mode drive circuit to be turned off through the MOS switches PM3 and NM3 when MOD is 0 and selects the voltage-mode operating mode, and to be turned on when MOD is 1 and selects the current-mode operating mode.

[0068] The high-side positive terminal HP is connected between the drain of the fourth PMOS switch (PM4) and the drain of the fourth NMOS switch (NM4), and the high-side inverting terminal HN is connected between the drain of the fifth PMOS switch (PM5) and the drain of the fifth NMOS switch (NM5).

[0069] In some specific implementations, the high-side positive input HP is connected between the drain of the fourth PMOS switch (PM4) and the drain of the fourth NMOS switch (NM4) through the second transmission gate, and the high-side inverting input HN is connected between the drain of the fifth PMOS switch (PM5) and the drain of the fifth NMOS switch (NM5) through the third transmission gate. The enable terminals of the second and third transmission gates receive the mode selection signal MOD, and the inverting enable terminals of the second and third transmission gates receive the non-signal MOD_B of the mode selection signal, so that the second and third transmission gates are turned off when the mode selection signal is the second mode selection signal, thereby achieving current-mode isolation and preventing it from interfering with the voltage-mode drive circuit.

[0070] When the mode selection signal MOD is 1, the current mode part works normally. When the driver generates a +1 signal, PM4 and NM5 are turned on, and the IB large and small circuits flow through HP to the external resistor and then to HN to generate an IB*R differential voltage. When the driver generates a -1 signal, PM5 and NM4 are turned on, and the IB large and small circuits flow through HN to the external resistor and then to HP to generate a -IB*R differential voltage.

[0071] Considering that when HP or HN short-circuits to ground due to a fault, a large short-circuit current will be generated due to the non-current-limiting circuit in the current-mode drive circuit. Therefore, this solution allows for further adjustments to the current-mode drive circuit. For some specific implementation methods, please refer to the appendix of the instruction manual. Figure 3 The current-mode drive circuit also includes a sixth PMOS switch (PM6), a seventh PMOS switch (PM7), a sixth NMOS switch (NM6), a seventh NMOS switch (NM7), and an eighth NMOS switch (NM8).

[0072] The drain of the sixth PMOS switch (PM6) is connected to the source of the third PMOS switch (PM3), the source of the sixth PMOS switch (PM6) is connected to the driving power supply, and the gate of the sixth PMOS switch (PM6) is connected to the gate of the seventh PMOS switch (PM7). The drain of the sixth NMOS switch (NM6) is connected to the source of the third NMOS switch (NM3), the source of the sixth NMOS switch (NM6) is grounded, and the gate of the sixth PMOS switch (NM6) is connected to the gate of the seventh NMOS switch (NM7). The gate of the seventh PMOS switch (PM7) is also connected to the drain of the seventh NMOS switch (NM7), the source of the seventh PMOS switch (PM7) is connected to the driving power supply, and the source of the seventh NMOS switch (NM7) is grounded. The gate of the eighth NMOS switch (NM8) is connected to the gate of the seventh NMOS switch (NM7), the drain of the eighth NMOS switch (NM8) is connected to the driving power supply, and the source of the eighth NMOS switch (NM8) is grounded.

[0073] This solution adds a tail current source PM6 to the top of PM3. When PM6=PM7 and NM8=NM7=NM6, the maximum short-circuit current is IB. By adding a current limiting module, this solution can reduce the risk of internal component burnout due to abnormal short circuits in external hardware when using current-type drives. Additionally, to save power, the aspect ratio between PM6 and PM7, and between NM8 and NM7 / NM6, can be appropriately increased.

[0074] To ensure compatibility with 3.3V power supply voltage applications and to appropriately increase the differential voltage between HP and HN, the drive current is often relatively large. Therefore, to ensure the circuit operates in the correct operating region, Figure 3 The PM3-PM6 and NM3-NM6 transistors are typically large. Larger MOSFET sizes introduce more parasitic capacitance. When PM4 and NM5 are on, or PM5 and NM4 are on, the parasitic capacitance causes the VBN (NMOS gate) voltage to rise and the VBP (PMOS gate) voltage to fall. Conversely, when PM4 and NM5 are off, or PM5 and NM4 are off, the parasitic capacitance causes the VBN voltage to fall and the VBP voltage to rise. These changes in VBN and VBP voltages lead to changes in the drive current, resulting in signal distortion between the two wires. To address this issue, some specific implementations are described in the appendix of the instruction manual. Figure 4 The current-mode drive circuit of this application also includes a capacitive coupling circuit.

[0075] The capacitively coupled circuit includes a second NOR gate and a third NOR gate. The first input of the second NOR gate is connected to the positive terminal POS of the circuit via an NOT gate, and the second input of the second NOR gate is connected to the negative terminal NEG of the circuit. The output of the second NOR gate is connected between the sixth PMOS switch (PM6) and the seventh PMOS switch (PM7) via a first circuit, and also between the sixth NMOS switch (NM6) and the seventh NMOS switch (NM7) via a second circuit. The first circuit includes two NOT gates connected in series and a capacitor. The second circuit includes three NOT gates connected in series and a capacitor. The first input of the third NOR gate is connected to the positive terminal POS of the circuit, and the second input of the second NOR gate is connected to the negative terminal NEG of the circuit via an NOT gate. The output of the third NOR gate is connected between the sixth PMOS switch (PM6) and the seventh PMOS switch (PM7) via a third circuit, and also between the sixth NMOS switch (NM6) and the seventh NMOS switch (NM7) via a fourth circuit. The third circuit includes two NOT gates connected in series and a capacitor. The fourth circuit includes three NOT gates connected in series and a capacitor. When a +1 signal needs to be generated, POS becomes 1, NEG remains 0, and after passing through a NOR gate and inverter unit CTR_P, VBP_F becomes 1, VBN_F becomes 0. After capacitive coupling, VBP rises and VBN falls, and... Figure 3 The parasitic capacitance has an opposite effect, thus reducing its influence. A similar effect is achieved when the driver generates a -1 signal.

[0076] In one embodiment, refer to the appendix to the specification. Figure 5 Some components of the current-mode drive circuit and the voltage-mode drive circuit are shared to form an integrated drive circuit. The integrated drive circuit includes the tenth PMOS switch (PM10), the eleventh PMOS switch (PM11), the twelfth PMOS switch (PM12), the tenth NMOS switch (NM10), the eleventh NMOS switch (NM11), and the twelfth NMOS switch (NM12).

[0077] The transmission terminal of the first control signal CTR_P is connected to the gate of the eleventh PMOS switch (PM11) through a NOT gate, and the transmission terminal of the first control signal CTR_P is connected to the gate of the twelfth NMOS switch (NM12); the transmission terminal of the second control signal CTR_N is connected to the gate of the twelfth PMOS switch (PM12) through a NOT gate, and the transmission terminal of the second control signal CTR_N is connected to the gate of the eleventh NMOS switch (NM11). The source of the eleventh PMOS switch (PM11) and the source of the twelfth PMOS switch (PM12) are connected to the drive power supply through the tenth PMOS switch (PM10); the drain of the eleventh PMOS switch (PM11) is connected to the drain of the eleventh NMOS switch (NM11), and the drain of the twelfth PMOS switch (PM12) is connected to the drain of the twelfth NMOS switch (NM12); the source of the eleventh NMOS switch (NM11) and the source of the twelfth NMOS switch (NM12) are grounded through the tenth NMOS switch (NM10).

[0078] The gate receive mode selection signal MOD of the tenth PMOS switch (PM10) and the gate receive mode selection signal MOD of the tenth NMOS switch (NM10) via a NOT gate. The high-side positive input HP is connected between the drain of the eleventh PMOS switch (PM11) and the drain of the eleventh NMOS switch (NM11), and the high-side inverting input HN is connected between the drain of the twelfth PMOS switch (PM12) and the drain of the twelfth NMOS switch (NM12).

[0079] In some specific implementations, the drive integrated circuit also includes a thirteenth PMOS switch (PM13), a fourteenth PMOS switch (PM14), a fifteenth PMOS switch (PM15), a thirteenth NMOS switch (NM13), a fourteenth NMOS switch (NM14), a fifteenth NMOS switch (NM15), a sixteenth NMOS switch (NM16), and a seventeenth NMOS switch (NM17).

[0080] The source of the thirteenth PMOS switch (PM13) is connected to the drive power supply. The drain of the thirteenth PMOS switch (PM13) is connected to the source of the eleventh PMOS switch (PM11) and the twelfth PMOS switch (PM12). The gate of the thirteenth PMOS switch (PM13) is connected to the gate of the fourteenth PMOS switch (PM14). The source of the fourteenth PMOS switch (PM14) is connected to the drive power supply. The drain of the fourteenth PMOS switch (PM14) is connected to the drain of the fourteenth NMOS switch (NM14). The drain of the thirteenth NMOS switch (NM13) is connected to the source of the eleventh NMOS switch (NM11) and the twelfth NMOS switch (NM12). The source of the thirteenth NMOS switch (NM13) is grounded. The gate of the thirteenth NMOS switch (NM13) is connected to the gate of the fourteenth NMOS switch (NM14). The source of the fourteenth NMOS switch (NM14) is grounded.

[0081] The gate of the fifteenth PMOS switch (PM15) receives the mode selection signal, the source of the fifteenth PMOS switch (PM15) is connected to the drive power supply, and the drain of the fifteenth PMOS switch (PM15) is connected to the gates of the thirteenth PMOS switch (PM13) and the fourteenth PMOS switch (PM14). The gate of the fifteenth NMOS switch (NM15) receives the mode selection signal through an NOT gate, the source of the fifteenth NMOS switch (NM15) is grounded, and the drain of the fifteenth NMOS switch (NM15) is connected to the gates of the thirteenth NMOS switch (NM13) and the fourteenth NMOS switch (NM14).

[0082] The gate of the sixteenth NMOS switch (NM16) is connected to the gate of the fourteenth NMOS switch (NM14), the source of the sixteenth NMOS switch (NM16) is grounded, the drain of the sixteenth NMOS switch (NM16) is connected to the source of the seventeenth NMOS switch (NM17), the drain of the seventeenth NMOS switch (NM17) is connected to the drive power supply, and the gate of the seventeenth NMOS switch (NM17) receives the mode selection signal.

[0083] This scheme still uses the MOD signal to achieve mode switching. PM11, NM12, and PM12, NM11 are shared switches for voltage and current mode drive circuits. When MOD is 1, the current mode drive circuit is selected, and its working principle is the same as... Figure 2The results are largely the same. When MOD is 0, a voltage-mode drive circuit is used. PM10 and NM10 short-circuit the tail current sources PM13 and NM13, while PM15 pulls up VBP and NM15 pulls down VBN to reduce module power consumption. When the drive generates +1, PM11 turns on, HP is pulled up to VDD, NM12 turns on, and HN is pulled down to 0, with the differential voltage between HP and HN being VDD. When the drive generates -1, PM12 turns on, HN is pulled up to VDD, NM11 turns on, and HP is pulled down to 0, with the differential voltage between HP and HN being -VDD.

[0084] In one embodiment, based on the foregoing embodiments, this application also provides a communication module, including the data transmission circuit of the foregoing embodiments.

[0085] The data transmission circuit and communication module provided by this invention have at least the following technical effects:

[0086] 1) This solution can integrate both voltage-type and current-type TX driving modes on a single chip, allowing users to switch flexibly according to their needs, thereby improving the applicability of the product;

[0087] 2) By adding a current limiting module, this solution can reduce the risk of internal components burning out due to abnormal short circuits in external hardware when using current-type drives;

[0088] 3) This solution, by adding a capacitive coupling circuit, can avoid the distortion of the two-wire signals caused by changes in the drive current, thereby reducing the impact of parasitic capacitance;

[0089] 4) This solution integrates the current-mode drive circuit and the voltage-mode drive circuit, and shares some components, which can reduce the size of the components and the area of ​​the module, making the chip applicable to more application scenarios.

[0090] It should be noted that the above embodiments can be freely combined as needed. The above description is only a preferred embodiment of the present invention. It should be pointed out that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A data transmission circuit, characterized by The application relates to a current-mode drive circuit and a voltage-mode drive circuit. The current-mode drive circuit is configured to be turned on when a first mode selection signal is received and turned off when a second mode selection signal is received. The voltage-mode drive circuit is configured to be turned off when the first mode selection signal is received and turned on when the second mode selection signal is received. The current-mode drive circuit comprises two groups of current-mode semiconductor switching elements, and when a +1 signal is driven, a first group of current-mode semiconductor switching elements is controlled to be turned on by a first control signal, so that a first positive differential voltage is generated between a high-side non-inverting terminal and a high-side inverting terminal. When a -1 signal is driven, a second group of current-mode semiconductor switching elements is controlled to be turned on by a second control signal, so that a first negative differential voltage is generated between the high-side non-inverting terminal and the high-side inverting terminal. The voltage-mode drive circuit comprises two voltage-mode semiconductor switching elements, and when the +1 signal is driven, a first voltage-mode semiconductor switching element is controlled to be turned on by the first control signal, so that a second positive differential voltage is generated between the high-side non-inverting terminal and the high-side inverting terminal; when the -1 signal is driven, a second voltage-mode semiconductor switching element is controlled to be turned on by the second control signal, so that a second negative differential voltage is generated between the high-side non-inverting terminal and the high-side inverting terminal. Part of components of the current-mode drive circuit and the voltage-mode drive circuit are shared to form a drive integrated circuit. The drive integrated circuit comprises a tenth PMOS switch, an eleventh PMOS switch, a twelfth PMOS switch, a tenth NMOS switch, an eleventh NMOS switch and a twelfth NMOS switch. A transmission end of the first control signal is connected to a gate of the eleventh PMOS switch through a NOT gate, and the transmission end of the first control signal is connected to a gate of the twelfth NMOS switch; a transmission end of the second control signal is connected to a gate of the twelfth PMOS switch through a NOT gate, and the transmission end of the second control signal is connected to a gate of the eleventh NMOS switch. A source of the eleventh PMOS switch and a source of the twelfth PMOS switch are connected to a driving power supply through the tenth PMOS switch; a drain of the eleventh PMOS switch is connected to a drain of the eleventh NMOS switch, and a drain of the twelfth PMOS switch is connected to a drain of the twelfth NMOS switch; a source of the eleventh NMOS switch and a source of the twelfth NMOS switch are grounded through the tenth NMOS switch. A gate of the tenth PMOS switch receives a mode selection signal, and a gate of the tenth NMOS switch receives the mode selection signal through a NOT gate. The high-side non-inverting terminal is connected between the drain of the eleventh PMOS switch and the drain of the eleventh NMOS switch, and the high-side inverting terminal is connected between the drain of the twelfth PMOS switch and the drain of the twelfth NMOS switch. The voltage-mode drive circuit comprises a first PMOS switch, a second PMOS switch, a first NMOS switch and a second NMOS switch.

2. The data transmission circuit of claim 1, wherein, ​ The gate of the first PMOS switch receives a mode selection signal, and the gate of the second NMOS switch receives the mode selection signal through a NOT gate; The second PMOS switch is the first voltage-mode semiconductor switching element, and the first NMOS switch is the second voltage-mode semiconductor switching element, and the gates of the second PMOS switch and the first NMOS switch are configured to receive the first control signal and the second control signal; The source of the first PMOS switch is connected to a driving power supply, and the drain of the first PMOS switch is connected to the source of the second PMOS switch; the drain of the second PMOS switch is connected to the drain of the first NMOS switch; and the source of the first NMOS switch is connected to the drain of the second NMOS switch; The source of the second NMOS switch is connected to ground; The high-side non-inverting terminal and the high-side inverting terminal are connected between the drain of the second PMOS switch and the drain of the first NMOS switch.

3. The data transmission circuit of claim 2, wherein, The voltage-mode driving circuit further comprises an OR gate and a first NOR gate; The transmission end of the first control signal and the transmission end of the second control signal are connected to the first input end of the OR gate through a NOT gate, the second input end of the OR gate is configured to receive an IDLE signal, and the output end of the OR gate is connected to the gate of the second PMOS switch; The transmission end of the first control signal and the transmission end of the second control signal are also connected to the first input end of the first NOR gate, the second input end of the first NOR gate is configured to receive the IDLE signal, and the output end of the first NOR gate is connected to the gate of the first NMOS switch; The high-side non-inverting terminal and the high-side inverting terminal are connected between the drain of the second PMOS switch and the drain of the first NMOS switch through a first transmission gate, the enable end and the inverse enable end of the first transmission gate are configured to receive the mode selection signal and the non-signal of the mode selection signal respectively, so that the first transmission gate is closed when the mode selection signal is the first mode selection signal.

4. The data transmission circuit of claim 1, wherein, The current-mode driving circuit comprises a third PMOS switch, a fourth PMOS switch, a fifth PMOS switch, a third NMOS switch, a fourth NMOS switch and a fifth NMOS switch; The first group of current-mode semiconductor switching elements comprises the fourth PMOS switch and the fifth NMOS switch, the transmission end of the first control signal is connected to the gate of the fourth PMOS switch through a NOT gate, and the transmission end of the first control signal is connected to the gate of the fifth NMOS switch; The second group of current-mode semiconductor switching elements comprises the fifth PMOS switch and the fourth NMOS switch, the transmission end of the second control signal is connected to the gate of the fifth PMOS switch through a NOT gate, and the transmission end of the second control signal is connected to the gate of the fourth NMOS switch; The source of the fourth PMOS switch and the source of the fifth PMOS switch are connected to a driving power source through the third PMOS switch; the drain of the fourth PMOS switch is connected to the drain of the fourth NMOS switch, and the drain of the fifth PMOS switch is connected to the drain of the fifth NMOS switch; the source of the fourth NMOS switch and the source of the fifth NMOS switch are grounded through the third NMOS switch; The gate of the third PMOS switch receives a mode selection signal through a NOT gate, and the gate of the third NMOS switch receives the mode selection signal; The high-side non-inverting terminal is connected between the drain of the fourth PMOS switch and the drain of the fourth NMOS switch, and the high-side inverting terminal is connected between the drain of the fifth PMOS switch and the drain of the fifth NMOS switch.

5. The data transmission circuit of claim 4, wherein, The high-side non-inverting terminal is connected between the drain of the fourth PMOS switch and the drain of the fourth NMOS switch through a second transmission gate, and the high-side inverting terminal is connected between the drain of the fifth PMOS switch and the drain of the fifth NMOS switch through a third transmission gate, The enable terminals of the second transmission gate and the third transmission gate receive the mode selection signal, and the inverse enable terminals of the second transmission gate and the third transmission gate receive a non-signal of the mode selection signal, so that the second transmission gate and the third transmission gate are closed when the mode selection signal is the second mode selection signal.

6. The data transmission circuit of claim 5, wherein, The current mode driving circuit further comprises a sixth PMOS switch, a seventh PMOS switch, a sixth NMOS switch, a seventh NMOS switch and an eighth NMOS switch, The drain of the sixth PMOS switch is connected to the source of the third PMOS switch, the source of the sixth PMOS switch is connected to the driving power source, and the gate of the sixth PMOS switch is connected to the gate of the seventh PMOS switch; the drain of the sixth NMOS switch is connected to the source of the third NMOS switch, the source of the sixth NMOS switch is grounded, and the gate of the sixth PMOS switch is connected to the gate of the seventh NMOS switch; the gate of the seventh PMOS switch is also connected to the drain of the seventh NMOS switch, the source of the seventh PMOS switch is connected to the driving power source, and the source of the seventh NMOS switch is grounded; The gate of the eighth NMOS switch is connected to the gate of the seventh NMOS switch, the drain of the eighth NMOS switch is connected to the driving power source, and the source of the eighth NMOS switch is grounded.

7. The data transmission circuit of claim 6, wherein, The current mode driving circuit further comprises a capacitor coupling circuit, and the capacitor coupling circuit comprises a second OR NOT gate and a third OR NOT gate, The first input end of the second NOR gate is connected with the positive pole of the circuit through a NOR gate connection circuit, the second input end of the second NOR gate is connected with the negative pole of the circuit, the output end of the second NOR gate is connected between the sixth PMOS switch and the seventh PMOS switch through a first circuit, and the output end of the second NOR gate is also connected between the sixth NMOS switch and the seventh NMOS switch through a second circuit; the first circuit comprises two NOR gates and a capacitor connected in series, and the second circuit comprises three NOR gates and a capacitor connected in series. The first input end of the third NOR gate is connected with the positive pole of the circuit, the second input end of the second NOR gate is connected with the negative pole of the circuit through a NOR gate, the output end of the third NOR gate is connected between the sixth PMOS switch and the seventh PMOS switch through a third circuit, and the output end of the third NOR gate is also connected between the sixth NMOS switch and the seventh NMOS switch through a fourth circuit; the third circuit comprises two NOR gates and a capacitor connected in series, and the fourth circuit comprises three NOR gates and a capacitor connected in series.

8. The data transmission circuit of claim 1, wherein, The driving integrated circuit further comprises a thirteenth PMOS switch, a fourteenth PMOS switch, a fifteenth PMOS switch, a thirteenth NMOS switch, a fourteenth NMOS switch, a fifteenth NMOS switch, a sixteenth NMOS switch and a seventeenth NMOS switch; The source of the thirteenth PMOS switch is connected with the driving power supply, the drain of the thirteenth PMOS switch is connected with the source of the eleventh PMOS switch and the twelfth PMOS switch, the gate of the thirteenth PMOS switch is connected with the gate of the fourteenth PMOS switch, the source of the fourteenth PMOS switch is connected with the driving power supply, and the drain of the fourteenth PMOS switch is connected with the drain of the fourteenth NMOS switch. The drain of the thirteenth NMOS switch is connected with the source of the eleventh NMOS switch and the twelfth NMOS switch, the source of the thirteenth NMOS switch is grounded, and the gate of the thirteenth NMOS switch is connected with the gate of the fourteenth NMOS switch; the source of the fourteenth NMOS switch is grounded. The gate of the fifteenth PMOS switch receives a mode selection signal, the source of the fifteenth PMOS switch is connected with the driving power supply, and the drain of the fifteenth PMOS switch is connected with the gates of the thirteenth PMOS switch and the fourteenth PMOS switch; the gate of the fifteenth NMOS switch receives the mode selection signal through a NOR gate, the source of the fifteenth NMOS switch is grounded, and the drain of the fifteenth NMOS switch is connected with the gates of the thirteenth NMOS switch and the fourteenth NMOS switch. A gate of the sixteenth NMOS switch is connected to a gate of the fourteenth NMOS switch, a source of the sixteenth NMOS switch is grounded, a drain of the sixteenth NMOS switch is connected to a source of the seventeenth NMOS switch, a drain of the seventeenth NMOS switch is connected to the driving power source, and a gate of the seventeenth NMOS switch receives a mode selection signal.

9. A communications module, characterized by A data transmission circuit comprising the data transmission circuit of any one of claims 1 to 8.

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