Dual-redundancy signal interlocking logic conversion circuit
By employing the inverse logic design and dual-redundancy design of the dual-redundancy signal interlocking logic conversion circuit, the problem of false triggering caused by the absence of upstream devices in aviation interlocking control was solved, achieving higher safety and reliability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-31
- Publication Date
- 2026-03-27
AI Technical Summary
In existing aviation interlocking control systems, the absence of upstream devices can easily lead to false triggering of downstream devices, thereby compromising the safety and reliability of the control process.
A dual-redundant signal interlocking logic conversion circuit is adopted, including an interface input conversion circuit, a logic voting circuit, a drive circuit, and a relay circuit. Through inverse logic design and dual-redundant design, it is ensured that the preceding logic is normally open and the logic after action is closed. The signal conversion is locked in conjunction with the logic voting circuit to avoid false triggering.
This improves the safety and reliability of the interlocking control process, avoids false triggering of downstream devices when upstream devices are absent, and enhances the reliability and safety of the circuit.
Smart Images
Figure CN121749974A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of aviation, and more particularly to a dual-redundant signal interlocking logic conversion circuit. Background Technology
[0002] In interlocking control, existing technologies typically trigger the action of subsequent devices by the action of the preceding device. However, since the preceding logic is normally closed and becomes open after the action, the absence of the preceding device can easily cause the subsequent device to be falsely triggered. This can lead to false triggering in the control process of aviation interlocking control, thereby compromising the safety and reliability of the control process. Summary of the Invention
[0003] To address the lack of security in existing aviation interlocking control processes, this invention provides a dual-redundant signal interlocking logic conversion circuit to improve the safety and reliability of the control process.
[0004] Therefore, the technical solution adopted by the present invention is as follows: A dual-redundant signal interlocking logic conversion circuit is provided, which includes an interface input conversion circuit, a logic voting circuit, a drive circuit, and a relay circuit. The interface input conversion circuit includes multiple sets of input / output interface chips. Each set of input / output interface chips outputs two outputs, and each output is connected to one input of the logic voting circuit. Each input of the logic voting circuit corresponds to one output, and each output is connected to one input of the driver circuit. Each input terminal of the drive circuit corresponds to one output terminal, and the multiple output terminals are connected to one input terminal of the relay circuit. The action signal input interface conversion circuit converts one input voltage into four TTL level outputs based on the action signal. The TTL level and external control signal are input to the logic voting circuit. The logic voting circuit outputs the corresponding level to the drive circuit based on the input TTL level and the external control signal. The drive circuit outputs the drive signal based on the input level, thereby driving the corresponding relay circuit to output the logically converted off-position signal.
[0005] According to the above scheme, the logic conversion circuit adopts a dual-redundancy design, which is specifically implemented by designing two sets of independent input interface chips in the interface input conversion circuit.
[0006] According to the above scheme, the logic voting circuit specifically includes four sets of AND gate chips, and each pair of AND gate chips is connected to the output port of an input interface chip.
[0007] According to the above scheme, the driving circuit specifically includes four groups of driving chips, and the input port of each group of driving chips is connected to the output port of an AND gate chip.
[0008] According to the above scheme, the relay circuit includes a combination of two or more electromagnetic relays and solid-state relays, with each set of electromagnetic relays and solid-state relays corresponding to a set of driver chips.
[0009] According to the above scheme, the logic truth value of the interface input conversion circuit is as follows: when the input / output interface chip select is 0, if the input is open, a high-level signal is output; if the input is a voltage power supply, a low-level signal is output. When the input / output interface chip select is 1, the chip outputs a high configuration when any signal is input.
[0010] According to the above scheme, the logical truth value of the logic voting circuit is as follows: when both the output signal of the interface input chip and the external control signal are input at a high level at the input terminal of the AND gate chip of the logic voting circuit, the AND gate chip outputs a high level; when at least one of the output signal of the interface input chip and the external control signal is input at a low level at the input terminal of the AND gate chip of the logic voting circuit, the AND gate chip outputs a low level.
[0011] According to the above scheme, each set of electromagnetic relays and solid-state relays is connected to the output port of a set of driver chips through resistors and transistors, and a normally closed detection data conversion device is connected between the electromagnetic relays and solid-state relays.
[0012] According to the above scheme, the input interface chip is specifically the HKA1300-PN / CQC chip.
[0013] A catapult device is also provided, which specifically utilizes a dual-redundant signal interlocking logic conversion circuit as described above. When the device is in a normal non-catapulting state, the action signal input voltage power supply is provided; when the device is in a catapult-delayed state, the action signal input is open.
[0014] The beneficial effects of this invention are as follows: By designing the output inverse logic of the interface input conversion circuit, this invention transforms the existing normally closed logic of the preceding stage and the open logic after the action into normally open logic of the preceding stage and the closed logic after the action. Furthermore, the logic voting circuit combines the output signal of the interface input conversion circuit and the external control signal to perform logic conversion locking, thereby controlling the interlocking action locking and outputting the departure signal after logic conversion and locking. This avoids the false triggering of the subsequent stage device when the preceding stage device is absent in the interlocking control, thus ensuring the safety of the interlocking control process.
[0015] Furthermore, the present invention uses an input / output interface chip of the interface input conversion circuit to output a high level when the input is open and a low level when the input is at normal operating voltage. This chip is connected to a logic voting circuit. The output level of the interface input conversion circuit and the external control signal are combined and logically converted by the AND gate chip of the logic voting circuit. When both the output level and the external control signal are high, the voting output is high, thereby closing the circuit when it is out of position, which increases the safety of the process of interlocking control using the circuit of the present invention.
[0016] Furthermore, this invention employs a dual-redundancy design, employing two sets of independent input / output interface chips. When one set of chip circuits fails, the other set of chip circuits can replace its function, thus avoiding overall circuit failure and improving the reliability and safety of the circuit. Attached Figure Description
[0017] Figure 1 This is a schematic diagram of the circuit structure of a dual-redundant signal interlocking logic conversion circuit according to an embodiment of the present invention. Detailed Implementation
[0018] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.
[0019] To address the issue of false triggering of downstream devices due to the absence of upstream devices in existing interlocking control technologies, this invention provides a dual-redundant signal interlocking logic conversion circuit, such as... Figure 1 As shown, the circuit includes: an interface input conversion circuit, a logic voting circuit, a drive circuit, and a relay circuit; wherein: The interface input conversion circuit includes multiple sets of input / output interface chips. Each set of input / output interface chips outputs two outputs, and each output is connected to one input of the logic voting circuit. Each input of the logic voting circuit corresponds to one output, and each output is connected to one input of the driver circuit. Each input terminal of the drive circuit corresponds to one output terminal, and the multiple output terminals are connected to one input terminal of the relay circuit. Specifically, the logic truth value of the interface input conversion circuit is as follows: when the input / output interface chip select is 0, if the input is open, a high-level signal is output; if the input is a voltage power supply, a low-level signal is output. When the input / output interface chip select is 1, the chip outputs a high configuration when any signal is input.
[0020] The action signal input interface conversion circuit converts one input voltage into four TTL level outputs based on the action signal. The TTL level and external control signal are input to the logic voting circuit. The logic voting circuit outputs the corresponding level to the drive circuit based on the input level and the external control signal. The drive circuit outputs the drive signal based on the input level, thereby driving the corresponding relay circuit to output the logically converted off-position signal.
[0021] Specifically, the logic voting circuit includes four sets of AND gate chips. The input terminals of every two sets of AND gate chips are connected to the output ports of an input interface chip, and external control signals are also input to the input terminals of each set of AND gate chips.
[0022] Specifically, the logical truth value of the logic voting circuit is as follows: when both the output signal of the interface input chip and the external control signal are input at a high level at the input terminal of the AND gate chip of the logic voting circuit, the AND gate chip outputs a high level; when at least one of the output signal of the interface input chip and the external control signal is input at a low level at the input terminal of the AND gate chip of the logic voting circuit, the AND gate chip outputs a low level.
[0023] Specifically, the driving circuit includes four sets of driving chips, and the input port of each set of driving chips is connected to the output port of an AND gate chip.
[0024] Specifically, the relay circuit includes a combination of two or more electromagnetic relays and solid-state relays, with each set of electromagnetic relays and solid-state relays corresponding to a set of input interface chips.
[0025] Specifically, in this embodiment, the relay circuit uses a combination of two sets of electromagnetic relays and solid-state relays, corresponding to two interface chips HKA1300-PN / CQC respectively. The normally open parts of the electromagnetic relays and solid-state relays are connected in series for output.
[0026] Specifically, the interface input conversion circuit adopts a dual-redundant design, including two sets of input / output interface chips. The input interface chip is specifically the HKA1300-PN / CQC. The output logic of the HKA1300-PN / CQC is all inverted logic. In SUPPLY / OPEN mode, the truth table for a low input is shown in Table 1. The interface input circuit converts one input into four outputs, which are respectively input to the two sets of input / output interface chips. The interface chips convert relatively high voltage levels to TTL level outputs.
[0027] Table 1 Truth Table of Input / Output Interface Chip Logic
[0028] Specifically, the logic voting circuit includes four sets of AND gate chips. The logic voting circuit adopts AND logic and is implemented using four AND gate chips. When all AND gate inputs are high, the output is high. The AND gate logic truth table is shown in Table 2. External control signals can be controlled through AND logic. Logic locking can be performed according to the control logic, and the interlocking action can be locked. When the control signal input is low, the logic does not change, thus realizing logic conversion locking.
[0029] Table 2 Truth Table for AND Gate Voting
[0030] In each group of electromagnetic relays and solid-state relays, the electromagnetic relays and solid-state relays are connected to the output ports of an input interface chip via resistors and transistors, respectively, and a normally closed detection data conversion device is connected between the electromagnetic relays and solid-state relays. In each combination of electromagnetic relays and solid-state relays, one drive chip output terminal is connected to the emitter and base of a first transistor via a first resistor and a second resistor, respectively, and the collector of the first transistor is connected to the electromagnetic relay; the other drive chip output terminal is connected to the emitter and base of a second transistor via a third resistor and a fourth resistor, respectively, and the collector of the second transistor is connected to the solid-state relay.
[0031] Specifically, under normal operating conditions, the enable signal of the input / output interface chip is L. When not converted, the signal input is normally closed, and becomes normally open after passing through the off-position signal logic conversion circuit. When converted, the off-position input is disconnected, and becomes closed after passing through the off-position signal logic conversion circuit. To ensure safety, in specific scenarios, the off-position output can be controlled to lock and remain in the normally open state. Alternatively, the off-position output can be controlled to become closed for BIT detection or forced output.
[0032] In addition, the present invention also provides an ejection device, which specifically utilizes a dual-redundant signal interlocking logic conversion circuit as described above, wherein when the device is in a normal non-ejection state, the action signal input voltage power supply is provided; when the device is in an ejection-out state, the action signal input is open.
[0033] Specifically, under normal operating conditions, the input / output interface chip enable signal is L, and the external control signal input is high. The ejection signal of the ejection device is used as the action signal input. When the device is in the normal non-ejection state, the action signal input voltage power supply is sent to the input / output interface chip, the input / output interface chip outputs a low level to the AND gate chip, and at the same time, the external control signal input is high. At this time, the AND gate chip of the logic voting circuit outputs a low level, and the input to the driver chip drives the relay circuit to output a normally open departure signal. When the device is in the ejection departure state, the action signal input is open to the input / output interface chip, the input / output interface chip outputs a high level to the AND gate chip of the logic voting circuit, and at the same time, the external control signal input is high. At this time, the AND gate chip of the logic voting circuit outputs a low level, and the input to the driver chip drives the relay circuit to output a closed departure signal.
[0034] Specifically, if the ejection signal of the ejection device is used as the action signal input, the output logic of the displacement signal is shown in Table 3: Table 3. Off-position signal output logic
[0035] The dual-redundant signal interlocking logic conversion circuit in this embodiment employs logic conversion via input / output interface chips and AND gate logic conversion. After software setup, it is implemented purely in hardware, resulting in fast response and the ability to detect circuit failures. The software-set output has a certain logic, and the circuit will only be set to be valid after a fault detection is normal. After setup, it becomes a purely hardware response circuit, making the circuit response speed faster. The input is split into four channels and then subjected to separate logic voting. After voting, it drives two heterogeneous relays, solid-state and electromagnetic, respectively. The circuit realizes the transition from high-voltage signal to weak-voltage control and then to high-voltage output isolation. Furthermore, it utilizes two co-current switches of the electromagnetic relays to achieve one channel for output and one channel for detection.
[0036] Furthermore, the AND gate logic input of the logic voting circuit adopts a pull-down method. The software will only run normally and output a high level after the power supply is normal and stable. Only then will the hardware circuit take effect, avoiding erroneous output caused by voltage instability. Moreover, the fault mode of the AND gate logic itself is to output a low level. When the circuit chip is damaged, it will not be driven, ensuring circuit safety. At the same time, the solid-state relay and electromagnetic relay are selected in normally open mode, which will also prevent false triggering and save current. The circuit design concept of this embodiment is to consider the idea of "better to fail than to output", so the circuit adopts a double redundancy design to ensure output safety.
[0037] This invention provides a dual-redundant signal interlocking logic conversion circuit. Through an interface input conversion circuit with inverse output logic design, and sequentially connected to a logic voting circuit, a drive circuit, and a relay circuit, it transforms the existing pre-stage logic (normally closed logic, open logic after action) into pre-stage logic (normally open logic, closed logic after action). Furthermore, the logic voting circuit combines the output signal of the interface input conversion circuit with external control signals to perform logic conversion locking, controlling the interlocking action locking, thereby outputting a departure signal after logic conversion and locking. This prevents the subsequent device from being falsely triggered when the pre-stage device is absent in the interlocking control, thus ensuring the safety of the interlocking control process.
[0038] Furthermore, the present invention uses an input / output interface chip of the interface input conversion circuit to output a high level when the input is open and a low level when the input is at normal operating voltage. This chip is connected to a logic voting circuit. The output level of the interface input conversion circuit and the external control signal are combined and logically converted by the AND gate chip of the logic voting circuit. When both the output level and the external control signal are high, the voting output is high, thereby closing the circuit when it is out of position, which increases the safety of the process of interlocking control using the circuit of the present invention.
[0039] Furthermore, this embodiment of the invention employs a dual-redundancy design, employing two sets of independent input / output interface chips. When one set of chip circuits fails, the other set of chip circuits can replace its function, thus avoiding overall circuit failure and improving the reliability and safety of the circuit.
[0040] It should be noted that, depending on the implementation needs, the various steps / components described in this application can be broken down into more steps / components, or two or more steps / components or parts of the operation of steps / components can be combined into new steps / components to achieve the purpose of this invention.
[0041] The order of the steps in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.
[0042] It should be understood that those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.
Claims
1. A dual-redundant signal interlocking logic conversion circuit, characterized in that, The circuit includes an interface input conversion circuit, a logic voting circuit, a drive circuit, and a relay circuit; The interface input conversion circuit includes multiple sets of input / output interface chips. Each set of input / output interface chips outputs two outputs, and each output is connected to one input of the logic voting circuit. Each input of the logic voting circuit corresponds to one output, and each output is connected to one input of the driver circuit. Each input terminal of the drive circuit corresponds to one output terminal, and the multiple output terminals are connected to one input terminal of the relay circuit. The action signal input interface conversion circuit converts one input voltage into four TTL level outputs based on the action signal. The TTL level and external control signal are input to the logic voting circuit. The logic voting circuit outputs the corresponding level to the drive circuit based on the input TTL level and the external control signal. The drive circuit outputs the drive signal based on the input level, thereby driving the corresponding relay circuit to output the logically converted off-position signal.
2. The dual-redundant signal interlocking logic conversion circuit according to claim 1, characterized in that, The logic conversion circuit adopts a dual-redundancy design, which is specifically implemented by designing two sets of independent input / output interface chips in the interface input conversion circuit.
3. The dual-redundant signal interlocking logic conversion circuit according to claim 1, characterized in that, The logic voting circuit specifically includes four sets of AND gate chips, with each pair of AND gate chips connected to the output port of an input interface chip.
4. The dual-redundant signal interlocking logic conversion circuit according to claim 1, characterized in that, The driving circuit specifically includes four sets of driving chips, and the input port of each set of driving chips is connected to the output port of an AND gate chip.
5. The dual-redundant signal interlocking logic conversion circuit according to claim 4, characterized in that, The relay circuit includes a combination of two or more electromagnetic relays and solid-state relays, with each set of electromagnetic relays and solid-state relays corresponding to a set of driver chips.
6. The dual-redundant signal interlocking logic conversion circuit according to claim 1, characterized in that, The logic truth of the interface input conversion circuit is as follows: when the input / output interface chip select is 0, if the input is open, a high-level signal is output; if the input is a power supply voltage, a low-level signal is output. When the input / output interface chip select is 1, the chip outputs a high configuration when any signal is input.
7. The dual-redundant signal interlocking logic conversion circuit according to claim 3, characterized in that, The logical truth value of the logic voting circuit is as follows: when both the output signal of the interface input chip and the external control signal are high-level inputs at the input terminal of the AND gate chip of the logic voting circuit, the AND gate chip outputs a high-level signal; when at least one of the output signal of the interface input chip and the external control signal is low-level inputs at the input terminal of the AND gate chip of the logic voting circuit, the AND gate chip outputs a low-level signal.
8. The dual-redundant signal interlocking logic conversion circuit according to claim 5, characterized in that, Each set of electromagnetic relays and solid-state relays is connected to the output port of a set of driver chips through a resistor and a transistor, and a normally closed detection data conversion device is connected between the electromagnetic relays and solid-state relays.
9. A dual-redundant signal interlocking logic conversion circuit according to claim 1, characterized in that, The input interface chip is specifically the HKA1300-PN / CQC chip.
10. A catapult device, characterized in that, The device specifically utilizes a dual-redundant signal interlocking logic conversion circuit as described in any one of claims 1-9, wherein when the device is in a normal non-ejection state, the action signal input voltage power supply is used; when the device is in an ejection-out state, the action signal input is open.