Dummy fins with reduced height and methods of forming the same

Abstract

The present disclosure relates to dummy fins with reduced height and methods of forming the same. One method includes forming a first protruding semiconductor fin and a dummy fin to protrude higher than a top surface of an isolation region. The first protruding semiconductor fin is parallel to the dummy fin. A gate stack is formed on a first portion of the first protruding semiconductor fin and a second portion of the dummy fin. The method also includes recessing a third portion of the first protruding semiconductor fin to form a recess, recessing a fourth portion of the dummy fin to reduce a height of the fourth portion of the dummy fin, and forming an epitaxial semiconductor region in the recess. The epitaxial semiconductor region grows toward the dummy fin.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to dummy fins with reduced height and methods of forming the same. BACKGROUND

[0002] Metal oxide semiconductor (MOS) devices are the basic building blocks in integrated circuits. MOS devices can have gate electrodes formed of polysilicon doped with p-type or n-type impurities that are doped using a doping process, such as ion implantation or thermal diffusion. The work function of the gate electrode can be adjusted to the band-edge of silicon. For n-type metal oxide semiconductor (NMOS) devices, the work function can be adjusted to be close to the conduction band of silicon. For p-type metal oxide semiconductor (PMOS) devices, the work function can be adjusted to be close to the valence band of silicon. Adjustment of the work function of the polysilicon gate electrode can be achieved by selecting the appropriate impurities.

[0003] MOS devices with polysilicon gate electrodes exhibit a carrier depletion effect, also known as polysilicon depletion effect. The polysilicon depletion effect occurs when an applied electric field sweeps away carriers from the gate region close to the gate dielectric, forming a depletion layer. In an n-doped polysilicon layer, the depletion layer includes ionized immobile donor sites, while in a p-doped polysilicon layer, the depletion layer includes ionized immobile acceptor sites. The depletion effect results in an increase in the effective gate dielectric thickness, making it more difficult to create an inversion layer at the surface of the semiconductor.

[0004] The polysilicon depletion problem can be addressed by forming metal gate electrodes, where the metal gates used in NMOS devices and PMOS devices can also have band-edge work functions. Thus, the resulting metal gate includes multiple layers to meet the requirements of NMOS devices and PMOS devices.

[0005] Formation of the metal gate typically involves forming a dummy gate dielectric and a dummy gate electrode, removing the dummy gate dielectric and the dummy gate electrode to form a trench, depositing a high-k dielectric layer and a metal layer into the trench, and performing a chemical mechanical polishing (CMP) process to remove excess portions of the high-k dielectric layer and the metal layer. The remaining portions of the metal layer form the metal gate. SUMMARY

[0006] According to a first aspect of the disclosure, there is provided a method for forming a semiconductor device, comprising: forming a first protruding semiconductor fin and a dummy fin, the first protruding semiconductor fin and the dummy fin protruding higher than a top surface of an isolation region, wherein the first protruding semiconductor fin is parallel to the dummy fin; forming a gate stack on a first portion of the first protruding semiconductor fin and a second portion of the dummy fin; recessing a third portion of the first protruding semiconductor fin to form a recess; recessing a fourth portion of the dummy fin to reduce a height of the fourth portion of the dummy fin; and forming an epitaxial semiconductor region in the recess, wherein the epitaxial semiconductor region grows towards the dummy fin.

[0007] According to a second aspect of the disclosure, there is provided a semiconductor device, comprising: an isolation region on a semiconductor substrate; a first protruding semiconductor fin protruding higher than a top surface of the isolation region; a semiconductor region connected to an end of the first protruding semiconductor fin; and a first dummy fin protruding higher than the top surface of the isolation region, wherein the first dummy fin comprises: a first portion having a first height; and a second portion having a second height smaller than the first height, wherein the semiconductor region laterally expands towards the second portion of the first dummy fin.

[0008] According to a third aspect of the disclosure, there is provided a semiconductor device, comprising: an isolation region on a semiconductor substrate; a dummy fin protruding higher than a top surface of the isolation region, wherein the dummy fin comprises: a first portion having a first height; and a second portion having a second height smaller than the first height; and a first source / drain region and a second source / drain region contacting opposite sidewalls of the second portion of the dummy fin. BRIEF DESCRIPTION OF DRAWINGS

[0009] Various features will become apparent to those of ordinary skill in the art upon reading and understanding the following detailed description. It should be noted that the various features will not necessarily be drawn to scale in the drawings. In fact, the dimensions of the various features will be arbitrarily increased or decreased for clarity of discussion.

[0010] FIG. 1 、 FIG. 2 、 FIG. 3A 、 FIG. 3B-1 、 FIG. 3B-2 、 FIG. 3B-3 、 FIG. 4A 、 FIG. 4B-1 、 FIG. 4B-2 、 FIG. 4B-3 、FIG. 4B-4 FIG. 4B-5 FIG. 5A FIG. 5B-1 FIG. 5B-2 FIG. 5B-3 FIG. 6 FIG. 7A FIG. 7B FIG. 8 FIG. 9A FIG. 9B FIG. 9C FIG. 9D FIG. 10A FIG. 10B FIG. 10C FIG. 10D FIG. 11A and FIG. 11B show a perspective view and cross-sectional views of intermediate stages in the formation of a fin field effect transistor (FinFET) having source / drain regions separated by dummy fins, in accordance with some embodiments.

[0011] FIG. 12 to FIG. 16 show a perspective view and cross-sectional views of intermediate stages in the formation of a FinFET having source / drain regions separated by dummy fins, in accordance with some embodiments.

[0012] FIG. 17 and FIG. 18 show a dummy fin and source / drain regions on opposite sides of the dummy fin, in accordance with some embodiments.

[0013] FIG. 19 show a process flow for forming a FinFET having source / drain regions separated by dummy fins, in accordance with some embodiments. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments, or examples, for implementing different features of the application. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the disclosure in any way. For example, in the following description, a first feature formed over or on a second feature can include embodiments in which the first and second features are formed in direct contact, and can also include embodiments in which additional features can be formed between the first and second features such that the first and second features can not be in direct contact. In addition, the present disclosure can repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0015] ​​​​​​​​​​​​​​​​​​Moreover, spatially relative terms (such as "beneath", "below", "lower", "above", "upper", and the like) can be used herein for ease of describing one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0016] According to some embodiments, fin field effect transistors (FinFETs) having source / drain regions separated from each other by dummy fin(s) and methods of forming the same are provided. The dummy fin(s) are partially recessed and narrowed. Intermediate stages of forming the transistors are shown according to some embodiments. Some variations of some embodiments are discussed. In the various views and illustrative embodiments, like reference numerals are used to represent like elements. The embodiments discussed herein provide examples that enable making or using the subject matter of the present disclosure, and one of ordinary skill in the art will readily understand modifications that can be made while remaining within the intended scope of the different embodiments. Like reference numerals and characters in the following drawings represent the same components. Although method embodiments can be discussed as being performed in a particular order, other method embodiments can be performed in any logical order.

[0017] FIG. 1 、 FIG. 2 、 FIG. 3A 、 FIG. 3B-1 、 FIG. 3B-2 、 FIG. 3B-3 、 FIG. 4A 、 FIG. 4B-1 、 FIG. 4B-2 、 FIG. 4B-3 、 FIG. 4B-4 、 FIG. 4B-5 、 FIG. 5A 、 FIG. 5B-1 、 FIG. 5B-2 、 FIG. 5B-3 、 FIG. 6 、 FIG. 7A 、 FIG. 7B 、 FIG. 8 、 FIG. 9A 、 FIG. 9B 、 FIG. 9C 、 FIG. 9D 、 FIG. 10A 、 FIG. 10B 、 FIG. 10C 、 FIG. 10D 、 FIG. 11A and FIG. 11B show cross-sectional and perspective views of intermediate stages in the formation of a FinFET and corresponding dummy fins according to some embodiments of the present disclosure. The processes shown in these figures are also schematically reflected in the flowchart of FIG. 1 1 as FIG. 19The process flow 300 shown.

[0018] FIG. 1 A perspective view of an initial structure is shown. The initial structure includes a wafer 10, which further includes a substrate 20. The substrate 20 can be a semiconductor substrate, which can be a silicon substrate, a silicon germanium substrate, or a substrate formed from other semiconductor materials. The substrate 20 can be doped with p-type or n-type impurities. An isolation region 22, such as a shallow trench isolation (STI) region, can be formed extending into the substrate 20 from a top surface of the substrate 20. The corresponding process is shown as FIG. 19 A portion of the substrate 20 between adjacent STI regions 22 is referred to as a semiconductor strip 24. According to some embodiments of the present disclosure, the semiconductor strip 24 is a portion of the original substrate 20, and thus the material of the semiconductor strip 24 is the same as the material of the substrate 20. According to alternative embodiments of the present disclosure, the semiconductor strip 24 is an alternative strip formed by etching a portion of the substrate 20 between the STI regions 22 to form a recess, and performing an epitaxy process to regrow another semiconductor material in the recess. Thus, the semiconductor strip 24 is formed of a semiconductor material that is different from the semiconductor material of the substrate 20. According to some embodiments, the semiconductor strip 24 is formed of Si, SiP, carbon-doped silicon, SiPC, SiGe, SiGeB, Ge, or a III-V compound semiconductor (e.g., InP, GaAs, AlAs, InAs, InAlAs, InGaAs, etc.).

[0019] The STI regions 22 can include a liner oxide (not shown), which can be a thermal oxide formed by thermal oxidation of a surface layer of the substrate 20. The liner oxide can also be a deposited silicon oxide layer formed using, for example, atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), chemical vapor deposition (CVD), etc. The STI regions 22 can further include a dielectric material over the liner oxide, which can be formed using flowable chemical vapor deposition (FCVD), spin-on, etc.

[0020] FIG. 2 Formation of a dielectric dummy strip 25 is shown. The corresponding process is shown as FIG. 19Process 304 in the process flow 300 shown. According to some embodiments, the dummy strip 25 is formed by etching one of the semiconductor strips 24 to form a recess, and then filling the recess with a dielectric material. According to other embodiments, other methods can be used to form the dielectric dummy strip 25. The dielectric material of the dielectric dummy strip 25 can be formed of a single, homogenous material, or can have a composite structure including more than one layer formed of different materials. The material of the dielectric dummy strip 25 includes, but is not limited to, Si02, SiON, Si3N4, SiCN, SiONC, HfO, TaN, etc., composite layers of the foregoing, and / or compounds of the foregoing. The bottom surface of the dielectric dummy strip 25 can be higher than, level with, or lower than the bottom surface of the STI region 22. The top surface of the dielectric dummy strip 25 can also be higher than, level with, or lower than the top surface of the semiconductor strips 24.

[0021] Referring to FIG. 3A , the STI region 22 is recessed. The top portions of the semiconductor strips 24 and the dielectric dummy strip 25 protrude higher than the top surface 22A of the remaining portion of the STI region 22 to form protruding fins 24’ and a dummy fin 25’, respectively. The corresponding process is shown as process 306 in the process flow 300 shown. FIG. 19 The etching can be performed using a dry etching process in which HF3 and NH3 are used as etching gases. According to alternative embodiments of the present disclosure, the recessing of the STI region 22 is performed using a wet etching process. For example, the etching chemistry can include a solution of HF.

[0022] In the above embodiments, the fins can be patterned by any suitable method. For example, one or more photolithography processes including a double patterning or multiple patterning process can be used to pattern the fins. In general, a double patterning or multiple patterning process combines photolithography and a self-alignment process, allowing a pattern to be produced with, for example, smaller pitch than is obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can then be used to pattern the fins.

[0023] Further referring to FIG. 3A , after the STI region 22 is recessed, a dummy gate stack 30 is formed on the top surfaces and sidewalls of the (protruding) fins 24’ and the dummy fin 25’. The corresponding process is shown as process 308 in the process flow 300 shown. FIG. 19Process 308 in the illustrated process flow 300. The dummy gate stack 30 may include a dummy gate dielectric 32 and a dummy gate electrode 34 above the dummy gate dielectric 32. The dummy gate electrode 34 may be formed, for example, using polysilicon or amorphous silicon, and may also use other materials. Each of the dummy gate stacks 30 may also include one (or more) hard mask layers 36 above the dummy gate electrode 34. The hard mask layers 36 may be formed of silicon nitride, silicon oxide, silicon carbonitride, or a multilayer thereof. The dummy gate stack 30 may span one or more protruding fins 24', dummy fins 25', and / or STI regions 22. The dummy gate stack 30 also has a longitudinal direction perpendicular to the longitudinal direction of the protruding fins 24'.

[0024] Next, gate spacers 38 are formed on the sidewalls of the dummy gate stack 30. According to some embodiments of this disclosure, the gate spacers 38 are formed of a dielectric material (e.g., SiO2, SiON, Si3N4, SiCN, SiONC, HfO, TaN, etc.) and may have a single-layer structure or a multilayer structure comprising multiple dielectric layers. The formation process may include depositing one or more blanket dielectric layers and then performing an anisotropic etching process to remove the horizontal portions of the blanket dielectric layers(s), leaving vertical portions on the sidewalls of the gate stack 30 as gate spacers 38. The blanket dielectric layers may be conformal layers deposited using conformal deposition methods such as atomic layer deposition (ALD), chemical vapor deposition (CVD), etc.

[0025] In the same process, where gate spacers 38 are formed, fin spacers 39 can also be formed. FIG. 3A Some examples of fin spacers 39 between adjacent protruding fins 24' and dummy fins 25' are schematically shown, with the fin spacers 39 indicated by dashed lines. Fin spacers 39 on the outer side of the protruding fins 24' are not shown; however, fin spacers may also be formed in these locations. FIG. 3B-1 , FIG. 3B-2 and FIG. 3B-3 Some examples of fin spacers 39 are shown. FIG. 3B-1 , FIG. 3B-2 and FIG. 3B-3 The cross-sectional view in the middle is from FIG. 3A The reference section 3B-3B was obtained. FIG. 3B-1 When the gap between adjacent protruding fins 24' and dummy fins 25' has a high aspect ratio and a short distance, the fin spacer 39 can completely fill the gap. FIG. 3B-2 In the example shown, most of the gap 27 is unfilled. According to some embodiments, the fin spacer 39 includes a horizontal portion at the bottom of the gap 27. According to alternative embodiments, the horizontal portion at the bottom of the gap 27 may also be removed in an anisotropic etching process.FIG. 3B-3 A fin spacer 39 is shown according to yet another alternative embodiment, in which small gaps 27 are left unfilled, while a majority of each of the gaps 27 is filled.

[0026] According to some embodiments of the disclosure, an etching process (hereinafter referred to as source / drain recessing) is performed to etch portions of the protruding fins 24’ that are not covered by the dummy gate stacks 30 and the gate spacers 38, resulting in the structure shown in FIG. 3B. At the same time, the protruding fins 24’ are etched, and the dummy fins 25’ can also be etched and recessed, such that the height and width of the dummy fins 25’ are significantly reduced. The corresponding process is shown as process 310 in the process flow 300 as shown in FIG. 3A. The portions of the fins 24’ directly underneath the dummy gate stacks 30 and the gate spacers 38 are protected from being etched. According to some embodiments, the top surface of the recessed semiconductor strips 24 can be lower than the top surface 22A of the STI region 22. The space left by the etched portions of the protruding fins 24’ is referred to as the recess 40. FIG. 4A FIG. 19 According to some embodiments, the portions 25’A of the dummy fins 25’ that are not directly underneath the gate spacers 38 and the dummy gate stacks 30 are partially recessed. In other words, the height of the portions 25’A of the dummy fins 25’ is reduced, and can be narrowed (or can not be narrowed) by the etching process. On the other hand, the portions 25’B of the dummy fins 25’ that are directly underneath the gate spacers 38 and the dummy gate stacks 30 are protected from the etching process, and are not recessed and narrowed. For example, the remaining height H2 of the portions 25’A is less than the height H1 of the portions 25’B. The height H1 of the portions 25’B is also the height of the portions 25’A before they are recessed. The ratio of H2 / H1 can be in the range of about 0.1 to about 0.9, and can be in the range of about 0.3 to about 0.7.

[0027] According to some embodiments, the recessing of the protruding fins 24’ and the recessing of the dummy fins 25’ are performed in a common process for etching the protruding fins 24’, and the etching chemistry used to recess the protruding fins 24’ is selected such that both the dummy fins 25’ and the protruding fins 24’ are etched simultaneously. According to alternative embodiments, the recessing of the protruding fins 24’ and the recessing of the dummy fins 25’ are performed in different processes. For example, the dummy fins 25’ can remain unetched while the protruding fins 24’ are etched, and then the dummy fins 25’ are etched, for example, in a cleaning process, while in the cleaning process the protruding fins 24’ can be etched simultaneously, or can not be etched.

[0028] According to some embodiments, the recessing of the protruding fins 24’ and the recessing of the dummy fins 25’ are performed in a common process for etching the protruding fins 24’, and the etching chemistry used to recess the protruding fins 24’ is selected such that both the dummy fins 25’ and the protruding fins 24’ are etched simultaneously. According to alternative embodiments, the recessing of the protruding fins 24’ and the recessing of the dummy fins 25’ are performed in different processes. For example, the dummy fins 25’ can remain unetched while the protruding fins 24’ are etched, and then the dummy fins 25’ are etched, for example, in a cleaning process, while in the cleaning process the protruding fins 24’ can be etched simultaneously, or can not be etched.

[0029] ​According to some embodiments, the etch process includes a dry etch process. The etch can be performed using direct plasma or remote plasma. The etch process can also be a radical etch process in which the plasma generated from the etch gas is filtered to remove ions, while radicals are left behind and used for etching. According to some embodiments, the process gas can include an etch gas, which can include CI2, HBr, CF4, CHF3, CH2F2, CH3F, C4F6, BCI3, SF6, H2, NF3, or a combination of the foregoing. The process gas can also include a passivation gas for tuning the etch selectivity ER 24’ / ER 25’ , which is the ratio of the etch rate ER 24’ / ER 25’ of the protruding fin 24' to the etch rate ER 24’ / ER 25’ of the dummy fin 25'. The passivation gas can include N2, O2, CO2, SO2, CO, CH4, SiCI4, or a combination of the foregoing. In addition, a dilution gas (carrier gas) such as Ar, He, Ne, or a combination of the foregoing can also be used. According to some embodiments, the etch is performed with a source power in a range between about 10 Watts and about 3,000 Watts. The etch can be performed with a bias power, which can be less than about 3,000 Watts. The pressure of the process gas can be in a range between about 1 mTorr and about 5 Torr, and the process gas flow rate can be in a range between about 1 seem and about 5,000 seem. In an example etch process, HBr and / or CI2 is used as the etch gas, and the etch selectivity ER 24’ / ER 25’ can be tuned by adjusting the flow rate of the passivation gas, where increasing the passivation gas will increase the etch selectivity, and vice versa. In addition, the etch selectivity ER 24’ / ER 25’ can be increased by decreasing the bias power, or decreased by increasing the bias power. In another example where the dummy fin 25' includes SiN and a wet etch is used, the addition of H3PO4 can increase the etch selectivity. According to some embodiments, the etch selectivity ER 24’ / ER 25’ is in a range between about 0.1 and about 5. In embodiments where the etch selectivity ER 24’ / ER 25’ is less than 1.0, an etch stop layer can be formed on top of the dummy fin 25' to protect the underlying portion of the dummy fin 25'. With the etch stop layer, the dummy fin 25' can have an etch rate greater than the protruding fin 24, even though the etch selectivity ER 24’ / ER 25’less than 1.0), but the dummy fins 25' can still have a desired portion left over after the protruding fins 24' are etched.

[0030] According to an alternative embodiment, the etching of the protruding fins 24' and the dummy fins 25' is performed using a wet etch process in which the etch chemistry can include HF and F2. The etch chemistry can also include an auxiliary etch chemistry for adjusting the etch selectivity ER 24’ / ER 25’ , which can include H2SO4, HC1, HBr, NH3, H3PO4, or a combination of the foregoing. Solvents including deionized water, ethanol, acetone, etc. can be used.

[0031] When the dummy fins 25' are recessed, the fin spacers 39 can also be recessed. FIG. 4B-1 、 FIG. 4B-2 、 FIG. 4B-3 、 FIG. 4B-4 and FIG. 4B-5 show some example profiles of some dummy fins 25' (after the etch process) and remaining fin spacers 39 (if any remain). In FIG. 4B-1 , no fin spacers remain after the fin spacers 39 are recessed. In FIG. 4B-2 , the dummy fins 25' have a step, and the fin spacers 39 have a top surface that continues from the top surface of the step, and the fin spacers 39 can have vertical outer sidewalls. In FIG. 4B-3 , the dummy fins 25' have a step, and the fin spacers 39 have a top surface that continues from the top surface of the step, where the height of the fin spacers 39 continuously decreases to zero. In FIG. 4B-4 , the dummy fins 25' have a step, and the fin spacers 39 have a U-shaped top surface, which can result from the profiles shown in FIG. 3B-2 and FIG. 3B-3 . FIG. 4B-5 shows a profile in which the dummy fins 25' and the lower portions of the fin spacers 39 are recessed further than shown in FIG. 4B-4 .

[0032] Next, epitaxial regions (source / drain regions) 42A and 42B (collectively 42) are formed by selectively growing semiconductor material from the recesses 40, and the resulting structure is shown in FIG. 5A . The corresponding process is shown as in FIG. 19Process 312 in the process flow 300 shown. The epitaxial regions 42A and 42B can be the same conductivity type (p-type or n-type) and can be formed in a common epitaxial process. Alternatively, the epitaxial regions 42A and 42B have opposite conductivity types and can be epitaxially grown in separate epitaxial processes. According to some embodiments, the epitaxial regions 42A and / or 42B include silicon germanium, silicon, silicon carbon, etc. Depending on whether the resulting FinFET is a p-type FinFET or an n-type FinFET, the epitaxy can be performed to in situ dope the p-type or n-type impurities. For example, when the resulting FinFET is a p-type FinFET, SiB, silicon germanium boron (SiGeB), GeB, etc. can be grown. Conversely, when the resulting FinFET is an n-type FinFET, silicon phosphorus (SiP), silicon carbon phosphorus (SiCP), etc. can be grown. After the epitaxial regions 42A and 42B completely fill the recesses 40, the epitaxial regions 42 begin to horizontally expand and can form facets. According to some embodiments, the epitaxial regions 42A and / or 42B are laterally spaced apart from the dummy fin 25', as shown by the solid lines. According to alternative embodiments, the epitaxial regions 42A and / or 42B are proximate to or contact the dummy fin 25', as shown by the dashed lines.

[0033] FIG. 5B-1 , FIG. 5B-2 and FIG. 5B-3 shows several cross-sectional views of the dummy fin 25' and the source / drain regions 42A and 42B, according to some embodiments. The cross-sectional views are taken from the reference cross-section 5B-5B in FIG. 5A . Referring to FIG. 5B-1 , for example, when the source / drain regions 42A and 42B are formed from the same semiconductor material (which can be either p-type or n-type), the source / drain regions 42A and 42B are symmetric with respect to the dummy fin 25'. The source / drain regions 42A and 42B also contact opposite sidewalls of the dummy fin 25' and are prevented from contacting each other by the dummy fin 25'. Referring to FIG. 5B-2 , for example, when the source / drain regions 42A and 42B are formed from different semiconductor materials (one p-type and the other n-type), the source / drain regions 42A and 42B are asymmetric with respect to the dummy fin 25'. FIG. 5B-3 shows an example in which the source / drain regions 42A and 42B are spaced apart from the dummy fin 25'.

[0034] In FIG. 5B-1 , FIG. 5B-2 and FIG. 5B-3In this case, dashed lines 25'-LE and 25'-RE are drawn to represent the left and right edges of dummy fins 25' if dummy fins 25' were not recessed. As can be seen, due to the recessing of dummy fins 25', additional space is provided by the etched portions of dummy fins 25', and source / drain regions 42A and 42B can extend into this additional space to have increased volume. Performance of the resulting FinFET is thereby improved. Additionally, when the recessing of dummy fins 25' is controlled, the likelihood of source / drain regions 42A and 42B merging (and thus electrically shorting) is not necessarily increased.

[0035] FIG. 6 A perspective view of the structure after formation of a contact etch stop layer (CESL) 46 and an interlayer dielectric (ILD) 48 is shown. The corresponding process is shown as process 314 in process flow 300 as shown in FIG. 3. FIG. 19 CESL 46 can be formed of silicon nitride, silicon carbon nitride, etc. CESL 46 can be formed using a conformal deposition method such as ALD or CVD, for example. ILD 48 can include a dielectric material formed using, for example, FCVD, spin-on, CVD, or another deposition method. ILD 48 can also be formed of an oxygen-containing dielectric material, which can be silicon oxide-based, such as silicon oxide, phosphorus silicon glass (PSG), boron silicon glass (BSG), boron phosphorus silicon glass (BPSG), etc. A planarization process (e.g., a chemical mechanical polishing (CMP) process or a mechanical lapping process) is performed to level the top surfaces of ILD 48, dummy gate stacks 30, and gate spacers 38 with one another.

[0036] FIG. 7A and FIG. 7B A perspective view and a cross-sectional view, respectively, in the formation of gate isolation regions 50 are shown. The corresponding process is shown as process 316 in process flow 300 as shown in FIG. 3. FIG. 19 FIG. 7B A reference cross-section 7B-7B in FIG. 7A is shown. The formation process can include etching dummy gate stacks 30 to form openings (occupied by gate isolation regions 50) that divide each of dummy gate stacks 30 into separate portions, as shown in both FIG. 7A and FIG. 7B As can be implemented from FIG. 7B The etching is performed until dummy fins 25' are exposed. The openings are then filled with a dielectric material(s) to form gate isolation regions 50.

[0037] Next, as FIG. 8 ​As shown, the dummy gate stack 30, including a hard mask layer 36, a dummy gate electrode 34, and a dummy gate dielectric 32, is replaced with a replacement gate stack 58. According to some embodiments of this disclosure, this replacement includes etching such a dummy gate stack 58 in one or more etching steps. FIG. 6 The hard mask layer 36, dummy gate electrode 34, and dummy gate dielectric 32 shown form an opening between the gate spacers 38. The corresponding process is shown as follows: FIG. 19 Process 318 in the process flow 300 shown.

[0038] Next, as FIG. 8 As shown, a (replacement) gate stack 58 is formed, which includes a gate dielectric 54 and a gate electrode 56. The corresponding process is shown as follows. FIG. 19 Process 320 in the process flow 300 shown. The formation of the gate stack 58 includes forming / depositing multiple layers and then performing a planarization process, such as a CMP process or a mechanical polishing process. According to some embodiments of this disclosure, each of the gate dielectrics 54 includes an interface layer (IL) as its lower portion. The IL is formed on the exposed surface of the protruding fin 24'. The IL may include an oxide layer, such as a silicon oxide layer, formed by a thermal oxidation, chemical oxidation, or deposition process of the protruding fin 24'. Each of the gate dielectrics 54 may also include a high-k dielectric layer formed above the IL. The high-k dielectric layer may include HfO2, ZrO2, HfZrO x HfSiO x HfSiON, ZrSiO x HfZrSiO x Al2O3, HfAlO x HfAlN, ZrAlO x Materials such as La2O3, TiO2, Yb2O3, and silicon nitride are used. The dielectric constant (k value) of high-k dielectric materials is higher than 3.9, and can be higher than approximately 7.0. The high-k dielectric layer can be formed as a conformal layer and extends on the sidewalls of the protruding fin 24' and the gate spacer 38. The gate dielectric 54 also extends on the top surface and sidewalls of the dielectric dummy fin 25'.

[0039] The sublayers in the gate electrode 56 may include, but are not limited to, titanium silicon nitride (TSN) layers, tantalum nitride (TaN) layers, titanium nitride (TiN) layers, titanium and aluminum-containing layers, additional TiN and / or TaN layers, and filler metal regions. Some of these sublayers define the work function of the corresponding FinFET. Furthermore, the metal layers of p-type FinFETs and n-type FinFETs may be different from each other, such that the work function of the metal layers is suitable for the corresponding p-type or n-type FinFET. The filler metal may include tungsten, cobalt, etc.

[0040] FIG. 8 Also shown is fin spacer 39, leaving some of fin spacers 39 behind, as an example. According to alternative embodiments, fin spacers 39 can be removed, as discussed in the previous paragraph.

[0041] Next, as shown in FIG. 9A and FIG. 9B , hard mask 60 is formed. According to some embodiments of the present disclosure, the formation of hard mask 60 includes recessing gate stack 58 by etching to form a recess, filling a dielectric material into the recess, and performing planarization to remove excess portions of the dielectric material.

[0042] FIG. 9A and FIG. 9B Also shown is the formation of source / drain silicide regions 62A and 62B, source / drain contact plugs 64A and 64B, and gate contact plugs 66A and 66B. The respective processes are shown as process 322 in process flow 300 as shown in FIG. 19 Thereby, FinFETs 70A and 70B are formed. According to some embodiments, both FinFETs 70A and 70B are p-type FinFETs or both are n-type FinFETs. According to alternative embodiments, FinFETs 70A and 70B include a p-type FinFET and an n-type FinFET.

[0043] In FIG. 9B , FIG. 9C , FIG. 9D and FIG. 5B-1 , FIG. 5B-2 and FIG. 5B-3 , several cross-sectional views of FIG. 9A are shown. FIG. 9B Some features in cross-section 9B-9B of FIG. 9A are shown. Replacement gates 58A and 58B (collectively, replacement gate stack 58) are separated from each other by dummy fin 25’ and gate isolation region 50. Gate contact plugs 66A and 66B are over and contact replacement gate stack 58A and 58B, respectively. FIG. 9C Some features in cross-section 9C-9C of FIG. 9A are shown schematically. FIG. 9D Some features in cross-section 9D-9D of FIG. 9A are shown schematically. Some, but not all, features in cross-section 5B-5B of FIG. 5B-1 , FIG. 5B-2 and FIG. 5B-3 may be found in cross-section 5B-5B of FIG. 9A .

[0044] FIG. 10A ,FIG. 10B 、 FIG. 10C and FIG. 10D Figures show some example profiles of a portion 25’A of dummy fin 25’ according to some embodiments (see also FIG. 4A ). These profiles are obtained from portions of the dummy fin directly underneath ILD 48 FIG. 9A ). In FIG. 10A , dummy fin 25’ has a trapezoidal shape. In FIG. 10B , dummy fin 25’ has a tapered profile with a rounded tip. In FIG. 10B , dummy fin 25’ has a top portion with vertical sidewalls and with a uniform width, and a bottom portion with a trapezoidal shape, where the top width TCDB is equal to the middle width MCDB, and smaller than the bottom width BCDB. In FIG. 10D , dummy fin 25’ has a triangular shape.

[0045] According to some embodiments, some dimensions of the resulting structure are discussed with reference to FIG. 9B and FIG. 10A . The height H1 FIG. 9B of dummy fin portion 25’B is selected to be within a certain range, and too large a value of H1 can result in the metal gate that should not be isolated being isolated, and too small a value of H1 can result in the dummy fin 25’ being completely removed when recessed, and thus defeating the purpose for which the dummy fin 25’ was formed. Thus, the height H1 of dummy fin portion 25’B can be selected to be within a range of about and about . The value of height H2 FIG. 10A of dummy fin portion 25’A is selected to be large enough to separate adjacent source / drain regions, while small enough to obtain additional volume for the source / drain regions. Thus, the height H2 of dummy fin portion 25’A is smaller than height H1, and can be selected to be within a range of about and about . The difference (H1-H2) can be greater than about and can be within a range of about and about . The top width TCDB and bottom width BCDB FIG. 9B of dummy fin portion 25’B can be equal or substantially equal to each other, e.g., the difference is less than about 5% of the bottom width BCDB. On the other hand, the top width TCDA and bottom width BCDA FIG. 10A of dummy fin portion 25’A have a relationship (BCDA>TCDA), and the difference (BCDA-TCDA) can be greater than about and can be less than 80% of the bottom width BCDA. In addition, there is a relationship (TCDB > TCDA), and a relationship (BCDA - TCDA) > (BCDB - TCDB). According to some embodiments, each of the widths TCDA, BCDA, TCDB, and BCDB can also be in a range between about 3 nm and about 1 pm.

[0046] It will be appreciated that dummy fins 25’ in different regions of the same device chip and the same wafer can have different sizes and / or shapes. For example, FIG. 11A and FIG. 11B Two dummy fins 25’ are shown in different device regions, and having different heights, different widths, and / or different shapes. The differences in height, width, and / or shape can be achieved by etching the dummy fins 25’ in different regions via separate etching processes.

[0047] FIG. 12 to FIG. 16 A cross-sectional view is shown of an intermediate stage in etching the protruding fins 24’ and dummy fins 25’, and forming source / drain regions, according to some embodiments of the disclosure. FIG. 12 to FIG. 16 The process shown corresponds to FIG. 4A , FIG. 4B-1 to FIG. 4B-5 , FIG. 5A and FIG. 5B-1 to FIG. 5B-3 The process shown. Unless otherwise noted, the materials and formation processes for the components in these embodiments are substantially the same as for the same components denoted by the same reference numerals in the preceding embodiments. Thus, details regarding the formation processes and materials for the components shown in FIG. 12 to FIG. 16 may be found in the discussion of the preceding embodiments.

[0048] The initial steps of these embodiments are substantially the same as FIG. 1 , FIG. 2 and FIG. 3A The initial steps of these embodiments are substantially the same as FIG. 12 A cross-section is shown taken from the cross-section 12-12 in FIG. 3A It will be appreciated that FIG. 12 shows more features than FIG. 3A For example, FIG. 12Device regions 100 and 200 are shown separated by boundary dummy fins 25'-0 at the boundaries. Three dummy fins 25' are shown, wherein the boundary dummy fins 25'-0 divide regions 100 and 200, while the inner dummy fins 25'-100 and 25'-200 are located within device regions 100 and 200, respectively. Protruding fins 24' and fin spacers 39 are also schematically shown. An etch mask 110 is formed to cover features in device region 200. According to some embodiments, the etch mask 110 may include a photoresist or may include a hard mask formed of TiN, BN, TaN, etc. Device region 100 is exposed through openings in the etch mask 110. The etch mask 110 may cover all or part of the dummy fins 25'-0, or may not cover the dummy fins 25'-0. Therefore, the left edge of the etching mask 110 can be located anywhere between the left edge 25'-LE and the right edge 25'-RE of the dummy fin 25' and includes the left edge 25'-LE and the right edge 25'-RE of the dummy fin 25'.

[0049] Next, one or more etching processes are performed to recess the protruding fin 24' and the dummy fin 25'-100. The fin spacer 39 may also be etched. The resulting structure is... FIG. 13 As shown in [the image]. FIG. 13 In the middle, the portion of the protruding fin 24' directly below the dummy gate stack 30 ( FIG. 3A The recesses are not recessed and are shown in dashed lines because these portions are in a different plane than those shown in the illustration. Therefore, the recess 40 is formed as a space left by the etched protruding fins 24'. The dummy fins 25'-0 may be etched or may be substantially unetched. (Reference) FIG. 4A The details of the etching process have been discussed and will therefore not be repeated here. As a result of the etching process(s), the dummy fins 25'-100 are lowered and narrowed. The dimensions and size comparisons of the dummy fins 25'-100 have been discussed in previous paragraphs and will not be repeated here. After the etching process, when the etching mask 110 includes photoresist, the etching mask 110 can be removed, or it can be left and used as a mask for subsequent epitaxial processes. In these embodiments, as FIG. 14 As shown, the etch mask 110 can be removed after the epitaxial process.

[0050] refer to FIG. 14 In the epitaxial process, source / drain regions 42A are formed. Next, an etch mask 114 is formed to cover device region 100, leaving device region 200 uncovered. The right edge of the etch mask 114 can be located anywhere between the left edge 25'-LE and the right edge 25'-RE of the dummy fin 25' and includes both the left edge 25'-LE and the right edge 25'-RE of the dummy fin 25'.

[0051] Next, an etch process is performed to recess the protruding fins 24’ and dummy fins 25’-200. The resulting structure is also shown in FIG. 15 Thus, the recesses 40 are formed as spaces left by the etched protruding fins 24’. Referring to FIG. 4A the details of the etch process are discussed and thus are not repeated here. As a result of the etch process, the dummy fins 25’-200 are lowered and narrowed. The fin spacers 39 are also etched and can be completely or partially removed. The dimensions and size ratios of the dummy fins 25’-200 can be the same as discussed in the previous paragraphs and are not repeated here. After the etch process, the etch mask 114 can be removed when the etch mask 110 comprises photoresist, or can be left in place and removed after the epitaxy process, as shown in FIG. 16 .

[0052] FIG. 16 The formation of the source / drain regions 42B is shown. The source / drain regions 42A have a different profile than the source / drain regions 42B and are asymmetric with respect to the boundary dummy fin 25’-0 from the source / drain regions 42B. For example, the source / drain regions 42A and 42B can have different dimensions, different shapes, different conductivity types, and / or different materials on opposite sides of and immediately adjacent to the boundary dummy fin 25’-0.

[0053] Referring to FIG. 12 , the left edge of the etch mask 110 can be at any location between and including the left edge 25’-LE and the right edge 25’-RE of the dummy fin 25’. Referring to FIG. 14 , the right edge of the etch mask 114 can be at any location between and including the left edge 25’-LE and the right edge 25’-RE of the dummy fin 25’. Thus, the etch masks 110 and 114 can overlap and cover some or all of the boundary dummy fin 25’-0. Alternatively, some or all of the boundary dummy fin 25’-0 can not be covered by one or both of the etch masks 110 and 114. These variations result in the boundary dummy fin 25’-0 having a different profile and height than selected. According to some embodiments, the boundary dummy fin 25’-0 is higher than the inner dummy fins 25’-100 and 25’-200, for example having a height greater than 1.1, greater than 1.5, or greater than 2.0 of H2 / H2’ (where the heights H2 and H2’ are shown in FIG. 16 .

[0054] FIG. 17Contours of dummy fins 25'-0, 25'-100, and 25'-200 are shown in accordance with some embodiments. Dummy fin 25'-0 can have a height that is greater than the height of both dummy fins 25'-100 and 25'-200. With the height of dummy fin 25'-0 being high, there is a higher process window for growing source / drain regions 42A and 42B without having to consider merging source / drain region 42A into source / drain region 42B. On the other hand, since source / drain regions 42A on opposite sides of dummy fin 25'-100 are symmetric to each other, the process is easier to control and thus dummy fin 25'-100 can be made smaller (with height H2' being less than height H2) to increase the volume of source / drain regions 42A. Similarly, since source / drain regions 42B on opposite sides of dummy fin 25'-200 are symmetric to each other, the process is easier to control and thus dummy fin 25'-200 can be made smaller to increase the volume of source / drain regions 42B. FIG. 17 An example is shown in which left and right portions of dummy fin 25'-0 are symmetric to each other.

[0055] FIG. 18 Contours of dummy fins 25'-0, 25'-100, and 25'-200 are shown in accordance with alternative embodiments. These embodiments are similar to the embodiments shown in FIG. 17 The embodiments shown are similar except that left and right portions of dummy fin 25'-0 are not symmetric to each other. For example, height HL of the left portion can be greater than height HR of the right portion, and each of heights HL and HR can be equal to or different from middle height HM.

[0056] Embodiments of the present disclosure have some advantageous features. By recessing the dummy fin, more space can be used to form source / drain regions with greater volume. The increase in volume of the source / drain regions results in an improvement in performance of the resulting FinFET.

[0057] According to some embodiments of the present disclosure, a method includes: forming a first protruding semiconductor fin and a dummy fin, the first protruding semiconductor fin and the dummy fin protruding higher than a top surface of an isolation region, wherein the first protruding semiconductor fin is parallel to the dummy fin; forming a gate stack on a first portion of the first protruding semiconductor fin and a second portion of the dummy fin; recessing a third portion of the first protruding semiconductor fin to form a recess; recessing a fourth portion of the dummy fin to reduce a height of the fourth portion of the dummy fin; and forming an epitaxial semiconductor region in the recess, wherein the epitaxial semiconductor region grows towards the dummy fin. In an embodiment, the epitaxial semiconductor region is blocked by the dummy fin that has been recessed. In an embodiment, recessing the third portion of the first protruding semiconductor fin and recessing the fourth portion of the dummy fin are performed in a common etching process. In an embodiment, when the fourth portion of the dummy fin is recessed, the second portion of the dummy fin directly below the gate stack is protected from being etched. In an embodiment, recessing the third portion of the first protruding semiconductor fin and recessing the fourth portion of the dummy fin are performed in different etching processes. In an embodiment, the height of the fourth portion of the dummy fin is reduced by more than 30% and less than about 70%.

[0058] According to some embodiments of the present disclosure, a device comprising: an isolation region on a semiconductor substrate; a first protruding semiconductor fin protruding higher than a top surface of the isolation region; a semiconductor region connected to an end of the first protruding semiconductor fin; and a first dummy fin protruding higher than the top surface of the isolation region, wherein the first dummy fin comprises a first portion having a first height; and a second portion having a second height less than the first height, wherein the semiconductor region laterally expands towards the second portion of the first dummy fin. In an embodiment, the device further comprises: a first gate stack on the first protruding semiconductor fin; and a gate isolation region contacting sidewalls of the first gate stack, wherein the gate isolation region is over and in contact with the first portion of the first dummy fin. In an embodiment, the device further comprises: a second protruding semiconductor fin protruding higher than the top surface of the isolation region; and a second gate stack on the second protruding semiconductor fin, wherein the second gate stack is separated from the first gate stack by the gate isolation region. In an embodiment, the semiconductor region contacts sidewalls of the second portion of the first dummy fin. In an embodiment, a ratio of the second height to the first height is in a range between about 0.3 and about 0.7. In an embodiment, the first portion of the first dummy fin has a first bottom width and a first top width, the first top width being equal to the first bottom width, and wherein the second portion of the first dummy fin has a second bottom width and a second top width, the second top width being less than the second bottom width. In an embodiment, the device further comprises: a second dummy fin protruding higher than the top surface of the isolation region, wherein the second dummy fin further comprises a third portion and a fourth portion, wherein the fourth portion of the second dummy fin and the second portion of the first dummy fin are on opposite sides of the semiconductor region, and the second height of the second portion of the first dummy fin is greater than a third height of the fourth portion of the second dummy fin. In an embodiment, the first dummy fin and the second dummy fin are parallel to each other.

[0059] According to some embodiments of the disclosure, a device comprising: an isolation region on a semiconductor substrate; a dummy fin protruding higher than a top surface of the isolation region, wherein the dummy fin comprises a first portion having a first height; and a second portion having a second height less than the first height; and first and second source / drain regions contacting opposite sidewalls of the second portion of the dummy fin. In embodiments, the device further comprises: a first FinFET comprising the first protruding semiconductor fin and the first source / drain region; and a second FinFET comprising a second protruding semiconductor fin on an opposite side of the dummy fin from the first protruding semiconductor fin, wherein the second FinFET comprises the second source / drain region. In embodiments, the first and second FinFETs have opposite conductivity types. In embodiments, the first and second FinFETs have the same conductivity type. In embodiments, the second height is less than about 90% of the first height.

[0060] The foregoing summary has outlined rather broadly the features of several embodiments so as to provide those skilled in the art with a better understanding of the various aspects of the disclosure. The skilled artisan should appreciate that they can readily employ the disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein without departing from the spirit and scope of the disclosure. Those skilled in the art should appreciate that they can readily use the disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein without departing from the spirit and scope of the disclosure.

[0061] Example 1. A method for forming a semiconductor device, comprising: forming a first protruding semiconductor fin and a dummy fin protruding higher than a top surface of an isolation region, wherein the first protruding semiconductor fin is parallel to the dummy fin; forming a gate stack on a first portion of the first protruding semiconductor fin and a second portion of the dummy fin; recessing a third portion of the first protruding semiconductor fin to form a recess; recessing a fourth portion of the dummy fin to reduce a height of the fourth portion of the dummy fin; and forming an epitaxial semiconductor region in the recess, wherein the epitaxial semiconductor region grows towards the dummy fin.

[0062] Example 2. The method of example 1, wherein the epitaxial semiconductor region is blocked by the dummy fin that has been recessed.

[0063] Example 3. The method of example 1, wherein recessing the third portion of the first protruding semiconductor fin and recessing the fourth portion of the dummy fin are performed in a common etch process.

[0064] Example 4. The method of example 3, wherein a ratio of a first etch rate of the third portion of the first protruding semiconductor fin to a second etch rate of the fourth portion of the dummy fin is in a range between about 0.1 and about 5.

[0065] Example 5. The method of example 1, wherein, when the fourth portion of the dummy fin is recessed, a second portion of the dummy fin directly below the gate stack is protected from being etched.

[0066] Example 6. The method of example 1, wherein recessing the third portion of the first protruding semiconductor fin and recessing the fourth portion of the dummy fin are performed in different etch processes.

[0067] Example 7. The method of example 1, wherein a height of the fourth portion of the dummy fin is reduced by more than 30% and less than about 70%.

[0068] Example 8. A semiconductor device comprising: an isolation region on a semiconductor substrate; a first protruding semiconductor fin protruding higher than a top surface of the isolation region; a semiconductor region connected to an end of the first protruding semiconductor fin; and a first dummy fin protruding higher than the top surface of the isolation region, wherein the first dummy fin comprises: a first portion having a first height; and a second portion having a second height less than the first height, wherein the semiconductor region laterally expands toward the second portion of the first dummy fin.

[0069] Example 9. The device of example 8, further comprising: a first gate stack on the first protruding semiconductor fin; and a gate isolation region contacting a sidewall of the first gate stack, wherein the gate isolation region is over and in contact with the first portion of the first dummy fin.

[0070] Example 10. The device of example 9, further comprising: a second protruding semiconductor fin protruding higher than the top surface of the isolation region; and a second gate stack on the second protruding semiconductor fin, wherein the second gate stack is separated from the first gate stack by the gate isolation region.

[0071] Example 11. The device of example 8, wherein the semiconductor region contacts sidewalls of the second portion of the first dummy fin.

[0072] Example 12. The device of example 8, wherein a ratio of the second height to the first height is in a range between about 0.3 and about 0.7.

[0073] Example 13. The device of example 8, wherein the first portion of the first dummy fin has a first bottom width and a first top width, the first top width being equal to the first bottom width, and wherein the second portion of the first dummy fin has a second bottom width and a second top width, the second top width being less than the second bottom width.

[0074] Example 14. The device of example 8, further comprising: a second dummy fin protruding higher than a top surface of the isolation region, wherein the second dummy fin further comprises a third portion and a fourth portion, wherein the fourth portion of the second dummy fin and the second portion of the first dummy fin are on opposite sides of the semiconductor region, and a second height of the second portion of the first dummy fin is greater than a third height of the fourth portion of the second dummy fin.

[0075] Example 15. The device of example 14, wherein the first dummy fin and the second dummy fin are parallel to each other.

[0076] Example 16. A semiconductor device comprising: an isolation region on a semiconductor substrate; a dummy fin protruding higher than a top surface of the isolation region, wherein the dummy fin comprises: a first portion having a first height; and a second portion having a second height less than the first height; and first and second source / drain regions contacting opposite sidewalls of the second portion of the dummy fin.

[0077] Example 17. The device of example 16, further comprising: a first fin field effect transistor (FinFET) comprising a first protruding semiconductor fin and the first source / drain region; and a second FinFET comprising a second protruding semiconductor fin on an opposite side of the dummy fin from the first protruding semiconductor fin, wherein the second FinFET comprises the second source / drain region.

[0078] Example 18. The device of example 17, wherein the first FinFET and the second FinFET have opposite conductivity types.

[0079] Example 19. The device of example 17, wherein the first FinFET and the second FinFET have the same conductivity type.

[0080] Example 20. The device of example 16, wherein the second height is less than about 90% of the first height.

Claims

1. A method for forming a semiconductor device, comprising: forming a plurality of first protruding semiconductor fins; removing one or more of the plurality of first protruding semiconductor fins to form a dummy fin in contact with a semiconductor substrate, the first protruding semiconductor fins and dummy fin protruding higher than a top surface of an isolation region, wherein the first protruding semiconductor fins are parallel to the dummy fin, wherein the first protruding semiconductor fins have a first height; forming a gate stack on a first portion of the first protruding semiconductor fins and a second portion of the dummy fin; recessing a third portion of the first protruding semiconductor fins to form a recess; recessing a fourth portion of the dummy fin to reduce a height of the fourth portion of the dummy fin to a second height, the second height being less than the first height; and forming an epitaxial semiconductor region in the recess, wherein the epitaxial semiconductor region grows towards the dummy fin, wherein the second portion of the dummy fin has a first bottom width and a first top width, the first top width being equal to the first bottom width, and wherein the fourth portion of the dummy fin has a second bottom width and a second top width, the second top width being less than the second bottom width.

2. The method of claim 1, wherein, The fourth portion of the dummy fin has a height equal to the first height prior to recessing the fourth portion.

3. The method of claim 1, wherein, Recessing the third portion of the first protruding semiconductor fins and recessing the fourth portion of the dummy fin are performed in a common etch process.

4. The method of claim 3, wherein, A ratio of a first etch rate of the third portion of the first protruding semiconductor fins to a second etch rate of the fourth portion of the dummy fin is in a range between 0.1 and 5.

5. The method of claim 1, wherein, When the fourth portion of the dummy fin is recessed, a second portion of the dummy fin directly below the gate stack is protected from being etched.

6. The method of claim 1, wherein, Recessing the third portion of the first protruding semiconductor fins and recessing the fourth portion of the dummy fin are performed in different etch processes.

7. The method of claim 1, wherein, The height of the fourth portion of the dummy fin is reduced by more than 30% and less than 70%.

8. A semiconductor device, comprising: an isolation region on a semiconductor substrate; a first protruding semiconductor fin protruding higher than a top surface of the isolation region, wherein the first protruding semiconductor fin has a first height; a semiconductor region connected to an end of the first protruding semiconductor fin; and a first dummy fin in contact with the semiconductor substrate and protruding higher than the top surface of the isolation region, wherein the first dummy fin comprises: a first portion having a second height; and a second portion having a third height less than both the first height and the second height, wherein the semiconductor region laterally expands towards the second portion of the first dummy fin, wherein the first portion of the first dummy fin has a first bottom width and a first top width, the first top width being equal to the first bottom width, and wherein the second portion of the first dummy fin has a second bottom width and a second top width, the second top width being less than the second bottom width.

9. The device of claim 8, further comprising: a first gate stack on the first protruding semiconductor fin; and a gate isolation region contacting a sidewall of the first gate stack, wherein the gate isolation region is over and in contact with the first portion of the first dummy fin.

10. The device of claim 9, further comprising: a second protruding semiconductor fin protruding higher than a top surface of the isolation region; and a second gate stack on the second protruding semiconductor fin, wherein the second gate stack is separated from the first gate stack by the gate isolation region.

11. The device of claim 8, wherein, the semiconductor region contacts sidewalls of the second portion of the first dummy fin.

12. The device of claim 8, wherein, a ratio of the third height to the second height is in a range between 0.3 and 0.

7.

13. The device of claim 8, further comprising: a second dummy fin protruding higher than a top surface of the isolation region, wherein the second dummy fin further comprises a third portion and a fourth portion, wherein the fourth portion of the second dummy fin and the second portion of the first dummy fin are on opposite sides of the semiconductor region, and a third height of the second portion of the first dummy fin is greater than a fourth height of the fourth portion of the second dummy fin.

14. The device of claim 13, wherein, the first dummy fin and the second dummy fin are parallel to each other.

15. A semiconductor device, comprising: an isolation region on a semiconductor substrate; a semiconductor fin protruding higher than the isolation region, wherein the semiconductor fin comprises a first top surface a dummy fin contacting the semiconductor substrate and protruding higher than a top surface of the isolation region, wherein the dummy fin comprises: a first portion comprising a second top surface that is flush with the first top surface; and a second portion comprising a third top surface that is lower than the first top surface; and a first source / drain region and a second source / drain region contacting opposite sidewalls of the second portion of the dummy fin, wherein the first portion of the dummy fin has a first bottom width and a first top width, the first top width being equal to the first bottom width, and wherein the second portion of the dummy fin has a second bottom width and a second top width, the second top width being less than the second bottom width.

16. The device of claim 15, further comprising: a first fin field effect transistor (FinFET) comprising the first protruding semiconductor fin and the first source / drain region; and a second FinFET comprising the second protruding semiconductor fin and the second source / drain region. a second FinFET including a second protruding semiconductor fin on an opposite side of the dummy fin from the first protruding semiconductor fin, wherein the second FinFET includes the second source / drain region.

17. The device of claim 16, wherein, The first FinFET and the second FinFET have opposite conductivity types.

18. The device of claim 16, wherein, The first FinFET and the second FinFET have the same conductivity type.

19. The device of claim 15, wherein, The second portion of the dummy fin has a second height that is less than 90% of a first height of the first portion. The first FinFET and the second FinFET have opposite conductivity types. The first FinFET and the second FinFET have the same conductivity type. The second portion of the dummy fin has a second height that is less than 90% of a first height of the first portion.

Images