Self-aligned gate isolation with asymmetric cut layout

Abstract

A method of forming a semiconductor structure includes forming fins over a substrate, forming shallow trench isolation regions around the fins, and forming nanosheet stacks that provide channels for nanosheet field effect transistors. The method also includes forming a channel protection liner over sidewalls and a portion of a top surface of a first nanosheet stack formed on a first fin, the channel protection liner further formed over a portion of the shallow trench isolation regions extending from the sidewalls of the first nanosheet stack to a second nanosheet stack formed on a second fin. The method also includes forming a gate stack around exposed portions of the nanosheet stacks, forming asymmetric self-aligned gate isolation structures over the channel protection liner, and forming symmetric self-aligned gate isolation structures over a portion of the shallow trench isolation regions between a third fin and a fourth fin.

Description

BACKGROUND

[0001] The present invention relates to semiconductors, and more specifically, to techniques for forming semiconductor structures. Semiconductors and integrated circuit chips have become ubiquitous in many products, particularly as they continue to decrease in cost and size. There is a continuing need to decrease the size of structural features and / or to provide a greater number of structural features for a given chip size. In general, miniaturization allows increased performance at lower power levels and lower cost. Current technology is at or near atomic-scale dimensions for certain micro devices, such as logic gates, field effect transistors (FETs), and capacitors. SUMMARY

[0002] Embodiments of the present invention provide techniques for forming self-aligned gate isolation structures with symmetric and asymmetric cut layouts.

[0003] In one embodiment, a method of forming a semiconductor structure includes forming a plurality of fins over a top surface of a substrate, forming a shallow trench isolation region around the plurality of fins over the top surface of the substrate, and forming a plurality of nanosheet stacks of channel material over the plurality of fins, the plurality of nanosheet stacks providing a channel for one or more nanosheet field effect transistors. The method further includes forming a channel protection liner over at least a portion of a sidewall and a top surface of a first nanosheet stack of the plurality of nanosheet stacks formed over a first fin of the plurality of fins, the channel protection liner further formed over a portion of the shallow trench isolation region extending from the portion of the sidewall of the first nanosheet stack toward a second nanosheet stack of the plurality of nanosheet stacks formed over a second fin of the plurality of fins. The method further includes forming a plurality of gate stacks around portions of the plurality of nanosheet stacks of channel material exposed by the channel protection liner, forming at least one asymmetric self-aligned gate isolation structure over the channel protection liner, and forming at least one symmetric self-aligned gate isolation structure over a portion of the shallow trench isolation region between a third fin of the plurality of fins and a fourth fin of the plurality of fins.

[0004] In another embodiment, a semiconductor structure includes a substrate, a plurality of fins disposed on a top surface of the substrate, a shallow trench isolation region disposed on the top surface of the substrate around the plurality of fins, and a plurality of nanosheet stacks of channel material disposed on the plurality of fins, the plurality of nanosheet stacks providing a channel for one or more nanosheet field effect transistors. The semiconductor structure further includes a channel protection liner disposed on at least a portion of a sidewall and a top surface of a first nanosheet stack of the plurality of nanosheet stacks, the first nanosheet stack disposed on a first fin of the plurality of fins, the channel protection liner further disposed on a portion of the shallow trench isolation region extending from the portion of the sidewall of the first nanosheet stack toward a second nanosheet stack of the plurality of nanosheet stacks, the second nanosheet stack disposed on a second fin of the plurality of fins. The semiconductor structure further includes a plurality of gate stacks around portions of the plurality of nanosheet stacks exposed by the channel protection liner, at least one asymmetric self-aligned gate isolation structure disposed on the channel protection liner, and at least one symmetric self-aligned gate isolation structure disposed on a portion of the shallow trench isolation region between a third fin of the plurality of fins and a fourth fin of the plurality of fins.

[0005] In another embodiment, an integrated circuit includes a nanosheet field effect transistor structure including a substrate, a plurality of fins disposed on a top surface of the substrate, a shallow trench isolation region disposed on the top surface of the substrate around the plurality of fins, and a plurality of nanosheet stacks of channel material disposed on the plurality of fins, the plurality of nanosheet stacks providing a channel for one or more nanosheet field effect transistors. The nanosheet field effect transistor structure further includes a channel protection liner disposed on at least a portion of a sidewall and a top surface of a first nanosheet stack of the plurality of nanosheet stacks, the first nanosheet stack disposed on a first fin of the plurality of fins, the channel protection liner further disposed on a portion of the shallow trench isolation region extending from the portion of the sidewall of the first nanosheet stack toward a second nanosheet stack of the plurality of nanosheet stacks, the second nanosheet stack disposed on a second fin of the plurality of fins. The nanosheet field effect transistor structure further includes a plurality of gate stacks around portions of the plurality of nanosheet stacks exposed by the channel protection liner, at least one asymmetric self-aligned gate isolation structure disposed on the channel protection liner, and at least one symmetric self-aligned gate isolation structure disposed on a portion of the shallow trench isolation region between a third fin of the plurality of fins and a fourth fin of the plurality of fins. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1A A top view depicting an aligned gate cut between two fins according to embodiments of the application.

[0007] Figure 1B A top view depicting misalignment and exaggerated gate cuts between two fins according to embodiments of the application.

[0008] Figure 2 A top view depicting asymmetric gate cuts in the topology of a static random access memory structure according to embodiments of the application.

[0009] Figure 3A A side view cross-sectional view of a semiconductor structure after patterning of nanosheet layers according to embodiments of the application.

[0010] Figure 3B A top view depicting a portion of a structure according to embodiments of the application. Figure 3A

[0011] Figure 4 A side view cross-sectional view of a structure after forming a channel protection liner, dummy gate, and gate hardmask according to embodiments of the application. Figure 3A

[0012] Figure 5A A first side view cross-sectional view of a structure after forming source / drain regions and planarization according to embodiments of the application. Figure 4

[0013] A second side view cross-sectional view of a structure after forming source / drain regions and planarization according to embodiments of the application. Figure 5B Figure 4 A side view cross-sectional view of a structure after removing a dummy gate according to embodiments of the application.

[0014] Figure 6 Figure 5A A side view cross-sectional view of a structure after patterning of a channel protection liner according to embodiments of the application.

[0015] Figure 7 A side view cross-sectional view of a structure after selective growth of a sacrificial nanosheet material according to embodiments of the application. Figure 6

[0016] A side view cross-sectional view of a structure after forming a self-aligned isolation layer according to embodiments of the application. Figure 8 Figure 7 A side view cross-sectional view of a structure after forming an organic planarization layer according to embodiments of the application.

[0017] Figure 9 Figure 8 A side view cross-sectional view of a structure after forming a self-aligned isolation layer according to embodiments of the application.

[0018] Figure 10 A side view cross-sectional view of a structure after forming an organic planarization layer according to embodiments of the application. Figure 9 ​​​​​​Side view of the structure.

[0019] Figure 11 The image depicts the patterning of symmetrical and asymmetrical gate cutouts according to embodiments of the present invention. Figure 10 Side view of the structure.

[0020] Figure 12 Depicting, according to embodiments of the present invention, the following after filling symmetrical and asymmetrical gate cutouts with dielectric material. Figure 11 Side view of the structure.

[0021] Figure 13 The image depicts the process after removing the organic planarization layer and sacrificial nanosheet material, according to an embodiment of the invention. Figure 12 A side view of the structure.

[0022] Figure 14 Depicting the process after forming the gate structure according to an embodiment of the present invention. Figure 13 A side view of the structure. Detailed Implementation

[0023] The illustrative embodiments of the present invention can be described herein in the context of an illustrative method for performing self-aligned gate isolation having symmetrical and asymmetrical cut layouts. However, it should be understood that the embodiments of the present invention are not limited to the illustrative methods, apparatus, systems, and devices, but rather can be applied more broadly to other suitable methods, apparatus, systems, and devices.

[0024] A FET is a transistor with a source, a gate, and a drain, and it has the effect of controlling the flow of majority carriers along a channel that runs between the source and drain and through the gate. The current through the channel between the source and drain can be controlled by a lateral electric field under the gate. The length of the gate determines how fast the FET switches and can be approximately the same as the length of the channel (e.g., the distance between the source and drain).

[0025] In some FETs, more than one gate or a multi-gate arrangement can be used to control the channel. Multi-gate FETs are promising candidates for scaling down complementary metal-oxide-semiconductor (CMOS) FET technology. However, the smaller size associated with multi-gate FETs (compared to single-gate FETs) requires greater control over performance issues such as short-channel effects, punch-through, MOS leakage current, and parasitic resistance present in multi-gate FETs.

[0026] Various techniques can be used to reduce the size of FETs. One technique is through the use of fin-shaped channels in FinFET devices. Prior to the advent of FinFET arrangements, CMOS devices were generally planar along the surface of the semiconductor substrate, in addition to the FET gate disposed on top of the channel. FinFETs utilize a vertical channel structure, increasing the surface area of the channel exposed to the gate. Thus, in a FinFET structure, the gate can more effectively control the channel, as the gate extends on more than one side or surface of the channel. In some FinFET configurations, the gate encloses three surfaces of a three-dimensional channel, rather than being disposed only on the top surface of a traditional planar channel.

[0027] Another technique for reducing FET size is through the use of stacked nanosheet channels formed on a semiconductor substrate. The stacked nanosheets can be two-dimensional nanostructures, such as thin sheets with a thickness ranging from about 1 to 100 nanometers (nm). Nanosheets and nanowires are viable options for scaling to 7 nm and beyond. The general process flow for forming a nanosheet stack involves removing a sacrificial layer between sheets of channel material, which can be formed of silicon germanium (SiGe), that can be formed of silicon (Si).

[0028] As the cell height scales, techniques for performing gate cuts do not meet the requirements, as the spacing between active areas is too small. A process known as self-aligned gate cut or self-aligned gate isolation can be used to scale active-to-active spacing to 5 nm and beyond. However, SAGE-induced gate cuts are not ideal in certain situations that require the use of asymmetric gate cuts. For example, static random access memory (SRAM) devices can utilize asymmetric gate cuts.

[0029] Figure 1A A top-down view 100 of an aligned gate cut 101 performed between two fins in a set of fins 102 on one of the two gate structures 104 is depicted. The aligned gate cut 101 represents an ideal case in which the gate cut 101 is perfectly aligned between adjacent fins 104 and has a small critical dimension 103 (e.g., in the range of 6 to 15 nm). Figure 1B A top-down view 150 of a misaligned gate cut 110 performed between two fins in a set of fins 102 on one of the two gate structures 104 is depicted. As depicted, the gate cut 110 is not perfectly aligned, as it is closer to one of the two adjacent fins 102 than the other. The misaligned gate cut 110 also has a larger critical dimension 130 (e.g., in the range of 15 to 40 nm).

[0030] To scale to 5 nm and beyond, the cell height 105 of twice the gate cut 101 to fin 104 spacing plus the critical dimension 103 of the gate cut 101 is about 40 nm with allowed variations. The gate cut 101 to fin 104 spacing should not pinch off, where the required spacing is twice the thickness of the gate stack including the high-k gate dielectric and work function metal (WFM) gate conductor (e.g., 2x(2+5) = 14 nm). Furthermore, assuming a total variation of the fin critical dimension uniformity (CDU), fin pitch walking (PW), gate cut CDU, and gate cut coverage parameters are tightly controlled to only 5 nm. Therefore, the CD of the gate cut 101 should be about 40 nm - (2x14 nm) - 5 nm = 7 nm, which is not achievable using conventional photolithography processes.

[0031] As noted above, self-aligned gate cut or self-aligned gate isolation techniques can be used for future cell height scaling. A self-aligned gate cut process flow can include fin patterning (e.g., fin and fin patterning of other layers including a passivation layer, a polysilicon layer, and a hardmask layer). Next, a liner dielectric can be formed, followed by a shallow trench isolation (STI) region. The STI region can then be recessed (e.g., perform fin reveal), followed by a dummy gate dielectric formation. A spacer (e.g., of polysilicon) is then formed, which merges or separates depending on the fin spacing. An isolation plug is then formed. The dummy gate is then patterned using a gate hardmask and a technique such as self-aligned double patterning (SADP). An anisotropic etch is then performed, where the anisotropic etch is selective to the isolation plug, the dummy gate dielectric, and the gate hardmask. In this way, symmetric gate cuts can be performed.

[0032] However, the self-aligned gate cut process is not suitable for forming asymmetric gate cuts, which are needed in some application scenarios. For example, as noted above, SRAM structures can utilize asymmetric gate cuts. SRAM is a type of memory device that provides high speed, low power consumption, and simple operation. Unlike dynamic random access memory (DRAM), SRAM does not require periodic refresh of stored data, and has a straightforward design. SRAM cells can be formed using different numbers of transistors.

[0033] Six-transistor (6T) SRAM cells are widely used as primary memory in microprocessor circuits. A 6T SRAM cell can include a first n-type FET device (nFET) connected to a first bit line node (BL), a first output node (Q), and a word line node (WL). A second nFET device of the 6T SRAM cell is connected to the Q node, a ground node (e.g., VSS), and a second output node (Q’). A first p-type FET device (pFET) is connected to the Q node, the Q’ node, and a voltage source or power supply node (e.g., VDD). A second pFET device is connected to the VDD node, the Q node, and the Q’ node. A third nFET device is connected to the VSS node, the Q node, and the Q’ node. A fourth nFET device is connected to a second bit line node (BLB), the WL node, and the Q’ node. The first and fourth nFET devices are pass-gate (PG) transistors of the 6T SRAM cell, the second and third nFET devices are pull-down (PD) transistors of the 6T SRAM cell, and the first and second pFET devices are pull-up (PU) transistors of the 6T SRAM cell.

[0034] Figure 2 A top view 200 of asymmetric gate cuts 209-1 and 209-2 of an SRAM cell is described. In the top view 200, element 201 shows a VSS (e.g., 0 volts (V) or “ground” voltage) connection, while element 203 shows a VDD (e.g., a positive power supply voltage) connection. Elements 205-1 and 205-2 show WL connections of the SRAM cell, while elements 207-1 and 207-2 show bit line connections (e.g., BL and BLB, respectively) of the SRAM cell. Elements 209-1 and 209-2 show asymmetric gate cuts that are disposed closer to one of the two adjacent fins rather than being symmetrically formed between the two adjacent fins.

[0035] The illustrative processes for performing self-aligned gate isolation with symmetric and asymmetric cut arrangements will now be described in more detail with reference to FIGS. 3-14.

[0036] Figure 3A A side cross-sectional view 300 of a semiconductor structure after patterning of a nanosheet stack on a substrate 302 is shown. A set of fins 304-1 through 304-5 (collectively, fins 304) is formed over the substrate 302. The set of fins 304 is surrounded by an STI region 306. A nanosheet stack including alternating layers 308 and 310 of sacrificial material and channel material is formed over each fin 304. While Figure 3A An example is shown in which there are three sacrificial layers 308 and three channel layers 310 in each nanosheet stack, but it should be understood that this is merely an example, and a nanosheet stack can include more or less than three sets of alternating layers of sacrificial material and channel material.

[0037] The substrate 302 can be a semiconductor structure formed of bulk silicon (Si), although other suitable materials can be used, such as various silicon-containing materials. Illustrative examples of silicon-containing materials suitable for the substrate 302 include, but are not limited to, Si, silicon germanium (SiGe), silicon germanium carbon (SiGeC), silicon carbide (SiC), polysilicon, epitaxial silicon, amorphous silicon, and multilayers thereof. Although silicon is the predominant semiconductor material used in wafer fabrication, alternative semiconductor materials can be employed, such as, but not limited to, germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), cadmium telluride (CdTe), and zinc selenide (ZnSe). In alternative embodiments, the substrate 302 can be a silicon-on-insulator (SOI) wafer. As is well known in the art, an SOI wafer includes an SOI layer separated from a substrate by a buried insulator. Suitable substrate materials include, but are not limited to, Si, strained Si, silicon carbide (SiC), Ge, SiGe, SiGeC, Si alloys, Ge alloys, GaAs, indium arsenide (InAs), indium phosphide (InP), or any combination thereof. Suitable dielectric materials for the buried insulator include, but are not limited to, oxide materials, such as silicon dioxide (SiO2). When the buried insulator is an oxide, the buried insulator can also be referred to as a buried oxide or BOX.

[0038] The substrate 302 can have a width or horizontal thickness (in the direction X-X') that varies as desired (e.g., based on the number of fins 304 or other device structures to be formed). The substrate 302 can have a height or vertical thickness (in the Y-Y' direction) ranging from 300 micrometers (pm) to 1000 pm.

[0039] The fins 304 can be formed of the same material as the underlying substrate 302. For example, in some embodiments, the fins 304 are formed from a bulk substrate using photolithography and etching (e.g., reactive ion etching (RIE)). Other suitable techniques such as sidewall image transfer (SIT), self-aligned double patterning (SADP), self-aligned multiple patterning (SAMP), self-aligned quadruple patterning (SAQP), etc. can be used to form the fins 304. In such cases, the fins 304 can be formed of the same material (e.g., Si) as the substrate 302. Alternatively, the fins 304 can be formed of a different material than the substrate 302 by first epitaxially growing the different material on the substrate 302 and then patterning to form the fins 304. For example, the fins 304 can be silicon germanium (SiGe) and the substrate 302 can be Si.

[0040] Each fin 304 may have a vertical thickness or height (in the Y-Y' direction) ranging from 20 to 35 nm and a horizontal thickness or width (in the X-X' direction) varying from 6 to 100 nm. For example... Figure 3A As shown, the different fins in fin 304 have different widths (e.g., fins 304-1, 304-2, and 304-3 are larger than fins 304-4 and 304-5 in the X-X' direction). The spacing between fins 304 can also vary, as will be described in further detail below.

[0041] The STI layer 306 can be formed of a dielectric material such as silicon oxide (SiOx), silicon nitride (SiN), silicon oxycarbide (SiOC), silicon oxynitride (SiON), or any other suitable dielectric material. The vertical thickness or height (in the Y-Y' direction) of the STI layer 306 is defined by the fin exposure treatment and will approximately match the horizontal level of the bottom surface of the nanosheet stack. As shown, the horizontal thickness or width (in the X-X' direction) of the STI layer 306 is defined by the spacing between the fins 304.

[0042] As described above, the nanosheet stack comprises alternating layers of sacrificial material 308 and channel material 310. The sacrificial layer 308 can be formed of any suitable material that can be selectively etched relative to the channel material 310. If the channel material 310 is Si, then the sacrificial layer 308 can be SiGe. If the channel material 310 is indium gallium arsenide (InGaAs), then the sacrificial layer 308 can be indium aluminum arsenide (InAlAs). Various other combinations of III-V materials can be used. The material of the sacrificial layer 308 is one that can be selectively removed relative to the material of the channel layer 310. The sacrificial layer 308 and the channel layer 310 can each have a thickness in the range of 4 nm to 15 nm. The nanosheet stack of the sacrificial layer 308 and the channel layer 310 can be epitaxially grown on the fin 304.

[0043] Figure 3A Two regions, denoted as 301 and 303, of the nanosheet stack formed on a common substrate 302 are shown. Region 301 is referred to herein as the "logic" region, and fins 304-1 and 304-2 provide nFET or pFET devices as needed for the logic devices of the resulting structure. Region 303 is referred to herein as the "SRAM" region, wherein fins 304-3, 304-4, and 304-5 provide nFET and pFET devices for forming SRAM cells (e.g., as shown in the diagram). Figure 2(As shown in top view 200). In some embodiments, fin 304-3 provides an nFET device, while fins 304-4 and 304-5 provide pFET devices. The spacing between fin 304-3 providing the nFET device and fin 304-4 providing the pFET device is... Figure 3A The element 305, represented in the diagram, can be approximately 40 nm. The width of the fin 304-4 is... Figure 3A The element 307, represented in the diagram, can be approximately 15 nm. The spacing between fins 304-4 and 304-5, which provide the pFET device, is [missing information]. Figure 3A The element 309 is represented in the image and can be approximately 30 nm.

[0044] Figure 3B It shows the result of Figure 3A The top view 350 shows the region 303 of the SRAM cell formed by the structure shown in the side cross-sectional view 300. Figure 3A Side view section 300 (and Figure 4 , 5A The side view section (6-14) is taken transversely or perpendicularly to fin 304.

[0045] Figure 4 This illustrates the process after forming the channel protection pad 312, the dummy gate 314, and the gate hard mask 316. Figure 3A A side cross-sectional view of the structure is shown in Figure 400. As shown, a channel protection liner 312 is formed on the STI region 306 and surrounds the nanosheet stack. The channel protection liner 312, also referred to as the pseudo-gate oxide layer 312, can have a uniform thickness in the range of 2 to 5 nm. The channel protection liner 312 can be formed using atomic layer deposition (ALD) or other suitable techniques. The channel protection liner 312 can be formed of an oxide, such as silicon dioxide (SiO2).

[0046] A dummy gate 314 is formed on the channel protection pad 312, filling the space between the nanosheet stacks and overfilling the structure. Measured from the channel protection pad 312 formed on the STI region 306, the dummy gate 314 can have a height or vertical thickness (in the Y-Y' direction) in the range of 60 to 200 nm. The dummy gate 314 can be formed from amorphous silicon (a-Si) or other suitable materials such as amorphous silicon germanium (a-SiGe), polycrystalline silicon (poly-Si), polycrystalline silicon germanium (poly-SiGe), etc. The dummy gate 314 can be formed using ALD, chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable processes.

[0047] A gate hard mask 316 is patterned on top of the dummy gate 314 (e.g., in the region where the gate for the resulting structure will be formed). The gate hard mask 316 can be formed using CVD, PVD, or other suitable processes. The gate hard mask 316 can be formed from SiO2, SiN, combinations thereof, etc. The gate hard mask 316 can have a height or vertical thickness (in the Y-Y' direction) in the range of 20 to 120 nm.

[0048] Figure 5A This shows the result after the source / drain region 318 is formed and flattened. Figure 4 First side view section of the structure, 500. Figure 5B This shows the process after the formation of source / drain region 318. Figure 4 Second side view of the structure, Figure 550. Figure 5B Also shown is a first spacer 320 formed between the sacrificial layer 308 and the source / drain region 318, and a second spacer 322 formed between the dummy gate 314 and the interlayer dielectric (ILD) 316. As described above, Figure 5A The side view section 500 is taken transversely or perpendicularly to the fin 304. Figure 5B The side view section 550 is taken along or parallel to one of the fins 304.

[0049] The source / drain regions 318 can be formed using epitaxial growth processes. In some embodiments, the epitaxial growth process includes in-situ doping (dopants are incorporated into the epitaxial material during epitaxy). The epitaxial material can be grown from a gaseous or liquid precursor. The epitaxial material can be grown using vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), rapid thermal chemical vapor deposition (RTCVD), metal-organic chemical vapor deposition (MOCVD), ultra-high vacuum chemical vapor deposition (UHVCVD), low-pressure chemical vapor deposition (LPCVD), finite reaction process CVD (LRPCVD), or other suitable processes. Epitaxial silicon, silicon-germanium (SiGe), germanium (Ge), and / or carbon-doped silicon (Si:C) can be doped during deposition by adding dopants (in-situ doping), such dopants being n-type dopants (e.g., phosphorus (P), arsenic (As), antimony (Sb), etc.) or p-type dopants (e.g., boron (B), boron fluoride (BF2), gallium (Ga), indium (In), thallium (TI), etc.), depending on the transistor type. The dopant concentration in the source / drain can be 1 × 10⁻⁶. 19 cm -3 Up to 3×10 21 cm -3 Within the range, or preferably within 2×10 20 cm -3 Up to 3×10 21 cm -3between.

[0050] The spacers 322 can be formed by depositing a conformal spacer liner, followed by an anisotropic spacer RIE. The spacers 320 can be formed by recessing the nanosheet stacks, followed by selective recessing of the sacrificial layers 308 of the nanosheet stacks (e.g., where the sacrificial layers 308 can be formed of SiGe, and the channel layers 310 can be formed of Si, as described above). The spacer material for the spacers 320 can then be filled in the recesses with a conformal spacer liner, with an isotropic etch process used to remove the spacer liner elsewhere. The spacers 320 and 322 can be formed of SiN, silicon carbon oxynitride (SiOCN), silicon carbon oxide (SiOC), SiC, silicon carbon nitride boron (SiBCN), etc., respectively.

[0051] Figure 6 A side cross-sectional view 600 of the structure is shown after removal of the dummy gate 314. Figure 5A The dummy gate 314 can be removed using a selective wet or dry etch process, such as a hot ammonia rinse. Removal of the dummy gate 314 exposes the channel protection liner 312.

[0052] Figure 7 A side cross-sectional view 700 of the structure is shown after patterning the channel protection liner 312 using the dummy oxide mask layer 324. Figure 6 The dummy oxide mask layer 324 is patterned on the portion of the fin 304-4 facing the fin 304-3 (e.g., for an SRAM device, the dummy oxide mask layer 324 protects the SRAM pFET side facing an nFET provided using the fin 304-3). The dummy oxide mask layer 324 can be formed and patterned using photolithography and etching or other suitable techniques.

[0053] The dummy oxide mask layer 324 can be formed of an organic planarization (OPL) material, such as a polyacrylate resin, an epoxy resin, a phenol formaldehyde resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, benzocyclobutene (BCB), etc. The dummy oxide mask layer 324 can be formed using spin coating or other suitable processes. The dummy oxide mask layer 324 can have a height or vertical thickness (in the Y-Y' direction) ranging from 60 to 200 nm, measured from the top of the channel protection liner 312 formed over the STI region 306. The width or horizontal thickness (in the X-X' direction) of the dummy oxide mask layer 324 can vary, e.g., based on the width of the fin 304-4 and the spacing between the fins 304-3 and 304-4. As shown in the cross-sectional view 700, the dummy oxide mask layer 324 can be patterned to expose the channel protection liner 312 on the portion of the fin 304-4 facing the fin 304-3. Figure 7As shown, the pseudo-oxide mask layer 324 extends from the middle of the top of the nanosheet stack on fin 304-4 to the middle of the STI region 306 between fins 304-3 and 304-4.

[0054] After the patterned pseudo-oxide mask layer 324, the channel protection pad 312 exposed by the patterned pseudo-oxide mask layer 324 is removed, for example, using an isotropic oxide dry etching process.

[0055] Figure 8 This illustrates the selective epitaxial growth 326 of a material (e.g., SiGe) after removing the patterned pseudo-oxide mask layer 324 (e.g., using ashing) and the sacrificial layer 308 of the nanosheet stack. Figure 7 Side cross-sectional view of the structure, 800. As shown, material 326 is grown on the exposed surface of the nanosheet stack not covered by the remaining channel protection liner 312. The epitaxial growth of material 326 can have a uniform thickness in the range of 5 to 30 nm.

[0056] Figure 9 This shows the process after the formation of the self-aligned isolation layer 328. Figure 8 Side cross-sectional view 900 of the structure. The self-aligned isolation layer 328 can be formed of a dielectric material such as SiO2, SiN, SiOCN, SiOC, SiC, SiBCN, etc. The self-aligned isolation layer 328 can be formed by depositing the dielectric material into the gap and then etching it back to the level of the top surface of the exposed material 326 as described above. The isolation layer 328 is self-aligned because it fills the gap between the material 326 on the STI region 306 and the remaining channel protection gasket 312.

[0057] Figure 10 This shows the result after the formation of OPL 330 on top of the self-aligned isolation layer 328 and material 326. Figure 9 The structure is shown in side cross-sectional view 1000. OPL 330 can be formed using spin coating with a material similar to that described above regarding pseudo-oxide mask layer 324. OPL 330 can have a height or vertical thickness (in the Y-Y' direction) in the range of 20 to 100 nm.

[0058] Figure 11 This shows the patterned gate notch in the OPL 330. Figure 10 Side section view of the structure, 1100. More specifically, Figure 11Symmetric gate cuts 1101 formed in OPL 330 in logic region 301 are shown, as well as asymmetric gate cuts 1103 formed in OPL 330 in SRAM region 303. Symmetric gate cuts 1101 and asymmetric gate cuts 1103 can be formed by patterning a mask on OPL 330 and etching exposed portions of OPL 330 to reveal portions of the underlying self-aligned spacer layer 328. Symmetric gate cuts 1101 and asymmetric gate cuts 1103 can be defined using photolithography. Asymmetric gate cuts 1103 expose portions of self-aligned spacer layer 328. Spacer layer 328 is self-aligned, so asymmetric gate cuts 1103 can therefore be considered self-aligned. As described elsewhere herein, in some embodiments, asymmetric gate cuts 1103 can be formed between fin 304-3, which provides an SRAM nFET device, and fin 304-4, which provides an SRAM pFET device. The portions of self-aligned spacer layer 328 exposed by asymmetric gate cuts 1103 are proximate to the nanosheet stack above fin 304-4, and so asymmetric gate cuts 1103 can be referred to as self-aligned asymmetric gate cuts.

[0059] Symmetric gate cuts 1101 expose self-aligned spacer layer 328 formed between fins 304-1 and 304-2 in logic region 301. Symmetric gate cuts 1101 can have a width or horizontal thickness (in direction X-X’) in the range of 15 to 35 nm.

[0060] As shown, asymmetric gate cuts 1103 expose at least a portion of self-aligned spacer layer 328 formed on remaining channel protection spacer 312. Asymmetric gate cuts 1103 can have a width or horizontal thickness (in direction X-X’) in the range of 15 to 35 nm.

[0061] Figure 12 A side view cross-sectional view 1200 of the structure after filling symmetric gate cuts 1101 and asymmetric gate cuts 1103 with dielectric material 332 is shown. Figure 11 Dielectric material 332 can include SiN, SiCO, SiC, or another suitable material.

[0062] Figure 13 A side view cross-sectional view 1300 of the structure after removing OPL 330 and sacrificial materials (e.g., sacrificial nanosheets 308 and material 326) is shown. Figure 12 OPL 330 can be removed using ashing. Sacrificial materials (e.g., 308 and 326) are removed using selective etching.

[0063] Figure 14 A side view cross-sectional view 1400 of the structure after forming gate structures 334 (e.g., using a replacement metal gate (RMG) process) is shown.Figure 13 A side cross-sectional view 1400 of the structure. The gate structure 334 can include a conformally deposited gate dielectric layer, followed by a gate conductor layer.

[0064] The gate dielectric layer can be formed of a high-k dielectric material. Examples of high-k materials include, but are not limited to, metal oxides such as hafnium oxide (Hf02), hafnium silicon oxide (Hf-Si-O), hafnium silicon oxynitride (HfSiON), lanthanum oxide (La203), lanthanum aluminum oxide (LaAl03), zirconium oxide (Zr02), zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide (Ta205), titanium oxide (Ti02), barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide (Y203), aluminum oxide (Al203), lead scandium tantalum oxide, and lead zinc niobate. The high-k material can also include dopants such as lanthanum (La), aluminum (Al), and magnesium (Mg). The gate dielectric layer can have a uniform thickness in the range of 1 nm to 4 nm.

[0065] The gate conductor layer can include a metal gate or work function metal (WFM). In some embodiments, the gate conductor layer is formed using atomic layer deposition (ALD) or another suitable process. For nFET devices, the WFM for the gate conductor layer can be titanium (Ti), aluminum (Al), titanium aluminum (TiAl), titanium aluminum carbon (TiAlC), a combination of Ti and Al alloys, a stack including a barrier layer (such as titanium nitride (TiN) or another suitable material) followed by one or more of the foregoing WFM materials, etc. For pFET devices, the WFM for the gate conductor can be TiN, tantalum nitride (TaN), or another suitable material. In some embodiments, the pFET WFM can include a metal stack in which a thicker barrier layer (e.g., TiN, TaN, etc.) is formed followed by a WFM such as Ti, Al, TiAl, TiAlC, or any combination of Ti and Al alloys. It will be appreciated that various other materials can be used for the gate conductor layer as desired.

[0066] The processes described above with respect to FIGS. 3-14 advantageously enable the formation of structures (such as integrated circuits) having symmetric and asymmetric self-aligned gate isolation. For the gate cut region, an additional gate cut structure is formed on the self-aligned gate isolation. For the asymmetric self-aligned gate isolation, some top portions of the isolation structure are formed on top of the nanosheet stack.

[0067] The process for forming the self-aligned gate isolation includes forming a channel protection liner (e.g., pseudo-oxide layer 312), and using a mask (e.g., pseudo-oxide mask 322) to protect at least some of the channel protection liner, and removing the unprotected liner to expose the channels of the nanosheet stacks. A sacrificial liner (e.g., material 326) is formed over the exposed channels of the nanosheet stacks, followed by forming a self-aligned gate isolation (e.g., self-aligned gate isolation layer 328). A sacrificial material (e.g., OPL 330) is formed over the self-aligned gate isolation and the sacrificial liner, followed by forming gate cuts (e.g., symmetric gate cuts 1101 and asymmetric gate cuts 1103) in the sacrificial material. The sacrificial material and the sacrificial liner are then removed, followed by an RMG treatment to form the gate structures.

[0068] In some embodiments, a method of forming a semiconductor structure includes forming a plurality of fins on a top surface of a substrate, forming an STI region surrounding the plurality of fins on the top surface of the substrate, and forming a plurality of nanosheet stacks of channel material on the plurality of fins, the plurality of nanosheet stacks providing channels for one or more nanosheet FETs. The method further includes forming a channel protection liner on at least a portion of sidewalls and a top surface of a first nanosheet stack of the plurality of nanosheet stacks formed over a first fin of the plurality of fins, the channel protection liner further formed on a portion of the STI region extending from a portion of the sidewalls of the first nanosheet stack toward a second nanosheet stack of the plurality of nanosheet stacks formed over a second fin of the plurality of fins. The method further includes forming a plurality of gate stacks surrounding portions of the plurality of nanosheet stacks exposed by the channel protection liner, forming at least one asymmetric self-aligned gate isolation structure over the channel protection liner, and forming at least one symmetric self-aligned gate isolation structure over a portion of the STI region between a third fin of the plurality of fins and a fourth fin of the plurality of fins.

[0069] The asymmetric self-aligned gate isolation structure formed on the channel protection liner can include a first portion formed adjacent to the sidewalls of the first nanosheet stack and a second portion formed on a portion of the top surface of the channel protection liner surrounding the top surface of the first nanosheet stack.

[0070] The first and second nanosheet stacks provide nanosheet channels for nanosheet FETs of at least one SRAM device structure. The first nanosheet stack can provide nanosheet channels for pFETs and the second nanosheet stack provides nanosheet channels for nFETs. A third nanosheet stack of the plurality of nanosheet stacks formed on the third fin and a fourth nanosheet stack of the plurality of nanosheet stacks formed on the fourth fin can provide nanosheet channels for nanosheet FETs of one or more logic device structures.

[0071] Forming the channel protection liner can include forming the channel protection liner around the plurality of nanosheet stacks and over the STI region between the plurality of fins, forming a dummy gate structure over the channel protection liner, patterning a gate hardmask over the dummy gate structure, and removing portions of the dummy gate structure exposed by the patterned gate hardmask. Forming the channel protection liner can also include forming source / drain regions in spaces formed by the removing of the dummy gate structure, and removing remaining portions of the dummy gate structure. Forming the channel protection liner can further include patterning a mask layer on portions of the channel protection liner that are on portions of the sidewalls and top surfaces of the first nanosheet stack and portions of the STI region that extend from the portions of the sidewalls of the first nanosheet stack to the second nanosheet stack, and removing portions of the channel protection liner exposed by the patterned mask layer.

[0072] Forming the plurality of nanosheet stacks can include forming alternating layers of sacrificial material and channel material, and the method can further include selectively growing additional sacrificial material on portions of the plurality of nanosheet stacks exposed by the channel protection liner. Forming the asymmetric self-aligned gate isolation structures and the symmetric self-aligned gate structure can include forming isolation material on structures around the additional sacrificial material. Forming the asymmetric self-aligned gate isolation structures and the symmetric self-aligned gate structure can also include forming OPL on the isolation material and the additional sacrificial material. Forming the asymmetric self-aligned gate isolation structures and the symmetric self-aligned gate structure can also include patterning the OPL to expose (i) at least a portion of the isolation material formed over the channel protection liner for the asymmetric self-aligned gate isolation structures and (ii) at least a portion of the isolation material formed over the STI region between the third and fourth nanosheet stacks for the symmetric self-aligned gate structure. Forming the asymmetric self-aligned gate isolation structures and the symmetric self-aligned gate structure can also include filling additional isolation material in regions exposed by the patterning of the OPL.

[0073] Forming the plurality of gate stacks includes removing the OPL, the sacrificial material of the nanosheet channel stacks, and the additional sacrificial material. Forming the plurality of gate stacks can also include forming gate dielectric and gate conductor in spaces formed by the removing of the OPL, the sacrificial material of the nanosheet channel stacks, and the additional sacrificial material.

[0074] In some embodiments, a semiconductor structure includes a substrate, a plurality of fins disposed on a top surface of the substrate, an STI region disposed on the top surface of the substrate surrounding the plurality of fins, and a plurality of nanosheet stacks of channel material disposed on the plurality of fins, the plurality of nanosheet stacks providing channels for one or more nanosheet FETs. The semiconductor structure further includes a channel protection liner disposed on at least a portion of sidewalls and a top surface of a first nanosheet stack of the plurality of nanosheet stacks, the first nanosheet stack disposed on a first fin of the plurality of fins, the channel protection liner further disposed on a portion of the STI region extending from a portion of the sidewalls of the first nanosheet stack toward a second nanosheet stack of the plurality of nanosheet stacks, the second nanosheet stack disposed on a second fin of the plurality of fins. The semiconductor structure further includes a plurality of gate stacks surrounding portions of the plurality of nanosheet stacks exposed by the channel protection liner, at least one asymmetric self-aligned gate isolation structure disposed above the channel protection liner, and at least one symmetric self-aligned gate isolation structure disposed above a portion of the STI region between a third fin of the plurality of fins and a fourth fin of the plurality of fins.

[0075] The asymmetric self-aligned gate isolation structure disposed on the channel protection liner can include a first portion disposed about the sidewalls of the first nanosheet stack and a second portion disposed about a portion of the top surface of the first nanosheet stack on the top surface of the channel protection liner.

[0076] The first nanosheet stack and the second nanosheet stack can provide nanosheet channels for nanosheet FETs of at least one SRAM device structure. The first nanosheet stack can provide nanosheet channels for pFETs and the second nanosheet stack provides nanosheet channels for nFETs. A third nanosheet stack of the plurality of nanosheet stacks disposed on the third fin and a fourth nanosheet stack of the plurality of nanosheet stacks disposed on the fourth fin can provide nanosheet channels for nanosheet FETs of one or more logic device structures.

[0077] In some embodiments, an integrated circuit includes a nanosheet FET structure including the above-described semiconductor structure.

[0078] It should be understood that the layers, structures, and regions shown in the figures are schematic representations for purposes of explanation only. In addition, one or more layers, structures, and regions typically used in forming a type of semiconductor device or structure can not be explicitly shown in a given figure for the sake of clarity. This does not imply that any layers, structures, and regions not explicitly shown are omitted from actual semiconductor structures. Further, it is understood that embodiments discussed herein are not limited to the specific materials, features and processing steps described herein. In particular, with respect to semiconductor processing steps, it is emphasized that the description provided herein is not intended to include all processing steps that can be necessary to form a functional semiconductor integrated circuit device. Rather, for economy of description, certain processing steps commonly used in forming semiconductor devices, such as wet cleaning and annealing steps, are not described here with the intent of not limiting the embodiments.

[0079] Further, the same or like reference numerals are used in all of the figures to represent the same or like features, elements or structures, and therefore, detailed explanations of the same or like features, elements or structures are not repeated for each figure. It is understood that the terms "about" or "substantially" as used with respect to thickness, width, percentage, range, etc. used herein are intended to mean approximate or nearly, but not exact. For example, as used herein, the terms "about" or "substantially" imply a small margin of error, such as ±5%, preferably less than 2% or 1% or less than the stated amount.

[0080] In the above description, various materials and dimensions for different elements are provided. Unless otherwise specified, these materials are given by way of example only and embodiments are not limited to the specific examples given. Similarly, unless otherwise indicated, all dimensions are given by way of example only and embodiments are not limited to the specific dimensions or ranges given.

[0081] Semiconductor devices and methods of forming the same in accordance with the above-described techniques can be used in a variety of applications, hardware, and / or electronic systems. Suitable hardware and systems for implementing embodiments of the present application can include, but are not limited to, personal computers, communication networks, electronic commerce systems, portable communication devices (e.g., cellular telephones and smart phones), solid state media storage devices, functional circuits, etc. Systems and hardware incorporating semiconductor devices are contemplated embodiments of the present application. Other implementations and applications of embodiments of the present application will be apparent to persons of ordinary skill in the art given the teachings herein.

[0082] In some embodiments, the above-described techniques are used in conjunction with semiconductor devices that can require or otherwise utilize, for example, complementary metal-oxide-semiconductor (CMOS), metal-oxide-semiconductor field-effect transistor (MOSFET), and / or fin field-effect transistor (FinFET). As non-limiting examples, the semiconductor devices can include, but are not limited to, CMOS, MOSFET, and FinFET devices, and / or semiconductor devices that use CMOS, MOSFET, and / or FinFET technology.

[0083] The various structures described above can be implemented in integrated circuits. The manufacturer can distribute the resulting integrated circuit chips in original wafer form (i.e., as a single wafer having a plurality of unpackaged chips), as bare chips, or in packages. In the latter case, the chips are mounted in single chip packages (e.g., a plastic carrier with leads that are affixed to a motherboard or other higher level carrier) or in multi-chip packages (e.g., a ceramic carrier with one or more of its surfaces covered with a layer of solder) to which an individual chip is affixed. In any case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of either (a) an intermediate product (e.g., motherboard) or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0084] The description of various embodiments of the present application has been presented for purposes of illustration but is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A method of forming a semiconductor structure, comprising: forming a plurality of fins over a top surface of a substrate; forming a shallow trench isolation region over the top surface of the substrate around the plurality of fins; forming a plurality of nanosheet stacks of channel material over the plurality of fins, the plurality of nanosheet stacks providing a channel for one or more nanosheet field effect transistors; forming a channel protection liner over at least a portion of a sidewall and a top surface of a first nanosheet stack of the plurality of nanosheet stacks formed over a first fin of the plurality of fins, the channel protection liner further formed over a portion of the shallow trench isolation region extending from the portion of the sidewall of the first nanosheet stack toward a second nanosheet stack of the plurality of nanosheet stacks formed over a second fin of the plurality of fins; forming a plurality of gate stacks around portions of the plurality of nanosheet stacks exposed by the channel protection liner; forming at least one asymmetric self-aligned gate isolation structure over the channel protection liner; and forming at least one symmetric self-aligned gate isolation structure over a portion of the shallow trench isolation region between a third fin of the plurality of fins and a fourth fin of the plurality of fins. the asymmetric self-aligned gate isolation structure formed over the channel protection liner comprises:

2. The method of claim 1, wherein, a first portion formed around a sidewall of the first nanosheet stack adjacent to the channel protection liner; and a second portion formed over a top surface of the channel protection liner around a portion of a top surface of the first nanosheet stack. the first nanosheet stack and the second nanosheet stack provide nanosheet channels for nanosheet field effect transistors of at least one static random access memory device structure.

3. The method of claim 1, wherein, the first nanosheet stack provides a nanosheet channel for a p-type nanosheet field effect transistor and the second nanosheet stack provides a nanosheet channel for an n-type nanosheet field effect transistor.

4. The method of claim 3, wherein, a third nanosheet stack of the plurality of nanosheet stacks formed over the third fin and a fourth nanosheet stack of the plurality of nanosheet stacks formed over the fourth fin provide nanosheet channels for nanosheet field effect transistors of one or more logic device structures.

5. The method of claim 3, wherein, 6. The method of claim 5, wherein forming the channel protection liner comprises: forming the channel protection liner around the plurality of nanosheet stacks and over the shallow trench isolation region between the plurality of fins; forming a dummy gate structure over the channel protection liner; patterning a gate hardmask over the dummy gate structure; and removing portions of the dummy gate structure exposed by the patterned gate hardmask.

7. The method of claim 6, wherein forming the channel protection liner further comprises: forming source / drain regions in spaces formed by removing the dummy gate structure; and removing remaining portions of the dummy gate structure. ​ ​ ​ 8. The method of claim 7, wherein forming the channel protection liner further comprises: patterning a mask layer on portions of the channel protection liner that surround portions of sidewalls and top surfaces of the first nanosheet stack and portions of the shallow trench isolation region that extend from portions of the sidewalls of the first nanosheet stack toward the second nanosheet stack; and removing portions of the channel protection liner exposed by the patterned mask layer.

9. The method of claim 8, wherein, Forming the plurality of nanosheet stacks includes forming alternating layers of sacrificial material and the channel material, and further includes selectively growing additional sacrificial material on portions of the plurality of nanosheet stacks exposed by the channel protection liner.

10. The method of claim 9, wherein forming the asymmetric self-aligned gate isolation structure and the symmetric self-aligned gate isolation structure includes forming isolation material on top of structures surrounding the additional sacrificial material.

11. The method of claim 10, wherein forming the asymmetric self-aligned gate isolation structure and the symmetric self-aligned gate isolation structure further includes forming an organic planarization layer on top of the isolation material and the additional sacrificial material.

12. The method of claim 11, wherein, Forming the asymmetric self-aligned gate isolation structure and the symmetric self-aligned gate isolation structure further includes patterning the organic planarization layer to expose (i) at least a portion of the isolation material formed on top of the channel protection liner for the asymmetric self-aligned gate isolation structure and (ii) at least a portion of the isolation material formed on top of the shallow trench isolation region between the third and fourth nanosheet stacks for the symmetric self-aligned gate isolation structure.

13. The method of claim 12, wherein forming the asymmetric self-aligned gate isolation structure and the symmetric self-aligned gate isolation structure further includes filling additional isolation material in regions exposed by patterning the organic planarization layer.

14. The method of claim 13, wherein, Forming the plurality of gate stacks includes removing the organic planarization layer, sacrificial material of the nanosheet stacks, and the additional sacrificial material.

15. The method of claim 13, wherein, Forming the plurality of gate stacks further includes forming gate dielectric and gate conductor in spaces formed by removing the organic planarization layer, sacrificial material of the nanosheet stacks, and the additional sacrificial material.

16. A semiconductor structure, comprising: a substrate; a plurality of fins disposed on a top surface of the substrate; a shallow trench isolation region disposed on the top surface of the substrate surrounding the plurality of fins; a plurality of nanosheet stacks of channel material disposed on the plurality of fins, the plurality of nanosheet stacks providing a channel for one or more nanosheet field effect transistors; a channel protection liner disposed on at least a portion of a sidewall and a top surface of a first nanosheet stack of the plurality of nanosheet stacks over a first fin of the plurality of fins, the channel protection liner further disposed over a portion of the shallow trench isolation region extending from the portion of the sidewall of the first nanosheet stack toward a second nanosheet stack of the plurality of nanosheet stacks over a second fin of the plurality of fins; a plurality of gate stacks surrounding portions of the plurality of nanosheet stacks exposed by the channel protection liner; at least one asymmetric self-aligned gate isolation structure disposed over the channel protection liner; and at least one symmetric self-aligned gate isolation structure disposed over a portion of the shallow trench isolation region between a third fin of the plurality of fins and a fourth fin of the plurality of fins. the asymmetric self-aligned gate isolation structure disposed over the channel protection liner includes:

17. The semiconductor structure of claim 16, wherein, a first portion disposed adjacent to the channel protection liner surrounding a sidewall of the first nanosheet stack; and a second portion disposed over a top surface of the channel protection liner surrounding a portion of a top surface of the first nanosheet stack. the first nanosheet stack and the second nanosheet stack provide nanosheet channels for nanosheet field effect transistors of at least one static random access memory device structure.

18. The semiconductor structure of claim 16, wherein, the first nanosheet stack provides nanosheet channels for p-type nanosheet field effect transistors and the second nanosheet stack provides nanosheet channels for n-type nanosheet field effect transistors.

19. The semiconductor structure of claim 18, wherein, a third nanosheet stack of the plurality of nanosheet stacks disposed over the third fin and a fourth nanosheet stack of the plurality of nanosheet stacks disposed over the fourth fin provide nanosheet channels for nanosheet field effect transistors of one or more logic device structures.

20. The semiconductor structure of claim 18, wherein, 21. An integrated circuit comprising: a nanosheet field effect transistor structure including the semiconductor structure of any one of claims 16 to 20. ​

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