Semiconductor package

Abstract

A semiconductor package includes a substrate, a plurality of semiconductor devices stacked on the substrate, a plurality of underfill fillets disposed between the plurality of semiconductor devices and between the substrate and the plurality of semiconductor devices, and a mold resin surrounding the plurality of semiconductor devices. At least one of the underfill fillets is exposed from a side surface of the mold resin.

Description

TECHNICAL FIELD

[0001] The present inventive concepts relate to semiconductor packages and methods of manufacturing the same, and more particularly, to semiconductor packages that are resistant to warpage and capable of preventing poor terminal contact and methods of manufacturing the same. BACKGROUND

[0002] Non-conductive films (NCFs) are often used as underfill in semiconductor packages. A semiconductor package can be a metal, plastic, glass, or ceramic enclosure containing one or more discrete semiconductor devices or integrated circuits. However, as the size and thickness of semiconductor devices decrease, the terminals of one of the semiconductor devices can not properly contact the terminals of another of the semiconductor devices, or warpage of one or more of the semiconductor devices can occur. SUMMARY

[0003] At least one embodiment of the present inventive concepts relates to a semiconductor package including a semiconductor device having a terminal that is less likely to have poor contact with another terminal and is resistant to warpage.

[0004] At least one embodiment of the present inventive concepts relates to a method of manufacturing a semiconductor package including a semiconductor device having a terminal that is less likely to have poor contact with another terminal and is resistant to warpage.

[0005] According to an example embodiment of the present inventive concepts, a semiconductor package is provided, including: a substrate; a plurality of semiconductor devices stacked on the substrate; a plurality of underfill fillets (e.g., non-conductive films) disposed between the plurality of semiconductor devices and between the substrate and the plurality of semiconductor devices; and a molded resin surrounding the plurality of semiconductor devices. At least one of the underfill fillets is exposed from a side surface of the molded resin.

[0006] According to an example embodiment of the present inventive concepts, a semiconductor package is provided, including: a package substrate; an interposer substrate stacked on the package substrate; a first sub-package and a second sub-package laterally arranged on the interposer substrate; and a first molded resin surrounding side surfaces of the first sub-package and the second sub-package. The first sub-package includes: a first sub-package substrate; a plurality of memory devices stacked on the first sub-package substrate; and underfill fillets disposed between the plurality of memory devices and between the first sub-package substrate and the plurality of memory devices. At least one of the underfill fillets horizontally protrudes about 200 μm to about 500 μm from a side surface of the plurality of memory devices.

[0007] According to an exemplary embodiment of the present inventive concept, there is provided a semiconductor package, including: a package substrate; a plurality of semiconductor devices stacked on the package substrate; a plurality of underfill fillets disposed between the plurality of semiconductor devices and between the package substrate and the plurality of semiconductor devices; and a molding resin surrounding the plurality of semiconductor devices. Each of the underfill fillets protrudes outside a side surface of the plurality of semiconductor devices. At least one of the underfill fillets is exposed from a side surface of the molding resin, and a side surface of the at least one of the underfill fillets exposed from the side surface of the molding resin is coplanar with the side surface of the molding resin. A distance between the side surface of the plurality of semiconductor devices and the side surface of the molding resin is not greater than 500 μm.

[0008] According to an exemplary embodiment of the present inventive concept, there is provided a method of manufacturing a semiconductor package, including: mounting a first non-conductive film (NCF) and a first semiconductor chip on a package substrate in a first mounting condition and mounting a second NCF and a second semiconductor chip on the first semiconductor chip in a second mounting condition. The first and second mounting conditions are temperature, pressure, and pressing time determined to minimize warpage of the semiconductor package. For example, one of the mounting conditions can be designed to fluidize one of the NCFs so that it is wider than the other NCF. For example, one of the mounting conditions can be designed to fluidize one of the NCFs so that it is exposed from a side surface of a molding resin surrounding the semiconductor chip and the other NCF is retained in the molding resin.

[0009] According to an exemplary embodiment of the present inventive concept, there is provided a method of manufacturing a semiconductor package, including: arranging and mounting a plurality of first non-conductive films (NCFs) and a plurality of first semiconductor devices corresponding to the plurality of first NCFs on a substrate in a first mounting condition; mounting a plurality of second NCFs and a plurality of second semiconductor devices on corresponding first semiconductor devices of the plurality of first semiconductor devices in a second mounting condition; forming a molding resin surrounding side surfaces of the plurality of first semiconductor devices and side surfaces of the plurality of second semiconductor devices; and performing singulation to obtain individual semiconductor packages. At least one of the first and second NCFs contacts each other after adjacent NCFs are mounted. BRIEF DESCRIPTION OF DRAWINGS

[0010] Exemplary embodiments of the present inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] FIG. 1A is a side sectional view of a semiconductor package according to an exemplary embodiment of the present inventive concept, FIG. 1B is a side view of the semiconductor package observable from a side, FIG. 1A is a side view of the semiconductor package observable from a side,

[0012] FIG. 2 is a partial side sectional view illustrating two adjacent bottom fill fillets according to an exemplary embodiment of the present inventive concept;

[0013] FIG. 3A is a side sectional view of a semiconductor package according to an exemplary embodiment of the present inventive concept, FIG. 3B is a side view of a semiconductor package observable from a side;

[0014] FIG. 4 is a flowchart illustrating a method of manufacturing a semiconductor package according to an exemplary embodiment of the present inventive concept;

[0015] FIG. 5A to FIG. 5G is a side sectional view illustrating a method of manufacturing a semiconductor package according to an exemplary embodiment of the present inventive concept;

[0016] FIG. 6 is a side sectional view illustrating a relationship between adjacent semiconductor devices and a bottom fill fillet when a first non-conductive film (NCF) is transformed into a first bottom fill fillet;

[0017] FIG. 7A to FIG. 7D is a partial top view illustrating a process in which a first NCF is gradually fluidized in lower portions of a plurality of adjacent first semiconductor devices and contacts each other;

[0018] FIG. 8 is a schematic diagram illustrating adjusting a warpage characteristic of a semiconductor package;

[0019] FIG. 9 is a side sectional view of a semiconductor package according to an exemplary embodiment of the present inventive concept; and

[0020] FIG. 10 is a side sectional view of a semiconductor package according to an exemplary embodiment of the present inventive concept. DETAILED DESCRIPTION

[0021] Hereinafter, exemplary embodiments of the present inventive concept will be described in detail with reference to the accompanying drawings. Like reference numerals denote like elements throughout the drawings, and descriptions given previously will be omitted.

[0022] A semiconductor package is in a form of "cry" to represent a type of warpage in which a center of the semiconductor package is raised compared to edges, and the semiconductor package is in a form of "smile" to represent a type of warpage in which edges of the semiconductor package are raised compared to the center.

[0023] FIG. 1A is a side sectional view of a semiconductor package 100 according to an exemplary embodiment of the present inventive concept.FIG. 1B is a side view of the semiconductor package 100, which is observable from a side.

[0024] Referring to FIG. 1A and FIG. 1B , the semiconductor package 100 includes a plurality of semiconductor devices 110 stacked on a substrate 101.

[0025] In some embodiments, the substrate 101 can be a printed circuit board (PCB). In this case, the substrate 101 can include a base substrate and upper and lower pads 106b and 106a formed on an upper surface and a lower surface of the base substrate, respectively. The upper and lower pads 106b and 106a can be exposed through a solder resist layer (not shown) covering the upper and lower surfaces of the base substrate. For example, the solder resist layer can be formed on the lower pad 106a, and a portion of the solder resist layer can be removed to expose a lower surface of the lower pad 106a.

[0026] The base substrate can include at least one material selected from a phenol resin, an epoxy resin, and a polyimide. For example, the base substrate can include at least one material selected from FR4, a tetrafunctional epoxy resin, a polyphenylene ether, an epoxy / polyphenylene ether, BT (bismaleimide triazine), Thermount, cyanate ester, polyimide, and a liquid crystal polymer.

[0027] The upper and lower pads 106b and 106a can include copper (Cu), aluminum (Al), nickel (Ni), stainless steel, or beryllium copper (BeCu). An internal wiring line (not shown) electrically connecting the upper pad 106b to the lower pad 106a can be formed in the base substrate. The upper and lower pads 106b and 106a can be portions exposed through a solder resist layer of the circuit wiring line obtained by forming a Cu foil on the upper and lower surfaces of the base substrate and patterning the Cu foil.

[0028] In some embodiments, the substrate 101 can be an interposer (e.g., an interposer substrate). In this case, the substrate 101 can include a base substrate formed of a semiconductor material and upper and lower pads 106b and 106a formed on an upper surface and a lower surface of the base substrate, respectively. The base substrate can be formed of, for example, a silicon wafer. In addition, an internal wiring line (not shown) can be formed in the upper surface, the lower surface, or the inside of the base substrate. In addition, a through via 103 electrically connecting the upper pad 106b to the lower pad 106a can be formed in the base substrate.

[0029] The external connection terminals 105 can be attached to the lower surface of the substrate 101. The external connection terminals 105 can be attached to, for example, the lower pads 106a. The external connection terminals 105 can be, for example, solder balls or bumps. The external connection terminals 105 can electrically connect the semiconductor package 100 to an external device. For example, the external connection terminals 105 can be made of a conductive material.

[0030] The plurality of semiconductor devices 110 can be mounted on the substrate 101. The plurality of semiconductor devices 110 can include a first semiconductor device 110a, a second semiconductor device 110b, a third semiconductor device 110c, and a fourth semiconductor device 110d sequentially stacked on the substrate 101.

[0031] The first to fourth semiconductor devices 110a, 110b, 110c, and 110d can have various semiconductor elements on an active surface of a semiconductor substrate. In some embodiments, the semiconductor substrate of the first to fourth semiconductor devices 110a, 110b, 110c, and 110d can include silicon (Si). In other embodiments, the semiconductor substrate of the first to fourth semiconductor devices 110a, 110b, 110c, and 110d can include a semiconductor atom such as germanium (Ge) or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). In some embodiments, the semiconductor substrate of the first to fourth semiconductor devices 110a, 110b, 110c, and 110d can have a silicon-on-insulator (SOI) structure. For example, the semiconductor substrate can include a buried oxide (BOX) layer. In some embodiments, the semiconductor substrate of the first to fourth semiconductor devices 110a, 110b, 110c, and 110d can include a conductive region, for example, a well doped with an impurity. In some embodiments, the semiconductor substrate of the first to fourth semiconductor devices 110a, 110b, 110c, and 110d can have various device isolation structures such as a shallow trench isolation (STI) structure.

[0032] Among the first to fourth semiconductor devices 110a, 110b, 110c, and 110d, a semiconductor device including a plurality of various types of individual devices can be formed. The plurality of various types of individual devices can include various microelectronic devices, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET) such as a complementary metal-insulator-semiconductor (CMOS) transistor, a large-scale integration (LSI) circuit such as an image sensor. For example, the image sensor can be a CMOS image sensor (CIS), a micro electro mechanical system (MEMS), an active device, or a passive device.

[0033] In some embodiments, the plurality of individual devices can be electrically connected to the conductive regions of the semiconductor substrates of the first through fourth semiconductor devices 110a, 110b, 110c, and 110d. The semiconductor devices can further include conductive wiring lines or conductive plugs that electrically connect at least two of the plurality of individual devices or the plurality of individual devices to the conductive regions of the semiconductor substrates of the first through fourth semiconductor devices 110a, 110b, 110c, and 110d. In addition, each of the plurality of individual devices can be electrically isolated from each of the other adjacent individual devices by an insulating layer.

[0034] Each of the first through fourth semiconductor devices 110a, 110b, 110c, and 110d can be, for example, a memory semiconductor chip. The memory semiconductor chip can be, for example, a volatile memory semiconductor chip such as a dynamic random access memory (DRAM) or a static random access memory (SRAM) or a non-volatile memory semiconductor chip such as a phase change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FeRAM), or a resistive random access memory (RRAM).

[0035] At least one of the plurality of semiconductor devices 110 can be a logic semiconductor chip, while the remaining semiconductor devices can be memory semiconductor chips. For example, the lowermost first semiconductor device 110a of the plurality of semiconductor devices 110 can be a logic semiconductor chip, while the remaining second through fourth semiconductor devices 110b, 110c, and 110d can be memory semiconductor chips. For example, the lowermost first semiconductor device 110a of the plurality of semiconductor devices 110 can be a controller chip (e.g., including a memory controller) for controlling the remaining second through fourth semiconductor devices 110b, 110c, and 110d, and the remaining second through fourth semiconductor devices 110b, 110c, and 110d can be high bandwidth memory (HBM) DRAM semiconductor chips.

[0036] In FIG. 1A and FIG. 1BIn the example shown in FIG. 1, four semiconductor devices are stacked on the substrate 101. However, embodiments of the inventive concept are not limited thereto, as the number of semiconductor devices stacked on the substrate 101 can be 2, 3, 5, or more. When all of the plurality of semiconductor devices 110 are memory semiconductor devices, the number of semiconductor devices 110 can be a multiple of 2. When the plurality of semiconductor devices 110 includes one or more logic semiconductor devices and the remaining semiconductor devices are memory semiconductor devices, the number of memory semiconductor devices included in the plurality of semiconductor devices 110 can be a multiple of 2. In some embodiments, the memory semiconductor devices included in the plurality of semiconductor devices 110 can be the same type of memory semiconductor device.

[0037] The first to fourth semiconductor devices 110a, 110b, 110c, and 110d included in the plurality of semiconductor devices 110 can include a plurality of through electrodes 113. The plurality of through electrodes 113 can be arranged, for example, in a matrix having a pitch of several tens of micrometers. Each of the plurality of through electrodes 113 can have a diameter of, for example, several micrometers to several tens of micrometers. In some embodiments, each of the plurality of through electrodes 113 can have a diameter of about 5 μm to about 15 μm and can be arranged at a pitch of about 25 μm to about 50 μm. For example, the through electrodes 113 in a given one of the semiconductor devices 110 stacked in the Z direction can be spaced apart from each other by 30 μm in the Y direction.

[0038] The first to fourth semiconductor devices 110a, 110b, 110c, and 110d included in the plurality of semiconductor devices 110 can be electrically connected to each other by a plurality of corresponding through electrodes 113. The first to fourth semiconductor devices 110a, 110b, 110c, and 110d included in the plurality of semiconductor devices 110 can be electrically connected to the substrate 101 by the plurality of through electrodes 113. The plurality of through electrodes 113 can provide at least one of a signal, a power supply, or a ground for the plurality of semiconductor devices 110.

[0039] Connection terminals 117 connected to the plurality of through electrodes 113 can be attached to lower surfaces of the first to fourth semiconductor devices 110a, 110b, 110c, and 110d included in the plurality of semiconductor devices 110. Each connection terminal 117 can have a diameter of, for example, several tens of micrometers. In an example embodiment of the inventive concept, the diameter of each connection terminal 117 is greater than the diameter of each of the plurality of through electrodes 113 and is less than the pitch at which the plurality of through electrodes 113 are arranged. For example, each connection terminal 117 can have a diameter of about 20 μm.

[0040] Each of the plurality of through electrodes 113 can be formed of a through silicon via (TSV). Each of the plurality of through electrodes 113 can include a wiring metal layer and a barrier metal layer surrounding the wiring metal layer.

[0041] The wiring metal layer can include Cu or tungsten (W). For example, the wiring metal layer can be formed of Cu, CuSn, CuMg, CuNi, CuZn, CuPd, CuAu, CuRe, CuW, W, or a W alloy. However, the inventive concept is not limited thereto. For example, the wiring metal layer can include one or more of Al, Au, Be, Bi, Co, Cu, Hf, In, Mn, Mo, Ni, Pb, Pd, Pt, Rh, Re, Ru, Ta, Te, Ti, W, Zn, and Zr, and a stacked structure of two or more of Al, Au, Be, Bi, Co, Cu, Hf, In, Mn, Mo, Ni, Pb, Pd, Pt, Rh, Re, Ru, Ta, Te, Ti, W, Zn, and Zr.

[0042] The barrier metal layer can include at least one material selected from W, WN, WC, Ti, TiN, Ta, TaN, Ru, Co, Mn, WN, Ni, and NiB, and can be formed of a single layer or multiple layers.

[0043] However, the material of each of the plurality of through electrodes 113 is not limited thereto. The barrier metal layer and the wiring metal layer can be formed by a physical vapor deposition (PVD) process or a chemical vapor deposition (CVD) process. However, the inventive concept is not limited thereto. In some embodiments, a spacer insulating layer can be interposed between the plurality of through electrodes 113 and a semiconductor substrate including the plurality of semiconductor devices 110. The spacer insulating layer can prevent the semiconductor devices formed in the first to fourth semiconductor devices 110a, 110b, 110c, and 110d included in the plurality of semiconductor devices 110 from directly contacting the plurality of through electrodes 113. The spacer insulating layer can be formed of an oxide layer, a nitride layer, a carbide layer, a polymer, or a combination of the above materials. In some embodiments, the spacer insulating layer can be formed using a CVD process. The spacer insulating layer can be formed of a high aspect ratio process (HARP) oxide layer based on ozone / orthosilicate tetraethyl (O3 / TEOS) formed by a sub-atmospheric CVD process.

[0044] In an exemplary embodiment of the inventive concept, the plurality of through electrodes 113 directly connect the active surfaces and the non-active surfaces of the first to fourth semiconductor devices 110a, 110b, 110c, and 110d included in the plurality of semiconductor devices 110 to each other. However, the inventive concept is not limited thereto. The plurality of through electrodes 113 can be formed in any one of a front via structure, a middle via structure, and a back via structure. Since the method of manufacturing the front via structure, the middle via structure, or the back via structure is disclosed in a plurality of documents such as Three Dimensional System Integration published by Springer in 2011, 3D Integration for VLSI Systems published by CRC Press in 2012, and Designing TSVs for 3D Integrated Circuits published by Springer in 2013, detailed descriptions thereof are omitted.

[0045] The lower pads 115a and the upper pads 115b electrically connected to the through electrodes 113 can be provided on the lower surfaces and the upper surfaces of the first to fourth semiconductor devices 110a, 110b, 110c, 110d included in the plurality of semiconductor devices 110. The lower pads 115a and the upper pads 115b can be formed at positions corresponding to the through electrodes 113 and can be electrically connected to the plurality of through electrodes 113. However, the inventive concept is not limited thereto. For example, the lower pads 115a and the upper pads 115b can be formed at positions separate from the through electrodes 113 and can be electrically connected to the through electrodes 113 via a redistribution layer. The lower pads 115a and the upper pads 115b can be defined by a standard protocol such as JEDEC standard, and each of the lower pads 115a and the upper pads 115b can have a thickness of several hundred nanometers to several micrometers. In addition, the lower pads 115a and the upper pads 115b can include at least one of Al, Cu, Ta, Ti, W, Ni, and Au.

[0046] The molding resin 140 surrounding the side surfaces of the plurality of semiconductor devices 110 can be provided on the substrate 101. The molding resin 140 can be formed of, for example, epoxy molding compound (EMC). In some embodiments, the molding resin 140 can be provided to cover the upper surface of the uppermost semiconductor device (here, the fourth semiconductor device 110d) among the plurality of semiconductor devices 110. In other embodiments, the molding resin 140 can expose the upper surface of the uppermost semiconductor device (here, the fourth semiconductor device 110d) among the plurality of semiconductor devices 110. For example, a portion of the molding resin 140 can be removed to expose the upper surface of the fourth semiconductor device 110d.

[0047] The underfill round corner 120 (e.g., an underfill layer) can be provided between the plurality of semiconductor devices 110 and between the substrate 101 and the plurality of semiconductor devices 110. For example, the underfill layer can be located between the substrate 101 and a bottom semiconductor device among the semiconductor devices 110, and the underfill layer can be located between each pair of semiconductor devices 110.

[0048] The underfill round corner 120 can fill a space between the first semiconductor device 110a and the substrate 101. Also, the underfill round corner 120 can fill spaces between the second to fourth semiconductor devices 110b, 110c, and 110d. The underfill round corner 120 can improve adhesion strength of components and / or prevent a decrease in physical strength due to deformation of components. In some embodiments, the underfill round corner 120 is provided in the space to remove empty spaces into which foreign substances or moisture can penetrate and / or prevent electromigration.

[0049] The underfill round corner 120 can protrude outside of side surfaces of the first to fourth semiconductor devices 110a, 110b, 110c, and 110d while filling spaces between the substrate 101 and the first to fourth semiconductor devices 110a, 110b, 110c, and 110d. In an example embodiment of the inventive concept, the first underfill round corner 120a is disposed in a space between the substrate 101 and the first semiconductor device 110a and protrudes outside from a side surface of the first semiconductor device 110a. In an example embodiment of the inventive concept, the second underfill round corner 120b is disposed in a space between the first semiconductor device 110a and the second semiconductor device 110b and protrudes outside from a side surface of the second semiconductor device 110b. In an example embodiment of the inventive concept, the third underfill round corner 120c is disposed in a space between the second semiconductor device 110b and the third semiconductor device 110c and protrudes outside from a side surface of the third semiconductor device 110c. In an example embodiment of the inventive concept, the fourth underfill round corner 120d is disposed in a space between the third semiconductor device 110c and the fourth semiconductor device 110d and protrudes outside from a side surface of the fourth semiconductor device 110d.

[0050] In some embodiments, the first to fourth underfill round corners 120a to 120d do not contact each other and are separated from each other. In some embodiments, two adjacent underfill round corners among the first to fourth underfill round corners 120a to 120d can contact each other and an interface is interposed therebetween. For example, an upper surface of the interface can contact one of the two adjacent underfill round corners, and a lower surface of the interface can contact the other of the two adjacent underfill round corners.

[0051] FIG. 2 is a partial side sectional view showing two adjacent bottom fill round corners according to an exemplary embodiment of the present inventive concept.

[0052] Referring to FIG. 2 , two adjacent bottom fill round corners 120j and 120k between three semiconductor devices 110i, 110j and 110k are provided. The two bottom fill round corners 120j and 120k protrude from side surfaces of the semiconductor devices 110i, 110j and 110k to the outside. As they protrude from the side surfaces of the semiconductor devices 110i, 110j and 110k to the outside, the two bottom fill round corners 120j and 120k bulge upward and downward as well as in a lateral direction.

[0053] In detail, the jth bottom fill round corner 120j and the jth semiconductor device 110j are disposed on the ith semiconductor device 110i, and the jth bottom fill round corner 120j is heated and pressed so that the jth bottom fill round corner 120j protrudes from a side surface of the jth semiconductor device 110j to the outside and solidifies. For example, physical pressure can be applied to the jth bottom fill round corner 120j so that the jth bottom fill round corner 120j is pressed.

[0054] Then, the kth bottom fill round corner 120k and the kth semiconductor device 110k are disposed on the jth semiconductor device 110j, and the kth bottom fill round corner 120k is heated and pressed so that the kth bottom fill round corner 120k protrudes from a side surface of the kth semiconductor device 110k to the outside. As the kth bottom fill round corner 120k is heated and pressed, the kth bottom fill round corner 120k bulges upward and downward while protruding toward the side surface of the kth semiconductor device 110k. When the bulging occurs beyond a certain level, the kth bottom fill round corner 120k contacts the jth bottom fill round corner 120j previously formed. At this time, as the jth bottom fill round corner 120j is previously solidified, an interface IF can be formed between the jth bottom fill round corner 120j and the kth bottom fill round corner 120k.

[0055] In addition, the kth bottom fill round corner 120k does not contact the jth bottom fill round corner 120j when the jth bottom fill round corner 120j has fluidity. Rather, after the jth bottom fill round corner 120j is solidified, the kth bottom fill round corner 120k is reflowed and contacts the solidified jth bottom fill round corner 120. Thus, at the contact point, a surface of the jth bottom fill round corner 120j and a surface of the kth bottom fill round corner 120k can contact each other at a predetermined angle θ. The angle θ is formed by tangents at the contact point, which can be an acute angle, a right angle or an obtuse angle. However, the present inventive concept is not limited thereto.

[0056] Referring back toFIG. 1A and FIG. 1B The underfill corner 120 can be, for example, a bisphenol A (BPA) epoxy resin, a bisphenol F (BPF) epoxy resin, an aliphatic epoxy resin, or a cycloaliphatic epoxy resin, and can further include a powder such as silica, alumina, zirconia, titania (e.g., titanium dioxide), ceria, magnesia, silicon carbide, or aluminum nitride as an inorganic filler.

[0057] In some embodiments, the first through fourth underfill corners 120a, 120b, 120c, and 120d included in the underfill corner 120 can be the same type of underfill corner. In other embodiments, at least two of the first through fourth underfill corners 120a, 120b, 120c, and 120d can have different inorganic fillers (e.g., different amounts and types), different types of resins, and / or resins having different physical properties.

[0058] At least one of the first through fourth underfill corners 120a, 120b, 120c, and 120d can protrude more outwardly than the other underfill corners. As shown in FIG. 1A the first underfill corner 120a can protrude L1 outwardly, and the second through fourth underfill corners 120b, 120c, and 120d can protrude L2 outwardly. In an exemplary embodiment, L1 is greater than L2. In some embodiments, L1 can be no greater than about 500 pm, such as about 200 pm to about 500 pm. In some embodiments, L1 can be about 30 pm to about 450 pm, about 60 pm to about 400 pm, about 100 pm to about 350 pm, or about 120 pm to about 300 pm.

[0059] When L1 is too large, the area occupied by the semiconductor package 100 can be too large. When L1 is too small, the tolerance can be too small such that it can be difficult to manufacture the semiconductor package 100.

[0060] An underfill corner that protrudes more outwardly than other underfill corner(s) of the underfill corner 120 can be exposed to the outside from the side surface of the molding resin 140. As shown in FIG. 1A the first underfill corner 120a can protrude more outwardly than the other underfill corners and extend to the side surface of the molding resin 140. In FIG. 1A , the first underfill corner 120a is shown as protruding the most outwardly. However, one of skill in the art can appreciate that another underfill corner 120 can protrude the most outwardly to be exposed to the side surface of the molding resin 140.

[0061] In some embodiments, at least one of the first through fourth underfill fillets 120a, 120b, 120c, and 120d is not exposed from the side surface of the molding resin 140. In some embodiments, at least two of the first through fourth underfill fillets 120a, 120b, 120c, and 120d can be exposed from the side surface of the molding resin 140. In some embodiments, the first underfill fillet 120a can be exposed from the side surface of the molding resin 140, and at least one of the second through fourth underfill fillets 120b, 120c, and 120d can be exposed from the side surface of the molding resin 140.

[0062] In an exemplary embodiment of the inventive concept, an underfill fillet (here, the first underfill fillet 120a) that extends to the side surface of the molding resin 140 and is exposed from the side surface of the molding resin 140 directly contacts the substrate 101. As shown, the exposed first underfill fillet 120a can contact the substrate 101 at the side surface of the molding resin 140 along a length C. FIG. 1B

[0063] In other embodiments, the exposed underfill fillet does not contact the substrate 101 at the side surface of the molding resin 140.

[0064] The substrate 101 and the first semiconductor device 110a can be spaced apart from each other by a first distance ha. The first semiconductor device 110a and the second semiconductor device 110b can be separated from each other by a second distance hb. The second semiconductor device 110b and the third semiconductor device 110c can be separated from each other by a third distance hc. The third semiconductor device 110c and the fourth semiconductor device 110d can be separated from each other by a fourth distance hd.

[0065] In an exemplary embodiment, the first distance ha through the fourth distance hd are different from each other. In an exemplary embodiment, a bottom fill fillet that protrudes more outward from the side surface of the plurality of semiconductor devices 110 has a smaller distance than another bottom fill fillet that protrudes less from the side surface of the semiconductor device 110. In some embodiments, as shown, FIG. 1A

[0066] As described above, at least two of the first through fourth underfill fillets 120a, 120b, 120c, and 120d can have inorganic fillers of different compositions (e.g., different contents and types), resins of different types, and / or resins having different physical properties.

[0067] ​​At least two of the first to fourth underfill corners 120a, 120b, 120c, and 120d can have, for example, different coefficients of thermal expansion (CTEs), viscosities, and glass transition temperatures (Tgs), depending on the content and type of inorganic filler and the type and physical properties of the resin.

[0068] In some embodiments, warpage of the semiconductor package 100 can be controlled by controlling the CTEs of the first to fourth underfill corners 120a, 120b, 120c, and 120d. The warpage of the semiconductor package 100 can be controlled by controlling the degree to which the underfill corners 120 (here, the first to fourth underfill corners 120a, 120b, 120c, and 120d) extend horizontally. That is, at least two of the first to fourth underfill corners 120a, 120b, 120c, and 120d can have different physical properties, and the lengths to which the first to fourth underfill corners 120a, 120b, 120c, and 120d extend horizontally and protrude can be different from one another. In this case, the physical properties of the underfill corner that extends horizontally and protrudes with a greater length have a greater effect on the warpage of the semiconductor package 100 than the physical properties of the underfill corner that extends horizontally and protrudes with a smaller length.

[0069] In FIG. 1A In the illustrated embodiment, since the first underfill corner 120a extends horizontally with a greater length than the second to fourth underfill corners 120b, 120c, and 120d, the first underfill corner 120a has a greater effect on the warpage of the semiconductor package 100 than the second to fourth underfill corners 120b, 120c, and 120d.

[0070] For example, when the length to which the first underfill corner 120a protrudes is the same as the length to which the second underfill corner 120b protrudes, L2, the semiconductor package 100 can bend in the form of a smile. At this time, assume that the first underfill corner 120a has a greater CTE than the CTE of the second underfill corner 120b. In this case, by simply causing the first underfill corner 120a to protrude horizontally with a length greater than L2, horizontal shrinkage of the first underfill corner 120a can be more reflected. As a result, the degree to which the semiconductor package 100 bends in the form of a smile can be reduced or warpage can be prevented. That is, the degree of warpage of the semiconductor package 100 can be controlled by increasing the length to which the first underfill corner 120a extends horizontally without additional changes. This is because the effect of the first underfill corner 120a having a greater CTE is increased.

[0071] In FIG. 1AIn the middle, it is shown that the first underfill corner 120a protrudes the most. However, another underfill corner, such as the second underfill corner 120b, the third underfill corner 120c, or the fourth underfill corner 120d, can protrude the most horizontally. As described above, by increasing the degree to which the second underfill corner 120b, the third underfill corner 120c, or the fourth underfill corner 120d protrudes horizontally, the physical properties of a certain underfill corner can have a greater effect on warpage of the semiconductor package 100.

[0072] Furthermore, in the manufacturing of the semiconductor package 100, when the underfill corners 120 are reflowed (e.g., fluidized) by applying heat and pressure, portions of the underfill corners 120 located around the center of the semiconductor devices 110 are fluidized toward the outside. At this time, the portions of the underfill corners 120 fluidized to the outside can concentrate at the outer edges of the semiconductor devices 110, such that normal connections of the semiconductor devices 110 can be degraded. In an exemplary embodiment, the underfill corners 120 around the center of the semiconductor devices 110 and between the center and the edges of the semiconductor devices 110 are simultaneously reflowed and concentrated around the edges of the semiconductor devices 110. The concentrated underfill corners 120 can lift the edges of the semiconductor devices 110 upward. Thus, the connections of the semiconductor devices 110 can be degraded. In particular, as the thickness of each semiconductor device 110 becomes smaller, the semiconductor devices 110 are more affected by such lifting.

[0073] Furthermore, the second through fourth underfill corners 120b, 120c, and 120d can more easily protrude horizontally than the first underfill corner 120a located under the lowest semiconductor device (the first semiconductor device 110a in FIG. 1A In the middle, it is shown that the first underfill corner 120a protrudes the most. However, another underfill corner, such as the second underfill corner 120b, the third underfill corner 120c, or the fourth underfill corner 120d, can protrude the most horizontally. As described above, by increasing the degree to which the second underfill corner 120b, the third underfill corner 120c, or the fourth underfill corner 120d protrudes horizontally, the physical properties of a certain underfill corner can have a greater effect on warpage of the semiconductor package 100.

[0074] By having the first underfill corner 120a sufficiently protrude horizontally, the lifting problem of the semiconductor devices 110 can be addressed, and the restriction on the flow path of the first underfill corner 120a can be alleviated.

[0075] In some embodiments, at least two of the bottom filler radii 120 protrude more horizontally than the other(s) bottom filler radii(s). In some embodiments, at least two of the bottom filler radii 120 are exposed to the outside from the side surface of the molding resin 140. FIG. 3A This is a side sectional view of a semiconductor package 100a according to an exemplary embodiment of the present invention. FIG. 3B This is a side view of the semiconductor package 100a, as seen from the side.

[0076] Reference FIG. 3A and FIG. 3B Semiconductor package 100a and reference FIG. 1A and FIG. 1B The semiconductor package 100 described is identical except that the bottom fill fillet 120a (i.e., the third bottom fill fillet 120c') extends beyond the side surface of the molding resin 140 and is exposed beyond it. Therefore, this difference will be described primarily below, and the previously given description may be omitted.

[0077] The third bottom filler rounded corner is 120c'. FIG. 1A The third bottom filler corner is 120c and extends horizontally further. FIG. 3A The diagram shows that the first to fourth bottom filler filler rounded corners 120a, 120b, 120c', and 120d do not touch each other. However, two of the first to fourth bottom filler filler rounded corners 120a, 120b, 120c', and 120d can touch each other, as shown in the diagram. FIG. 2 As shown. When by making FIG. 1A The third bottom filler rounded corner 120c protrudes horizontally to achieve more. FIG. 3A When the third bottom fillet is rounded to 120c', the third distance hc' between the second semiconductor device 110b and the third semiconductor device 110c can be less than 120c'. FIG. 1A The third distance hc.

[0078] As referenced above FIG. 1A and FIG. 1B In order to precisely control the warpage of the semiconductor package 100a, the lengths of the horizontally extending second to fourth bottom filler rounded corners 120b, 120c' and 120d can also be controlled.

[0079] For example, like in FIG. 1A As in the semiconductor package 100, the warpage of the semiconductor package 100a can be controlled by controlling the length of the protruding first bottom filler radius 120a. However, FIG. 3AThe warpage of the semiconductor package 100a can not be sufficiently controlled. At this time, by controlling the length of the third underfill corner 120c' protruding, the warpage of the semiconductor package 100a can be more precisely controlled.

[0080] As described above with reference to FIG. 1A , even if the length of the first underfill corner 120a protruding has been increased, the semiconductor package 100a can be curved in a smiling form. At this time, it is assumed that the third underfill corner 120c' has a CTE smaller than that of the second underfill corner 120b and the second underfill corner 120b has a CTE smaller than that of the first underfill corner 120a. In this case, by simply making the third underfill corner 120c' horizontally protrude by a length greater than L2, the property that the third underfill corner 120c' is less horizontally shrunk than the first underfill corner 120a can be more reflected to the semiconductor package 100a. That is, the CTE of the third underfill corner 120c' is smaller than that of the first underfill corner 120a, and the property that the third underfill corner 120c' is less horizontally shrunk than the first underfill corner 120a can be more reflected to the semiconductor package 100a. As a result, the degree to which the semiconductor package 100a is curved in a smiling form can be reduced.

[0081] In the semiconductor package according to at least one example embodiment of the inventive concept, the poor contact of the terminal can be prevented and the warpage of the semiconductor package can be minimized.

[0082] FIG. 4 FIG. 1 is a flowchart illustrating a method of manufacturing a semiconductor package according to an example embodiment of the inventive concept. FIG. 5A to FIG. 5G FIG. 2 is a side sectional view illustrating a method of manufacturing a semiconductor package according to an example embodiment of the inventive concept.

[0083] Referring to FIG. 4 and FIG. 5A , in operation S110, a plurality of first semiconductor devices 110a are disposed on the substrate 101 and mounted on the substrate 101 in a first mounting condition.

[0084] In FIG. 5A , only one first semiconductor device 110a is illustrated. However, on the substrate 101 extending in the X and Y directions, a plurality of first semiconductor devices 110a can be disposed and mounted, for example, in a grid structure.

[0085] The first non-conductive film (NCF) 120a' can be attached to a respective one of the plurality of first semiconductor devices 110a, respectively. In an exemplary embodiment, the first NCF 120a' has the same size as the first semiconductor device 110a in the horizontal direction (the direction of the XY plane). In an exemplary embodiment, the thickness ha' of the first NCF 120a' is greater than the height of each connection terminal 117 in the Z direction. In this case, the connection terminal 117 can be surrounded by the first NCF 120a'. However, in other embodiments, the lower end of the connection terminal 117 can be partially exposed from the first NCF 120a'.

[0086] Since the substrate 101 and the first semiconductor device 110a are described in detail with reference to FIG. 1A The detailed description will be omitted.

[0087] With reference to FIG. 5B , the first semiconductor device 110a is mounted on the substrate 101 in a first mounting condition. The first mounting condition includes the temperature, the pressure, and the time during mounting of the first semiconductor device 110a.

[0088] In some embodiments, the temperature of the first mounting condition can be about 180°C to about 280°C. In some embodiments, the pressure of the first mounting condition can be about 5 kPa to about 200 kPa. The time of the first mounting condition can be about 1 second to about 100 seconds. The temperature, the pressure, and the time are closely related, and for example, the same mounting result can be obtained by slightly increasing the time while slightly decreasing the pressure under a certain mounting condition. In addition, for example, the same mounting result can be obtained by slightly increasing the temperature while slightly decreasing the time under a certain mounting condition. In addition, for example, the same mounting result can be obtained by slightly increasing the pressure while slightly decreasing the temperature under a certain mounting condition. The degree to which the first NCF 120a' is fluidized and protrudes horizontally can be controlled by appropriately controlling the mounting conditions such as the temperature, the pressure, and the time.

[0089] By cooling the first NCF 120a' that is fluidized and protruded, the first underfill fillet 120a can be obtained.

[0090] By using the method of manufacturing a semiconductor package according to at least one exemplary embodiment of the inventive concept, contact failure of a terminal can be prevented and warpage of the semiconductor package can be minimized.

[0091] FIG. 6 is a side cross-sectional view illustrating a relationship between adjacent semiconductor devices and an underfill fillet when the first NCF 120a' is transformed into the first underfill fillet 120a.

[0092] With reference to FIG. 6, a first underfill fillet 120a is provided to each of the two adjacent first semiconductor devices 110a, respectively. In some embodiments, the adjacent first underfill fillets 120a contact each other and are partially integrated. Then, the first semiconductor devices 110a and the first underfill fillets 120a can be molded by a molding resin. When the first semiconductor devices 110a and the first underfill fillets 120a are molded by the molding resin and then separated and singulated along a separation line 120aSL, side surfaces of the first underfill fillets 120a can be exposed from side surfaces of the molding resin.

[0093] FIG. 7A to FIG. 7D is a partial top view illustrating a process in which first NCFs 120a'1, 120a'2, 120a'3, and 120a'4 are gradually fluidized in lower portions of a plurality of adjacent first semiconductor devices 110a1, 110a2, 110a3, and 110a4 and contact each other.

[0094] Referring to FIG. 7A , a portion of four first semiconductor devices 110a1, 110a2, 110a3, and 110a4 arranged in a grid configuration is illustrated. The four first semiconductor devices 110a1, 110a2, 110a3, and 110a4 can be attached to the substrate 101 by corresponding first NCFs 120a'1, 120a'2, 120a'3, and 120a'4, respectively. Since two surfaces of each of the first NCFs 120a'1, 120a'2, 120a'3, and 120a'4 are adhesive, the first NCFs 120a'1, 120a'2, 120a'3, and 120a'4 can attach the four first semiconductor devices 110a1, 110a2, 110a3, and 110a4 to the substrate 101.

[0095] Referring to FIG. 7B , when heat and pressure are applied to the plurality of first semiconductor devices 110a1, 110a2, 110a3, and 110a4, each of the first NCFs 120a'1, 120a'2, 120a'3, and 120a'4 is fluidized and starts to horizontally protrude from lower portions of the plurality of first semiconductor devices 110a1, 110a2, 110a3, and 110a4, respectively.

[0096] At this time, although not illustrated in FIG. 7B , a distance between each of the plurality of first semiconductor devices 110a1, 110a2, 110a3, and 110a4 and the substrate 101 can be reduced, and connection terminals 117 under the plurality of first semiconductor devices 110a1, 110a2, 110a3, and 110a4 can contact corresponding upper pads 106b of the substrate 101 (refer to FIG. 5A and FIG. 5B).

[0097] Referring to FIG. 7C , the first NCFs 120a'1, 120a'2, 120a'3, and 120a'4 fluidized by heat are maintained in a fluidized state by continuously applying heat and pressure, and protrude more horizontally from the lower portions of the plurality of first semiconductor devices 110a1, 110a2, 110a3, and 110a4. In addition, the first NCFs 120a'1, 120a'2, 120a'3, and 120a'4 can be merged with adjacent first NCFs 120a'1, 120a'2, 120a'3, and 120a'4.

[0098] FIG. 6 The cross-section shown can correspond to a cross-section taken along the line VI-VI' of FIG. 7C .

[0099] In FIG. 7C , it is shown that the first NCFs 120a'1, 120a'2, 120a'3, and 120a'4 adjacent to each other in the X direction or the Y direction are merged with each other. However, in some embodiments, the first NCFs 120a'1, 120a'2, 120a'3, and 120a'4 in a diagonal direction can be merged with each other. In some embodiments, at a common corner of the first NCFs 120a'1, 120a'2, 120a'3, and 120a'4, the substrate 101 can still be exposed.

[0100] Then, the plurality of second semiconductor devices 110b, the plurality of third semiconductor devices 110c, and the plurality of fourth semiconductor devices 110d can be sequentially stacked on the corresponding first semiconductor devices among the plurality of first semiconductor devices 110a1, 110a2, 110a3, and 110a4 by a similar method.

[0101] Referring to FIG. 7D , the molding resin is formed and then singulated along the separation line 120aSL to obtain a separated semiconductor package. At this time, as described above, at the common corner (marked with EG) of the first NCFs 120a'1, 120a'2, 120a'3, and 120a'4, the substrate 101 can be exposed without being covered by the first NCFs 120a'1, 120a'2, 120a'3, and 120a'4. In such a portion, the molding resin can directly contact the substrate 101.

[0102] Such a portion can be observed in the cross-section shown in FIG. 1B . That is, referring back to FIG. 1B , outside the portion where the substrate 101 contacts the first bottom-filling fillet 120a, the substrate 101 can contact the molding resin 140.

[0103] Referring to FIG. 4 and FIG. 5C In operation S120, each of the plurality of second semiconductor devices 110b is mounted on a corresponding first semiconductor device of the plurality of first semiconductor devices 110a under a second mounting condition.

[0104] Each second non-conductive film can be attached to each of the plurality of second semiconductor devices 110b. When the plurality of second semiconductor devices 110b is completely mounted under the second mounting condition, the second non-conductive film can be transformed into a second underfill round 120b.

[0105] In some embodiments, the second non-conductive film is substantially identical to the first non-conductive film 120a'. In other embodiments, the second non-conductive film has at least one physical property that is different from at least one of the first non-conductive film 120a'.

[0106] In an exemplary embodiment, a second distance hb between the first semiconductor device 110a and the second semiconductor device 110b is different from a first distance ha between the substrate 101 and the first semiconductor device 110a. In some embodiments, the second distance hb can be greater than the first distance ha.

[0107] Referring to FIG. 4 and FIG. 5D In operation S130, each of the plurality of third semiconductor devices 110c is mounted on a corresponding second semiconductor device of the plurality of second semiconductor devices 110b under a third mounting condition.

[0108] Each third non-conductive film can be attached to each of the plurality of third semiconductor devices 110c. When the plurality of third semiconductor devices 110c has been mounted under the third mounting condition, the third non-conductive film can be transformed into a third underfill round 120c.

[0109] In some embodiments, the third non-conductive film can be substantially identical to the first non-conductive film 120a' and / or the second non-conductive film. In other embodiments, the third non-conductive film can have at least one physical property that is different from at least one of the first non-conductive film 120a' and the second non-conductive film.

[0110] In an exemplary embodiment, a third distance hc between the second semiconductor device 110b and the third semiconductor device 110c is different from at least one of the first distance ha and the second distance hb. In an exemplary embodiment, the third distance hc is greater than the first distance ha.

[0111] Referring to FIG. 4 and FIG. 5EIn operation S140, each of the plurality of fourth semiconductor devices 110d is mounted on a corresponding third semiconductor device of the plurality of third semiconductor devices 110c in a fourth mounting condition.

[0112] Each fourth non-conductive film can be attached to each of the plurality of fourth semiconductor devices 110d. When the plurality of fourth semiconductor devices 110d has been mounted in the fourth mounting condition, the fourth non-conductive film can be transformed into a fourth under-fill round corner 120d.

[0113] In some embodiments, the fourth non-conductive film can be substantially the same as the first non-conductive film 120a' to the third non-conductive film. In other embodiments, the fourth non-conductive film can have at least one physical property that is different from at least one of the first non-conductive film 120a' to the third non-conductive film.

[0114] In an exemplary embodiment, a fourth distance hd between the third semiconductor device 110c and the fourth semiconductor device 110d is different from at least one of the first distance ha to the third distance hc. In some embodiments, the fourth distance hd can be greater than the first distance ha.

[0115] Each of the second mounting condition, the third mounting condition, and the fourth mounting condition includes a temperature, a pressure, and a time during mounting of each of the second semiconductor device 110b, the third semiconductor device 110c, and the fourth semiconductor device 110d.

[0116] In some embodiments, the temperature of each of the first to third mounting conditions can be about 180℃ to about 280℃. In some embodiments, the pressure of each of the first to third mounting conditions can be about 5kPa to about 200kPa. The time of each of the first to third mounting conditions can be about 1 second to about 100 seconds. Since the correlation between the temperature, the pressure, and the time has been described in detail with reference to FIG. 5B The additional description of the correlation between the temperature, the pressure, and the time will be omitted.

[0117] In the process described with reference to FIG. 5B to FIG. 5E It is shown that the adjacent first under-fill round corners 120a contact each other. However, the adjacent first under-fill round corners 120a do not have to contact each other. In other embodiments, the plurality of first to fourth semiconductor devices 110a to 110d can be mounted such that at least one of the first to fourth under-fill round corners 120a to 120d contacts an adjacent under-fill round corner.

[0118] In the process described with reference to FIG. 4 and FIG. 5F In operation S150, the molding resin 140 is formed to surround side surfaces of the first to fourth semiconductor devices 110a to 110d.

[0119] In an exemplary embodiment, the upper surface of the fourth semiconductor device 110d is coated with the molding resin 140. In other embodiments, the molding resin 140 can expose the upper surface of the fourth semiconductor device 110d. For example, portions of the molding resin 140 covering the upper surface can be removed to expose the upper surface.

[0120] Since the molding resin 140 has been described with reference to FIG. 1A and FIG. 1B , a detailed description thereof will be omitted.

[0121] Referring to FIG. 4 and FIG. 5G , in operation S160, singulation is performed by cutting to obtain individual semiconductor packages 100.

[0122] The cutting method can be performed by mechanical sawing or laser sawing. However, the inventive concept is not limited thereto.

[0123] When the singulation is performed, the molding resin 140 is cut along the separation line 120aSL as shown in FIG. 6 and FIG. 7D , so that the first underfill fillet 120a can be exposed from the side surface of the molding resin 140.

[0124] FIG. 8 is a schematic diagram showing warpage control of the semiconductor package 100.

[0125] Referring to FIG. 8 , when the semiconductor device 110 is curved in a smiling form (i.e., in a U shape), the warpage characteristics of the underfill fillets are controlled to form a crying form (i.e., in an inverted U shape), so that warpage of the entire semiconductor package 100 can be minimized.

[0126] Conversely, when the warpage of the semiconductor device 110 is in a crying form (i.e., in an inverted U shape), the warpage characteristics of the underfill fillets are controlled to form a smiling form (i.e., in a U shape), so that warpage of the entire semiconductor package 100 can be minimized.

[0127] The temperature, pressure, and time of the first to fourth mounting conditions described above can be determined to minimize warpage of the semiconductor package 100. In addition, the properties of the non-conductive film used to form the first to fourth underfill fillets 120a, 120b, 120c, and 120d can be determined so that warpage of the semiconductor package 100 is minimized.

[0128] By controlling the first to fourth mounting conditions, the degree to which the first to fourth underfill corners 120a, 120b, 120c, and 120d protrude horizontally can be controlled. Thus, electrical connections between the semiconductor devices 110 can be ensured, and warpage of the semiconductor package 100 can be controlled.

[0129] As described above, considering that the properties of the underfill corners that protrude more horizontally have a greater influence on warpage of the semiconductor package 100, warpage of the semiconductor package 100 can be controlled by controlling the degree to which the first to fourth underfill corners 120a, 120b, 120c, and 120d protrude horizontally.

[0130] FIG. 9 FIG. 1 is a side cross-sectional view illustrating a semiconductor package 1 according to an example embodiment of the present inventive concept.

[0131] Referring to FIG. 9 The interposer substrate 20 is located on the package substrate 10, and the first sub-package 100s and the second sub-package 200 are horizontally arranged on the interposer substrate 20. The first sub-package 100s and the second sub-package 200 can be encapsulated by the first molding resin 30.

[0132] The first sub-package 100s can be the same as the semiconductor package 100 described with reference to FIG. 1A and a detailed description thereof will be omitted. The first sub-package substrate 101s of the first sub-package 100s can be the same as the substrate 101 described with reference to FIG. 1A .

[0133] The second sub-package 200 includes a first semiconductor chip 210. The first semiconductor chip 210 can be attached to the interposer substrate 20 such that an active surface 212 faces the interposer substrate 20. The first semiconductor chip 210 can be electrically connected to the interposer substrate 20 via first connection terminals 216 arranged on the active surface 212. The first connection terminals 216 can be, for example, solder balls or bumps. A first underfill material layer 230 can be formed to fill a space between the second sub-package 200 and the interposer substrate 20. The first underfill material layer 230 can be formed of, for example, an epoxy resin. The first underfill material layer 230 can be a portion of the first molding resin 30 formed by, for example, a molded underfill (MUF) method. The second sub-package 200 can be, for example, a wafer level package (WLP).

[0134] The first semiconductor chip 210 can be a processor unit (e.g., a central processing unit). The first semiconductor chip 210 can be a microprocessor unit (MPU) or a graphics processor unit (GPU).

[0135] The semiconductor substrate forming the first semiconductor chip 210 can include, for example, silicon (Si). Alternatively, the semiconductor substrate forming the first semiconductor chip 210 can include a semiconductor element such as germanium (Ge) or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). Alternatively, the semiconductor substrate forming the first semiconductor chip 210 can have a silicon-on-insulator (SOI) structure. For example, the semiconductor substrate forming the first semiconductor chip 210 can include a buried oxide layer (BOX). The semiconductor substrate forming the first semiconductor chip 210 can include a conductive region, for example, an impurity-doped well. The semiconductor substrate forming the first semiconductor chip 210 can have various device isolation structures such as a shallow trench isolation (STI) structure.

[0136] In the first semiconductor chip 210, a semiconductor device including a plurality of individual devices of various types can be formed. The plurality of individual devices can include microelectronic devices, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET) such as a complementary metal-insulator-semiconductor (CMOS) transistor, a system large-scale integration (LSI) device, an image sensor such as a CMOS image sensor (CIS), a microelectromechanical system (MEMS), an active device, or a passive device. The plurality of individual devices can be electrically connected to a conductive region of the semiconductor substrate forming the first semiconductor chip 210. The semiconductor device can further include a conductive wiring line or a conductive plug that electrically connects the plurality of individual devices to the conductive region of the semiconductor substrate forming the first semiconductor chip 210 or electrically connects at least two of the plurality of individual devices. In addition, the plurality of individual devices can be electrically isolated from adjacent other individual devices by an insulating layer.

[0137] The first sub-package 100s and the second sub-package 200 can be mounted on the interposer substrate 20.

[0138] The interposer substrate 20 can include a base substrate formed of a semiconductor material and an upper pad and a lower pad formed on an upper surface and a lower surface of the base substrate, respectively. The base substrate can be formed of, for example, a silicon wafer or a glass substrate. In addition, an internal wiring line can be formed on the upper surface and / or the lower surface of the base substrate and / or in the base substrate. In addition, in the base substrate, a through via electrically connecting the upper pad to the lower pad can be formed.

[0139] The interposer substrate 20 can be mounted on the package substrate 10 through a connection terminal 25. The connection terminal 25 can be, for example, a solder ball or a bump.

[0140] The package substrate 10 can be, for example, a printed circuit board (PCB). The package substrate 10 can include a base substrate and upper and lower pads 16 formed on upper and lower surfaces thereof, respectively. The upper and lower pads 16 can be exposed through a solder resist layer covering the upper and lower surfaces of the base substrate.

[0141] The upper and lower pads 16 can have the same configuration as that of the upper and lower pads 106b and 106a described with reference to FIG. 1, and detailed descriptions thereof will be omitted. FIG. 1A The base substrate can have the same configuration as that of the base substrate described with reference to FIG. 1, and detailed descriptions thereof will be omitted. FIG. 1A The base substrate can have the same configuration as that of the base substrate described with reference to FIG. 1, and detailed descriptions thereof will be omitted.

[0142] The external connection terminals 15 can be attached to the lower surface of the package substrate 10. The external connection terminals 15 can be attached to, for example, the lower pads 16. The external connection terminals 15 can be, for example, solder balls or bumps. The external connection terminals 15 can electrically connect the semiconductor package 1 to an external device.

[0143] A first molding resin 30 surrounding a side surface of each of the first and second sub-packages 100s and 200 can be further formed on the package substrate 10. The first molding resin 30 can be formed of, for example, EMC. The first molding resin 30 can be formed separately from the molding resin of the first sub-package 100s.

[0144] In some embodiments, as shown in FIG. 2, the upper surface of the first sub-package 100s can be covered with the first molding resin 30. However, in other embodiments, the upper surface of the first sub-package 100s is not covered with the first molding resin 30. For example, an upper surface of the fourth semiconductor device 110d, which is the uppermost semiconductor device among the plurality of semiconductor devices 110 included in the first sub-package 100s, is not covered with the first molding resin 30. FIG. 9 In FIG. 2, the upper surface of the second sub-package 200 is shown as being non-co-planar with the upper surface of the first sub-package 100s. However, the upper surface of the second sub-package 200 can be co-planar with the upper surface of the first sub-package 100s. In this case, the upper surface of the fourth semiconductor device 110d and the upper surface of the first semiconductor chip 210 can be exposed from the first molding resin 30.

[0145] FIG. 9 In FIG. 2, the upper surface of the second sub-package 200 is shown as being non-co-planar with the upper surface of the first sub-package 100s. However, the upper surface of the second sub-package 200 can be co-planar with the upper surface of the first sub-package 100s. In this case, the upper surface of the fourth semiconductor device 110d and the upper surface of the first semiconductor chip 210 can be exposed from the first molding resin 30.

[0146] The second molding resin 140s surrounding a side surface of the semiconductor device 110 of the first sub-package 100s can correspond to the second molding resin 140 described with reference to FIG. 1. FIG. 1A ​The molding resin 140 is described. The second molding resin 140s may contact the first molding resin 30. Furthermore, at least one of the first underfill filler rounded corners 120a to 120d may extend to the interface between the second molding resin 140s and the first molding resin 30. In some embodiments, the first underfill filler rounded corners 120a to 120d protrude from the side surface of the semiconductor device 110 toward the interface.

[0147] The heat dissipation component 40 can be disposed on the first sub-package 100s and the second sub-package 200. The heat dissipation component 40 can be, for example, a heat sink, a heat pipe, or a liquid-cooled cold plate.

[0148] The heat dissipation component 40 may cover the upper surfaces of the first sub-package 100s, the second sub-package 200, and the first molding resin 30. In some embodiments, the heat dissipation component 40 may cover the upper surface of the fourth semiconductor device 110d, the upper surface of the first semiconductor chip 210, and the upper surface of the first molding resin 30.

[0149] A thermal interface material (TIM) may be provided between the first sub-package 100s and the second sub-package 200 and the heat dissipation member 40. The TIM may be formed of an insulating material or a material comprising an insulating material capable of maintaining electrical insulation. The TIM may include, for example, epoxy resin. The TIM may be, for example, an epoxy resin containing mineral oil, grease, gap filler, phase change gel, phase change material pad, or filler particles.

[0150] FIG. 10 This is a side sectional view showing an exemplary embodiment of a semiconductor package 1a according to a concept of the present invention.

[0151] because FIG. 10 Semiconductor package 1a and FIG. 9 The only difference between the semiconductor packages 1 is the construction of the first sub-package 100s, so this difference will be the main focus of the description.

[0152] The first sub-package 100s also includes a memory controller 110L (e.g., control circuitry) between the semiconductor device 110 and the first sub-package substrate 101s. A fifth bottom filler rounded corner 120L is disposed between the memory controller 110L and the first sub-package substrate 101s.

[0153] In this case, at least one of the first to fifth bottom filling fillets 120a, 120b, 120c, 120d, and 120L can extend to an interface between the second molding resin 140s and the first molding resin 30. A side surface of at least one of the first to fifth bottom filling fillets 120a, 120b, 120c, 120d, and 120L extending to the interface between the second molding resin 140s and the first molding resin 30 can be coplanar with a side surface of the first sub-package substrate 101s.

[0154] While the present concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details can be made therein without departing from the spirit and scope of the disclosure.

[0155] This application claims the benefit of priority to Korean Patent Application No. 10-2020-0001579, filed on January 6, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

Claims

1. A semiconductor package, comprising: substrate; Multiple semiconductor devices stacked on the substrate; Multiple bottom-filled rounded corners are disposed between the plurality of semiconductor devices and between the substrate and the plurality of semiconductor devices; as well as Molding resin surrounding the plurality of semiconductor devices. At least one of the bottom filler rounded corners is exposed from the side surface of the molding resin, and the side surface of the at least one of the bottom filler rounded corners is coplanar with the side surface of the molding resin.

2. The semiconductor package of claim 1, wherein the bottom fill filler rounded corner includes a first bottom fill filler rounded corner disposed between the substrate and the plurality of semiconductor devices, and wherein the first bottom fill filler rounded corner is exposed from a side surface of the molding resin.

3. The semiconductor package according to claim 2, wherein the distance between the side surface of the semiconductor device and the side surface of the molding resin is not greater than 500 μm.

4. The semiconductor package of claim 2, wherein the plurality of semiconductor devices comprises a first semiconductor device, a second semiconductor device, a third semiconductor device, and a fourth semiconductor device sequentially stacked on the first bottom filler rounded corner. The plurality of bottom fill fillets further include a second bottom fill fillet between the first semiconductor device and the second semiconductor device, a third bottom fill fillet between the second semiconductor device and the third semiconductor device, and a fourth bottom fill fillet between the third semiconductor device and the fourth semiconductor device. At least one of the second bottom filler rounded corner, the third bottom filler rounded corner, and the fourth bottom filler rounded corner is not exposed from the side surface of the molding resin.

5. The semiconductor package of claim 4, wherein each of the first to fourth bottom filler rounded corners comprises an inorganic filler, and at least two of the first to fourth bottom filler rounded corners comprise different amounts of inorganic filler.

6. The semiconductor package of claim 4, wherein each of the first to fourth bottom filler rounded corners protrudes from the side surface of the plurality of semiconductor devices.

7. The semiconductor package of claim 2, wherein the portion of the first bottom-filled rounded corner exposed from the molding resin contacts the upper surface of the substrate.

8. The semiconductor package of claim 7, wherein the substrate contacts the molding resin at a corner of the substrate.

9. A semiconductor package, comprising: Packaging substrate; Intermediate layer substrate stacked on the packaging substrate; A first sub-package and a second sub-package are arranged laterally on the interposer substrate; as well as A first molding resin surrounding the side surfaces of the first sub-package and the second sub-package. The first sub-encapsulation includes: First sub-package substrate; Multiple memory devices stacked on the first sub-package substrate; and The bottom is filled with rounded corners and disposed between the plurality of memory devices and between the first sub-package substrate and the plurality of memory devices. At least one of the bottom fillet rounded corners protrudes horizontally from the side surface of the plurality of storage devices by 200 μm to 500 μm.

10. The semiconductor package of claim 9, wherein the first sub-package further comprises a second molding resin surrounding the plurality of memory devices, and At least one of the bottom filler rounded corners extends to the interface between the first molding resin and the second molding resin.

11. The semiconductor package of claim 10, wherein the plurality of memory devices comprises a first memory device, a second memory device, a third memory device, and a fourth memory device sequentially stacked on the first sub-package substrate, and The bottom filler rounded corners include: A first bottom filler rounded corner is disposed between the first sub-package substrate and the first memory device; a second bottom filler rounded corner is disposed between the first memory device and the second memory device; a third bottom filler rounded corner is disposed between the second memory device and the third memory device; and a fourth bottom filler rounded corner is disposed between the third memory device and the fourth memory device.

12. The semiconductor package of claim 11, wherein the first bottom filler rounded corner of the bottom filler rounded corners protrudes horizontally the most.

13. The semiconductor package of claim 11, wherein the bottom filler rounded corners protrude from the side surfaces of the plurality of memory devices toward the side surface of the second molding resin.

14. The semiconductor package of claim 11, wherein at least two of the first to fourth bottom filler rounded corners comprise inorganic fillers of different compositions.

15. The semiconductor package of claim 11, wherein at least two of the first to fourth bottom filler rounded corners have different coefficients of thermal expansion.

16. The semiconductor package of claim 11, wherein at least two of the first to fourth bottom filler rounded corners are in contact with each other and an interface is interposed therebetween.

17. The semiconductor package of claim 10, wherein the side surface of at least one of the bottom filler rounded corners extending to the interface between the first molding resin and the second molding resin is coplanar with the side surface of the first sub-package substrate.

18. The semiconductor package of claim 9, wherein the first sub-package further comprises a memory controller chip disposed between the first sub-package substrate and the plurality of memory devices.

19. The semiconductor package of claim 18, wherein the plurality of memory devices are electrically interconnected with each other via through-silicon vias (TSVs).

20. A semiconductor package, comprising: Packaging substrate; Multiple semiconductor devices stacked on the packaging substrate; Multiple bottom-filled rounded corners are disposed between the multiple semiconductor devices and between the packaging substrate and the multiple semiconductor devices; as well as Molding resin surrounding the plurality of semiconductor devices. Each of the wherein the bottom-filled rounded corners protrudes to the outside of the side surfaces of the plurality of semiconductor devices. At least one of the bottom filler rounded corners is exposed from a side surface of the molding resin, and the side surface of the bottom filler rounded corner exposed from the side surface of the molding resin is coplanar with the side surface of the molding resin. The distance between the side surface of the plurality of semiconductor devices and the side surface of the molding resin is no greater than 500 μm.

Images