An airborne VDB receiver based on RF agile transceiver AD9361

Abstract

The invention discloses an airborne VDB receiver based on a radio frequency agile transceiver AD9361, comprising an antenna S1, a radio frequency preprocessing circuit S2, an AD9361 circuit S3, a signal processing circuit S4, a serial port driving circuit S5 and a power supply and clock circuit S6; the invention reduces the design complexity, uses more software to replace hardware, reduces more hardware debugging links, and more thoroughly realizes the design of software radio; the radio frequency channel module of the existing receiver is omitted, the volume is reduced by about 30%, the weight is reduced by about 50%, and the power consumption is reduced by about 30%; the digital circuit replaces most of the analog circuits in the existing equipment, greatly improving the reliability of the equipment.

Description

Technical Field

[0001] The invention relates to an airborne VDB receiver based on a radio frequency agile transceiver AD9361, belonging to the field of radio navigation. Background Art

[0002] The airborne VDB (VHF Data Broadcasting) receiver is a component of the Ground-Based Augmentation System (GBAS), which is the only satellite navigation system currently recognized by the International Civil Aviation Organization (ICAO) that supports Class I precision approach of aircraft. It can provide precision guidance for the precision approach and landing of aircraft, and can also provide enhancement for the local airspace of a certain terminal. The airborne VDB receiver operates in the frequency band of 108.0 to 117.95 MHz. Its main function is to receive and demodulate the space broadcast messages sent by the GBAS ground station, obtain the data of the final approach segment and the corresponding correction information such as pseudorange to assist the aircraft in completing precision approach and landing.

[0003] The design idea of ​​the existing airborne VDB receiver is to build an RF channel through discrete components such as preselectors, low-noise amplifiers, mixers, attenuators, filters, etc. to down-convert the RF signal received by the antenna to an intermediate frequency, and then convert it into a digital signal through an analog-to-digital converter (A / D), and demodulate the message information through signal processing software.

[0004] The disadvantages of existing airborne VDB receivers are: (1) complex circuit structure and low reliability; (2) large size and heavy weight, which may burden or make it impossible to equip aircraft with payload volume and weight requirements.

[0005] At present, there is no relevant literature report on an airborne VDB receiver based on a radio frequency agile transceiver to solve the above problems in China. Summary of the invention

[0006] The purpose of the present invention is to provide an airborne VDB receiver based on the RF agile transceiver AD9361 to solve the problems raised in the above background technology. The existing airborne VDB receiver has high design complexity, large size and heavy weight, and a new VDB receiver is designed. The design method based on the RF agile transceiver is adopted, and a single chip is used to replace the complex RF channel circuit, so that the entire VDB receiver only needs one circuit board to achieve the purpose of simplifying the design and reducing weight.

[0007] To achieve the above purpose, the present invention adopts the following technical solutions:

[0008] An airborne VDB receiver based on a radio frequency agile transceiver AD9361 comprises an antenna S1, a radio frequency preprocessing circuit S2, an AD9361 circuit S3, a signal processing circuit S4, a serial port driving circuit S5 and a power supply and clock circuit S6. When the receiver is working, the working channel of the signal channel is first matched to the channel set by the user. After the VDB receiver receives a frequency control command sent by an external control device through a data bus, the signal is converted by the serial port driving circuit S5 and then enters the signal processing circuit S4 for analysis and processing. The signal processing circuit S4 sets the working frequency of the AD9361 circuit S3 to a predetermined frequency according to the frequency control command. The VDB receiver After the receiver receives the spatial VDB signal through the antenna S1, it first enters the RF preprocessing circuit S2 for bandpass filtering, amplification, and differential conversion, and then enters the AD9361 circuit S3. The AD9361 circuit S3 performs AD sampling on the signal and sends it to the signal processing circuit S4. The signal processing circuit S4 performs D8PSK demodulation and decoding on the VDB signal to obtain the valid information of the VDB message, and then encodes the decoded data as required and outputs it through the serial port driver circuit S5. At the same time, the signal processing circuit S4 and the AD9361 circuit S3 jointly realize digital AGC control; the power supply and clock circuit S6 provides power and clock for each circuit of the receiver.

[0009] The RF preprocessing circuit S2 includes a bandpass filter A1, a low-noise amplifier A2 and a balun circuit A3. After the VDB spatial signal is received by the antenna S1, it first enters the bandpass filter A1 for bandpass filtering processing. The bandpass filter selects a bandpass filter with a passband slightly wider than the VDB signal frequency band range of 108.0 to 117.95 MHz; then it enters the low-noise amplifier A2 to reduce the noise coefficient of the RF channel; finally, it enters the balun circuit A3, converts the input single-ended signal into a differential signal, and then sends it to the AD9361 circuit S3, and the RF preprocessing is completed.

[0010] The operating parameters of the receiving channel of the AD9361 circuit S3, including the receiving frequency and the filter bandwidth, are given by the signal processing circuit S4 according to the frequency set by the user, and the AGC adjustment value is given by the signal processing circuit S4 according to the received signal strength.

[0011] The signal processing circuit S4 includes an FPGA circuit B1 and a DSP circuit B2. After the VDB signal enters the signal processing circuit S4 through AD sampling of the AD9361 circuit S3, the FPGA circuit B1 designs a digital filter for further bandpass filtering. The parameters of the designed digital filter are: a Butterworth IIR filter with a center frequency f s =10.5MHz, lower cutoff frequency f c1 =10KHz, upper cutoff frequency f c2=14KHz; after the signal is band-pass filtered, it is extracted, filtered, synchronized, D8PSK demodulated, decoded, and error corrected in the FPGA circuit B1 to obtain the valid data of the VDB message, and then the data is sent to the DSP circuit B2 for encoding as required and then output to the serial port driver circuit for output.

[0012] Compared with the prior art, the beneficial effects of the present invention are: 1) reducing the design complexity, using more software to replace hardware, reducing more hardware debugging links, and more thoroughly realizing the design of software radio;

[0013] (2) The RF channel module of the existing receiver is eliminated, which reduces the volume by about 30%, the weight by about 50%, and the power consumption by about 30%;

[0014] (3) Digital circuits have replaced most of the analog circuits in existing equipment, greatly improving the reliability of the equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a schematic diagram of the composition structure of the present invention;

[0016] Figure 2 It is a schematic diagram of the structure of the radio frequency preprocessing circuit in the present invention;

[0017] Figure 3 It is a schematic diagram of the structure of the signal processing circuit in the present invention;

[0018] Figure 4 The characteristic diagram of the bandpass filter designed in the FPGA circuit of the present invention;

[0019] Explanation of the reference numerals: S1 - antenna; S2 - RF preprocessing circuit; S3 - AD9361 circuit; S4 - signal processing circuit; S5 - serial port drive circuit; S6 - power supply and clock circuit; A1 - bandpass filter; A2 - low noise amplifier; A3 - balun circuit; B1 - FPGA circuit; B2 - DSP circuit. DETAILED DESCRIPTION

[0020] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0021] See also Figure 1, a VDB receiver is designed, including antenna S1, RF preprocessing circuit S2, AD9361 circuit S3, signal processing circuit S4 and serial port driving circuit S5, as well as power supply and clock circuit S6. When the receiver is working, it is necessary to first match the working channel of the signal channel to the channel set by the user. After the VDB receiver receives the frequency control command sent from the outside through the data bus, it goes through the level conversion of the serial port driving circuit S5 and enters the signal processing circuit S4 for analysis and processing. The signal processing circuit S4 sets the working frequency of the AD9361 circuit S3 to the predetermined frequency according to the frequency control command; after the VDB receiver receives the spatial VDB signal through the antenna S1, it first enters the RF preprocessing circuit S2 for bandpass filtering, amplification, and differential conversion processing, and then enters the AD9361 circuit S3, AD9 The 361 circuit S3 performs AD sampling on the signal and sends it to the signal processing circuit S4. The signal processing circuit S4 performs D8PSK demodulation and decoding on the VDB signal to obtain the valid information of the VDB message, and then encodes the decoded data according to the requirements of Appendix M of the aviation industry standard HB8392-2013 "Technical Requirements for Multi-Mode Receivers (MMR) for Civil Aircraft" of the People's Republic of China, and outputs it through the serial port driver circuit S5. At the same time, the signal processing circuit S4 and the AD9361 circuit S3 jointly realize digital AGC control; the power supply and clock circuit S6 provides power and clock for each circuit of the receiver.

[0022] See also Figure 2 The RF preprocessing circuit S2 in the present invention includes a bandpass filter A1, a low noise amplifier A2, and a balun circuit A3. After the VDB spatial signal is received by the antenna S1, it first enters the bandpass filter A1 for bandpass filtering. The bandpass filter selects a bandpass filter with a passband slightly wider than the VDB signal frequency band range of 108.0-117.95MHz; then it enters the low noise amplifier A2 to reduce the noise coefficient of the RF channel; finally, it enters the balun circuit A3, converts the input single-ended signal into a differential signal, and then sends it to the AD9361 circuit S3. At this point, the RF preprocessing is completed.

[0023] See also Figure 3 The signal processing circuit S4 in the present invention includes an FPGA circuit B1 and a DSP circuit B2. Since the bandwidth of the VDB signal is ±12KHz, and the minimum receiving bandwidth that the AD9361 circuit S3 can achieve is 200KHz, after the VDB signal enters the signal processing circuit S4 through AD sampling of the AD9361 circuit S3, the FPGA circuit B1 needs to design a digital filter for further bandpass filtering. The parameters of the designed digital filter are: a Butterworth IIR filter with a center frequency f s =10.5MHz, lower cutoff frequency f c1 =10KHz, upper cutoff frequency fc2 =14KHz, the characteristics of this bandpass filter refer to Figure 4 After the signal is band-pass filtered, it is extracted, filtered, synchronized, D8PSK demodulated, decoded, and error corrected in the FPGA circuit B1 to obtain the valid data of the VDB message, and then the data is sent to the DSP circuit B2 for encoding in accordance with the requirements of Appendix M of the Aviation Industry Standard of the People's Republic of China HB8392-2013 "Technical Requirements for Multi-Mode Receivers (MMR) for Civil Aircraft" and then output to the serial port driver circuit for output.

[0024] The above is a preferred embodiment of the present invention. For ordinary technicians in this field, according to the teachings of the present invention, without departing from the principles and spirit of the present invention, changes, modifications, substitutions and variations made to the implementation methods are still within the scope of protection of the present invention.

Claims

1. An airborne VDB receiver based on RF agile transceiver AD9361, characterized in that: It includes an antenna S1, a radio frequency preprocessing circuit S2, an AD9361 circuit S3, a signal processing circuit S4, a serial port driving circuit S5, and a power supply and clock circuit S6; When the receiver is working, firstly, the working channel of the signal channel is matched to the channel set by the user. After the VDB receiver receives the frequency control command sent by the external control device through the data bus, it enters the signal processing circuit S4 for analysis and processing after the level conversion of the serial port driving circuit S5. The signal processing circuit S4 sets the working frequency of the AD9361 circuit S3 to the predetermined frequency according to the frequency control command. After the VDB receiver receives the spatial VDB signal through the antenna S1, it first enters the RF preprocessing circuit S2 for bandpass filtering, amplification, and differential conversion processing, and then enters the AD9361 circuit S3. The AD9361 circuit S3 performs AD sampling on the signal and sends it to the signal processing circuit S4. The signal processing circuit S4 performs D8PSK demodulation and decoding on the VDB signal to obtain the valid information of the VDB message, and then encodes the decoded data according to the requirements and outputs it through the serial port driving circuit S5. At the same time, the signal processing circuit S4 and the AD9361 circuit S3 jointly realize digital AGC control. The power supply and clock circuit S6 provides power supply and clock for each circuit of the receiver. The RF preprocessing circuit S2 includes a bandpass filter A1, a low noise amplifier A2 and a balun circuit A3. After the VDB spatial signal is received by the antenna S1, it first enters the bandpass filter A1 for bandpass filtering. The bandpass filter selects a bandpass filter with a passband slightly wider than the VDB signal frequency band range of 108.0 to 117.95 MHz; then it enters the low noise amplifier A2 to reduce the noise coefficient of the RF channel; finally, it enters the balun circuit A3, converts the input single-ended signal into a differential signal, and then sends it to the AD9361 circuit S3. At this point, the RF preprocessing is completed; The operating parameters of the receiving channel of the AD9361 circuit S3, including the receiving frequency and the filter bandwidth, are given by the signal processing circuit S4 according to the frequency set by the user, and the AGC adjustment value is given by the signal processing circuit S4 according to the received signal strength; The signal processing circuit S4 includes an FPGA circuit B1 and a DSP circuit B2. After the VDB signal enters the signal processing circuit S4 through AD sampling of the AD9361 circuit S3, the FPGA circuit B1 designs a digital filter for further bandpass filtering. The parameters of the designed digital filter are: a Butterworth IIR filter with a center frequency f s =10.5MHz, lower cutoff frequency f c1 =10KHz, upper cutoff frequency f c2 =14KHz; after the signal is band-pass filtered, it is extracted, filtered, synchronized, D8PSK demodulated, decoded, and error corrected in the FPGA circuit B1 to obtain the valid data of the VDB message, and then the data is sent to the DSP circuit B2 for encoding as required and then output to the serial port driver circuit for output.

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