Memory device and operation method thereof

Abstract

The present disclosure relates to an operating method of a memory device. The operating method of the memory device may include performing a programming operation on a memory block in response to a programming command from a controller, and when the programming operation fails, applying a programming voltage to a dummy word line connected to a dummy cell in the memory block so that the dummy cell has an indication threshold voltage higher than a normal pass voltage, and providing a programming failure signal to the controller.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2019-0173110, filed on December 23, 2019, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure are directed to a memory device. Background Art

[0004] Recently, the computing environment paradigm has shifted to a ubiquitous computing environment where a computer system can be used almost anywhere, anytime. As a result, the use of portable electronic devices such as mobile phones, digital cameras, and notebook computers is growing rapidly. Such portable electronic devices typically use a memory system that utilizes a memory device, i.e., a data storage device. The data storage device can be used as a primary memory device or an auxiliary memory device of the portable electronic device.

[0005] Since the data storage device using the memory device has no mechanical drive, the data storage device has excellent stability and durability, high information access speed and low power consumption. As an example of a memory system having these advantages, the data storage device includes a universal serial bus (USB) memory device, a memory card with various interfaces, a solid state drive (SSD), etc. Summary of the invention

[0006] Various embodiments relate to a memory device and an operating method thereof capable of securing reliability by retaining data in a memory block even when a progressive defect occurs in a corresponding memory block.

[0007] In an embodiment, an operating method of a memory device may include: performing a programming operation on a memory block in response to a programming command from a controller; and when the programming operation fails, applying a programming voltage to a dummy word line connected to a dummy cell within the memory block so that the dummy cell has an indication threshold voltage higher than a normal pass voltage, and providing a programming failure signal to the controller.

[0008] In an embodiment, a memory device may include: a memory block including memory cells and dummy cells; a main word line connected to the memory cells; a dummy word line connected to the dummy cells; a voltage supply circuit adapted to: perform a programming operation on the memory block in response to a programming command from a controller, and when the programming operation fails, apply a programming voltage to the dummy word line so that the dummy cell has an indication threshold voltage higher than a normal pass voltage; and control logic adapted to provide a programming failure signal to the controller when the programming operation fails.

[0009] In an embodiment, a method for operating a memory device may include: in response to a program command for a program failure cell array, applying a program voltage to a dummy word line connected to a dummy cell within the program failure cell array; and in response to a subsequent program command for the program failure cell array, providing a program failure signal when failure mark data is sensed from the program failure cell array.

[0010] According to the present embodiment, a memory device and an operating method thereof capable of ensuring reliability by retaining data in a memory block even when a progressive defect occurs in a corresponding memory block can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a diagram illustrating a data processing system including a memory device according to an embodiment of the present disclosure.

[0012] Figure 2 is a diagram illustrating a memory device according to an embodiment of the present disclosure.

[0013] Figures 3 to 5 is a flowchart describing the operation of a memory device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0014] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be understood that the following description will focus on parts required for understanding the operation according to the embodiment, and will exclude descriptions of other parts to avoid unnecessarily obscuring the subject matter of the present disclosure.

[0015] Hereinafter, various embodiments will be described in detail with reference to the accompanying drawings.

[0016] Figure 1 is a diagram exemplarily showing an example of a data processing system 100 including a memory device 150 according to an embodiment of the present disclosure.

[0017] Reference Figure 1 , the data processing system 100 may include a host 102 and a memory system 110 .

[0018] The host 102 may include an electronic device, for example, a portable electronic device such as a mobile phone, an MP3 player, and a laptop computer, or a non-portable electronic device such as a desktop computer, a game console, a TV, and a projector.

[0019] The host 102 may include one or more OS (operating systems). The OS manages and controls all functions and operations of the host 102, and provides interactive operations between the host 102 and a user who uses the data processing system 100 or the memory system 110. The OS may support functions and operations corresponding to the user's purpose of use, and may be divided into a general-purpose OS and a mobile OS according to the mobility of the host 102. Among the OSs, the general-purpose OS may be divided into a personal OS and an enterprise OS according to the user's use environment.

[0020] The memory system 110 may operate to store data of the host 102 in response to a request of the host 102. For example, the memory system 110 may be implemented as any of various types of storage devices including an SSD (Solid State Drive), an MMC (Multi Media Card) such as an eMMC (Embedded MMC), an RS-MMC (Reduced Size MMC), or a micro MMC, an SD (Secure Digital) card such as a mini SD or micro SD card, a USB (Universal Serial Bus) storage device, a UFS (Universal Flash Storage) device, a CF (Compact Flash) card, a Smart Media Card, and a Memory Stick.

[0021] The memory system 110 may be implemented by various types of memory devices. For example, the memory device may include volatile memory devices such as DRAM (dynamic random access memory) and SRAM (static RAM), and non-volatile memory devices such as ROM (read only memory), MROM (mask ROM), PROM (programmable ROM), EPROM (erasable programmable ROM), EEPROM (electrically erasable programmable ROM), FRAM (ferroelectric ROM), PRAM (phase change RAM), MRAM (magnetic RAM), RRAM (resistive RAM), and flash memory. The flash memory may have a 3D stacked structure.

[0022] The memory system 110 may include a memory device 150 and a controller 130. The memory device 150 may store data for the host 102, and the controller 130 may control data storage in the memory device 150.

[0023] The controller 130 and the memory device 150 may be integrated into one semiconductor device. For example, the controller 130 and the memory device 150 may be integrated into one semiconductor device to constitute an SSD. When the memory system 110 is used as an SSD, the operation speed of the host 102 connected to the memory system 110 may be increased. Further, the controller 130 and the memory device 150 may be integrated into one semiconductor device to constitute a memory card. For example, the controller 130 and the memory device 150 may constitute a memory card such as a PC card (PCMCIA: Personal Computer Memory Card International Association), a CF card, an SMC (Smart Media Card), a memory stick, an MMC such as an RS-MMC or a micro MMC, an SD card such as a mini SD, a micro SD, or an SDHC, and a UFS device.

[0024] As another example, the memory system 110 may constitute a computer, a UMPC (ultra mobile PC), a workstation, a netbook, a PDA (personal digital assistant), a portable computer, a web tablet, a tablet computer, a wireless phone, a mobile phone, a smart phone, an e-book, a PMP (portable multimedia player), a portable game console, a navigation system, a black box, a digital camera, a DMB (digital multimedia broadcasting) player, a three-dimensional TV, a smart TV, a digital audio recorder, a digital audio player, a digital photo recorder, a digital photo player, a digital video recorder, a digital video player, a storage device constituting a data center, a device capable of transmitting / receiving information in a wireless environment, one of the various electronic devices constituting a home network, one of the various electronic devices constituting a computer network, one of the various electronic devices constituting a telematics network, an RFID (radio frequency identification) device, or one of the various components constituting a computing system.

[0025] The memory device 150 may be a nonvolatile memory device, and the stored data is retained even if power is not supplied. The memory device 150 may store data provided from the host 102 through a programming operation, and provide the data stored in the memory device 150 to the host 102 through a read operation. The memory device 150 may include a plurality of memory blocks, each of the plurality of memory blocks may include a plurality of pages, and each of the plurality of pages may include a plurality of memory cells coupled to a word line. In an embodiment, the memory device 150 may be a flash memory. The flash memory may have a 3D stacked structure.

[0026] The controller 130 may control the memory device 150 in response to a request from the host 102. For example, the controller 130 may provide the host 102 with data read from the memory device 150, and store the data provided from the host 102 in the memory device 150. For this operation, the controller 130 may control a read operation, a program operation, and an erase operation of the memory device 150.

[0027] For example, the controller 130 may receive a write command and write data from the host 102. The controller 130 may generate a program command for a plurality of pages in response to the write command to store data in the memory device 150. The controller 130 may provide the generated program command and data to the memory device 150.

[0028] Figure 1 1 and 1. The first block BLOCK1 among the plurality of memory blocks included in the memory device 150 and the plurality of pages included in the first block BLOCK1 are shown. The controller 130 may generate a program command in the order of the first to third pages PAGE1 to PAGE3 of the first block BLOCK1 and provide the program command to the memory device 150. In order to quickly process the write command, the controller 130 may perform an operation of generating a program command according to a pipeline scheme and providing the generated command to the memory device 150. For example, the controller 130 may generate a program command for the second page PAGE2 and the third page PAGE3 while providing the program command for the first page PAGE1 to the memory device 150.

[0029] When stress is accumulated on word lines, etc. while the user uses the memory device 150, a progressive defect may occur in a memory block. That is, although the memory block operates normally during the test before the memory device 150 is shipped, a defect may occur in the memory block thereafter. The programming operation cannot be performed normally in the defective block. For example, when the memory device 150 programs data to a defective memory block, the data may not be programmed as expected, which results in a programming failure.

[0030] When the result obtained by performing the program operation on the first block BLOCK1 indicates that a program failure occurs, the memory device 150 may provide a program failure signal for the first block BLOCK1 to the controller 130. Since the first block BLOCK1 may have a defect, the controller 130 may determine the first block BLOCK1 as a defective block. The controller 130 may not generate a program command for the defective block so that the program operation is no longer performed on the defective block.

[0031] Even after the controller 130 determines that the first block BLOCK1 is a defective block, the memory device 150 may perform a program operation on the first block BLOCK1. For example, because the controller 130 operates according to a pipeline scheme, the controller 130 may generate and provide a program command for the second page PAGE2 and the third page PAGE3 before determining that the first block BLOCK1 is a defective block. However, depending on the cause of the defective memory block, when the program operation is performed on the defective memory block, the defective memory block may be degraded. When the defective block is degraded, the data programmed in the defective block may be damaged.

[0032] However, the controller 130 canceling the generation or provision of program commands for the second and third pages PAGE2 and PAGE3 to protect the data stored in the defective first block BLOCK1 may reduce the performance of the memory system 110. This is because the controller 130 needs to stop the operation of the pipeline scheme in order to cancel the generation or provision of the program commands.

[0033] According to an embodiment of the present disclosure, even if a program failure occurs in a memory block and the memory block is determined to be a defective block, a program command for the defective block is provided, and the memory device 150 may interrupt the program operation for the defective block. Although the controller 130 provides the program command for the defective block to the memory device 150 without stopping the operation of the pipeline scheme, the program operation for the defective block may not be performed. Therefore, while ensuring the reliability of the data stored in the defective block, the performance of the memory system 110 may be improved.

[0034] Will refer to Figures 2 to 5 The structure and operation of the memory device 150 according to various embodiments are described.

[0035] Figure 2 is a diagram showing a structure of a memory device 150 according to an embodiment.

[0036] The memory device 150 may include a voltage supply circuit 310 , a read / write circuit 320 , a memory cell array 330 , and control logic 350 .

[0037] The memory cell array 330 may include a plurality of memory blocks. The plurality of memory blocks may be coupled to the voltage supply circuit 310 through a drain selection line DSL, a plurality of word lines, and a source selection line SSL. The plurality of memory blocks may be coupled to the read / write circuit 320 through a plurality of bit lines BL1 to BLm. Figure 2 The memory cell array 330 including a single memory block is illustrated.

[0038] Reference Figure 2, the memory cell array 330 may include a plurality of cell strings 340 connected to a plurality of bit lines BL1 to BLm. The cell string 340 of each column may include one or more drain select transistors DST and one or more source select transistors SST. Between the drain select transistors DST and the source select transistors SST, a plurality of memory cells MC1 to MCn may be connected in series.

[0039] The source of the source select transistor SST may be connected to a common source line CSL. The drain of the drain select transistor DST may be connected to a bit line. The gate of the source select transistor SST included in different cell strings may be connected to a source select line SSL. The gate of the drain select transistor DST may be connected to a drain select line DSL. The memory cells MC1 to MCn may be connected to main word lines MWL1 to MWLn. A group of memory cells connected to the same word line among the memory cells included in different cell strings may be referred to as a physical page. In an embodiment, each of the memory cells may store 1 bit of data or multi-bit data therein. When each of the memory cells may store multi-bit data therein, a physical page may include a plurality of logical pages. A logical page may correspond to a minimum unit in which the memory device 150 may perform a programming operation at one time. A storage block may include memory cells connected to a plurality of main word lines. A storage block may correspond to a minimum unit in which the memory device 150 may perform an erase operation at one time.

[0040] The memory device 150 may further include a dummy word line between the selection line and the main word line. For example, the memory device 150 may include a first dummy word line DWL1 between the source selection line SSL and the first main word line MWL1, and a second dummy word line DWL2 between the drain selection line DSL and the nth main word line MWLn. The memory block may further include dummy cells DC1 and DC2 connected to the dummy word line. For example, the memory device 150 may erase the memory block and then program the dummy cells DC1 and DC2 of the memory block, thereby reducing the threshold voltage difference between the selection transistors and the memory cells adjacent to each other. When the dummy cells DC1 and DC2 are erased and then programmed, the dummy cells DC1 and DC2 may have a threshold voltage referred to as an initial threshold voltage. When the threshold voltage difference between the selection transistors and the memory cells adjacent to each other is reduced, the inter-band tunneling may be reduced to reduce the charge loss of the data stored in the memory cell.

[0041] With the development of technology, the integration of the memory device 150 has gradually increased. The increase in the integration of the memory device 150 indicates that the distance between the memory cells is reduced, and the reduction in the distance between the memory cells indicates that the distance between adjacent word lines and the distance between adjacent bit lines are reduced. As the distance between the word lines and the distance between the bit lines are reduced, the word lines or the bit lines may be unexpectedly connected to each other. When the word lines or the bit lines are unexpectedly connected to each other, the memory device 150 cannot perform the expected operation on the memory cell. When the memory device 150 cannot perform the expected operation on the memory cell, the reliability of the write / read operation of the memory device 150 may be reduced.

[0042] Even if the word lines or bit lines have not been coupled to each other in a test step before the memory device 150 is shipped, they may be coupled to each other due to voltage stress applied to the word lines and bit lines when a user uses the memory device 150. When program operations are continuously performed on defective blocks associated with the word lines or bit lines coupled to each other, the memory device 150 may not be able to store normal data therein, and data already stored in the defective blocks may also be damaged.

[0043] According to an embodiment of the present disclosure, when a programming failure occurs in a certain memory block, the memory device 150 may apply a programming voltage to a dummy word line DWL associated with the memory block, thereby increasing the threshold voltage of a dummy cell DC connected to the dummy word line DWL. The dummy word line DWL may be Figure 2 , or both of the dummy word lines DWL1, DWL2, or both shown in . For example, when the memory device applies a programming voltage to the dummy word line DWL1, the threshold voltage of the dummy cell DC1 may increase. When a programming operation is performed on a certain memory block, the memory device 150 may determine whether the memory block is a defective block based on the threshold voltage of the dummy cell DC associated with the memory block. When it is determined that the memory block associated with the programming operation is a defective block, the memory device 150 may stop the programming operation.

[0044] The voltage supply circuit 310 may supply a program voltage, a read voltage, and a pass voltage to a word line according to an operation mode. The voltage supply circuit 310 may generate a plurality of voltages based on an external power supply voltage supplied to the memory device 150. The voltage supply circuit 310 may select one of the memory blocks (or sectors) in the memory cell array, select one of the word lines of the selected memory block, and supply a word line voltage to the selected word line. If necessary, the voltage supply circuit 310 may supply a word line voltage to an unselected word line.

[0045] For example, during a read operation, the read / write circuit 320 may float the bit line by precharging the bit line. The voltage supply circuit 310 may apply a read voltage to the selected word line and a pass voltage to the unselected word line. The word line connected to the selected memory cell may be referred to as the selected word line. The word line other than the selected word line may be referred to as the unselected word line. According to the threshold voltage of the memory cell and the voltage applied to the word line connected to the memory cell, a current may flow through the memory cell. The read voltage is a voltage for distinguishing between the data indicated by the selected memory cell, and may have a value between two threshold voltage states among the voltage states that the memory cell may have. The pass voltage that allows current to flow regardless of the threshold voltage value of the unselected memory cell may have a higher voltage than the threshold voltage state that the memory cell may have. For example, during a normal read operation, the normal pass voltage applied to the dummy word line DWL may be higher than the initial threshold voltage. A normal read operation indicates a read operation performed before a memory block associated with the read operation or the program verification operation is determined as a defective block when the memory device 150 performs a read operation or a program verification operation. When the voltage supply circuit 310 applies a read voltage and a pass voltage, a current may flow through a bit line connected to a selected memory cell having a threshold voltage lower than the read voltage, and no current may flow through a bit line connected to a selected memory cell having a threshold voltage higher than the read voltage. Depending on whether a current flows through a bit line connected to each of the page buffers, different data may be buffered. Therefore, the threshold voltage states of the memory cells may be distinguished from each other according to the read operation.

[0046] During a verification / normal read operation, the read / write circuit 320 may operate as a sense amplifier to read data from the memory cell array. During a programming operation, the read / write circuit 320 may operate as a write driver to drive the bit line according to the data to be stored in the memory cell array. During a programming operation, the read / write circuit 320 may receive data to be stored in the memory cell array from a buffer (not shown) and drive the bit line according to the received data. The read / write circuit 320 may include a plurality of page buffers 322 to 326, each of the plurality of page buffers 322 to 326 corresponds to a bit line or a bit line pair, and each of the page buffers 322 to 326 may include a plurality of latches (not shown). The page buffers 322 to 326 may be connected to the memory cell array 330 via bit lines BL1 to BLm.

[0047] The plurality of page buffers 322 to 326 may buffer data received from the controller 130 together with a program command. During a program operation, the plurality of page buffers may transmit the buffered data to a selected memory cell through the bit lines BL1 to BLm. During a program verification operation, the page buffers 322 to 326 may sense data from a selected memory cell through the bit lines BL1 to BLm. During a read operation, the page buffers 322 to 326 may sense data from a memory cell in a selected page through the bit lines BL1 to BLm, and may output the sensed data to a data input / output circuit (not shown). During an erase operation, the page buffers 322 to 326 may float the bit lines BL1 to BLm.

[0048] The control logic 350 may receive commands and addresses from the controller 130. The control logic 350 may control the voltage supply circuit 310 and the read / write circuit 320 in response to the commands and addresses. For example, the control logic 350 may operate the read / write circuit 320 as a sense amplifier or a write driver according to the commands. The control logic 350 may transmit the commands and addresses to the voltage supply circuit 310, and control the voltage supply circuit 310 to supply a program voltage, a read voltage, a pass voltage, etc. to selected word lines and unselected word lines.

[0049] Will refer to Figures 3 to 5 The operation of the memory device 150 according to the embodiment is described in detail.

[0050] Figure 3 is a flowchart illustrating the operation of the memory device 150 with respect to a program command according to an embodiment.

[0051] In step S302 , the control logic 350 may receive a program command and program data from the controller 130 .

[0052] In step S304, the memory device 150 may perform a program operation on the memory block in response to the program command. Figure 4 The programming operation of step S304 is described in detail.

[0053] In step S306 , the control logic 350 may determine a program state through the program operation of step S304 .

[0054] When the programming status is determined to be passed (“passed” in step S306 ), the control logic 350 may provide a programming pass signal to the controller 130 in step S312 .

[0055] When the program status is determined to be a fail (“Fail” in step S306 ), the memory device 150 may perform steps S308 and S310 .

[0056] In step S308 , the control logic 350 may control the voltage supply circuit 310 to program the dummy word line DWL of the memory block.

[0057] For example, the voltage supply circuit 310 may precharge all bit lines associated with the storage block to a programming enable voltage. The programming enable voltage may be a ground voltage GND. When the bit lines associated with the storage block are precharged to the programming enable voltage, the voltage supply circuit 310 may apply a pass voltage to the main word lines MWL1 to MWLn. In an embodiment, the voltage supply circuit 310 may also apply a pass voltage to a dummy word line DWL. When the pass voltage is applied to the main word lines MWL1 to MWLn, the memory cells in the storage block may be turned on. When a programming voltage is applied to the dummy word line DWL while the memory cells are turned on, the dummy cell DC connected to the dummy word line DWL may be programmed. The voltage supply circuit 310 may apply a programming voltage to the dummy word line DWL, thereby increasing the threshold voltage of the dummy cell DC to a voltage higher than the normal pass voltage. The increased threshold voltage may indicate that the storage block is a defective block. The increased threshold voltage is referred to as an indication threshold voltage.

[0058] When the memory device 150 performs a normal read operation, because the threshold voltages of all dummy cells DC are higher than the normal pass voltage, no current can flow through all bit lines associated with the storage block. Therefore, regardless of the data stored in the selected memory cell, the page buffer can buffer the fail mark data. For example, according to the values ​​sensed from the bit lines BL1 to BLm when no current flows through the bit lines BL1 to BLm, the fail mark data can be data in which all data bits are "0" or "1". During a subsequent programming verification operation, the control logic 350 can determine whether the storage block is a defective block based on the data buffered in the page buffer. When the storage block is determined to be a defective block during a subsequent programming verification operation, the control logic 350 can interrupt the programming operation on the defective block.

[0059] When the program state is determined to be interrupted ("interrupted" in step S306), the memory device 150 may perform steps S309 and S310. When fail flag data is detected in the program verification operation, the memory device 150 may interrupt the program state determination.

[0060] In step S309 , the memory device 150 may interrupt the programming operation.

[0061] In step S310 , the memory device 150 may provide a program fail signal to the controller 130 .

[0062] Figure 4 is a flowchart illustrating a program operation of the memory device 150 according to an embodiment. Figure 4Sub-operations that may be included in step S304 are shown.

[0063] A programming operation may include multiple programming loops. A programming loop may include a programming period and a programming verification period.

[0064] Step S402 may correspond to a programming period. The programming period may include a setup sub-period, a pass pulse sub-period, a programming pulse sub-period, and a discharge sub-period.

[0065] During the setting sub-period, the voltage supply circuit 310 may precharge the bit line connected to the selected series including the selected memory cell to the program enable voltage, and may precharge the bit line connected to the unselected series including the unselected memory cell to the program inhibit voltage. The bit line connected to the selected string is referred to as the selected bit line. The bit line connected to the unselected string is referred to as the unselected bit line. The program enable voltage may be the ground voltage GND. The program inhibit voltage may be the power supply voltage Vcc. During the setting sub-period, a selection voltage may be applied to the drain select line DSL.

[0066] When a program enable voltage is applied to a selected bit line and a select voltage is applied to a drain select line DSL, the drain select transistor DST may be turned on. Thus, the selected string may not be floated. According to the program enable voltage applied to the selected bit line, the selected string may be precharged.

[0067] When a program inhibit voltage is applied to an unselected bit line and a selection voltage is applied to a drain selection line DSL, the drain selection transistor DST may be turned off. Thus, the unselected string may be floated. The channel potential of the unselected string may increase due to the selection voltage. For example, the channel potential of the unselected string may increase to a level at which the threshold voltage of the drain selection transistor DST is lowered by the selection voltage.

[0068] During the pass pulse sub-period, the voltage supply circuit 310 may apply a pass voltage to an unselected word line coupled to an unselected memory cell. In an embodiment, the pass voltage may be applied to a selected word line coupled to a selected memory cell. When the pass voltage is applied to the selected word line, the selected memory cell included in the selected string may be turned on. Because the channel of the unselected string floats, when the pass voltage is applied to the unselected word line, the channel potential of the unselected string may increase.

[0069] During the programming pulse sub-period, the voltage supply circuit 310 may apply a programming voltage to the selected word line. When the difference between the level of the channel potential and the level of the programming voltage applied to the selected word line is equal to or greater than the reference value, the selected memory cell may be programmed. When the programming voltage is applied to the selected word line, the selected memory cell included in the selected string among the memory cells connected to the selected word line may be programmed. Because the channel of the unselected string floats, the channel potential of the unselected string may increase when the programming voltage is applied to the selected word line. Because the channel potential of the unselected string is increased simultaneously when the pass voltage and the programming voltage are applied, the difference between the level of the channel potential and the level of the programming voltage applied to the selected word line may be less than the reference value. Therefore, the memory cell included in the unselected string may not be programmed.

[0070] During the discharge sub-period, the voltage supply circuit 310 may discharge the voltage precharged to the bit line and the voltage applied to the word line.

[0071] Step S404 may correspond to a program verification period.

[0072] During the program verification period, the voltage supply circuit 310 may apply a verification voltage to the selected word line and a pass voltage to the unselected word lines. The voltage supply circuit 310 may apply a normal pass voltage to a dummy word line DWL among the unselected word lines. The verification voltage may be a voltage for verifying whether the selected memory cell has an expected threshold voltage, and may have a value between two threshold voltage states among voltage states that the memory cell may have.

[0073] The read / write circuit 320 may perform a verification operation by applying a verification voltage and a pass voltage to compare the data buffered in the page buffer with the data and the fail flag data received from the controller 130. The fail flag data indicates data buffered in the page buffer when the dummy memory cell DC is programmed to the indicated threshold voltage. The fail flag data may be sensed from the bit lines BL1 to BLm when no current flows through the bit lines BL1 to BLm.

[0074] When the data buffered in the page buffer is equal to the data received from the controller 130 (“PASS” in step S404 ), the control logic 350 may determine the program state as PASS in step S406 .

[0075] When the data buffered in the page buffer is equal to the fail mark data (“fail mark data” in step S404 ), the control logic 350 may determine that the memory block is a defective block in step S412 , and thus may determine the program state as interrupted.

[0076] According to an embodiment, although a program command is provided for a defective block, in step S402, the memory device 150 may apply only one program voltage and interrupt the program operation according to the result of applying the single program voltage. Because the program operation for the defective block is interrupted, the data stored in the defective block can be protected.

[0077] When the data buffered in the page buffer is different from both the data received from the controller 130 and the fail flag data ("Fail" in step S404), the selected memory cell may not be fully programmed. In step S408, the control logic 350 may determine whether the number of program loops reaches a maximum value.

[0078] When the number of programming loops has not reached the maximum value ("No" in step S408), in step S410, the control logic 350 may change the programming voltage to be applied to the selected word line in the next programming loop. For example, when the memory device 150 performs a programming operation according to the ISPP (Incremental Step Pulse Programming) method, the control logic 350 may increase the programming voltage. Further, the memory device 150 may perform step S402 again during the next programming loop. For example, during the next programming loop, the selected memory cell having a threshold voltage higher than the verification voltage may become program-inhibited. For example, during the next programming loop, the selected memory cell having a threshold voltage equal to or lower than the verification voltage may remain program-enabled.

[0079] When the number of program loops reaches the maximum value (“Yes” in step S408 ), the control logic 350 may determine that the program status is a fail in step S414 .

[0080] Figure 5 is a flow chart illustrating the operation of the memory device 150 with respect to a read command according to an embodiment.

[0081] In step S502 , the control logic 350 may receive a read command from the controller 130 .

[0082] In step S504, the voltage supply circuit 310 may apply a read voltage to a selected word line of a memory block associated with a read command, and apply a pass voltage to unselected word lines. When step S504 is performed for the first time, because the control logic 350 has not yet checked whether the memory block is a defective block, the control logic 350 may perform a normal read operation. That is, the voltage supply circuit 310 may apply a normal pass voltage to a dummy word line DWL among unselected word lines. Based on the threshold voltage of the memory cell, data may be buffered in a page buffer.

[0083] In step S506 , the read / write circuit 320 may determine whether the data buffered in the page buffer is equal to the fail flag data.

[0084] When the memory block associated with the read operation is a defective block, the dummy cell DC included in the memory block may have an indication threshold voltage. Because the indication threshold voltage is higher than the normal pass voltage, as a result of a normal read operation, no current may flow through all bit lines associated with the memory block. When no current flows through all bit lines, regardless of the data actually stored in the selected memory cell, the fail mark data may be buffered in the page buffer. When a normal read operation is performed on a defective block, the memory device 150 cannot provide the data provided by the controller 130.

[0085] When the data is different from the fail flag data (“No” in step S506 ), the control logic 350 may provide the data to the controller 130 in step S510 .

[0086] When the data is equal to the fail flag data ("Yes" in step S506), in step S508, the control logic 350 may determine that the memory block is a defective block and increase the pass voltage applied to the dummy word line DWL. For example, the memory device 150 may increase the pass voltage applied to the dummy word line DWL to a voltage higher than the indicated threshold voltage.

[0087] The memory device 150 may perform step S504 again by applying a pass voltage higher than the indicated threshold voltage to the dummy word line DWL instead of performing a normal read operation. The read operation performed by applying a pass voltage higher than the indicated threshold voltage to the dummy word line DWL is referred to as an additional read operation.

[0088] During the additional read operation, the current in all dummy cells DC included in the memory block may not be interrupted. Therefore, when the additional read operation is performed, the data buffered in the page buffer in step S506 may not be the fail mark data, but the data actually programmed in the selected memory cell. In step S510, the read / write circuit 320 may provide the data to the controller 130.

[0089] According to an embodiment, when a read operation is performed on a defective block in which a dummy cell DC has been programmed, the memory device 150 can perform an additional read operation by applying a pass voltage higher than the indicated threshold voltage to the dummy word line DWL. Even if the dummy cell DC of the defective block is programmed and thus the threshold voltage of the dummy cell DC is increased, the memory device 150 can read the data stored in the defective block.

[0090] According to an embodiment, when a program failure occurs in a certain memory block, the memory device 150 may apply a program voltage to the dummy word line DWL so that the dummy cells DC of the memory block have an indication threshold voltage, thereby indicating that the memory block is a defective block.

[0091] During a normal read operation on a certain memory block, when fail flag data is buffered in the page buffer because no current flows through the dummy cell DC, the memory device 150 may determine that the memory block is a defective block. Even during a program verification operation performed in response to a program command from the controller 130, the memory device 150 may perform a normal read operation and thus determine whether the memory block associated with the program command is a defective block.

[0092] Although a program command for a defective block is received from the controller 130, when the memory block associated with the program command is determined to be a defective block, the memory device 150 may stop the program operation. Therefore, the memory device 150 may protect the data stored in the defective block without interrupting the operation of the pipeline scheme. That is, according to various embodiments of the present invention, the performance and reliability of the memory system 110 including the memory device 150 may be improved.

[0093] Although various embodiments have been described for purposes of illustration, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.

Claims

1. A method for operating a memory device, comprising: In response to a program command from a controller, performing a program operation on a memory block according to a pipeline scheme; and When the programming operation fails, a programming voltage is applied to a dummy word line connected to a dummy cell in the memory block so that the dummy cell has an indication threshold voltage higher than a normal pass voltage, the memory block is determined as a defective block, and a programming failure signal is provided to the controller, Wherein, after the storage block is determined to be a defective block, the controller provides a program command for the defective block to the memory device without stopping the operation of the pipeline scheme, and the memory device applies a programming voltage and interrupts the programming operation according to the result of applying the single programming voltage.

2. The operating method according to claim 1, wherein performing the programming operation comprises: precharging the selected bit line to a program enable voltage and precharging the unselected bit lines to a program inhibit voltage; applying a pass voltage to unselected word lines; increasing a threshold voltage of a selected memory cell by applying the programming voltage to the selected word line; performing a verify operation to verify the selected memory cell; and When fail flag data is detected as a result of the verification operation, the program fail signal is provided to the controller. 3 . The operating method according to claim 2 , wherein the fail flag data is detected when no current flows through a bit line coupled to the selected memory cell.

4. The operating method according to claim 2, wherein performing the verification operation comprises: applying a verification voltage to the selected word line; applying the pass voltage to the unselected word lines; and The normal pass voltage is applied to the dummy word line.

5. The operating method according to claim 4, further comprising: In response to a read command from the controller, performing a normal read operation on the memory block; When the fail flag data is read as a result of the normal read operation, retrying the read operation by applying a pass voltage higher than the indication threshold voltage to the dummy word line; and The controller is provided with data acquired as a result of the retry.

6. A memory device comprising: A storage block including a memory cell and a dummy cell; a main word line connected to the memory cell; a dummy word line connected to the dummy cell; Voltage supply circuit: In response to a program command from a controller, a program operation is performed on the memory block according to a pipeline scheme, and When the programming operation fails, applying a programming voltage to the dummy word line so that the dummy cell has an indication threshold voltage higher than a normal pass voltage, and determining the storage block as a defective block; as well as control logic, providing a programming failure signal to the controller when the programming operation fails, Wherein, after the storage block is determined to be a defective block, the controller provides a program command for the defective block to the memory device without stopping the operation of the pipeline scheme, and the memory device applies a programming voltage and interrupts the programming operation according to the result of applying the single programming voltage.

7. The memory device according to claim 6, The voltage supply circuit performs the programming operation by: Precharging the selected bit line to a program enable voltage and precharging the unselected bit lines to a program inhibit voltage, Apply a pass voltage to the unselected word lines. increasing the threshold voltage of the selected memory cell by applying the programming voltage to the selected word line, and performing a verify operation to verify the selected memory cell, Wherein when fail flag data is detected as a result of the verify operation, the control logic provides the program fail signal to the controller. 8 . The memory device of claim 7 , wherein the fail flag data is detected when no current flows through a bit line coupled to the selected memory cell.

9. The memory device of claim 7 , wherein the voltage supply circuit performs the verification operation by: applying a verification voltage to the selected word line, applying the pass voltage to the unselected word lines, and The normal pass voltage is applied to the dummy word line.

10. The memory device according to claim 9, The voltage supply circuit further comprises: In response to a read command from the controller, a normal read operation is performed on the memory block, and When the fail flag data is read as a result of the normal read operation, retrying the read operation by applying a pass voltage higher than the indication threshold voltage to the dummy word line, A read / write circuit is further included to provide the controller with data acquired as a result of the retry.

11. A method for operating a memory device, the method comprising: In response to a program command, performing a program operation on the memory block according to a pipeline scheme; In response to a program command for a program failure cell array, applying a program voltage to a dummy word line connected to a dummy cell in the program failure cell array so that the dummy cell has an indication threshold voltage higher than a normal pass voltage, and determining the storage block as a defective block; and In response to a subsequent program command for the program failure cell array, when fail flag data is sensed from the program failure cell array, providing a program fail signal, Wherein, after the storage block is determined to be a defective block, the controller provides a program command for the defective block to the memory device without stopping the operation of the pipeline scheme, and the memory device applies a programming voltage and interrupts the programming operation according to the result of applying the single programming voltage.

12. The operating method according to claim 11, further comprising: In response to a subsequent read command for the program fail cell array, when the fail flag data is sensed from the program fail cell array, data is read from the program fail cell array by increasing a pass voltage applied to the dummy word line.

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