Display device

Abstract

A display device is provided, including: a substrate including a display region and a non-display region located outside the display region, the display region including a plurality of pixel regions; a pixel circuit layer including a plurality of circuit elements located in the display region; a display element layer including a plurality of light emitting elements in the display region on the pixel circuit layer; and a first alignment line and a second alignment line located on the substrate and each including a main line and a sub-line, the main line being located at the same layer as at least one electrode in the display element layer, the sub-line being electrically connected to the main line and located at the same layer as at least one electrode in the pixel circuit layer, wherein the first alignment line and the second alignment line do not include the main line in the non-display region, and include the sub-line spaced apart from one edge of the substrate.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2019-0173286, filed on December 23, 2019, with the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of this disclosure relate to a display device and a method of manufacturing a display device. Background Technology

[0004] In recent years, techniques have been developed for fabricating micro-light-emitting elements using materials with highly reliable inorganic crystal structures and for fabricating light-emitting devices using these micro-light-emitting elements. For example, techniques have been developed for configuring light sources for light-emitting devices using micro-light-emitting elements with dimensions ranging from nanometers to micrometers. Such light-emitting devices can be used in various electronic devices, such as display devices or lighting devices.

[0005] The light-emitting elements can be fabricated by dispersing them in a predetermined solution and provided to the light-emitting area of ​​the pixel by inkjet printing, slot coating, or the like. When a predetermined voltage is applied to the first and second alignment lines of the pixel, an electric field is formed between the first and second alignment lines, and the light-emitting elements self-align between the first and second alignment lines. Summary of the Invention

[0006] Each of the first alignment line and the second alignment line may have a multi-layer structure, the multi-layer structure including a main line and a sub-line, the main line being located in the same layer as at least one electrode in a display element layer including a plurality of light-emitting elements, and the sub-line being located in the same layer as at least one electrode in a pixel circuit layer.

[0007] In this scenario, during the process of cutting the cell region from the mother substrate, the cross-section of the sub-line can be exposed along the cutting line. The sub-line can serve as a path for static electricity inflow into the cell region.

[0008] One aspect of some embodiments of this disclosure provides a display device capable of reducing or preventing electrostatic inflow caused by alignment lines. Another aspect of some embodiments of this disclosure provides a method for manufacturing a display device capable of reducing or preventing electrostatic inflow caused by alignment lines.

[0009] A display device according to some embodiments of the present disclosure includes a substrate including a display area and a non-display area located outside the display area, the display area including a plurality of pixel areas; a pixel circuit layer including a plurality of circuit elements located in the display area; a display element layer including a plurality of light emitting elements located in the display area on the pixel circuit layer; and a first alignment line and a second alignment line located on the substrate and each including a main line and a sub line, the main line being located at the same layer as at least one electrode in the display element layer, the sub line being electrically connected to the main line and located at the same layer as at least one electrode in the pixel circuit layer, wherein the first alignment line and the second alignment line do not include the main line in the non-display area and include the sub line spaced apart from one edge of the substrate.

[0010] The display element layer can include a first electrode and a second electrode located in each pixel area on the pixel circuit layer, a first insulating layer located on one area of the first electrode and the second electrode, and a light emitting element located between the first electrode and the second electrode of each pixel area.

[0011] The first electrode and the second electrode can be spaced apart from each other at the same layer in each pixel area, wherein a first end portion of the light emitting element is electrically connected to the first electrode of the corresponding pixel, and wherein a second end portion of the light emitting element is electrically connected to the second electrode of the corresponding pixel.

[0012] The display device can further include a second insulating layer partially located on only one area of the light emitting element without covering the first end portion and the second end portion of the light emitting element.

[0013] The display device can further include a first contact electrode connecting the first end portion and the first electrode of the corresponding pixel to each other and a second contact electrode connecting the second end portion and the second electrode of the corresponding pixel to each other, wherein a third insulating layer is interposed between the first contact electrode and the second contact electrode.

[0014] An upper surface of the sub line and one end portion can be covered by the third insulating layer.

[0015] The display device can further include an encapsulation film located on the third insulating layer.

[0016] The main line of each of the first alignment line and the second alignment line can be located at the same layer as at least one of the first electrode and the second electrode.

[0017] Each of the light emitting elements can include a first conductive semiconductor layer doped with a first conductive dopant, a second conductive semiconductor layer doped with a second conductive dopant, and an active layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer.

[0018] Each of the light emitting elements can include a rod-shaped light emitting diode having a micro- or nano-scale size.

[0019] A method of manufacturing a display device according to some embodiments of the disclosure includes: preparing a mother substrate including a plurality of display panels each including a display area and a non-display area; forming a sub-line of each of first and second alignment lines when forming a pixel circuit layer on each of the display panels; and forming a main line of each of the first and second alignment lines when forming a first electrode and a second electrode on each pixel area of the display area of each of the display panels; providing a plurality of light emitting elements on each pixel area and applying a power source to the first and second alignment lines to align the light emitting elements; forming a first contact electrode and a second contact electrode and an insulating layer interposed between the first and second contact electrodes, wherein the first and second contact electrodes connect a first end portion and a second end portion of each of the light emitting elements to the first and second electrodes, respectively; and separating the mother substrate into each of the display panels along a cutting line, wherein the forming of the sub-line includes forming a groove area in the sub-line in an area in which the sub-line overlaps the cutting line in a thickness direction.

[0020] One end portion of the sub-line can be exposed by the groove area, and an upper surface of the sub-line and the one end portion are covered by the insulating layer.

[0021] The forming of the sub-line can include forming at least one sub-line at a same layer as at least one electrode when forming the at least one electrode in the pixel circuit layer.

[0022] The forming of the main line can include forming the main line of each of the first and second alignment lines on the sub-line of each of the first and second alignment lines to be electrically connected to each sub-line.

[0023] The forming of the main line can include forming an extension portion extending in a width direction in the main line in an area overlapping the groove area in a thickness direction.

[0024] The forming of the insulating layer can further include forming an encapsulation film on the insulating layer.

[0025] The aligning of the light emitting elements can include removing the main line on the non-display area after completing the aligning of the light emitting elements.

[0026] The main line and the sub-line can be electrically connected to each other through at least one contact hole.

[0027] Each of the light emitting elements can include a first conductive semiconductor layer doped with a first conductive dopant, a second conductive semiconductor layer doped with a second conductive dopant, and an active layer disposed between the first and second conductive semiconductor layers.

[0028] Each of the light-emitting elements may include a rod-shaped light-emitting diode with a micrometer- or nanometer-sized dimension.

[0029] The display device and method of manufacturing the display device according to some embodiments of the present disclosure can reduce or prevent static electricity flowing into the unit due to the alignment lines during the display panel manufacturing process by forming alignment lines using only the main line in the area near the cutting line. Attached Figure Description

[0030] The above and other aspects of this disclosure will become more apparent from the accompanying drawings, which describe embodiments of the present disclosure in more detail, in which:

[0031] FIG. 1A and FIG. 1B These are perspective and cross-sectional views illustrating light-emitting elements according to some embodiments of the present disclosure;

[0032] FIG. 2A and FIG. 2B These are perspective and cross-sectional views illustrating light-emitting elements according to some embodiments of the present disclosure;

[0033] FIG. 3A and FIG. 3B These are perspective and cross-sectional views illustrating light-emitting elements according to some embodiments of the present disclosure;

[0034] FIG. 4 This is a plan view illustrating a display device according to some embodiments of the present disclosure;

[0035] FIG. 5A to FIG. 5C It is shown that it includes FIG. 4 A circuit diagram of an example of a sub-pixel in a display device;

[0036] FIG. 6 This is a floor plan view showing an example of a display device, which is enlarged. FIG. 4 The first area, A1;

[0037] FIG. 7 This is a plan view showing an example of a sub-pixel, magnified in size. FIG. 6 The second region A2;

[0038] FIG. 8A It shows along FIG. 6 An example diagram of the subpixels intercepted by line I-I';

[0039] FIG. 8B It shows along FIG. 7 A cross-sectional view of an example of the subpixels intercepted by line II-II';

[0040] FIG. 9This is a flowchart illustrating a method of manufacturing a display device according to some embodiments of the present disclosure;

[0041] FIG. 10 It is a diagram used to describe the alignment lines formed on the mother substrate;

[0042] FIG. 11 This is a plan view showing an example of a sub-pixel, magnified in size. FIG. 10 The third region B; and

[0043] FIG. 12 to FIG. 16 It is along FIG. 11 The sectional view taken from line III-III' is used to describe the manufacturing process. FIG. 9 A view of the method of displaying the device. Detailed Implementation

[0044] The features of the inventive concept and the methods for implementing it can be more readily understood by referring to the accompanying drawings and the detailed description of the embodiments. Hereinafter, embodiments will be described in more detail with reference to the accompanying drawings. However, the described embodiments may be implemented in various different forms and should not be construed as limited to the embodiments shown herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey aspects and features of the inventive concept to those skilled in the art. Therefore, processes, elements, and techniques not essential for a full understanding of aspects and features of the inventive concept by those skilled in the art are not described.

[0045] Unless otherwise stated, the same reference numerals always denote the same elements in the drawings and written description, and therefore, their descriptions will not be repeated. Additionally, portions unrelated to the description of the embodiments may be omitted to make the description clearer. In the drawings, the relative dimensions of elements, layers, and regions may be exaggerated for clarity.

[0046] In this document, various embodiments are described with reference to cross-sectional views that serve as schematic diagrams of implementations and / or intermediate structures. Therefore, variations in the shapes shown in the illustrations due to, for example, manufacturing techniques and / or tolerances, are to be expected. Furthermore, the specific structural or functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments according to the concepts of this disclosure. Therefore, the embodiments disclosed herein should not be construed as limited to the shapes specifically shown in the regions, but will include deviations in shape due to, for example, manufacturing processes.

[0047] For example, an implantation region shown as rectangular will typically have rounded or curved features at its edges and / or a gradient of implantation concentration, rather than a binary change from an implantation region to a non-implantation region. Similarly, a buried region formed by implantation can result in some implantation in the area between the buried region and the surface through which the implantation occurs. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to represent the actual shape of the areas of the device and are not intended to be limiting. Furthermore, as those skilled in the art will recognize, the described embodiments can be modified in various different ways without departing entirely from the spirit and scope of this disclosure.

[0048] In the detailed description, numerous specific details are set forth for illustrative purposes to provide a thorough understanding of the various embodiments. However, it will be apparent that various embodiments can be practiced without these specific details or using one or more equivalent configurations. In other instances, well-known structures and apparatuses are shown in block diagram form to avoid unnecessarily obscuring the various embodiments.

[0049] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Therefore, without departing from the spirit and scope of this disclosure, the first element, first component, first region, first layer, or first section described below may be designated as a second element, second component, second region, second layer, or second section.

[0050] For ease of explanation, spatial relative terms such as “below,” “under,” “below,” “below,” “above,” and “above” are used herein to describe the relationship between one element or feature and another element(s) as shown in the figures. It will be understood that, in addition to the orientation depicted in the figures, the spatial relative terms are intended to include different orientations of the device in use or operation. For example, if the device in the figures is flipped, the element described as “below,” “below,” or “below” other elements or features will then be positioned “above” that other element or feature. Thus, the exemplary terms “below” and “below” can encompass both above and below orientations. The device may be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein should be interpreted accordingly. Similarly, when a first part is described as being arranged “above” a second part, this means that the first part is arranged above or below the second part, rather than being limited to its upper side based on the direction of gravity.

[0051] Additionally, in this specification, the phrase "in a plane" or "plan view" means the target portion viewed from above, and the phrase "in a cross section" means the cross section formed by vertically cutting the target portion viewed from the side.

[0052] It will be understood that when an element, layer, region, or component is referred to as being "on," "connected to," or "linked to" another element, layer, region, or component, it may be directly "on," directly "connected to," or directly "linked to" that other element, layer, region, or component, or there may be one or more intervening elements, layers, regions, or components. However, "direct connection / direct link" means that one component is directly connected to or linked to another component without any intermediate components. Similarly, other expressions describing relationships between components, such as "between," "closely between," or "proximately" and "directly proximate," can be interpreted similarly. Furthermore, it will be understood that when an element or layer is referred to as being "between" two elements or layers, the element or layer may be the only element or layer between the two elements or layers, or there may be one or more intervening elements or layers.

[0053] For the purposes of this disclosure, when a statement such as “at least one of…” follows an element of a list, it modifies the entire list rather than individual elements of the list. For example, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as, for example, XYZ, XYY, YZ, and ZZ. Throughout the text, the same references denote the same elements. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0054] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “an” are intended to include the plural forms as well. It will also be understood that when the terms “comprises,” “comprising,” “have,” “having,” “includes,” and “including” are used in this specification, they specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0055] As used herein, the terms “substantially,” “about,” “approximately,” and similar terms are used as terms of approximation rather than terms of degree, and are intended to take into account the inherent biases of measured or calculated values ​​that would be recognized by one of ordinary skill in the art. As used herein, “about” or “approximately” includes the stated value and the average of the specific value within an acceptable range of deviations determined by one of ordinary skill in the art, taking into account measurement issues and errors associated with the measurement of a specific quantity (i.e., limitations of the measurement system). For example, “about” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. Additionally, when “may” is used to describe embodiments of this disclosure, it means “one or more embodiments of this disclosure.”

[0056] When a particular implementation can be carried out differently, the specific process sequence can be performed in a different order than that described. For example, two consecutively described processes can be performed substantially simultaneously, or in the reverse order of their description.

[0057] The electronic or electrical devices and / or any other related devices or components described herein according to embodiments of this disclosure can be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuits), software, or a combination of software, firmware, and hardware. For example, various components of these devices may be formed on a single integrated circuit (IC) chip or on separate IC chips. Alternatively, various components of these devices may be implemented on flexible printed circuit films, tape-on packages (TCPs), printed circuit boards (PCBs), or formed on a substrate.

[0058] Furthermore, the various components of these devices can be processes or threads that run on one or more processors in one or more computing devices, execute computer program instructions, and interact with other system components for performing the various functions described herein. The computer program instructions are stored in memory, which may be implemented in the computing device using standard storage devices such as, for example, random access memory (RAM). The computer program instructions may also be stored in other non-transitory computer-readable media, such as, for example, CD-ROMs, flash drives, etc. Moreover, those skilled in the art will recognize that, without departing from the spirit and scope of embodiments of this disclosure, the functions of various computing devices may be combined or integrated into a single computing device, or the functions of a particular computing device may be distributed across one or more other computing devices.

[0059] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept pertains. It will also be understood that, unless expressly defined herein, terms such as those defined in common dictionaries shall be interpreted as having the same meaning as in the context of this specification and / or the relevant field, and shall not be interpreted in an idealized or overly formal sense.

[0060] FIG. 1A and FIG. 1B These are perspective and cross-sectional views illustrating light-emitting elements according to some embodiments of the present disclosure. FIG. 1A and FIG. 1B The image shows a rod-shaped light-emitting element (LD) with a cylindrical shape, but the type and / or shape of the light-emitting element (LD) is not limited to this.

[0061] refer to FIG. 1A and FIG. 1B The light-emitting element (LD) may include a first conductive semiconductor layer 11, a second conductive semiconductor layer 13, and an active layer 12 interposed between the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13. For example, the light-emitting element (LD) may be a stacked configuration in which the first conductive semiconductor layer 11, the active layer 12, and the second conductive semiconductor layer 13 are sequentially stacked in one direction.

[0062] The light-emitting element (LD) can be arranged in a strip shape extending in one direction. The light-emitting element (LD) can have one end portion and another end portion along one direction. One of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 can be located at one end portion of the light-emitting element (LD), and the other of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 can be located at the other end portion of the light-emitting element (LD).

[0063] The light-emitting element (LD) can be a rod-shaped light-emitting diode. Here, rod shape includes a shape similar to a rod or a strip similar to a bar, such as a cylinder or a polygonal cylinder, that is longer in the longitudinal direction than in the width direction (i.e., has an aspect ratio greater than 1). The shape of the cross-section of the light-emitting element (LD) is not particularly limited. For example, the length L of the light-emitting element (LD) can be greater than its diameter D (or the width of the cross-section).

[0064] Light-emitting elements (LDs) can have diameters D and / or lengths L ranging from nanometers to micrometers (e.g., the range of nanometers or micrometers). However, the size of a light-emitting element (LD) is not limited to these dimensions. For example, the size of a light-emitting element (LD) can vary depending on the design conditions of various devices (e.g., display devices) that use light-emitting devices employing LDs as light sources.

[0065] The first conductive semiconductor layer 11 may include at least one n-type semiconductor layer. For example, the first conductive semiconductor layer 11 may include a semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include an n-type semiconductor layer doped with a first conductive dopant such as Si, Ge, or Sn. However, the materials used to configure the first conductive semiconductor layer 11 are not limited to these, and various materials other than those described above may be used to configure the first conductive semiconductor layer 11.

[0066] The active layer 12 may be located on the first conductive semiconductor layer 11 and may be formed in a single quantum well structure or a multiple quantum well structure. In other embodiments, a capping layer doped with a conductive dopant may be formed on and / or below the active layer 12. For example, the capping layer may be formed of an AlGaN layer or an InAlGaN layer. Materials such as AlGaN or AlInGaN can be used to form the active layer 12, and various materials other than those described above may also be used to configure the active layer 12.

[0067] When a voltage equal to or greater than the threshold voltage is applied across the light-emitting element (LD), the LD emits light, and electron-hole pairs couple in the active layer 12. By controlling the light emission of the LD using this principle, the LD can be used as a light source for various light-emitting devices, including pixels in a display device.

[0068] The second conductive semiconductor layer 13 may be located on the active layer 12 and may include a semiconductor layer of a different type than the first conductive semiconductor layer 11. For example, the second conductive semiconductor layer 13 may include at least one p-type semiconductor layer. For example, the second conductive semiconductor layer 13 may include at least one semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include a p-type semiconductor layer doped with a second conductive dopant such as Mg. However, the materials used to configure the second conductive semiconductor layer 13 are not limited to these, and various materials other than those described above may also be used to configure the second conductive semiconductor layer 13.

[0069] The light-emitting element (LD) may also include an insulating film INF disposed on its surface. The insulating film INF may be formed on the surface of the LD to at least surround the outer circumferential surface of the active layer 12, and may also surround a region of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13. However, the insulating film INF may expose two end portions of the LD that may have different polarities. For example, the insulating film INF may expose both end portions of the LD without covering the corresponding ends of each of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 located at both ends of the LD in the longitudinal direction, for example, the two planes (i.e., the upper surface and the lower surface) of a cylinder.

[0070] The insulating film INF may include, but is not limited to, at least one insulating material selected from silicon dioxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), and titanium dioxide (TiO2). That is, the materials used in the insulating film INF are not particularly limited, and the insulating film INF can be configured from various insulating materials.

[0071] In some embodiments, in addition to the first conductive semiconductor layer 11, the active layer 12, the second conductive semiconductor layer 13, and / or the insulating film INF, the light-emitting element LD may also include other components. For example, the light-emitting element LD may also include at least one phosphor layer, active layer, semiconductor layer, and / or electrode layer located at one end of the first conductive semiconductor layer 11, the active layer 12, and / or the second conductive semiconductor layer 13.

[0072] FIG. 2A and FIG. 2B These are perspective and cross-sectional views showing light-emitting elements according to other embodiments of the present disclosure. FIG. 3A and FIG. 3B These are perspective and cross-sectional views showing light-emitting elements according to other embodiments of the present disclosure.

[0073] refer to FIG. 2A and FIG. 2B The light-emitting element (LD) may further include at least one electrode layer 14 located at one end of the second conductive semiconductor layer 13. (See reference) FIG. 3A and FIG. 3B The light-emitting element LD may also include at least one other electrode layer 15 located at one end of the first conductive semiconductor layer 11.

[0074] Each of electrode layers 14 and 15 may be an ohmic contact electrode, but is not limited thereto. Additionally, each of electrode layers 14 and 15 may comprise a metal or a conductive metal oxide. For example, each of electrode layers 14 and 15 may be formed individually or in combination of chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), their oxides or alloys, transparent electrode materials (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO)). Electrode layers 14 and 15 may be substantially transparent or translucent. Therefore, light generated in the light-emitting element LD can pass through electrode layers 14 and 15 and can be emitted to the outside of the light-emitting element LD.

[0075] According to some embodiments, the insulating film INF may at least partially surround the outer circumferential surfaces of electrode layers 14 and 15, or may not at least partially surround the outer circumferential surfaces of electrode layers 14 and 15. That is, the insulating film INF may be selectively formed on the surfaces of electrode layers 14 and 15. Additionally, the insulating film INF may be formed to expose two end portions of the light-emitting element LD with different polarities. For example, the insulating film INF may expose at least one region of electrode layers 14 and 15. However, this disclosure is not limited thereto, and the insulating film INF may be omitted.

[0076] Because the insulating film INF is disposed on the surface of the light-emitting element LD, for example, on the surface of the active layer 12, short circuits between the active layer 12 and at least one electrode can be reduced or prevented (e.g., short circuits can be prevented with at least one of the contact electrodes connected to the respective end portions of the light-emitting element LD). Therefore, the electrical stability of the light-emitting element LD can be guaranteed.

[0077] Furthermore, because the insulating film INF is formed on the surface of the light-emitting element (LD), surface defects of the LD can be reduced or minimized, and the lifespan and efficiency of the LD can be improved. Additionally, because the insulating film INF is formed on the LD, even if multiple LDs are positioned close together, undesirable short circuits between the LDs can be reduced or prevented.

[0078] In some implementations, the light-emitting element (LD) can be manufactured using a surface treatment process (e.g., a coating process). For example, when multiple LDs are mixed in a fluid solution (or solvent) and then provided to each emitting area (e.g., the emitting area of ​​each pixel), the LDs can be uniformly dispersed in the solution rather than uniformly aggregated. Here, the emitting area can be the area where the LD emits light and can be distinguished from the non-emitting areas.

[0079] The insulating film INF itself can be formed into a hydrophobic film using a hydrophobic material. Alternatively, a hydrophobic film made of a hydrophobic material can be additionally formed on the insulating film INF. The hydrophobic material can be a fluorinated material to exhibit hydrophobicity. Alternatively, the hydrophobic material can be applied to the light-emitting element LD in the form of a self-assembled monolayer (SAM). In this case, the hydrophobic material may include octadecyltrichlorosilane, fluoroalkyltrichlorosilane, perfluoroalkyltriethoxysilane, etc. Alternatively, the hydrophobic material can be a commercially available fluorinated material, such as Teflon. TM Or Cytop TM , or the corresponding materials.

[0080] Light-emitting devices including light-emitting elements (LDs) can be used in various types of devices (including display devices) that require a light source. For example, at least one micro-light-emitting element (LD) (e.g., multiple micro-light-emitting elements (LDs) each having a size ranging from nanometers to micrometers) can be located in each pixel area of ​​a display panel, and the light source (or light source unit) of each pixel can be configured using micro-light-emitting elements (LDs). However, the application of light-emitting elements (LDs) is not limited to the display devices disclosed herein. For example, light-emitting elements (LDs) can be used in other types of devices that require a light source (such as lighting devices).

[0081] FIG. 4 This is a plan view showing a display device according to some embodiments of the present disclosure. FIG. 4 This is shown as a reference that can be used. FIG. 1A to FIG. 3B The described example of a display device that uses a light-emitting element (LD) as a light source includes a display panel (PNL). The structure of the display panel (PNL) is briefly shown based on the display area (DA). However, according to some embodiments, at least one driving circuit unit (e.g., at least one of a scan driver and a data driver) and / or multiple lines may also be positioned on the display panel (PNL).

[0082] refer to FIG. 4 The display panel PNL may include a base layer SUB1 (or substrate), power lines PL1 and PL2, and pixels PXL located on the base layer SUB1. The display panel PNL and the base layer SUB1 may include a display area DA in which an image is displayed and a non-display area NDA separated from the display area DA.

[0083] The display area DA can be located in the central area of ​​the display panel PNL, and the non-display area NDA can be positioned along the edge of the display panel PNL to completely or partially surround the display area DA. However, the positions of the display area DA and the non-display area NDA are not limited to this, and the positions of the display area DA and the non-display area NDA can be changed.

[0084] The base layer SUB1 can be configured with the base components of the display panel PNL. For example, the base layer SUB1 can be configured with the base components of the lower panel (e.g., the lower plate of the display panel PNL).

[0085] The base layer SUB1 can be a rigid substrate or a flexible substrate, and the material or physical properties of the base layer SUB1 are not particularly limited. For example, the base layer SUB1 can be a rigid substrate made of glass or tempered glass, or a flexible substrate made of a thin film of plastic or metal material. Furthermore, the base layer SUB1 can be a transparent substrate, but is not limited to this. For example, the base layer SUB1 can be a translucent substrate, an opaque substrate, or a reflective substrate.

[0086] One area on the base layer SUB1 may be defined as a display area DA in which pixel PXL is located, and the remaining areas on the base layer SUB1 may be defined as non-display areas NDA. For example, the base layer SUB1 may include a display area DA and a non-display area NDA located outside the display area DA, wherein the display area DA includes a plurality of pixel areas in which pixel PXL is formed. In the non-display area NDA, a first alignment line AL1, a second alignment line AL2, various lines connected to pixel PXL in the display area DA, and / or internal circuit units may be located.

[0087] Each of the first alignment line AL1 and the second alignment line AL2 can be formed as a multi-layer structure. Each of the first alignment line AL1 and the second alignment line AL2 can have a multi-layer structure including sub-lines SUL1 and SUL2 and a main line located in the same layer as at least one of the first pixel electrode and the second pixel electrode (hereinafter also referred to as the first electrode and the second electrode), which will be described later. For example, as... FIG. 4 As shown, in the non-display area NDA, the first alignment line AL1 and the second alignment line AL2 can be configured solely by sublines SUL1 and SUL2. This will refer to... FIG. 6 to FIG. 8B Detailed description.

[0088] The first power line PL1 may extend across the display area DA in the second direction DR2 and may be repeatedly arranged along the first direction DR1. The first power line PL1 may be a common line connected to all pixels PXL, and a first power supply VDD (or a first power supply voltage) may be applied to the first power line PL1.

[0089] Similarly, a second power line PL2 may extend across the display area DA in the second direction DR2 and may be repeatedly arranged along the first direction DR1. The second power line PL2 may be a common line, and a second power supply VSS (or a second power supply voltage) may be applied to the second power line PL2. Here, the first power supply VDD and the second power supply VSS may have different voltage levels. For example, the first power supply VDD may have a higher voltage level than the second power supply VSS.

[0090] Pixel PXL may include at least one light-emitting element (LD) electrically connected between a first power line PL1 and a second power line PL2 and driven by corresponding scan signals and data signals. For example, pixel PXL may include according to FIG. 1A to FIG. 3B At least one rod-shaped light-emitting diode in any of the embodiments. For example, the pixel PXL may include a plurality of rod-shaped light-emitting diodes having dimensions from nanometer to micrometer scale and connected in parallel with each other between a first power line PL1 and a second power line PL2. The rod-shaped light-emitting diodes may be configured as the light source of the pixel PXL.

[0091] Furthermore, pixel PXL may include multiple sub-pixels SPX1, SPX2, and SPX3. For example, pixel PXL may include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3.

[0092] The first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 can emit different colors of light. For example, the first sub-pixel SPX1 can be a red sub-pixel for emitting red light, the second sub-pixel SPX2 can be a green sub-pixel for emitting green light, and the third sub-pixel SPX3 can be a blue sub-pixel for emitting blue light. However, the color, type, number, etc., of the sub-pixels of the configuration pixel PXL are not particularly limited. For example, the color of the light emitted from each of the sub-pixels can be changed differently. FIG. 4 The illustration shows pixels PXL arranged in a strip shape within the display area DA, but this disclosure is not limited thereto. For example, pixels PXL can be positioned in various pixel array configurations.

[0093] In some embodiments, pixel PXL (or each of the sub-pixels) may be configured as an active pixel. However, the type, structure, and / or driving method of pixel PXL in a display device suitable for embodiments of this disclosure are not particularly limited. For example, pixel PXL may be configured as a pixel of a display device having various passive or active structures.

[0094] FIG. 5A to FIG. 5C It is shown FIG. 4 A circuit diagram of an example of a subpixel of a display device. FIG. 5A to FIG. 5C The sub-pixel SPX shown in the image can be FIG. 4 The first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 are disposed in the display panel PNL, and the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may have substantially the same or similar structures. Therefore, in reference FIG. 5A to FIG. 5C In the description, the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 are collectively referred to as sub-pixels SPX.

[0095] First, refer to FIG. 5A The sub-pixel SPX includes a light source unit LSU that emits light at a brightness corresponding to the data signal. Additionally, the sub-pixel SPX may optionally further include a pixel circuit PXC for driving the light source unit LSU.

[0096] According to some embodiments, the light source unit (LSU) may include a plurality of light-emitting elements (LDs) electrically connected between a first power supply (VDD) and a second power supply (VSS). In some embodiments, the light-emitting elements (LDs) may be connected in parallel with each other, but the disclosed embodiments are not limited thereto. For example, the plurality of light-emitting elements (LDs) may be connected between the first power supply (VDD) and the second power supply (VSS) in a hybrid series / parallel configuration.

[0097] The first power supply VDD and the second power supply VSS can have different potentials, allowing the light-emitting element LD to emit light. For example, the first power supply VDD can be set to a high potential, and the second power supply VSS can be set to a low potential. Here, during the light-emitting period of the sub-pixel SPX, the potential difference between the first power supply VDD and the second power supply VSS can be set to be equal to or greater than the threshold voltage of the light-emitting element LD.

[0098] At the same time, despite FIG. 5A The illustration shows light-emitting elements (LDs) connected in parallel with each other in the same direction (e.g., forward direction) between a first power supply VDD and a second power supply VSS; however, embodiments of this disclosure are not limited to this. For example, some of the LDs may be connected in a first direction (e.g., forward direction) between the first power supply VDD and the second power supply VSS to form a corresponding effective light source, and one or more other LDs may be connected in a second direction (e.g., reverse direction). As another example, at least one sub-pixel SPX may consist of only a single LD (e.g., a single effective light source connected in the forward direction between the first power supply VDD and the second power supply VSS).

[0099] Each of the light-emitting elements (LDs) has one end portion connected to the corresponding pixel circuit PXC via a first electrode (i.e., the first pixel electrode), and is connected to the first power supply VDD (reference) via the pixel circuit PXC and the first power supply line PL1. FIG. 4 The other end portion of each of the light-emitting elements (LDs) can be connected to the second power supply VSS (reference) via the second electrode (i.e., the second pixel electrode) and the second power supply line PL2. FIG. 4 ).

[0100] The light source unit (LSU) can emit light with a brightness corresponding to the drive current provided through the corresponding pixel circuit (PXC). Therefore, an image (e.g., a predetermined image) can be displayed in the display area (DA).

[0101] The pixel circuit PXC can be connected to the scan lines and data lines of the corresponding sub-pixel SPX. For example, in FIG. 5A and FIG. 5BIn the example, when sub-pixel SPX is located in the i-th row and j-th column of display area DA, the pixel circuit PXC of sub-pixel SPX can be connected to the i-th scan line Si and the j-th data line Dj of display area DA. The pixel circuit PXC may include a first transistor T1, a second transistor T2, and a storage capacitor Cst.

[0102] The first transistor T1 (or driving transistor) can be connected between the first power supply VDD and the light source unit LSU. The gate electrode of the first transistor T1 can be connected to the first node N1. The first transistor T1 can control the driving current supplied to the light source unit LSU according to the voltage of the first node N1.

[0103] The second transistor T2 (or switching transistor) may be connected between the data line (e.g., the j-th data line Dj) and the first node N1. The gate electrode of the second transistor T2 may be connected to the scan line (e.g., the i-th scan line Si).

[0104] The second transistor T2 can be turned on in response to a scan signal with a gate turn-on voltage (e.g., a low voltage) from a scan line (e.g., the i-th scan line Si) to electrically connect the data line (e.g., the j-th data line Dj) and the first node N1 to each other.

[0105] For each frame period, the data signal for the corresponding frame can be provided to the data line (e.g., the j-th data line Dj), and the data signal can be transmitted to the first node N1 via the second transistor T2. Therefore, the voltage corresponding to the data signal can be charged into the storage capacitor Cst.

[0106] One electrode of the storage capacitor Cst can be connected to a first power supply VDD, and the other electrode can be connected to a first node N1. The storage capacitor Cst can be charged with a voltage corresponding to the data signal supplied to the first node N1 during each frame period, and can maintain the charged voltage until the data signal of the next frame is provided.

[0107] At the same time, FIG. 5A In the diagram, the transistors (e.g., first transistor T1 and second transistor T2) of the pixel circuit PXC are shown as P-type transistors, but embodiments of this disclosure are not limited thereto. For example, at least one of the first transistor T1 and the second transistor T2 may be changed to an N-type transistor.

[0108] For example, such as FIG. 5B As shown, both the first transistor T1 and the second transistor T2 can be N-type transistors. In this case, during each frame period, the gate turn-on voltage of the scan signal used to write the data signal provided to the data line (e.g., the j-th data line Dj) into the sub-pixel SPX can be a high-level voltage. Similarly, the voltage of the data signal used to turn on the first transistor T1 can be a waveform that is similar to the voltage used to turn on the first transistor T1.FIG. 5A The waveform of the voltage at which the first transistor T1 is turned on is the opposite of the voltage waveform shown. For example, in FIG. 5B In this context, as the grayscale value to be expressed increases, the data signal can be increased to have a higher voltage level.

[0109] Besides varying the connection positions of some circuit elements and the voltage levels of control signals (e.g., scan signals and data signals) depending on the transistor type, FIG. 5B The configuration and operation of the sub-pixel SPX shown are similar to FIG. 5A The configuration and operation of the sub-pixel SPX are basically similar. Therefore, details regarding... FIG. 5B Detailed description of the subpixel SPX.

[0110] Meanwhile, the structure of the pixel circuit PXC is not limited to FIG. 5A and FIG. 5B The structure shown is illustrated. That is, the pixel circuit PXC can be configured as a pixel circuit with various structures and / or driving methods. For example, the pixel circuit PXC can be as follows: FIG. 5C As shown in the diagram.

[0111] refer to FIG. 5C In addition to the corresponding scan line (e.g., the i-th scan line Si), the pixel circuit PXC may also be connected to at least one other scan line (or control line). For example, the pixel circuit PXC of the sub-pixel SPX located in the i-th row of the display area DA may also be connected to the (i-1)-th scan line Si-1 and / or the (i+1)-th scan line Si+1. Furthermore, in addition to the first power supply VDD and the second power supply VSS, the pixel circuit PXC may also be connected to another power supply. For example, the pixel circuit PXC may also be connected to the initialization power supply Vint. The pixel circuit PXC may include the first transistor T1 to the seventh transistor T7 and the storage capacitor Cst.

[0112] A first transistor T1 can be connected between a first power supply VDD and a light source unit LSU. One electrode of the first transistor T1 (e.g., the source electrode) can be connected to the first power supply VDD via a fifth transistor T5 and a first power line PL1, and the other electrode of the first transistor T1 (e.g., the drain electrode) can be connected to an electrode of the light source unit LSU (e.g., the first electrode of the corresponding sub-pixel SPX) via a sixth transistor T6. The gate electrode of the first transistor T1 can be connected to a first node N1. The first transistor T1 can control the drive current supplied to the light source unit LSU according to the voltage of the first node N1.

[0113] A second transistor T2 may be connected between a data line (e.g., the j-th data line Dj) and an electrode of the first transistor T1. The gate electrode of the second transistor T2 may be connected to a corresponding scan line (e.g., the i-th scan line Si). When a scan signal with a gate-on voltage is provided to the scan line (e.g., the i-th scan line Si), the second transistor T2 may be turned on, thereby electrically connecting the data line (e.g., the j-th data line Dj) to an electrode of the first transistor T1 to provide a voltage level for a control signal. Therefore, when the second transistor T2 is turned on, the data signal provided from the data line (e.g., the j-th data line Dj) may be transmitted to the first transistor T1.

[0114] The third transistor T3 can be connected between the other electrode (e.g., the drain electrode) of the first transistor T1 and the first node N1. The gate electrode of the third transistor T3 can be connected to the corresponding scan line (e.g., the i-th scan line Si). When a scan signal with a gate turn-on voltage is provided from the scan line (e.g., the i-th scan line Si), the third transistor T3 can be turned on, thereby connecting the first transistor T1 in the form of a diode.

[0115] A fourth transistor T4 can be connected between the first node N1 and the initialization power supply Vint. The gate electrode of the fourth transistor T4 can be connected to the previous scan line, for example, the (i-1)th scan line Si-1. When a scan signal with a gate-on voltage is provided to the (i-1)th scan line Si-1, the fourth transistor T4 can be turned on, thereby transmitting the voltage of the initialization power supply Vint to the first node N1. Here, the voltage of the initialization power supply Vint can be equal to or less than the minimum voltage of the data signal.

[0116] The fifth transistor T5 can be connected between the first power supply VDD and the first transistor T1. The gate electrode of the fifth transistor T5 can be connected to a corresponding emitter control line, such as the i-th emitter control line Ei. When an emitter control signal with a gate cutoff voltage (e.g., a high voltage) is provided to the emitter control line (e.g., the i-th emitter control line Ei), the fifth transistor T5 can be turned off, and under other conditions, the fifth transistor T5 can be turned on.

[0117] The sixth transistor T6 can be connected between the first transistor T1 and the first electrode of the light source unit LSU, for example, between the first transistor T1 and the second node N2 connected to the first electrode of the light source unit LSU. The gate electrode of the sixth transistor T6 can be connected to a corresponding emitter control line, for example, the i-th emitter control line Ei. When an emitter control signal with a gate cutoff voltage is provided to the emitter control line (e.g., the i-th emitter control line Ei), the sixth transistor T6 can be turned off, and under other conditions, the sixth transistor T6 can be turned on.

[0118] A seventh transistor T7 can be connected between the first electrode of the light source unit LSU and the initialization power supply Vint, for example, between the second node N2 connected to the first electrode of the light source unit LSU and the initialization power supply Vint. The gate electrode of the seventh transistor T7 can be connected to any of the subsequent scan lines, for example, the (i+1)th scan line Si+1. When a scan signal with a gate-on voltage is provided to the (i+1)th scan line Si+1, the seventh transistor T7 can be turned on to provide the voltage of the initialization power supply Vint to the first electrode of the light source unit LSU. In this case, the voltage of the first electrode of the light source unit LSU can be initialized during each initialization period in which the voltage of the initialization power supply Vint is transmitted to the light source unit LSU.

[0119] The control signal used to control the operation of the seventh transistor T7 can be modified in various ways. For example, the gate electrode of the seventh transistor T7 can be connected to the scan line of the corresponding horizontal line, i.e., the i-th scan line Si. In this case, when the scan signal of the gate turn-on voltage is provided to the i-th scan line Si, the seventh transistor T7 can be turned on to provide the voltage of the initialization power supply Vint to one electrode of the light source unit LSU.

[0120] The storage capacitor Cst can be connected between the first power supply VDD and the first node N1. The storage capacitor Cst can store the data signal provided to the first node N1 and the voltage corresponding to the threshold voltage of the first transistor T1 in each frame period.

[0121] At the same time, FIG. 5C In the diagram, all the transistors in the pixel circuit PXC (e.g., the first transistor T1 to the seventh transistor T7) are shown as P-type transistors, but the disclosed embodiments are not limited thereto. For example, at least one of the first transistor T1 to the seventh transistor T7 may be changed to an N-type transistor.

[0122] Furthermore, the structures applicable to the sub-pixel SPX of this disclosure are not limited to... FIG. 5A to FIG. 5C The embodiments shown herein, and in other embodiments, may have various structures for the sub-pixel SPX. For example, in other embodiments, the pixel circuit PXC in the sub-pixel SPX may be configured as a pixel circuit with various structures and / or driving methods. Furthermore, the sub-pixel SPX may be configured in a passive light-emitting display device, etc. In this case, the pixel circuit PXC may be omitted, and each of the first and second electrodes of the light source unit LSU may be directly connected to scan lines, data lines, power lines, control lines, etc.

[0123] FIG. 6 This is a floor plan view showing an example of a display device, which is enlarged. FIG. 4 The first region, A1. FIG. 6This illustrates a display element layer (LDL) based on (see...) FIG. 8B The structure of pixel PXL and pixel circuit layer PCL, wherein the light-emitting element LD of pixel PXL is located on pixel circuit layer PCL.

[0124] Pixel circuit layer PCL can be formed on the reference FIG. 4 The base layer SUB1 is described and may include a first power line PL1, a second power line PL2, and a reference. FIG. 5A to FIG. 5C The pixel circuit PXC is described. (e.g.) FIG. 6 As shown, the pixel circuit layer PCL may include a second power line PL2.

[0125] According to some embodiments of this disclosure, alignment lines AL1 and AL2 may have a multilayer structure including main lines and sub-lines SUL1 and SUL2. Here, in the alignment operation of the light-emitting element LD, the lines of the first alignment line AL1 and the second alignment line AL2 located in the same layer as the pixel electrodes ELT1 and ELT2 (hereinafter also referred to as electrodes ETL1 and ETL2) may be referred to as main lines.

[0126] The first alignment line AL1 may have a passage through at least one third contact hole CH3 (reference). FIG. 10 The main line and the first sub-line SUL1 are electrically connected to each other, and the second alignment line AL2 may have a fourth contact hole CH4 (see reference). FIG. 10 The main line and the second sub-line SUL2 are electrically connected to each other. Here, the size, shape and / or number of the third contact hole CH3 formed in the first alignment line AL1 and the size, shape and / or number of the fourth contact hole CH4 formed in the second alignment line AL2 are not limited, and various modifications and implementations can be made in other embodiments.

[0127] Each of the main lines may be formed simultaneously with a first pixel electrode ELT1 and / or a second pixel electrode ELT2, so as to be formed in the same layer as the first pixel electrode ELT1 and / or the second pixel electrode ELT2. Hereinafter, the first pixel electrode ELT1 is also referred to as the first electrode ELT1, and the second pixel electrode ELT2 is also referred to as the second electrode ELT2. Furthermore, each of the sub-lines SUL1 and SUL2 may be positioned below the corresponding main line to overlap with it. For example, each of the sub-lines SUL1 and SUL2 may be formed together with (e.g., simultaneously formed with) at least one electrode formed in the pixel circuit layer PCL, so as to be located in the same layer as the at least one electrode.

[0128] As described above, when the first alignment line AL1 and the second alignment line AL2 are formed as a multilayer structure, the resistance of the first alignment line AL1 and the second alignment line AL2 can be effectively reduced. Therefore, in subsequent alignment operations of the light-emitting element LD, the voltage drop generated in each of the first alignment line AL1 and the second alignment line AL2 can be reduced or minimized. Therefore, in the operation of aligning the light-emitting element LD, the required alignment voltage can be transmitted to the first pixel electrode ELT1 and the second pixel electrode ELT2 of each pixel PXL.

[0129] Furthermore, when each of the first alignment line AL1 and the second alignment line AL2 is formed as a multilayer structure to reduce resistance, the required alignment voltage can be uniformly delivered to the layers located as shown in the figure. FIG. 10 Each of the plurality of unit regions CEL1 and CEL2 on the mother substrate 100 shown. Therefore, the light-emitting element LD can be effectively aligned between each of the first pixel electrode ELT1 and the second pixel electrode ELT2, while the alignment process of the light-emitting element LD is also performed for the plurality of unit regions CEL1 and CEL2 on the mother substrate 100. Therefore, the quality and manufacturing efficiency of the light-emitting display device can be improved.

[0130] Refer again FIG. 6 Pixel PXL can be formed in pixel region PXA. Pixel region PXA may include sub-pixel regions SPA1, SPA2, and SPA3 corresponding to the sub-pixels SPX1, SPX2, and SPX3 that configure pixel PXL.

[0131] The pixel region PXA may include a first sub-pixel region SPA1 in which a first sub-pixel SPX1 is formed, a second sub-pixel region SPA2 in which a second sub-pixel SPX2 is formed, and a third sub-pixel region SPA3 in which a third sub-pixel SPX3 is formed. In each of the first sub-pixel region SPA1, the second sub-pixel region SPA2, and the third sub-pixel region SPA3, at least one pair of first electrodes ELT1 and second electrodes ELT2 and at least one light-emitting element LD connected between the first electrodes ELT1 and the second electrodes ELT2 may be positioned.

[0132] The first sub-pixel SPX1 may include a first electrode ELT1 and a second electrode ELT2 spaced apart from each other in the first sub-pixel region SPA1, and at least one first light-emitting element LD1 connected between the first electrode ELT1 and the second electrode ELT2. Similarly, the second sub-pixel SPX2 may include a first electrode ELT1 and a second electrode ELT2 spaced apart from each other in the second sub-pixel region SPA2, and at least one second light-emitting element LD2 connected between the first electrode ELT1 and the second electrode ELT2. The third sub-pixel SPX3 may include a first electrode ELT1 and a second electrode ELT2 spaced apart from each other in the third sub-pixel region SPA3, and at least one third light-emitting element LD3 connected between the first electrode ELT1 and the second electrode ELT2.

[0133] The first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 can emit light of the same color or different colors. For example, each of the first light-emitting elements LD1 can be a red light-emitting diode for emitting red light, each of the second light-emitting elements LD2 can be a green light-emitting diode for emitting green light, and each of the third light-emitting elements LD3 can be a blue light-emitting diode for emitting blue light.

[0134] As another example, all of the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 can be blue light-emitting diodes for emitting blue light. In this case, in order to configure a full-color pixel PXL, a light conversion layer and / or a color filter for converting the color of the light emitted from the respective sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 can be positioned on one or more of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3.

[0135] The first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may have substantially the same or similar structures. For ease of description, any one of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 will be collectively referred to as sub-pixel SPX. Furthermore, at least one of the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 will be collectively referred to as light-emitting element LD, and the structure of the sub-pixel SPX will be described in detail below.

[0136] The first electrode ELT1 and the second electrode ELT2 may be arranged to be spaced apart from each other in each sub-pixel region SPA, and may be positioned such that the first electrode ELT1 and the second electrode ELT2 face each other in at least one region. For example, the first electrode ELT1 and the second electrode ELT2 may be arranged parallel to each other and spaced apart from each other along a first direction DR1 (e.g., spaced apart from each other by a predetermined distance). Each of the first electrode ELT1 and the second electrode ELT2 may extend along a second direction DR2 intersecting the first direction DR1. However, the disclosed embodiments are not limited thereto. For example, the shape of the first electrode ELT1 and the second electrode ELT2, their mutual arrangement, etc., may be varied in other embodiments.

[0137] The first electrode ELT1 can be electrically connected to a first connecting electrode CNL1 (or a first connecting line) extending in the first direction DR1. The first connecting electrode CNL1 can be connected to a reference via a first contact hole CH1. FIG. 5A to FIG. 5C The pixel circuit PXC (or the first transistor T1) is described.

[0138] The second electrode ELT2 can be electrically connected to a second connecting electrode CNL2 (or a second connecting line) extending in the first direction DR1. The second connecting electrode CNL2 can extend to an adjacent sub-pixel SPX or sub-pixel region SPA (e.g., second sub-pixel SPX2 and third sub-pixel SPX3, or second sub-pixel region SPA2 and third sub-pixel region SPA3). The second connecting electrode CNL2 can be electrically connected to the second power line PL2 (or electrically connected to the first sub-power line PL2-1, the second sub-power line PL2-2, and the third sub-power line PL2-3 included in the second power line PL2) through the second contact hole CH2.

[0139] Simultaneously, the first sub-line SUL1 and the second sub-line SUL2 may be located in the non-display area NDA. The first sub-line SUL1 may extend generally along the second direction DR2. The first sub-line SUL1 may also extend along the first direction DR1 toward each of a plurality of sub-pixels SPX positioned adjacent to each other. For example, some regions of the first sub-line SUL1 may be positioned to overlap with a portion of the first connection electrode CNL1 of the first sub-pixel SPX1 on the third direction DR3. The first sub-line SUL1 and the first connection electrode CNL1 may be electrically connected to each other in some regions.

[0140] The first sub-line SUL1 may be bent and extended in a first direction DR1 in a region adjacent to the first sub-pixel SPX1. One end of the bent and extended first sub-line SUL1 may be spaced apart from the cleaving line CL by a distance (e.g., a predetermined distance) d1. The cleaving line CL may be part of the mother substrate 100 (reference). FIG. 10 Divide into cell regions CEL1 and CEL2 (refer to) FIG. 10The cutting lines formed during each process in ).

[0141] The second sub-line SUL2 may extend along the first direction DR1 in a region adjacent to the first sub-pixel SPX1. The second sub-line SUL2 may extend toward the first sub-pixel SPX1 adjacent to the second sub-line SUL2 in the first direction DR1. Some regions of the second sub-line SUL2 may overlap with a portion of the second connecting electrode CNL2 of the first sub-pixel SPX1 in a third direction DR3 (which is substantially perpendicular to both the first direction DR1 and the second direction DR2). The second sub-line SUL2 and the second connecting electrode CNL2 may be electrically connected to each other in some regions.

[0142] One end of the second sub-line SUL2 can be spaced apart from the dicing line CL by a distance (e.g., a predetermined distance) d2. The dicing line CL can be used to cut the mother substrate 100 (reference). FIG. 10 Divide into cell regions CEL1 and CEL2 (refer to) FIG. 10 Each of the processes in ) is formed.

[0143] The main line can be integrally formed on the pixel circuit layer PCL along with the first pixel electrode ELT1, the second pixel electrode ELT2, the first connection electrode CNL1, and the second connection electrode CNL2. However, after the self-alignment of the light-emitting element LD is completed, the main line can be removed in the region excluding the first pixel electrode ELT1, the second pixel electrode ELT2, the first connection electrode CNL1, and the second connection electrode CNL2.

[0144] FIG. 7 This is a plan view showing an example of a sub-pixel, magnified in size. FIG. 6 The second region, A2.

[0145] refer to FIG. 7 The sub-pixel region SPA may include at least one pair of first electrodes ELT1 and second electrodes ELT2, as well as a light-emitting region EMA, in which at least one light-emitting element LD is positioned between the first electrodes ELT1 and the second electrodes ELT2.

[0146] According to some embodiments, the light-emitting region EMA may be defined by a embankment BNK surrounding the light-emitting region EMA. Each of the first electrode ELT1 and the second electrode ELT2 may have a single-layer structure or a multi-layer structure. For example, the first electrode ELT1 may have a multi-layer structure including a first reflective electrode and a first conductive coating, and the second electrode ELT2 may have a multi-layer structure including a second reflective electrode and a second conductive coating.

[0147] The first electrode ELT1 can be connected to the first connecting electrode CNL1. The first electrode ELT1 can be integrally connected to the first connecting electrode CNL1. For example, the first electrode ELT1 can be formed by branching at least one branch from the first connecting electrode CNL1. When the first electrode ELT1 and the first connecting electrode CNL1 are integrally formed, the first connecting electrode CNL1 can be considered as a region of the first electrode ELT1. However, the disclosed embodiments are not limited thereto. For example, in other embodiments of this disclosure, the first electrode ELT1 and the first connecting electrode CNL1 can be formed separately from each other, and in other embodiments, they can be electrically connected to each other through at least one contact hole or through hole.

[0148] The first connecting electrode CNL1 may have a single-layer structure or a multi-layer structure. For example, the first connecting electrode CNL1 may include a first sub-connecting electrode integrally connected to the first reflective electrode and a second sub-connecting electrode integrally connected to the first conductive coating. The first connecting electrode CNL1 may have the same cross-sectional structure (or stacked structure) as the first electrode ELT1, but the disclosed embodiments are not limited thereto.

[0149] The first electrode ELT1 and the first connecting electrode CNL1 can be connected to the pixel circuit PXC of the sub-pixel SPX through the first contact hole CH1, for example FIG. 5A to FIG. 5C The pixel circuit PXC shown in any of the examples.

[0150] The first contact hole CH1 may be located outside the light-emitting region EMA of the sub-pixel SPX. For example, the first contact hole CH1 may overlap with the embankment BNK and may be located around the light-emitting region EMA. In this case, when the first contact hole CH1 is covered by the embankment BNK, the visibility of the pattern in the light-emitting region EMA may be reduced, or the pattern in the light-emitting region EMA may be prevented from being seen. However, this disclosure is not limited thereto. For example, in other embodiments of this disclosure, at least one first contact hole CH1 may be located inside the light-emitting region EMA.

[0151] Pixel circuits (PXCs) can be located below light-emitting elements (LDs) positioned within the corresponding sub-pixel regions (SPAs). For example, each pixel circuit (PXC) can be formed in a pixel circuit layer below the light-emitting element (LD) (see [link]). FIG. 8B It is located in the “PCL” (or formed in a layer of circuit elements including circuit elements such as transistors) and can be connected to the first electrode ELT1 through the first contact hole CH1.

[0152] The second electrode ELT2 can be connected to the second connecting electrode CNL2. For example, the second electrode ELT2 can be integrally connected to the second connecting electrode CNL2. For example, the second electrode ELT2 can be formed by branching at least one branch from the second connecting electrode CNL2. When the second electrode ELT2 and the second connecting electrode CNL2 are integrally formed, the second connecting electrode CNL2 can be considered as a region of the second electrode ELT2. However, this disclosure is not limited thereto. For example, in other embodiments of this disclosure, the second electrode ELT2 and the second connecting electrode CNL2 can be formed separately from each other and can be electrically connected to each other through at least one contact hole or through hole.

[0153] Similar to the first connecting electrode CNL1, the second connecting electrode CNL2 may have a single-layer structure or a multi-layer structure.

[0154] The second electrode ELT2 and the second connecting electrode CNL2 can be connected to the second power supply VSS (reference). FIG. 4 For example, the second electrode ELT2 and the second connecting electrode CNL2 can be connected to the second power supply line PL2 (reference) via the second contact hole CH2 and the second power supply VSS. FIG. 6 And connect to the second power supply VSS.

[0155] The second contact hole CH2 may be located outside the light-emitting region EMA of the sub-pixel SPX. For example, the second contact hole CH2 may overlap with the embankment BNK and may be located around the light-emitting region EMA. In this case, when the second contact hole CH2 is covered by the embankment BNK, the visibility of the pattern in the light-emitting region EMA may be reduced, or the pattern in the light-emitting region EMA may be prevented from being seen. However, this disclosure is not limited thereto. For example, in other embodiments, at least one second contact hole CH2 may be located inside the light-emitting region EMA.

[0156] A region of the second power line PL2 for providing the second power supply VSS may be located in the pixel circuit layer (see “PCL” in 8B) below the light-emitting element LD. For example, the second power line PL2 may be located in the pixel circuit layer PCL below the light-emitting element LD and may be connected to the second electrode ELT2 through the second contact hole CH2. However, this disclosure is not limited thereto, and in other embodiments, the location of the second power line PL2 may be varied.

[0157] The first partition wall PW1 may overlap with a region of the first electrode ELT1 and may be located below the first electrode ELT1. Similarly, the second partition wall PW2 may overlap with a region of the second electrode ELT2 and may be located below the second electrode ELT2. The first partition wall PW1 and the second partition wall PW2 may be spaced apart from each other in the light-emitting region EMA and may protrude upward from a corresponding one of the first electrode ELT1 and the second electrode ELT2. For example, the first electrode ELT1 may be located on the first partition wall PW1 to protrude from the first partition wall PW1 in the height direction (or thickness direction or third direction DR3) of the base layer SUB1. Similarly, the second electrode ELT2 may be located on the second partition wall PW2 to protrude from the second partition wall PW2 in the height direction of the base layer SUB1.

[0158] At least one light-emitting element (LD) (e.g., multiple light-emitting elements LD) may be arranged between the first electrode ELT1 and the second electrode ELT2 of the sub-pixel SPX. The multiple light-emitting elements LD may be connected in parallel in the light-emitting region EMA, in which the first electrode ELT1 and the second electrode ELT2 are positioned facing each other.

[0159] exist FIG. 7 In this configuration, the light-emitting elements (LDs) are aligned between the first electrode ELT1 and the second electrode ELT2 along a first direction DR1, for example, in a horizontal direction. However, the arrangement direction of the light-emitting elements (LDs) is not limited to this. For example, at least one of the light-emitting elements (LDs) may be arranged in an inclined direction (e.g., at an angle relative to the first direction DR1).

[0160] Each of the light-emitting elements (LDs) is electrically connected between a first electrode ELT1 and a second electrode ELT2 of the sub-pixel SPX. For example, a first end portion of each of the light-emitting elements (LDs) is electrically connected to the first electrode ELT1, and a second end portion of each of the light-emitting elements (LDs) is electrically connected to the second electrode ELT2.

[0161] In some embodiments, the first end portion of each of the light-emitting elements (LDs) may not be directly located on the first electrode ELT1, but may be electrically connected to the first electrode ELT1 via at least one contact electrode (e.g., via the first contact electrode CNE1). However, this disclosure is not limited thereto. For example, in other embodiments, the first end portion of the light-emitting element (LD) may be in direct contact with the first electrode ELT1 to be electrically connected to the first electrode ELT1.

[0162] Similarly, the second end portion of each of the light-emitting elements LD may not be directly located on the second electrode ELT2, but may be electrically connected to the second electrode ELT2 via at least one contact electrode (e.g., the second contact electrode CNE2). However, this disclosure is not limited thereto. For example, in other embodiments, the second end portion of each of the light-emitting elements LD may be in direct contact with the second electrode ELT2 for electrical connection to the second electrode ELT2.

[0163] Each of the light-emitting elements (LDs) can be a small-sized (e.g., nanometer- to micrometer-scale) light-emitting diode made of a material with an inorganic crystal structure. For example, such as FIG. 1A to FIG. 3B As shown in any of the embodiments, each of the light-emitting elements (LDs) can be a miniature rod-shaped light-emitting diode with dimensions ranging from nanometers to micrometers. However, the types of light-emitting elements (LDs) applicable to this disclosure are not limited thereto. For example, a light-emitting element (LD) can be a light-emitting diode formed, for example, by a growth method, and having a core-shell structure, wherein the core-shell structure has dimensions ranging from nanometers to micrometers.

[0164] The light-emitting element (LD) can be prepared in a dispersed form in a predetermined solution and provided to the light-emitting region EMA of each sub-pixel SPX via inkjet printing, slot coating, or other methods. For example, the LD can be mixed with a volatile solvent and provided to the light-emitting region EMA. In this case, when a predetermined voltage is applied to the first electrode ELT1 and the second electrode ELT2 of the sub-pixel SPX, an electric field is formed between the first electrode ELT1 and the second electrode ELT2, and therefore, the LD can self-align between the first electrode ELT1 and the second electrode ELT2. After the LD is aligned, the solvent is evaporated or removed by other methods, thereby stably arranging the LD between the first electrode ELT1 and the second electrode ELT2. Furthermore, a first contact electrode CNE1 and a second contact electrode CNE2 are formed on the first end portion and the second end portion of the LD, respectively, thereby stably connecting the LD between the first electrode ELT1 and the second electrode ELT2.

[0165] First contact electrode (see) FIG. 8B The “CNE1” in the diagram can be formed on the first end portion of the light-emitting element LD (see [link]). FIG. 8B On the “EP1” in the diagram and on at least one region of the first electrode ELT1 corresponding to the first end portion of the light-emitting element LD, to physically connect and / or electrically connect the first end portion of the light-emitting element LD to the first electrode ELT1. Similarly, the second contact electrode (see…) FIG. 8B The “CNE2” in the diagram can be formed on the second end portion of the light-emitting element LD (see [link]). FIG. 8BThe second end portion of the light-emitting element LD is physically connected to and / or electrically connected to the second electrode ELT2 on at least one region of the second electrode ELT2 corresponding to the second end portion of the light-emitting element LD.

[0166] The light-emitting element (LD) located in the sub-pixel region SPA can form the light source of the corresponding sub-pixel SPX. For example, when the driving current flows in at least one sub-pixel SPX during each frame period, the light-emitting element (LD) connected in the forward direction between the first electrode ELT1 and the second electrode ELT2 of the sub-pixel SPX can emit light with a brightness corresponding to the driving current.

[0167] The luminescent area EMA can be surrounded by a dam NK. For example, the dam NK can be located between two adjacent sub-pixels SPX so as to surround the luminescent area EMA of the sub-pixel SPX.

[0168] FIG. 8A It shows along FIG. 6 An example diagram of subpixels intercepted by line I-I'. FIG. 8B It shows along FIG. 7 A cross-sectional view of an example of a subpixel cut off by line II-II'.

[0169] FIG. 8A and FIG. 8B The diagram illustrates any sub-pixel region SPA (e.g., the first sub-pixel region SPA1) of the display panel PNL. According to some embodiments, the aforementioned first sub-pixel SPX1, second sub-pixel SPX2, and third sub-pixel SPX3 may have substantially the same or similar cross-sectional structures. Therefore, for ease of description, they will be compared with... FIG. 7 The structure of each sub-pixel SPX is fully described by the cross-section of the first sub-pixel region SPA1 corresponding to line II-II'.

[0170] refer to FIG. 8A and FIG. 8B The pixel circuit layer PCL and the display element layer LDL can be located sequentially in each sub-pixel region SPA on the base layer SUB1.

[0171] According to some implementations, the pixel circuit layer (PCL) and the display element layer (LDL) can be completely formed in the display area DA of the display panel PNL. For example, the pixel circuit layer (PCL) can be formed on one surface of the base layer SUB1, and the display element layer (LDL) can be formed on the base layer SUB1 on which the pixel circuit layer (PCL) is formed.

[0172] The pixel circuit layer (PCL) may include circuit elements for configuring the pixel circuit (PXC) of the sub-pixel (SPX), as well as a first power line (PL1) and a second power line (PL2). The display element layer (LDL) may include the light-emitting element (LD) of the sub-pixel (SPX).

[0173] The pixel circuit layer (PCL) may include multiple circuit elements located in the display area (DA). For example, the pixel circuit layer (PCL) may include multiple circuit elements formed in the sub-pixel area (SPA) to configure the pixel circuit (PXC) of the sub-pixel (SPX). For example, the pixel circuit layer (PCL) may include multiple transistors located in the sub-pixel area (SPA), for example, reference... FIG. 5A and FIG. 5B The first transistor T1 and the second transistor T2 are described. Furthermore, although... FIG. 8A and FIG. 8B Not shown in the diagram, but in some embodiments, the pixel circuit layer PCL may include a storage capacitor Cst located in the sub-pixel region SPA, and various signal lines connected to the pixel circuit PXC (e.g., see reference 1). FIG. 5A and FIG. 5B The i-th scan line Si and j-th data line Dj are described, as well as various power lines connected to the pixel circuit PXC and / or the light-emitting element LD (e.g., first power line PL1 and second power line PL2 for transmitting the first power supply VDD and the second power supply VSS, respectively).

[0174] The plurality of transistors included in the pixel circuit PXC (e.g., first transistor T1 and second transistor T2) may have substantially the same or similar cross-sectional structures. However, this disclosure is not limited thereto, and in another embodiment, at least some of the plurality of transistors may have different types and / or structures.

[0175] The pixel circuit layer PCL may include multiple insulating layers. For example, the pixel circuit layer PCL may include a buffer layer BFL, a gate insulating film GI, a first interlayer insulating film ILD1 and a second interlayer insulating film ILD2, and a first passivation film PSV1 and a second passivation film PSV2, which are sequentially stacked on one surface of the base layer SUB1.

[0176] A buffer layer (BFL) can reduce or prevent impurities from diffusing into circuit elements. The buffer layer (BFL) can be configured as a single layer or as multiple layers of at least two layers. When the buffer layer (BFL) is disposed in multiple layers, each layer can be formed of the same material or different materials. In other embodiments, the buffer layer (BFL) may be omitted.

[0177] Each of the first transistor T1 and the second transistor T2 may include a semiconductor layer SCL, a gate electrode GE, a first transistor electrode ET1, and a second transistor electrode ET2. Meanwhile, in FIG. 8BIn this embodiment, the first transistor T1 and the second transistor T2 include a first transistor electrode ET1 and a second transistor electrode ET2 formed separately from the semiconductor layer SCL. However, this disclosure is not limited thereto. For example, in other embodiments of this disclosure, the first transistor electrode ET1 and / or the second transistor electrode ET2 included in at least one transistor located in each sub-pixel region SPA may be integrally configured with each semiconductor layer SCL.

[0178] The semiconductor layer SCL may be located on the buffer layer BFL. For example, the semiconductor layer SCL may be located between the gate insulating film GI and the base layer SUB1 on which the buffer layer BFL is formed. The semiconductor layer SCL may include a first region in contact with the first transistor electrode ET1, a second region in contact with the second transistor electrode ET2, and a channel region located between the first region and the second region. One of the first region and the second region may be a source region, and the other may be a drain region.

[0179] The semiconductor layer SCL can be a semiconductor pattern formed from polycrystalline silicon, amorphous silicon, oxide semiconductor, etc. Furthermore, the channel region of the semiconductor layer SCL can be an intrinsic semiconductor as an undoped semiconductor pattern, and the first and second regions of the semiconductor layer SCL can be doped (e.g., doped with predetermined impurities) semiconductor patterns, respectively.

[0180] The gate electrode GE may be located on the semiconductor layer SCL, with the gate insulating film GI interposed between them. For example, the gate electrode GE may be positioned between the gate insulating film GI and the first interlayer insulating film ILD1 to overlap with at least one region of the semiconductor layer SCL.

[0181] The first transistor electrode ET1 and the second transistor electrode ET2 may be located on the semiconductor layer SCL and the gate electrode GE, with at least one of the first interlayer insulating film ILD1 and the second interlayer insulating film ILD2 interposed between them. For example, the first transistor electrode ET1 and the second transistor electrode ET2 may be located between the second interlayer insulating film ILD2 and the first passivation film PSV1. The first transistor electrode ET1 and the second transistor electrode ET2 may be electrically connected to the semiconductor layer SCL. For example, the first transistor electrode ET1 and the second transistor electrode ET2 may be connected to the first region and the second region of the semiconductor layer SCL, respectively, through contact holes passing through the gate insulating film GI and the first interlayer insulating film ILD1 and the second interlayer insulating film ILD2.

[0182] Meanwhile, at least one transistor included in the pixel circuit PXC (e.g., FIG. 5A and FIG. 5BEither the first transistor electrode ET1 and the second transistor electrode ET2 of the first transistor T1 shown can be electrically connected to the first electrode ELT1 of the light source unit LSU located on the second passivation film PSV2 through the first contact hole CH1 passing through the first passivation film PSV1 and the second passivation film PSV2.

[0183] At least one signal line and / or power line connected to the sub-pixel SPX may be located on the same layer as an electrode of the circuit element of the pixel circuit PXC. For example, a second power line PL2 for providing a second power supply VSS (e.g., in...) FIG. 8B The first sub-power line PL2-1 included in the second power line PL2 may be located on the same layer as the gate electrode GE of each of the first transistor T1 and the second transistor T2, and may be electrically connected to the second electrode ELT2 of the light source unit LSU located on the first passivation film PSV1 and the second passivation film PSV2 through at least one second contact hole CH2 and through a bridging pattern BRP located on the same layer as the first transistor electrode ET1 and the second transistor electrode ET2. However, in other embodiments, the structure and / or position of the second power line PL2 may be varied.

[0184] The display element layer (LDL) may include a first partition wall (PW1) and a second partition wall (PW2), a first electrode (ELT1) and a second electrode (ELT2), a first insulating layer (INS1), a light-emitting element (LD), a second insulating layer (INS2), a first contact electrode (CNE1) and a second contact electrode (CNE2), a third insulating layer (INS3), and an encapsulation film (ENC) sequentially positioned and / or formed on the pixel circuit layer (PCL).

[0185] The first separator wall PW1 and the second separator wall PW2 may be located on the pixel circuit layer PCL. The first separator wall PW1 and the second separator wall PW2 may be spaced apart from each other in the light-emitting region EMA. The first separator wall PW1 and the second separator wall PW2 may protrude in the height direction on the pixel circuit layer PCL. The first separator wall PW1 and the second separator wall PW2 may have substantially the same height, but are not limited thereto.

[0186] The first partition wall PW1 may be located between the pixel circuit layer PCL and the first electrode ELT1. The first partition wall PW1 may be positioned adjacent to the first end portion EP1 of the light-emitting element LD. For example, one side surface of the first partition wall PW1 may be located at a certain distance from the first end portion EP1 of the light-emitting element LD, and may face the first end portion EP1 at a certain distance.

[0187] The second separator wall PW2 may be located between the pixel circuit layer PCL and the second electrode ELT2. The second separator wall PW2 may be positioned adjacent to the second end portion EP2 of the light-emitting element LD. For example, one side surface of the second separator wall PW2 may be located at a certain distance from the second end portion EP2 of the light-emitting element LD, facing the second end portion EP2.

[0188] The first partition wall PW1 and the second partition wall PW2 can have various shapes. For example, the first partition wall PW1 and the second partition wall PW2 can have the following shapes: FIG. 8B The diagram shows a trapezoidal cross-sectional shape that narrows upwards. In this case, each of the first partition wall PW1 and the second partition wall PW2 may have an inclined surface on at least one side surface. As another example, the first partition wall PW1 and the second partition wall PW2 may have a semi-circular or semi-elliptical cross-section that narrows upwards. In this case, each of the first partition wall PW1 and the second partition wall PW2 may have a curved surface on at least one side surface. That is, in this disclosure, the shape of the first partition wall PW1 and the second partition wall PW2 is not particularly limited and can be varied. Furthermore, at least one of the first partition wall PW1 and the second partition wall PW2 may be omitted, or their positions may be changed.

[0189] The first separator PW1 and the second separator PW2 may comprise an insulating material, which may include inorganic and / or organic materials. For example, the first separator PW1 and the second separator PW2 may comprise at least one inorganic film, which may comprise various inorganic insulating materials, including SiN. x SiO x Alternatively, the first separator PW1 and the second separator PW2 may comprise at least one layer of at least one organic film comprising various organic insulating materials, a photoresist film, etc., or may be configured as a single layer or multiple layers of insulator comprising a combination of organic / inorganic materials. That is, the configuration materials of the first separator PW1 and the second separator PW2 can be varied.

[0190] In some embodiments, the first partition wall PW1 and the second partition wall PW2 can be used as reflective members. For example, the first partition wall PW1 and the second partition wall PW2, together with the first electrode ELT1 and the second electrode ELT2 disposed on the first partition wall PW1 and the second partition wall PW2, can be used as reflective members that typically guide light emitted from each of the light-emitting elements LD to a desired direction to improve the light efficiency of the pixel PXL.

[0191] The first electrode ELT1 and the second electrode ELT2 can be located on the first separator PW1 and the second separator PW2, respectively. The first electrode ELT1 and the second electrode ELT2 can be spaced apart from each other in the light-emitting region EMA.

[0192] The first electrode ELT1 and the second electrode ELT2, located on the first partition wall PW1 and the second partition wall PW2 respectively, may have shapes corresponding to the shapes of the first partition wall PW1 and the second partition wall PW2 respectively. For example, the first electrode ELT1 and the second electrode ELT2 may have inclined surfaces or curved surfaces corresponding to the shapes of the first partition wall PW1 and the second partition wall PW2 respectively, and may protrude in the height direction (or thickness direction) of the pixel circuit layer PCL.

[0193] Each of the first electrode ELT1 and the second electrode ELT2 may include at least one conductive material. For example, each of the first electrode ELT1 and the second electrode ELT2 may include at least one of the following materials: metals such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Ti and their alloys; conductive oxides such as ITO, IZO, ZnO or ITZO; and conductive polymers such as PEDOT, but not limited thereto.

[0194] Furthermore, each of the first electrode ELT1 and the second electrode ELT2 may be configured as a single layer or multiple layers. For example, each of the first electrode ELT1 and the second electrode ELT2 may include at least one reflective electrode layer. In addition, each of the first electrode ELT1 and the second electrode ELT2 may optionally further include at least one of the following: a transparent electrode layer located on and / or below the reflective electrode layer; and a conductive coating layer covering at least one layer on the upper part of the reflective electrode layer and / or the transparent electrode layer.

[0195] Each of the reflective electrode layers of the first electrode ELT1 and the second electrode ELT2 may be configured with a conductive material having uniform reflectivity. For example, the reflective electrode layer may include at least one of metals and alloys thereof, such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, and Cr, but is not limited thereto. That is, the reflective electrode layer may be configured with various reflective conductive materials. When each of the first electrode ELT1 and the second electrode ELT2 includes a reflective electrode layer, light emitted from the two end portions of each of the light-emitting elements LD (e.g., from the first end portion EP1 and the second end portion EP2) may further travel or be guided in the direction of displaying the image (e.g., typically in the direction of the front surface). For example, when the first electrode ELT1 and the second electrode ELT2 each have inclined or curved surfaces corresponding to the shapes of the first partition wall PW1 and the second partition wall PW2, and are positioned facing the end portions EP1 and EP2 of the light-emitting element LD, the light emitted from the first end portion EP1 and the second end portion EP2 of each of the light-emitting elements LD can be reflected by the first electrode ELT1 and the second electrode ELT2, and can further travel or be guided towards the front surface direction of the display panel PNL (e.g., the upward direction of the base layer SUB1). Therefore, the efficiency of the light emitted from the light-emitting element LD can be improved.

[0196] Furthermore, the transparent electrode layer of each of the first electrode ELT1 and the second electrode ELT2 can be configured with various transparent electrode materials. For example, the transparent electrode layer may include ITO, IZO, or ITZO, but is not limited thereto. In some embodiments, each of the first electrode ELT1 and the second electrode ELT2 may be configured as a three-layer structure having an ITO / Ag / ITO stack. As described above, when the first electrode ELT1 and the second electrode ELT2 are configured as a multilayer structure with at least two or more layers, the voltage drop due to signal delay can be reduced or minimized. Therefore, the desired voltage can be efficiently delivered to the light-emitting element LD.

[0197] Furthermore, when each of the first electrode ELT1 and the second electrode ELT2 includes a conductive coating covering the reflective electrode layer and / or the transparent electrode layer, damage to the reflective electrode layers of the first electrode ELT1 and the second electrode ELT2 due to defects generated during the manufacturing process of the pixel PXL, etc., can be reduced or prevented. However, the conductive coating may be selectively included in the first electrode ELT1 and the second electrode ELT2, and may be omitted in other embodiments. Furthermore, the conductive coating may be considered as a component of each of the first electrode ELT1 and the second electrode ELT2, or as a separate component located on the first electrode ELT1 and the second electrode ELT2.

[0198] The first insulating layer INS1 may be located on a region of the first electrode ELT1 and the second electrode ELT2. For example, the first insulating layer INS1 may be formed to cover a region of the first electrode ELT1 and the second electrode ELT2, and may include an opening portion that exposes another region of the first electrode ELT1 and the second electrode ELT2.

[0199] In some embodiments, firstly, the first insulating layer INS1 may be formed to completely cover the first electrode ELT1 and the second electrode ELT2. When the light-emitting element LD is provided and on the first insulating layer INS1 as shown... FIG. 7 After alignment as shown, the first insulating layer INS1 may be partially opened to expose the first electrode ELT1 and the second electrode ELT2 at predetermined portions of the top surfaces of each of the first partition wall PW1 and the second partition wall PW2. Alternatively, after the provisioning and alignment of the light-emitting element LD are completed, the first insulating layer INS1 may be patterned into a single pattern locally located below the light-emitting element LD.

[0200] That is, the first insulating layer INS1 can be inserted between the first electrode ELT1 and the second electrode ELT2 and the light-emitting element LD, and can expose at least one area of ​​each of the first electrode ELT1 and the second electrode ELT2. After the first electrode ELT1 and the second electrode ELT2 are formed, the first insulating layer INS1 can be formed to cover the first electrode ELT1 and the second electrode ELT2, thereby reducing or preventing damage to the first electrode ELT1 and the second electrode ELT2 and / or metal deposition in subsequent processes. In addition, the first insulating layer INS1 can stably support each of the light-emitting elements LD. In other embodiments, the first insulating layer INS1 can be omitted.

[0201] A light-emitting element (LD) can be provided and aligned within a light-emitting region EMA having a first insulating layer INS1. For example, the LD can be provided to the EMA via an inkjet printing method, and the LD can be aligned between the first electrode ELT1 and the second electrode ELT2 by an alignment voltage (e.g., a predetermined alignment voltage or alignment signal) applied to the first electrode ELT1 and the second electrode ELT2. As described later, to align the LD, a reference voltage (e.g., a ground voltage) can be applied to the second electrode ELT2, and a predetermined alternating current (AC) voltage can be applied to the first electrode ELT1. An electric field is formed between the first electrode ELT1 and the second electrode ELT2, and the LD can self-align between the first electrode ELT1 and the second electrode ELT2 within the light-emitting region EMA.

[0202] The embankment BNK may be located on the first insulating layer INS1. For example, the embankment BNK may be formed between two adjacent sub-pixels SPX to surround the light-emitting region EMA of the sub-pixel SPX, thereby forming a pixel-defining film that divides the light-emitting region EMA of the sub-pixel SPX.

[0203] The dam section BNK can be formed with a second height that is higher than the first height of the first partition wall PW1 and the second partition wall PW2. In this case, during the operation of supplying the light-emitting element LD to each light-emitting region EMA, the dam section BNK can serve as a dam structure to reduce or prevent the flow of the solution in which the light-emitting element LD is mixed into the light-emitting region EMA of the adjacent sub-pixel SPX or to control the amount (e.g., a predetermined amount) of the solution to be supplied to each light-emitting region EMA.

[0204] The dam BNK can be formed to block light emitted from each emitting region EMA from flowing into adjacent emitting regions EMA and to prevent light interference. For this purpose, a dam BNK can be formed to block light emitted from the emitting element LD of each sub-pixel SPX from passing through the dam BNK.

[0205] The second insulating layer INS2 may be located on the light-emitting element LD (e.g., the light-emitting element LD disposed between the first electrode ELT1 and the second electrode ELT2), and may expose the first end portion EP1 and the second end portion EP2 of the light-emitting element LD. For example, the second insulating layer INS2 may not cover the first end portion EP1 and the second end portion EP2 of the light-emitting element LD, and may be partially located on only one region of the light-emitting element LD. The second insulating layer INS2 may be formed in a separate pattern on each light-emitting region EMA, but is not limited thereto. Furthermore, as... FIG. 8B As shown, when there is a space between the first insulating layer INS1 and the light-emitting element LD before the second insulating layer INS2 is formed, the space can be filled by the second insulating layer INS2. Therefore, the light-emitting element LD can be supported more stably.

[0206] The first contact electrode CNE1 and the second contact electrode CNE2 may be located on the first electrode ELT1 and the second electrode ELT2, and on the first end portion EP1 and the second end portion EP2 of the light-emitting element LD, respectively. In some embodiments, such as FIG. 8B As shown, the first contact electrode CNE1 and the second contact electrode CNE2 may be located in the same layer. In this case, the first contact electrode CNE1 and the second contact electrode CNE2 may be formed using the same conductive material in the same process, but are not limited thereto.

[0207] The first contact electrode CNE1 and the second contact electrode CNE2 can electrically connect the first end portion EP1 and the second end portion EP2 of the light-emitting element LD to the first electrode ELT1 and the second electrode ELT2, respectively.

[0208] For example, the first contact electrode CNE1 may be located in a sub-pixel region SPA in which the second insulating layer INS2 is positioned. The first contact electrode CNE1 may be located on the first electrode ELT1 to contact a region of the first electrode ELT1 located in the corresponding sub-pixel region SPA. Furthermore, the first contact electrode CNE1 may be located on a first end portion EP1 to contact the first end portion EP1 of at least one light-emitting element LD located in the corresponding sub-pixel region SPA. The first end portion EP1 of at least one light-emitting element LD located in the sub-pixel region SPA may be electrically connected to the first electrode ELT1 located in the corresponding sub-pixel region SPA via the first contact electrode CNE1.

[0209] The third insulating layer INS3 may be located in the sub-pixel region SPA in which the first contact electrode CNE1 is positioned. The third insulating layer INS3 may cover the second insulating layer INS2, the first contact electrode CNE1, and the embankment BNK located in the corresponding sub-pixel region SPA.

[0210] Similar to the first insulating layer INS1 and the second insulating layer INS2, the third insulating layer INS3 may be configured as a single layer or multiple layers, and may include at least one inorganic insulating material and / or an organic insulating material. For example, the third insulating layer INS3 may include various types of organic / inorganic insulating materials, including SiN. x Furthermore, the third insulating layer INS3 may include an insulating material that is different from the insulating material of the first insulating layer INS1 and the second insulating layer INS2, or may include at least some of the same insulating material as the first insulating layer INS1 and the second insulating layer INS2.

[0211] The second contact electrode CNE2 may be located in each sub-pixel region SPA in which the third insulating layer INS3 is positioned. The second contact electrode CNE2 may be located on the second electrode ELT2 to contact a region of the second electrode ELT2 located in the corresponding sub-pixel region SPA. Furthermore, the second contact electrode CNE2 may be located on the second end portion EP2 to contact the second end portion EP2 of at least one light-emitting element LD located in the corresponding sub-pixel region SPA. The second end portion EP2 of at least one light-emitting element LD located in each sub-pixel region SPA may be electrically connected to the second electrode ELT2 located in the corresponding sub-pixel region SPA via the second contact electrode CNE2.

[0212] The encapsulation film ENC can be formed on or located on the surface of the base layer SUB1, on which the first partition wall PW1 and the second partition wall PW2, the first electrode ELT1 and the second electrode ELT2, the light-emitting element LD, the first contact electrode CNE1 and the second contact electrode CNE2, and the embankment BNK are formed, thereby covering the first partition wall PW1 and the second partition wall PW2, the first electrode ELT1 and the second electrode ELT2, the light-emitting element LD, the first contact electrode CNE1 and the second contact electrode CNE2, and the embankment BNK. The encapsulation film ENC can be an inorganic insulating film comprising inorganic materials or an organic insulating film comprising organic materials. For example, the encapsulation film ENC can have a structure in which at least one inorganic film and at least one organic film are alternately stacked. Furthermore, in other embodiments, at least one outer coating layer may also be positioned on the third insulating layer INS3. This will be discussed later in the references. FIG. 12 Describes the non-display area NDA.

[0213] FIG. 9 This is a flowchart illustrating a method for manufacturing a display device according to some embodiments of the present disclosure. FIG. 10 It is a diagram used to describe the alignment lines formed on the mother substrate. FIG. 11 This is a plan view showing an example of a sub-pixel, magnified in size. FIG. 10 The third region, B. FIG. 12 to FIG. 16 It is along FIG. 11 The sectional view taken from line III-III' is used to describe the manufacturing process. FIG. 9 A view of the method of displaying the device.

[0214] In the following text, reference will be made to FIG. 9 as well as FIG. 10 to FIG. 16 A method for manufacturing a light-emitting display device according to some embodiments of the present disclosure is described.

[0215] In the method of manufacturing a display device, a mother substrate 100 (or substrate SUB1 (i.e., the base layer SUB1 described above)) (S100) may be prepared.

[0216] After multiple display panels are formed (e.g., simultaneously or substantially simultaneously) on a mother substrate 100, the display panels can be individually separated by a cutting process. Here, the display panel may be a reference. FIG. 4 as well as FIG. 6 to FIG. 8B One of the display panels described.

[0217] The mother substrate 100 may include unit regions CEL1 and CEL2 for forming a plurality of display panels. The unit regions CEL1 and CEL2 of the mother substrate 100 may include a display area DA and a non-display area NDA located outside the display area DA, wherein the display area DA includes a plurality of pixel areas PXA. The unit regions CEL1 and CEL2 may be defined by a cutting line CL including a first cutting line CL1 and a second cutting line CL2.

[0218] A first alignment pad AP1 and a second alignment pad AP2 may be included in a region (e.g., an edge region) of the mother substrate 100.

[0219] A first sub-line SUL1 and a second sub-line SUL2 (S200) including a trench region TC can be formed as a pixel circuit layer PCL, a first alignment line AL1, and a second alignment line AL2.

[0220] When substrate SUB1 is prepared, a pixel circuit layer PCL can be formed on substrate SUB1, and sub-lines SUL1 and SUL2 of the first alignment line AL1 and the second alignment line AL2 can be formed on substrate SUB1. Each of sub-lines SUL1 and SUL2 can be formed in the same layer as at least one electrode in the pixel circuit layer PCL during the same operation. For example, the first sub-line SUL1 and the second sub-line SUL2 can be formed on the first passivation film PSV1. Each of the first sub-line SUL1 and the second sub-line SUL2 can be configured as a single layer or multiple layers.

[0221] The first sub-line SUL1 and the second sub-line SUL2 may include a trench region TC. The trench region TC is a discontinuity between the first sub-line SUL1 and the second sub-line SUL2, and can be formed by a photolithography process. FIG. 12 As shown, the groove region TC can be formed in the region near the cutting line CL. Since the cutting line CL corresponds to the periphery of each of the cell regions CEL1 and CEL2, the cross-sections of the first sub-line SUL1 and the second sub-line SUL2 can be exposed along the cutting line CL when the groove region TC is not present in the first sub-line SUL1 and the second sub-line SUL2.

[0222] The trench region TC provides a space in which the cross-sections of the first sub-line SUL1 and the second sub-line SUL2 can be covered by a third insulating layer INS3 and / or an encapsulation film ENC during subsequent display device manufacturing processes. Therefore, static electricity can be reduced or prevented from flowing into the cell regions CEL1 and CEL2 from the outside.

[0223] The trench region TC may have a rectangular shape in the plane. Sub-lines SUL1 and SUL2, separated by the trench region TC, may be positioned relative to the cutting line CL, which serves as a reference line, and spaced apart from each other in the left-right direction by distances (e.g., predetermined distances) d1 and d2. In this case, the distances d1 and d2 are sufficient to ensure that the exposed cross-sections of sub-lines SUL1 and SUL2 have space that can be covered by the third insulating layer INS3 and / or the encapsulation film ENC.

[0224] Furthermore, a main line MAL1 and MAL2, including extension portions MAL1_ad and MAL2_ad, can be formed on a substrate SUB1 on which a pixel circuit layer PCL and sub-lines SUL1 and SUL2, forming a first electrode ELT1 and a second electrode ELT2, as well as the first alignment line AL1 and the second alignment line AL2 (S300).

[0225] The main lines MAL1 and MAL2 of the first alignment line AL1 and the second alignment line AL2 may be formed together with the first electrode ELT1 and the second electrode ELT2 (e.g., they may be formed simultaneously or substantially simultaneously). The first electrode ELT1 and the second electrode ELT2 may be formed in the pixel region PXA of each display area DA.

[0226] The main lines MAL1 and MAL2 of the first alignment line AL1 and the second alignment line AL2 can be connected to the first electrode ELT1 and the second electrode ELT2, respectively. Furthermore, the main lines MAL1 and MAL2 of the first alignment line AL1 and the second alignment line AL2 can be electrically connected to the sub-lines SUL1 and SUL2 of the first alignment line AL1 and the second alignment line AL2, respectively. For example... FIG. 10 As shown, the first main line MAL1 can be electrically connected to the first sub-line SUL1 via the third contact hole CH3. The second main line MAL2 can be electrically connected to the second sub-line SUL2 via the fourth contact hole CH4. Although only one third contact hole CH3 and only one fourth contact hole CH4 are shown for ease of description, multiple third contact holes CH3 and fourth contact holes CH4 can be formed for satisfactory transmission of alignment signals.

[0227] The first main line MAL1 and the second main line MAL2 may each include extended portions MAL1_ad and MAL2_ad. The extended portions MAL1_ad and MAL2_ad may be wider / extended sections of the first main line MAL1 and the second main line MAL2 in the width direction (e.g., the second direction DR2), and can be formed by a photolithography process. FIG. 11As shown, extensions MAL1_ad and MAL2_ad can be formed in the region near the cutting line CL. Extensions MAL1_ad and MAL2_ad can be formed in sections of the first main line MAL1 and the second main line MAL2 that overlap with the trench region TC in the thickness direction (e.g., the third direction DR3). For a self-aligned light-emitting element LD, an alignment voltage (e.g., a predetermined alignment voltage) is applied through the first alignment line AL1 and the second alignment line AL2. Since the trench region TC is the region where sub-lines SUL1 and SUL2 are absent, its resistance can be greater than the resistance of other sections formed by multiple layers, including the main lines MAL1 and MAL2 and the sub-lines SUL1 and SUL2.

[0228] When an alignment voltage is applied through the first alignment line AL1 and the second alignment line AL2, the increase in resistance due to the trench region TC can be reduced or prevented by increasing the area of ​​the main lines MAL1 and MAL2 via the extension portions MAL1_ad and MAL2_ad.

[0229] The lengths of the extension portions MAL1_ad and MAL2_ad in the extension direction (e.g., the first direction DR1) may be the same as the length of the trench region TC in the extension direction (e.g., the first direction DR1). For example, the extension portions MAL1_ad and MAL2_ad may be approximately the same width as the trench region TC. However, this disclosure is not limited to this, and various changes can be made to the lengths of the extension portions MAL1_ad and MAL2_ad in the extension direction (e.g., the first direction DR1) and in the width direction (e.g., the second direction DR2) to reduce the increased resistance due to the trench region TC.

[0230] For reference FIG. 6 to FIG. 8B As described, the embankment BNK may be located on the first insulating layer INS1. For example, the embankment BNK may be formed between two adjacent sub-pixels SPX to surround the light-emitting region EMA of the sub-pixel SPX, thereby configuring a pixel-defining film that divides the light-emitting region EMA of the sub-pixel SPX. In addition, a light-emitting element LD (S400) may be provided and aligned.

[0231] A light-emitting element (LD) can be provided on a substrate SUB1 on which a first electrode ELT1 and a second electrode ELT2, as well as a first alignment line AL1 and a second alignment line AL2, are formed. Multiple light-emitting elements (LDs) can be provided to each pixel region PXA of the display area DA using one or more methods, such as inkjet printing. Furthermore, simultaneously or subsequently with the provision of the light-emitting elements (LDs), power can be applied to the first alignment line AL1 and the second alignment line AL2 via the first alignment pad AP1 and the second alignment pad AP2 to align the light-emitting elements (LDs) between the first pixel electrode ELT1 and the second pixel electrode ELT2 (i.e., the first electrode ELT1 and the second electrode ELT2) connected to the first alignment line AL1 and the second alignment line AL2.

[0232] For reference FIG. 6 to FIG. 8B As described, after the self-alignment of the light-emitting element LD is completed, the main lines MAL1 and MAL2 can be removed from the non-display area NDA. At this time, the first insulating layer INS1 located on the main lines MAL1 and MAL2 can also be removed.

[0233] In addition, a first contact electrode CNE1 and a second contact electrode CNE2, a third insulating layer INS3 and an encapsulation film ENC (S500) can be formed.

[0234] First contact electrode CNE1 and second contact electrode CNE2 may be formed on a substrate SUB1 on which the light-emitting element LD is aligned. Each of the first contact electrodes CNE1 can connect a first end portion EP1 of at least one of the light-emitting elements LD to a first electrode ELT1 located in the corresponding pixel region PXA. Furthermore, each of the second contact electrodes CNE2 can connect a second end portion EP2 of each of the light-emitting elements LD to a second electrode ELT2 located in the corresponding pixel region PXA.

[0235] like FIG. 8A and FIG. 8B As shown, the third insulating layer INS3 can be inserted between the first contact electrode CNE1 and the second contact electrode CNE2. The third insulating layer INS3 and the encapsulation film ENC can be sequentially stacked on the sub-lines SUL1 and SUL2 located in the non-display area NDA. At this time, the cross-sections of sub-lines SUL1 and SUL2 exposed by the trench region TC can be covered by the third insulating layer INS3 and the encapsulation film ENC.

[0236] Furthermore, by performing a cutting process along the cutting line CL, the light-emitting display panels (or unit regions CEL1 and CEL2) formed together on the mother substrate 100 can be separated individually (S600). According to the example, the cutting process can be a laser process using a laser LS. Thereafter, module processes, etc., can be performed on each display panel PNL.

[0237] Although the technical spirit of this disclosure has been described in detail with reference to the above embodiments, it should be noted that the above embodiments are for illustrative purposes and not for limiting purposes. Furthermore, those skilled in the art will understand that various modifications are possible within the scope of the technical spirit of this disclosure.

[0238] The scope of this disclosure is not limited to the details described in the detailed description of the specification, but should be defined by the claims. Furthermore, it should be understood that all changes or modifications derived from the meaning and scope of the claims and their equivalents are included within the scope of this disclosure.

Claims

1. A display device comprising: a substrate including a display region and a non-display region located outside the display region, the display region including a plurality of pixel regions; a pixel circuit layer including a plurality of circuit elements located in the display region; a display element layer including a plurality of light emitting elements located in the display region on the pixel circuit layer; and a first alignment line and a second alignment line located on the substrate and each including a main line and a sub line, the main line being located at the same layer as at least one electrode in the display element layer, the sub line being electrically connected to the main line and located at the same layer as at least one electrode in the pixel circuit layer, wherein the first alignment line and the second alignment line do not include the main line in the non-display region and include the sub line spaced apart from one edge of the substrate. the display element layer includes:

2. The display device according to claim 1, wherein a first electrode and a second electrode located in each of the plurality of pixel regions on the pixel circuit layer; a first insulating layer located on a partial region of the first electrode and a partial region of the second electrode; and the light emitting element located between the first electrode and the second electrode of each of the plurality of pixel regions. the first electrode and the second electrode are spaced apart from each other at the same layer in each of the plurality of pixel regions, 3. The display device of claim 2, wherein, wherein a first end portion of the light emitting element is electrically connected to the first electrode of a corresponding pixel, and wherein a second end portion of the light emitting element is electrically connected to the second electrode of the corresponding pixel. 4.The display device according to claim 3, further comprising a second insulating layer partially located on only one region of the light emitting element without covering the first end portion and the second end portion of the light emitting element. 5.The display device according to claim 4, further comprising: a first contact electrode connecting the first end portion and the first electrode of the corresponding pixel to each other; and a second contact electrode connecting the second end portion and the second electrode of the corresponding pixel to each other, wherein a third insulating layer is interposed between the first contact electrode and the second contact electrode. an upper surface and one end portion of the sub line are covered by the third insulating layer. 7.The display device according to claim 6, further comprising an encapsulation film located on the third insulating layer.

6. The display device of claim 5, wherein, the main line of each of the first alignment line and the second alignment line is located at the same layer as at least one of the first electrode and the second electrode. each of the light emitting elements includes:

8. The display device according to claim 2, wherein a first conductive semiconductor layer doped with a first conductive dopant; 9. The display device according to claim 1, wherein a second conductive semiconductor layer doped with a second conductive dopant; and an active layer provided between the first conductive semiconductor layer and the second conductive semiconductor layer. each of the light emitting elements includes a rod-shaped light emitting diode having a size of micrometer or nanometer. ​ 10. The display device of claim 9, wherein, ​

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