Display device

Abstract

A display device includes a driver comprising a flexible circuit board connected to a display panel. The driver further includes: a first source circuit board; a second source circuit board; a main circuit board including a controller for generating a power supply voltage, the main circuit board applying the power supply voltage to each of the first and second source circuit boards; and a connector connecting the first and second source circuit boards. The connector is electrically connected to a first voltage line of a plurality of voltage lines of the first source circuit board that is most adjacent to the second source circuit board, and a second voltage line of a plurality of voltage lines of the second source circuit board that is most adjacent to the first source circuit board.

Description

[0001] Cross-references to related applications

[0002] This patent application claims priority to Korean Patent Application No. 10-2020-0004071, filed on January 13, 2020, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to display devices. More specifically, this disclosure relates to display devices with improved reliability. Background Technology

[0004] In a display device, after the display panel is manufactured, it is connected to a circuit board. For example, the circuit board is bonded to the display panel using tape auto-bonding (TAB) with anisotropic conductive film (ACF). Summary of the Invention

[0005] This disclosure provides a display device that, by including a connector connecting circuit boards spaced apart from each other, is able to prevent defects in the display panel caused by overcurrent (current deflection) when the power supply voltages supplied to the spaced-apart circuit boards have different voltages due to differences in the length between the lines, and is able to minimize the differences between the power supply voltages applied to the spaced-apart circuit boards.

[0006] An embodiment of the present invention provides a display device comprising: a display panel including a plurality of pixels and a plurality of display pads connected to the plurality of pixels and arranged in a first direction and spaced apart from each other; and a driver for applying a power supply voltage to the plurality of pixels. The driver includes: a plurality of flexible circuit boards connected to the plurality of display pads; a first source circuit board including a plurality of voltage lines connected to the first flexible circuit board; a second source circuit board arranged in the first direction and spaced apart from the first source circuit board, and the second source circuit board including a plurality of voltage lines connected to the second flexible circuit board; a main circuit board including a controller for generating the power supply voltage, a first main line connecting the controller to the first source circuit board, and a second main line connecting the controller to the second source circuit board; and a connector electrically connected to one of the plurality of voltage lines of the first source circuit board and one of the plurality of voltage lines of the second source circuit board adjacent to the first source circuit board voltage line. The first main line has a length different from the length of the second main line.

[0007] The connector includes: a first sub-connection portion connected to one of the plurality of voltage lines disposed on the first source circuit board; a second sub-connection portion connected to the voltage line most adjacent to the voltage line on the first source circuit board among the plurality of voltage lines disposed on the second source circuit board; and a resistor portion disposed between the first sub-connection portion and the second sub-connection portion, wherein the resistor portion has a relatively higher resistance than the first sub-connection portion and the second sub-connection portion.

[0008] The resistor portion comprises the same material as the first sub-connection portion and the second sub-connection portion.

[0009] The resistor portion includes a predetermined pattern with a curved shape.

[0010] The resistor portion includes a pattern with a Z-shaped design.

[0011] The resistor portion comprises a material different from that of the first sub-connection portion and the second sub-connection portion.

[0012] The connector includes: a plurality of connection portions extending in the first direction and arranged in a second direction intersecting the first direction to be spaced apart from each other; and a resistor portion disposed at at least one of the plurality of connection portions.

[0013] The driver further includes: a first connecting board for connecting the main circuit board to the first source circuit board; and a second connecting board for connecting the main circuit board to the second source circuit board.

[0014] The first main line is connected to one of the multiple voltage lines of the first source circuit board via the first connecting plate, and the second main line is connected to the voltage line of the multiple voltage lines of the second source circuit board that is most adjacent to the voltage line of the first source circuit board via the second connecting plate.

[0015] Each of the first source circuit board and the second source circuit board is provided in multiples, and the driver further includes connectors connecting adjacent first source circuit boards and adjacent second source circuit boards.

[0016] As described above, since the display device includes a connector that connects to a circuit board that receives the same power supply voltage, the difference between power supply voltages caused by voltage drop can be compensated, and therefore, the heat generation of the display device can be reduced. Attached Figure Description

[0017] The above and other advantages of this disclosure will become more apparent when considered in conjunction with the accompanying drawings, and with reference to the detailed description, wherein:

[0018] Figure 1 This is a perspective view showing a display panel according to an exemplary embodiment of the present disclosure;

[0019] Figure 2 This illustrates the process before the flexible circuit board is attached to the display pad area. Figure 1 The plan view of the display panel is shown in the image;

[0020] Figure 3 This is an equivalent circuit diagram of a pixel according to an exemplary embodiment of the present disclosure;

[0021] Figure 4 This is a cross-sectional view showing the pixels of a display panel according to an exemplary embodiment of the present disclosure;

[0022] Figure 5A This is an enlarged plan view showing a display panel according to an exemplary embodiment of the present disclosure;

[0023] Figure 5B It is along in Figure 5A The cross-sectional view taken by line I-I' is shown in the figure;

[0024] Figure 6 This is a perspective view showing a display panel according to an exemplary embodiment of the present disclosure;

[0025] Figure 7 This is a plan view showing a connector according to an exemplary embodiment of the present disclosure;

[0026] Figure 8 This is a plan view showing a connector according to an exemplary embodiment of the present disclosure;

[0027] Figure 9 This is a plan view showing a connector according to an exemplary embodiment of the present disclosure;

[0028] Figure 10 This is a plan view showing a connector according to an exemplary embodiment of the present disclosure;

[0029] Figure 11 This is a plan view showing a connector according to an exemplary embodiment of the present disclosure; and

[0030] Figure 12 This is a plan view showing a connector according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0031] In this disclosure, it will be understood that when an element or layer is referred to as being "on", "connected to", or "bonded to" another element or layer, the element or layer may be directly on, directly connected to, or directly bonded to the other element or layer, or there may be intermediate elements or intermediate layers.

[0032] The same reference numerals always refer to the same elements. In the accompanying drawings, the thickness, scale, and dimensions of components are exaggerated in order to effectively describe the technical content.

[0033] As used herein, the term “and / or” can include any and all combinations of one or more of the relevant listed items.

[0034] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe different elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or part from another. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or part discussed below may be referred to as a second element, component, area, layer, or part. As used herein, unless the context clearly indicates otherwise, the singular forms “an,” “a,” and “the (described)” are also intended to include the plural forms.

[0035] For ease of description, spatial relative terms such as “below,” “under,” “down,” “above,” and “above” may be used here to describe the relationship of one element or feature as shown in the accompanying drawings to other elements or features(s).

[0036] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that, unless so explicitly defined herein, terms (such as those defined in a commonly used dictionary) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an ideal or overly formal sense.

[0037] It will also be understood that, when used in this specification, the terms "may include" and / or "comprising" indicate the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. This disclosure will be described in detail below with reference to the accompanying drawings.

[0038] Figure 1 This is a perspective view showing a display panel according to an exemplary embodiment of the present disclosure. Figure 2 This illustrates the process before the flexible circuit board is attached to the display pad area. Figure 1 The diagram shows a floor plan of the display panel. Figure 3 This is an equivalent circuit diagram of a pixel according to an exemplary embodiment of the present disclosure. Figure 4 This is a cross-sectional view showing the pixels of a display panel according to an exemplary embodiment of the present disclosure. Figure 5A This is an enlarged plan view showing a display panel according to an exemplary embodiment of the present disclosure. Figure 5B It is along in Figure 5A The cross-sectional view taken by line I-I' is shown in the figure.

[0039] Reference Figure 1 and Figure 2 The display device DD may include a display panel DP and a driver CM. In this exemplary embodiment, the driver CM may include a flexible circuit board FPCB, source circuit boards PCB1 and PCB2, a main circuit board MPCB, and connection boards CPCB1 and CPCB2.

[0040] Although not shown separately, the display device DD may also include housing members, and depending on the type of display panel DP, may also include a backlight unit.

[0041] The display panel DP can be a liquid crystal display panel, a plasma display panel, an electrophoretic display panel, a microelectromechanical system (MEMS) display panel, an electrowetting display panel, or an organic light-emitting display panel; however, it should not be subject to any particular restrictions.

[0042] The display panel DP may include a first display substrate 100 and a second display substrate 200. The second display substrate 200 may be disposed on the first display substrate 100. A grayscale display layer may be disposed between the first display substrate 100 and the second display substrate 200 to generate an image. The grayscale display layer may be a liquid crystal layer, an organic light-emitting layer, or an electrophoretic layer.

[0043] like Figure 1 As shown, the display panel DP can display an image via the display surface DP-IS. The display surface DP-IS can be substantially parallel to the plane defined by the first direction axis DR1 and the second direction axis DR2. The display surface DP-IS can include a display area DA and a non-display area NDA. The non-display area NDA can be positioned along the edge of the display surface DP-IS. The display area DA can be surrounded by the non-display area NDA.

[0044] Figure 1 The non-display area NDA surrounding the display area DA is shown; however, it should not be limited to or restricted by this, and the non-display area NDA may be set on only one side area adjacent to the driver CM.

[0045] The third direction axis DR3 can indicate the normal direction of the display surface DP-IS, that is, the thickness direction of the display panel DP. In this exemplary embodiment, the front (or upper) and rear (or lower) surfaces of each component can be distinguished from each other relative to the third direction axis DR3. However, the first direction axis DR1, the second direction axis DR2, and the third direction axis DR3 are merely exemplary. In the following, the first direction, the second direction, and the third direction can be indicated by the first direction axis DR1, the second direction axis DR2, and the third direction axis DR3, respectively, and can be assigned the same reference numerals as the first direction axis DR1, the second direction axis DR2, and the third direction axis DR3.

[0046] In exemplary embodiments of this disclosure, the display panel DP includes a flat display surface DP-IS; however, it should not be limited to or restricted by this. The display device DD may include a curved display surface or a three-dimensional display surface. A three-dimensional display surface may include multiple display areas facing different directions from each other.

[0047] One end of the flexible printed circuit board (FPCB) can be attached to the display panel (DP) using a conductive adhesive. The conductive adhesive may include anisotropic conductive film (ACF). Hereinafter, anisotropic conductive film (ACF) will be described as a conductive adhesive.

[0048] In this exemplary embodiment, the flexible circuit boards (FPCBs) can be arranged on the first direction DR1, spaced apart from each other. Each flexible circuit board (FPCB) can be connected to a corresponding pad (PD) on the display pad area PDA.

[0049] In this exemplary embodiment, the display pad area PDA is disposed on the first display substrate 100; however, this disclosure should not be limited to or restricted by this. According to another exemplary embodiment of this disclosure, the display pad area PDA may be disposed on the second display substrate 200.

[0050] Each flexible printed circuit board (FPCB) may include drive circuitry mounted thereon to drive the display panel (DP), such as a data drive circuit (DDC). The data drive circuitry (DDC) may be mounted on each FPCB using a chip-on-film (COF) method.

[0051] In addition, the number of data drive circuits (DDC) and flexible circuit boards (FPCB) can be varied depending on the resolution of the display panel (DP), the size of the display panel (DP), and the specifications of the data drive circuits (DDC).

[0052] The main circuit board (MPCB) may include a controller (CU) and multiple main lines that transmit signals generated by the controller (CU) to connection boards (CPCB1 and CPCB2).

[0053] The controller CU may include a timing controller and a power supply. The controller CU may receive control signals, image data, and external power from the display device DD. The control signals may include a vertical synchronization signal as a frame separation signal, a horizontal synchronization signal as a line separation signal, a data enable signal that indicates a data input period, and a master clock signal.

[0054] The timing controller generates gate control signals and data control signals. It outputs the gate control signals to the gate drive circuit (GDC), described later, and the data control signals to the data drive circuit (DDC). The timing controller also converts image data to a specification suitable for the data drive circuit (DDC) and outputs the converted image data to the DDC. The power supply utilizes external power to generate the power required for the operation of the display device (DD). Additionally, the power supply generates power supply voltages ELVSS and ELVDD to drive pixels (PX).

[0055] Figure 1 and Figure 2 The diagram illustrates a common line connected to the controller CU, a first main line EM-L connecting the common line to a first connection board CPCB1 to provide the power voltages ELVSS and ELVDD generated by the controller CU to the first connection board CPCB1, and a second main line EM-R connecting the common line to a second connection board CPCB2 to provide the power voltages ELVSS and ELVDD generated by the controller CU to the second connection board CPCB2. The first main line EM-L and the second main line EM-R can be connected to the controller CU via the common line. Therefore, the first main line EM-L and the second main line EM-R can have different lengths, IR-1 and IR-2. For example, the length of the first main line EM-L connected to the first connection board CPCB1 can be longer than the length of the second main line EM-R connected to the second connection board CPCB2.

[0056] Source circuit boards PCB1 and PCB2 can be connected to the other end of the flexible circuit board FPCB. Source circuit boards PCB1 and PCB2 may include insulating films and conductive lines disposed between the insulating films.

[0057] In this disclosure, the conductive lines of the source circuit boards PCB1 and PCB2 that receive power supply voltages ELVSS and ELVDD from the main circuit board MPCB can be defined as voltage lines. Figure 1 and Figure 2 As a representative example, a first voltage line EL-L disposed in a first source circuit board PCB1 and a second voltage line EL-R disposed in a second source circuit board PCB2 are shown.

[0058] One end of connecting boards CPCB1 and CPCB2 can be connected to source circuit boards PCB1 and PCB2, and the other end of connecting boards CPCB1 and CPCB2 can be connected to the main circuit board MPCB. Connecting boards CPCB1 and CPCB2 can provide signals from the controller CU of the main circuit board MPCB to source circuit boards PCB1 and PCB2. The shape and number of connecting boards CPCB1 and CPCB2 should not be particularly limited, as long as connecting boards CPCB1 and CPCB2 electrically connect the main circuit board and source circuit boards that are spaced apart from each other. For example, connecting boards CPCB1 and CPCB2 may also include source circuit boards (not shown) arranged on the first direction DR1 and spaced apart from each other, and connect the main circuit board MPCB to the source circuit boards (not shown). For example, a source circuit board adjacent to the first source circuit board PCB1 can be connected to the first source circuit board PCB1 through a connector SP disposed between the source circuit boards. In this case, the source circuit board adjacent to the first source circuit board PCB1 can receive the same signal as the signal transmitted from the main circuit board MPCB to the first source circuit board PCB1. In addition, a source circuit board adjacent to the second source circuit board PCB2 can be connected to the second source circuit board PCB2 through a connector SP disposed between the source circuit boards. In this case, the source circuit board adjacent to the second source circuit board PCB2 can receive the same signal as the signal transmitted from the main circuit board MPCB to the second source circuit board PCB2.

[0059] Alternatively, according to another exemplary embodiment, the connecting boards CPCB1 and CPCB2 can be omitted, and in this case, the main circuit board MPCB can directly contact the source circuit boards PCB1 and PCB2.

[0060] The connector SP can be disposed between source circuit boards PCB1 and PCB2, which are spaced apart from each other, and can electrically connect source circuit boards PCB1 and PCB2. In this disclosure, the connector SP can electrically connect the first voltage line EL-L, which is the closest to the second voltage line PCB2 among the voltage lines of the first source circuit board PCB1, and the second voltage line EL-R, which is the closest to the first source circuit board PCB1 among the voltage lines of the second source circuit board PCB2.

[0061] In this disclosure, the first voltage line EL-L may be the line most adjacent to the second source circuit board PCB2 among the voltage lines included in the first source circuit board PCB1, and the second voltage line EL-R may be the line most adjacent to the first source circuit board PCB1 among the voltage lines included in the second source circuit board PCB2.

[0062] In this disclosure, the first flexible circuit board FP-L may be the flexible circuit board most adjacent to the second source circuit board PCB2 in the flexible circuit board FPCB connected to the first source circuit board PCB1, and the second flexible circuit board FP-R may be the flexible circuit board most adjacent to the first source circuit board PCB1 in the flexible circuit board FPCB connected to the second source circuit board PCB2.

[0063] Reference Figure 5A and Figure 5B The connector SP according to this disclosure may include a substrate film SUB and a conductive conductor SR. The conductor SR may be disposed in the substrate film SUB and may have a shape in which at least a portion of the conductor SR is exposed. Figure 5B The diagram shows a shape in which one surface of the conductor SR is fully exposed; however, the shape of the conductor SR should not be limited to or restricted by this. That is, the conductor SR may have a shape in which some areas of the conductor SR that overlap with the first voltage line EL-L and the second voltage line EL-R are exposed and connected to the first voltage line EL-L and the second voltage line EL-R.

[0064] The first source circuit board PCB1 may include films BF1-L and BF2-L as well as voltage lines. Figure 5B A first voltage line EL-L is shown as a representative example of a voltage line. The second source circuit board PCB2 may include films BF1-R and BF2-R, as well as the voltage line. Figure 5B The second voltage line EL-R is shown as a representative example of a voltage line.

[0065] The first voltage line EL-L can be exposed through a contact hole formed in the second membrane BF2-L. The portion of the first voltage line EL-L exposed by the second membrane BF2-L can be connected to one end of the conductor SR. The second voltage line EL-R can be exposed through a contact hole formed in the second membrane BF2-R. The portion of the second voltage line EL-R exposed by the second membrane BF2-R can be connected to the other end of the conductor SR. Therefore, the connector SP can electrically connect the adjacent voltage lines EL-L and EL-R among the voltage lines of the first source circuit board PCB1 and the second source circuit board PCB2.

[0066] The power supply voltages ELVDD and ELVSS can be transmitted from the controller CU of the main circuit board MPCB to the first flexible circuit board FP-L through the first main line EM-L, the first connecting board CPCB1 and the first voltage line EL-L.

[0067] In addition, the power supply voltages ELVDD and ELVSS can be transmitted from the controller CU of the main circuit board MPCB to the second flexible circuit board FP-R via the second main line EM-R, the second connecting board CPCB2, and the second voltage line EL-R.

[0068] In this scenario, when power supply voltages ELVDD and ELVSS, generated by the controller CU and having the same voltage level, are transmitted through the first main line EM-L and the second main line EM-R, which have different lengths IR-1 and IR-2, different voltage drops (IR drops) will occur in the first main line EM-L and the second main line EM-R due to their different resistances. Consequently, power supply voltages ELVDD and ELVSS with different voltage levels are supplied to the first flexible circuit board FP-L and the second flexible circuit board FP-R, respectively. Therefore, heat generation will occur on either the first flexible circuit board FP-L or the second flexible circuit board FP-R.

[0069] According to this disclosure, a connector SP can be provided to electrically connect the adjacent lines of voltage lines included in the first source circuit board PCB1 and the voltage lines included in the second source circuit board PCB2. The connector SP can form a path that allows power supply voltages ELVDD and ELVSS, which have different voltage levels due to different voltage drops, to not be directly transmitted to the first flexible circuit board FP-L and the second flexible circuit board FP-R, and compensates for the different voltage levels of power supply voltages ELVDD and ELVSS. Therefore, overheating can be prevented on either the first flexible circuit board FP-L or the second flexible circuit board FP-R.

[0070] Figure 2 The diagram illustrates the arrangement of signal lines GL1 to GLn, DL1 to DLm, and PL-D, as well as pixels PX11 to PXnm, in a planar view. Signal lines GL1 to GLn, DL1 to DLm, and PL-D may include multiple gate lines GL1 to GLn, multiple data lines DL1 to DLm, and auxiliary signal line PL-D.

[0071] Gate lines GL1 to GLn may extend in a first direction DR1 and may be arranged in a second direction DR2. Data lines DL1 to DLm may intersect with gate lines GL1 to GLn while being insulated from them. Data lines DL1 to DLm may extend in the second direction DR2 and may be arranged in the first direction DR1.

[0072] Gate lines GL1 to GLn and data lines DL1 to DLm can be configured to overlap with the display area DA. Auxiliary signal lines PL-D can be configured to overlap with the non-display area NDA and can be connected to gate lines GL1 to GLn and data lines DL1 to DLm.

[0073] The auxiliary signal line PL-D, connected to the data lines DL1 to DLm, can be disposed on a different layer than the layer on which the data lines DL1 to DLm are disposed. The data lines DL1 to DLm can be electrically connected to corresponding signal lines within the auxiliary signal line PL-D via contact holes CH. The contact holes CH can be defined to pass through at least one insulating layer disposed between the data lines DL1 to DLm and the auxiliary signal line PL-D. As a representative example, Figure 2 Two contact holes CH are shown.

[0074] According to another exemplary embodiment of this disclosure, the contact hole CH can be omitted. Data lines DL1 to DLm and auxiliary signal lines PL-D can be disposed on the same layer. In this case, the data lines DL1 to DLm and the auxiliary signal lines PL-D that are connected to each other can be a single signal line. Alternatively, the data lines and auxiliary signal lines that are connected to each other can be different parts of this single signal line.

[0075] Each of pixels PX11 to PXnm can be connected to a corresponding gate line among gate lines GL1 to GLn and a corresponding data line among data lines DL1 to DLm. Each of pixels PX11 to PXnm may include pixel driving circuitry and a display element.

[0076] Figure 2 The diagram shows pixels PX11 to PXnm arranged in a matrix; however, the arrangement of pixels PX11 to PXnm should not be limited to or restricted by this arrangement. That is, pixels PX11 to PXnm can be arranged in a pentile or diamond pattern.

[0077] like Figure 2 As shown, pads (PDs) can be arranged in the display pad area (PDA) to be spaced apart from each other in the first direction (DR1). Pads (PDs) can be connected to one end of the flexible circuit board (FPCB).

[0078] The gate drive circuit (GDC) can be integrated into the display panel (DP) using either silicon oxide gate driver (OSG) or amorphous silicon gate driver (ASG) technology.

[0079] As a representative example Figure 3 An equivalent circuit diagram of a pixel PX is shown, which is connected to a gate line GL among gate lines GL1 to GLn, a data line DL among data lines DL1 to DLm, and a power line PL.

[0080] Pixel PX may include a first transistor T1, a second transistor T2, a capacitor Cst, and an organic light-emitting element OD. The first transistor T1 may include an input electrode and an output electrode. The first transistor T1 may output a data signal applied to the data line DL in response to a gate signal applied to the gate line GL.

[0081] The capacitor Cst may include a first capacitor electrode connected to the first transistor T1 and a second capacitor electrode receiving a first power supply voltage ELVDD. The capacitor Cst may be charged with a charge corresponding to the difference between the voltage corresponding to the data signal from the first transistor T1 and the first power supply voltage ELVDD.

[0082] The second transistor T2 may include a control electrode connected to the output electrode of the first transistor T1 and the first capacitor electrode of the capacitor Cst, an input electrode receiving a first power supply voltage ELVDD supplied via the power line PL, and an output electrode. The output electrode of the second transistor T2 may be connected to an organic light-emitting element OD.

[0083] The second transistor T2 can control the drive current flowing through the organic light-emitting element OD in response to the amount of charge charged in the capacitor Cst. The on-time of the second transistor T2 can be determined by the amount of charge charged in the capacitor Cst. The output electrode of the second transistor T2 can apply a voltage with a voltage level lower than the first power supply voltage ELVDD to the organic light-emitting element OD.

[0084] The organic light-emitting element (OD) may include a first electrode connected to the second transistor T2 and a second electrode receiving a second power supply voltage ELVSS. The organic light-emitting element (OD) may include a light-emitting pattern disposed between the first electrode and the second electrode.

[0085] The organic light-emitting element (OD) can emit light during the on-time of the second transistor T2. The light generated by the organic light-emitting element OD can have a color determined by the material forming the light-emitting pattern. For example, the color of the light generated by the organic light-emitting element OD can be one of red, green, and blue.

[0086] Figure 4 This is a cross-sectional view corresponding to the pixels PX of the display panel DP. (Refer to...) Figure 4 A display panel (DP) can include multiple insulating layers, semiconductor patterns, conductive patterns, and signal lines. The insulating layers, semiconductor layers, and conductive layers can be formed through coating or deposition processes. Then, the insulating layers, semiconductor layers, and conductive layers can be selectively patterned using photolithography. This allows the formation of insulating layers, semiconductor patterns, conductive patterns, and signal lines.

[0087] The substrate layer BL may include a synthetic resin layer. The synthetic resin layer may include a thermosetting resin. The substrate layer BL may have a multilayer structure. For example, the substrate layer BL may have a three-layer structure consisting of a synthetic resin layer, an adhesive layer, and a synthetic resin layer. Specifically, the synthetic resin layer may be a polyimide resin layer; however, the materials used for the synthetic resin layer should not be particularly limited. The synthetic resin layer may include at least one of acrylic resins, methacrylic resins, polyisoprene, vinyl resins, epoxy resins, polyurethane resins, cellulose resins, siloxane resins, polyamide resins, and perylene resins. The substrate layer BL may include a glass substrate, a metal substrate, or an organic / inorganic composite substrate.

[0088] At least one inorganic layer may be formed on the upper surface of the substrate layer BL. The inorganic layer may include at least one of alumina, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. The inorganic layer may be formed in multiple layers. The inorganic layer may form a barrier layer and / or a buffer layer. In this exemplary embodiment, the display panel DP may include a buffer layer BFL.

[0089] The buffer layer (BFL) can increase the adhesion between the substrate layer (BL) and the semiconductor pattern. The buffer layer (BFL) may include a silicon oxide layer and a silicon nitride layer, and the silicon oxide layer and silicon nitride layer may be stacked alternately on top of each other.

[0090] Semiconductor patterns can be disposed on the buffer layer BFL. Semiconductor patterns may include polycrystalline silicon, however, they should not be limited to or restricted by this. Semiconductor patterns may also include amorphous silicon or metal oxides.

[0091] Figure 4 Only a portion of the semiconductor pattern is shown in the planar view; however, the semiconductor pattern can also be disposed in other areas of the pixel PX. The semiconductor pattern can be arranged on the pixel PX according to specific rules. The semiconductor pattern can have different electrical properties depending on the doping level. The semiconductor pattern can include heavily doped regions and undoped regions. Heavily doped regions can be doped with N-type or P-type dopants. A P-type transistor can include a heavily doped region doped with P-type dopants.

[0092] The source S1, active region A1, and drain D1 of the first transistor T1 can be formed from a semiconductor pattern, and the source S2, active region A2, and drain D2 of the second transistor T2 can be formed from a semiconductor pattern. The sources S1 and S2 and the drains D1 and D2 can extend from the active regions A1 and A2 in opposite directions to each other.

[0093] A first insulating layer 10 may be disposed on a buffer layer BFL. The first insulating layer 10 may overlap with the pixel PX and may cover a semiconductor pattern. The first insulating layer 10 may be an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. In this exemplary embodiment, the first insulating layer 10 may have a single-layer structure of silicon oxide. Not only the first insulating layer 10, but also the insulating layers described later, may be inorganic layers and / or organic layers, and may have a single-layer or multi-layer structure. Inorganic layers may include at least one of the materials described above.

[0094] Gates G1 and G2 can be disposed on the first insulating layer 10. Gates G1 and G2 can be part of a metal pattern. Gates G1 and G2 can overlap with active regions A1 and A2, respectively. In the process of doping semiconductor patterns, gates G1 and G2 can be used as masks.

[0095] The second insulating layer 20 may be disposed on the first insulating layer 10 and may cover gates G1 and G2. The second insulating layer 20 may overlap with the pixel PX in a common manner. The second insulating layer 20 may be an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure. In this exemplary embodiment, the second insulating layer 20 may have a single-layer structure of silicon oxide layer.

[0096] The upper electrode UE can be disposed on the second insulating layer 20. The upper electrode UE can overlap with the gate G2 of the second transistor T2. The upper electrode UE can be part of a metal pattern. A portion of the gate G2 and the upper electrode UE overlapping that portion of the gate G2 can define a capacitor Cst. According to another exemplary embodiment, the upper electrode UE can be omitted.

[0097] The third insulating layer 30 may be disposed on the second insulating layer 20 and may cover the upper electrode UE. In this exemplary embodiment, the third insulating layer 30 may have a single-layer structure of silicon oxide. The first connection electrode CNE1 may be disposed on the third insulating layer 30. The first connection electrode CNE1 may be connected to the connection signal line SCL through a contact hole CNT-1 defined through the first insulating layer 10, the second insulating layer 20 and the third insulating layer 30. The connection signal line SCL may include the drain D2 of the second transistor T2, gate lines GL1 to GLn, data lines DL1 to DLm or power line PL.

[0098] A fourth insulating layer 40 may be disposed on the third insulating layer 30 to cover the first connecting electrode CNE1. The fourth insulating layer 40 may have a single-layer structure of silicon oxide. A fifth insulating layer 50 may be disposed on the fourth insulating layer 40. The fifth insulating layer 50 may be an organic layer. A second connecting electrode CNE2 may be disposed on the fifth insulating layer 50. The second connecting electrode CNE2 may be connected to the first connecting electrode CNE1 through a contact hole CNT-2 defined through the fourth insulating layer 40 and the fifth insulating layer 50.

[0099] A sixth insulating layer 60 may be disposed on the fifth insulating layer 50 and may cover the second connecting electrode CNE2. The sixth insulating layer 60 may be an organic layer. A first electrode AE ​​may be disposed on the sixth insulating layer 60. The first electrode AE ​​may be connected to the second connecting electrode CNE2 through a contact hole CNT-3 defined through the sixth insulating layer 60. An opening OP may be defined by a pixel defining layer PDL. At least a portion of the first electrode AE ​​may be exposed through the opening OP of the pixel defining layer PDL.

[0100] The display area DP-DA may include a light-emitting area PXA and a non-light-emitting area NPXA adjacent to the light-emitting area PXA. The non-light-emitting area NPXA may surround the light-emitting area PXA. In this exemplary embodiment, the light-emitting area PXA may be defined as the portion corresponding to the first electrode AE ​​exposed through the opening OP.

[0101] The hole control layer (HCL) can be commonly disposed in the emitting region PXA and the non-emitting region NPXA. The HCL may include a hole transport layer and may also include a hole injection layer. The emitting layer (EML) can be disposed on the HCL. The EML can be disposed in the region corresponding to the opening (OP). That is, the EML can be formed in each pixel PX.

[0102] An electronic control layer (ECL) can be disposed on the light-emitting layer (EML). The ECL may include an electron transport layer and may also include an electron injection layer. A hole control layer (HCL) and the ECL can be commonly formed in multiple pixels (PX) using an aperture mask. A second electrode (CE) can be disposed on the ECL. The second electrode (CE) may have a monolithic shape and be commonly disposed in the pixels (PX).

[0103] The upper insulating layer (TFL) may be disposed on the second electrode (CE). The upper insulating layer (TFL) may include multiple thin layers. The upper insulating layer (TFL) may include a capping layer and a thin-film encapsulation layer. The thin-film encapsulation layer may include multiple inorganic layers and an organic layer disposed between the inorganic layers. The inorganic layers may be silicon nitride layers, silicon oxynitride layers, or silicon oxide layers. The organic layers may include acrylic organic layers; however, they should not be limited to or restricted by this.

[0104] Inorganic layers can protect organic light-emitting elements (ODs) (such as organic light-emitting diodes OLEDs) from moisture / oxygen, while organic layers can protect organic light-emitting elements (ODs) (such as organic light-emitting diodes OLEDs) from foreign substances such as dust particles.

[0105] A capping layer can be disposed on and in contact with the second electrode CE. The capping layer may include an organic material. The capping layer can protect the second electrode CE from subsequent processes (e.g., sputtering processes) and can improve the luminous efficiency of the organic light-emitting element OD (e.g., organic light-emitting diode OLED).

[0106] Figure 6 This is a perspective view showing a display panel according to an exemplary embodiment of the present disclosure. Figure 6 In the figures, the same reference numerals indicate Figures 1 to 5B The same elements are used in the same way, and therefore, detailed descriptions of the same elements will be omitted.

[0107] According to this exemplary embodiment, the driver CM-1 may include a flexible circuit board FPCB connected to a display panel DP, source circuit boards PCB-1 and PCB-2 connected to the flexible circuit board FPCB, connecting boards CPCB1 and CPCB2 connected to the source circuit boards PCB-1 and PCB-2, a main circuit board MPCB connected to the connecting boards CPCB1 and CPCB2, and a connector SP connecting the source circuit boards PCB-1 and PCB-2 that are adjacent to each other.

[0108] In this exemplary embodiment, the driver CM-1 may further include a first connector CNT-L connecting adjacent first daughter boards PC-L1 and PC-L2 in the first source circuit board PCB-1 and a second connector CNT-R connecting adjacent second daughter boards PC-R1 and PC-R2 in the second source circuit board PCB-2.

[0109] In this exemplary embodiment, the first source circuit board PCB-1 may include first daughter boards PC-L1 and PC-L2. The first daughter boards PC-L1 and PC-L2 can receive the first signal generated by the controller CU equally through the main line EL-A.

[0110] The second source circuit board PCB-2 may include second daughter boards PC-R1 and PC-R2. Second daughter boards PC-R1 and PC-R2 can equally receive the second signal generated by the controller CU via the main line EL-A. The first signal and the second signal applied to the first source circuit board PCB-1 and the second source circuit board PCB-2 respectively may be the same as or different from each other.

[0111] According to this exemplary embodiment, first daughter boards PC-L1 and PC-L2 may be arranged on a first direction DR1 and spaced apart from each other. A first connector CNT-L may electrically connect the spaced-apart first daughter boards PC-L1 and PC-L2. The connection method between the first connector CNT-L and the first daughter boards PC-L1 and PC-L2 should not be particularly limited, as long as the first daughter boards PC-L1 and PC-L2 are electrically connected to each other.

[0112] Additionally, the second daughter boards PC-R1 and PC-R2 can be arranged spaced apart from each other on the first direction DR1. The second connector CNT-R can electrically connect the spaced-apart second daughter boards PC-R1 and PC-R2. The connection method between the second connector CNT-R and the second daughter boards PC-R1 and PC-R2 should not be particularly limited, as long as the second daughter boards PC-R1 and PC-R2 are electrically connected to each other. Figure 6 In this circuit, the first source circuit board PCB-1 includes two first daughter boards PC-L1 and PC-L2, and the second source circuit board PCB-2 includes two second daughter boards PC-R1 and PC-R2; however, they should not be limited to or restricted by this. The number of daughter boards included in the source circuit boards PCB-1 and PCB-2, as well as the number of connectors connecting the daughter boards, can vary depending on the resolution of the display panel DP, the size of the display panel DP, and the specifications of the data drive circuit DDC (see reference). Figure 5A ).

[0113] Figure 7 This is a plan view showing a connector according to an exemplary embodiment of the present disclosure. Figure 8 This is a plan view showing a connector according to an exemplary embodiment of the present disclosure. Figure 9 This is a plan view showing a connector according to an exemplary embodiment of the present disclosure. Figure 10 This is a plan view showing a connector according to an exemplary embodiment of the present disclosure. Figure 11 This is a plan view showing a connector according to an exemplary embodiment of the present disclosure. Figure 12 This is a plan view illustrating a connector according to an exemplary embodiment of the present disclosure. In the following, it will be... Figures 7 to 12 The description of the connector described herein can be applied to the reference. Figures 1 to 6 The connector is described. Figures 7 to 12 In the figures, the same / similar reference numerals indicate Figures 1 to 6 The same / similar elements will be referenced, and therefore, detailed descriptions of identical elements will be omitted. In the following text, references will be made to... Figures 7 to 11 The type and material of the substrate film described should not be particularly limited, as long as it is a substrate layer on which a conductive material can be disposed. Additionally, refer to... Figures 7 to 11 One end of the described connector can be connected to the first voltage line EL-L (see reference). Figure 1 And the other end of the connector can be connected to the second voltage line EL-R (see reference). Figure 1 ).

[0114] Reference Figure 7 According to this exemplary embodiment, the connector SP-1 may include a substrate film SUB-1, a conductive connection portion SR-1, and a resistor portion RT-1. The resistor portion RT-1 may have a higher resistance than the connection portion SR-1. The resistor portion RT-1 should not be particularly limited, as long as it is implemented by a passive element (resistor, capacitor, inductor) or includes a material different from the connection portion SR-1 and having a higher resistance than the connection portion SR-1.

[0115] exist Figure 7 In this design, the connection portion SR-1 and the resistor portion RT-1 are exposed on the rear surface SP-B of the connector SP-1; however, they should not be limited to or restricted by this. That is, only the portion of the connection portion SR-1 that connects to the source circuit boards PCB1 and PCB2 may be exposed, and the other portions of the connection portion SR-1 and the resistor portion RT-1 may be provided to be covered by an insulating layer.

[0116] Reference Figure 8 The connector SP-2 according to this exemplary embodiment may include a substrate film SUB-2, a conductive connection portion SR-2, and a resistor portion RT-2.

[0117] The connecting portion SR-2 may include a first connecting portion SR1, a second connecting portion SR2, and a third connecting portion SR3, which extend in one direction and are arranged in a direction intersecting the one direction to be spaced apart from each other.

[0118] The resistor section RT-2 may have a relatively higher resistance than the connection section SR-2. The resistor section RT-2 should not be particularly limited, as long as it is implemented by a passive component or includes a material that is different from the connection section SR-2 and has a higher resistance than the connection section SR-2.

[0119] In this exemplary embodiment, the resistor portion RT-2 may include a plurality of resistors R1 and R2 connected to at least one of the first connection portion SR1, the second connection portion SR2, and the third connection portion SR3. That is, the resistor portion RT-2 may be disposed at at least one of the plurality of connection portions (e.g., the first connection portion SR1, the second connection portion SR2, and the third connection portion SR3).

[0120] Reference Figure 9The connector SP-3 according to this exemplary embodiment may include a first sub-connection portion SR-L, a second sub-connection portion SR-R, and a resistor portion SR-C, all of which are conductive.

[0121] In this exemplary embodiment, the first sub-connection portion SR-L, the second sub-connection portion SR-R, and the resistor portion SR-C may comprise the same material. The resistor portion SR-C may be disposed between the first sub-connection portion SR-L and the second sub-connection portion SR-R. The first sub-connection portion SR-L, the resistor portion SR-C, and the second sub-connection portion SR-R may be integrally disposed with each other; however, for ease of explanation, they will be described separately.

[0122] The resistor portion SR-C may include a predetermined pattern. For example, the resistor portion SR-C may include a pattern with a predetermined curve. Therefore, although the first sub-connection portion SR-L, the second sub-connection portion SR-R, and the resistor portion SR-C are formed of the same material, the resistor portion SR-C with the predetermined pattern may have a relatively longer length in the allocated region than the lengths of the first sub-connection portion SR-L and the second sub-connection portion SR-R, and thus, the resistor portion SR-C can be used as a resistor.

[0123] Reference Figure 10 The connector SP-4 according to this exemplary embodiment may include a first sub-connection portion SR-L, a second sub-connection portion SR-R, and a resistor portion SR-C, all of which are conductive.

[0124] In this exemplary embodiment, the first sub-connection portion SR-L, the second sub-connection portion SR-R, and the resistor portion SR-C may comprise the same material. The resistor portion SR-C may be disposed between the first sub-connection portion SR-L and the second sub-connection portion SR-R. The first sub-connection portion SR-L, the resistor portion SR-C, and the second sub-connection portion SR-R may be integrally disposed with each other; however, for ease of explanation, they will be described separately.

[0125] The resistor portion SR-C may include a predetermined pattern. For example, the resistor portion SR-C may include a pattern with a zigzag shape. Therefore, although the first sub-connection portion SR-L, the second sub-connection portion SR-R, and the resistor portion SR-C are formed of the same material, the resistor portion SR-C with the predetermined pattern may have a relatively longer length in the allocated area than the length of the first sub-connection portion SR-L and the second sub-connection portion SR-R, and therefore, the resistor portion SR-C can be used as a resistor.

[0126] Reference Figure 11The connector SP-5 according to this exemplary embodiment may include a first sub-connection portion SR-L, a second sub-connection portion SR-R, and a resistor portion RT-5, all of which are conductive.

[0127] In this exemplary embodiment, the first sub-connection portion SR-L, the second sub-connection portion SR-R, and the resistor portion RT-5 may comprise materials different from each other. The resistor portion RT-5 may be disposed between the first sub-connection portion SR-L and the second sub-connection portion SR-R.

[0128] In this exemplary embodiment, the resistor portion RT-5 may include a material having a relatively higher resistance than the first sub-connection portion SR-L and the second sub-connection portion SR-R. For example, when the first sub-connection portion SR-L and the second sub-connection portion SR-R are made of metallic material, the resistor portion RT-5 may include a metallic material having a relatively higher resistance than the first sub-connection portion SR-L and the second sub-connection portion SR-R. Therefore, the resistor portion RT-5 can function as a resistor between the first sub-connection portion SR-L and the second sub-connection portion SR-R.

[0129] Reference Figure 12 The SP-6 connector can have the same characteristics as... Figures 7 to 11 Connectors SP-1, SP-2, SP-3, SP-4, and SP-5 have different conductivity and can be provided in the form of wiring with the substrate film removed. The shape and number of connectors SP-6 should not be particularly limited, as long as connectors SP-6 are provided in the form of wiring.

[0130] Although exemplary embodiments of this disclosure have been described, it should be understood that this disclosure is not limited to these exemplary embodiments, but rather that various changes and modifications can be made by those skilled in the art within the spirit and scope of this disclosure as claimed below.

[0131] Therefore, the subject matter disclosed herein should not be limited to any single embodiment described herein, and the scope of the inventive concept should be determined in accordance with the appended claims.

Claims

1. A display device, wherein, The display device includes: a display panel including a plurality of pixels and a plurality of display pads connected to the plurality of pixels and arranged apart from each other in a first direction; and a driver applying a power voltage to the plurality of pixels, the driver including: a plurality of flexible circuit boards connected to the plurality of display pads; a first source circuit board including a plurality of voltage lines connected to a first flexible circuit board among the plurality of flexible circuit boards; a second source circuit board arranged in the first direction apart from the first source circuit board and including a plurality of voltage lines connected to a second flexible circuit board among the plurality of flexible circuit boards; a main circuit board including a controller generating the power voltage, a first main line connecting the controller to the first source circuit board, and a second main line connecting the controller to the second source circuit board; and a connector electrically connected to one of the plurality of voltage lines of the first source circuit board and one of the plurality of voltage lines of the second source circuit board most adjacent to the one of the plurality of voltage lines of the first source circuit board, wherein the first main line has a length different from a length of the second main line.

2. The display device according to claim 1, wherein The connector includes: a first sub-connection part connected to the one of the plurality of voltage lines provided on the first source circuit board; a second sub-connection part connected to the one of the plurality of voltage lines most adjacent to the one of the plurality of voltage lines of the first source circuit board provided on the second source circuit board; and a resistor part provided between the first sub-connection part and the second sub-connection part and having a relatively higher resistance than the first sub-connection part and the second sub-connection part.

3. The display device of claim 2, wherein, The resistor part includes the same material as the first sub-connection part and the second sub-connection part.

4. The display device according to claim 3, wherein The resistor part includes a predetermined pattern having a curved shape.

5. The display device according to claim 3, wherein The resistor part includes a pattern having a zigzag shape.

6. The display device according to claim 2, wherein The resistor part includes a different material from the first sub-connection part and the second sub-connection part.

7. The display device according to claim 1, wherein The connector includes: a plurality of connection parts extending in the first direction and arranged apart from each other in a second direction crossing the first direction; and a resistor part provided at at least one of the plurality of connection parts.

8. The display device according to claim 1, wherein The driver further includes: a first connection plate connecting the main circuit board to the first source circuit board; and a second connection plate connecting the main circuit board to the second source circuit board.

9. The display device of claim 8, wherein, The first main line is connected to the one of the plurality of voltage lines of the first source circuit board through the first connection plate, and the second main line is connected to the one of the plurality of voltage lines of the second source circuit board most adjacent to the one of the plurality of voltage lines of the first source circuit board through the second connection plate.

10. The display device according to claim 1, wherein The first source circuit boards and the second source circuit boards are each provided as a plurality, and the driver further includes connectors connected between adjacent first source circuit boards and between adjacent second source circuit boards.

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