Static random access memory cell and semiconductor device structure

Abstract

A static random access memory (SRAM) cell of the present disclosure includes a first pull-down device, a second pull-down device, a first pass gate device, and a second pass gate device disposed in a first p-well on a substrate; a third pull-down device, a fourth pull-down device, a third pass gate device, and a fourth pass gate device disposed in a second p-well on the substrate; a first pull-up device and a second pull-up device disposed in an n-well disposed between the first p-well and the second p-well; and a first landing pad between the second pull-down device and the first pull-up device. The first landing pad is electrically coupled to a gate structure of the second pass gate device by way of a first gate via.

Description

Technical Field

[0001] This disclosure relates to a static random access memory (SRAM) cell, and more particularly to a static random access memory cell having orthogonal metal lines. Background Technology

[0002] The semiconductor industry has experienced rapid growth. Technological advancements in semiconductor materials and design have resulted in several generations of semiconductor devices, each with smaller and more complex circuits than the previous generation. In the development of integrated circuits (ICs), functional density (e.g., the number of interconnects per unit chip area) typically increases, while geometric dimensions (e.g., the smallest components (or lines) that can be produced using manufacturing processes) shrink. This miniaturization process usually benefits by increasing production efficiency and reducing associated costs. However, these advancements have also indeed increased the complexity of semiconductor device processes and manufacturing.

[0003] In deep sub-micron integrated circuit technology, embedded static random access memory (SRAM) devices have become popular memory cells in high-speed communications, image processing, and system-on-chip (SoC) products. For example, dual-port (DP) SRAM devices allow parallel operation, such as 1R (1 read) 1W (1 write) and 2R (2 reads) or 2W (2 writes) in a single cycle, thus offering higher bandwidth than single-port SRAM. In advanced technologies with reduced feature sizes and increased package density, low load and high speed of the cell structure are crucial elements for embedded memory and SoC products. Dual-port SRAM cells can have complex metal routing, which can pose challenges for routing setup and lithography process windows. Therefore, while current dual-port SRAM cells are generally sufficient for their intended purpose, they are not satisfactory in all aspects. Summary of the Invention

[0004] This disclosure provides an SRAM cell. The SRAM cell includes a first pull-down device (PD-1), a second pull-down device (PD-2), a first transmission gate device (PG-1), and a second transmission gate device (PG-2), disposed in a first p-well on a substrate, wherein the active regions of the second transmission gate device (PG-2) and the second pull-down device (PD-2) are aligned along a first direction; a third pull-down device (PD-3), a fourth pull-down device (PD-4), a third transmission gate device (PG-3), and a fourth transmission gate device (PG-4) are disposed in a second p-well on the substrate, wherein the third… The active regions of the transmission gate device (PG-3) and the aforementioned third pull-down device (PD-3) are aligned along a first direction; a first pull-up device (PU-1) and a second pull-up device (PU-2) are disposed in an n-well disposed between the first p-well and the second p-well, wherein the active region of the first pull-up device (PU-1) extends along the first direction; and a first landing pad is disposed between the second pull-down device (PD-2) and the first pull-up device (PU-1), wherein the first landing pad is electrically coupled to a gate structure of the second transmission gate device (PG-2) via a path of a first gate via.

[0005] This disclosure provides an SRAM cell. The SRAM cell may include a first pull-down device (PD-1), a second pull-down device (PD-2), a first transmission gate device (PG-1), and a second transmission gate device (PG-2), disposed in a first p-well on a substrate; a third pull-down device (PD-3), a fourth pull-down device (PD-4), a third transmission gate device (PG-3), and a fourth transmission gate device (PG-4), disposed in a second p-well on the substrate; and a first pull-up device (PU-1) and a second pull-up device (PU-2), disposed in an n-well between the first p-well and the second p-well. The first pull-down device (PD-1), the second pull-down device (PD-2), and the first pull-up device (PU-1) share a gate structure extending along a first direction. The drain of the first pull-down device (PD-1), the drain of the second pull-down device (PD-2), and the drain of the first pull-up device (PU-1) are electrically coupled to a first long contact.

[0006] This disclosure provides an SRAM cell. The SRAM cell includes a first pull-down device (PD-1), a second pull-down device (PD-2), a first transmission gate device (PG-1), and a second transmission gate device (PG-2), disposed in a first p-well on a substrate; a third pull-down device (PD-3), a fourth pull-down device (PD-4), a third transmission gate device (PG-3), and a fourth transmission gate device (PG-4), disposed in a second p-well on the substrate; and a first pull-up device (PU-1) and a second pull-up device (PU-2), disposed in an n-well between the first p-well and the second p-well. The first transmission gate device (PG-1) and the first pull-down device (PD-1) share a first active region extending along a first direction. The second transmission gate device (PG-2) and the second pull-down device (PD-2) share a second active region extending along the first direction. The third active region of the first pull-up device (PU-1) extends along the first direction. The first active region and the second active region are separated from each other by a first interval. The second active region and the third active region are separated from each other by a second interval that is greater than the first interval. Attached Figure Description

[0007] The features disclosed herein will be better understood from the following embodiments and accompanying drawings. It should be emphasized that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of illustration.

[0008] Figure 1 This is a schematic circuit diagram of a dual-ended static random access memory (DP SRAM) cell constructed according to various configurations of this disclosure.

[0009] Figure 2 This is an alternative schematic circuit diagram of a dual-ended static random access memory (DP SRAM) cell constructed according to various configurations of this disclosure.

[0010] Figure 3 This is a schematic diagram of a dual-ended static random access memory (DP SRAM) array constructed according to various configurations of this disclosure.

[0011] Figure 4A This is a schematic layout of a dual-ended static random access memory (DP SRAM) cell, as shown in various forms according to this disclosure.

[0012] Figure 4B As shown in the various forms disclosed herein, Figure 4A A simplified schematic layout of the dual-ended static random access memory (DP SRAM) cells in the image.

[0013] Figure 5This is a schematic diagram of various metal layers of a dual-ended static random access memory (DP SRAM) cell as seen along the direction of the active region, according to various embodiments of this disclosure.

[0014] Figure 6 This is a schematic diagram of various metal layers of a dual-ended static random access memory (DP SRAM) cell as seen along the direction of the gate structure, according to various configurations of an embodiment of this disclosure.

[0015] Figure 7 This is an embodiment of the word line of a dual-ended static random access memory (DP SRAM) cell, as shown in various forms according to this disclosure.

[0016] Figure 8 This is an embodiment of the word line of a dual-ended static random access memory (DP SRAM) cell, as shown in various forms according to this disclosure.

[0017] Figure 9 This is an embodiment of the word line of a dual-ended static random access memory (DP SRAM) cell, as shown in various forms according to this disclosure.

[0018] The reference numerals in the attached figures are explained as follows:

[0019] 100: DP SRAM cell

[0020] 101: First Inverter

[0021] 102: Second inverter

[0022] 104: First transmission gate device

[0023] 106: Second transmission gate device

[0024] 108: Third transmission gate device

[0025] 110: Fourth transmission gate device

[0026] 112: First character line

[0027] 114: Second character line

[0028] 122: First Yuan Line

[0029] 124: First complementary bit line

[0030] 132: Second bit line

[0031] 134: Second complementary bit line

[0032] 142: First pull-up device

[0033] 144: Second pull-up device

[0034] 146: First pull-down device

[0035] 148: Second pull-down device

[0036] 150: Third pull-down device

[0037] 152: Fourth pull-down device

[0038] 10: DP SRAM device

[0039] 12: SRAM array

[0040] 14: First character line (WL-A) driver / selector

[0041] 16: Second character line (WL-B) driver / selector

[0042] 18: First Y-multiplexer (MUX) and sensing amplifier

[0043] 20: Second Y-multiplexer (MUX) and sensing amplifier

[0044] 200: DP SRAM cell

[0045] 202: Substrate

[0046] 204-1: First Active Zone

[0047] 204-2: Second Active Zone

[0048] 204-3: Third Active Zone

[0049] 204-4: Fourth Active Zone

[0050] 204-5: Fifth Active Zone

[0051] 204-6: The Sixth Active Zone

[0052] 206: First pull-up device

[0053] 208: Second pull-up device

[0054] 210: First transmission gate device

[0055] 212: Second transmission gate device

[0056] 214: Third transmission gate device

[0057] 216: Fourth transmission gate device

[0058] 218: First pull-down device

[0059] 220: Second pull-down device

[0060] 222: Third pull-down device

[0061] 224: Fourth pull-down device

[0062] 226-1: The First WL-A Landing Mat

[0063] 226-2: Second WL-A Landing Pad

[0064] 228-1: The First WL-B Landing Pad

[0065] 228-2: Second WL-B landing pad

[0066] 230-1: First Yuan Line

[0067] 230-2: Second bit line

[0068] 232-1: First complementary bit line

[0069] 232-2: Second complementary bit line

[0070] 234: First complementary power line

[0071] 236: Second complementary power line

[0072] 238: Power cord

[0073] 240: First long contact

[0074] 242: Second long connection

[0075] 244: Third long connection point

[0076] 246: Fourth long junction

[0077] 252: First gate via

[0078] 254: Second gate via

[0079] 256: Third gate via

[0080] 258: Fourth gate via

[0081] 260: First Vss through hole

[0082] 262: Second Vss through-hole

[0083] 272: First source junction

[0084] 274: Second source junction

[0085] 276: Third source junction

[0086] 278: Fourth source junction

[0087] 280: Fifth source junction

[0088] 282: Sixth Source Junction

[0089] 1000: n-type well

[0090] 2000: P-type well

[0091] 2000-1: First P-type well

[0092] 2000-2: Second p-type well

[0093] S1: First Interval

[0094] S2: Second Interval

[0095] W: Width

[0096] L: Length

[0097] 204: Active Zone

[0098] 205: Isolation layer

[0099] SW: Well

[0100] G: Gate structure

[0101] GV: Gate via

[0102] V1: First through hole

[0103] V2: Second through hole

[0104] V3: Third through hole

[0105] M1: First metal layer

[0106] M2: Second metal layer

[0107] M3: Third Metal Layer

[0108] M4: Fourth Metal Layer

[0109] V0: Through hole

[0110] C: Contact

[0111] 290: First metal micro-motion characteristic

[0112] 294: Contact pad

[0113] 296: Contact pad

[0114] 302: Contact pad

[0115] 304: Contact pad

[0116] W1: First width

[0117] W2: Second width

[0118] 291: Second metal micro-motion characteristics

[0119] 295: Contact pad

[0120] 297: Contact pad

[0121] 306: Contact pad

[0122] 308: Contact pad Detailed Implementation

[0123] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific examples of the components and arrangements of this disclosure are described below for simplification. Naturally, these examples are not intended to limit this disclosure. For example, if the description states that a first feature is formed on or above a second feature, it may include embodiments where the first and second features are in direct contact, or embodiments where an additional feature is formed between the first and second features, so that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples of this disclosure. This repetition is for simplification and clarity and does not inherently define the relationships between the various embodiments and / or configurations discussed.

[0124] Furthermore, reference numerals and / or letters may be repeated in various embodiments of this disclosure. This repetition is intended for simplicity and clarity and does not, in itself, define the relationships between the various embodiments and / or configurations discussed. In addition, the description below of forming one feature on another feature, connecting to another feature, and / or coupling to another feature may include embodiments where the features are formed in direct contact, and may also include embodiments where additional features are inserted between features so that the features are not in direct contact. Furthermore, spatially relative terms such as “lower,” “higher,” “horizontal,” “vertical,” “above,” “up,” “below,” “down,” “top,” “bottom,” and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.) are used to facilitate understanding of the relationship between one feature and another in this disclosure. Spatially relative terms are intended to cover different orientations of the means comprising the feature.

[0125] Furthermore, unless specifically denied, singular words contain plural words, and vice versa. When a number or range of numbers is described using terms such as "approximately," "about," or similar, the term is intended to encompass reasonable numbers that include the stated number, such as + / - 10% of the stated number or other values ​​understood by one of ordinary skill in the art. For example, the term "approximately 5 nanometers (nm)" covers a size range from 4.5 nm to 5.5 nm.

[0126] Figure 1 and Figure 2 This is a schematic circuit diagram of a dual-ended random access memory (DP SRAM) cell 100. The DP SRAM cell 100 can be implemented using planar field-effect transistors (FETs) or multi-gate FETs. A planar FET includes a gate structure that senses a planar channel region along one surface of its active region, hence the name. A multi-gate FET includes a gate structure in contact with at least two surfaces of its active region. Examples of multi-gate FETs include fin FETs (FinFETs) and multi-bridge channel (MBC) FETs. A FinFET includes a fin-shaped active region rising from the substrate, and gate structures disposed on the top surface and sidewalls of the fin-shaped active region. An MBC FET includes at least one channel member extending between two source / drain features, and a gate structure completely surrounding the at least one channel member. Due to its gate structure surrounding the channel member, an MBC FET can also be called a gate-all-around (GAA) FET or a surrounding gate transistor (SGT). Depending on their shape and orientation, the channel components in an MBC FET can be referred to as nanosheets, semiconductor wires, nanowires, nanostructures, nanopillars, nanobundles, or nanobridges. In some cases, an MBC FET can be referred to by the shape of its channel components. For example, an MBC FET having one or more nanosheet channel components can also be referred to as a nanosheet transistor or nanosheet FET. To avoid any ambiguity, embodiments of this disclosure are applicable to DP SRAM cells 100 implemented using planar FETs or multi-gate FETs.

[0127] In some embodiments, the DP SRAM cell 100 may include a total of 10 transistors and may be referred to as a 10T SRAM cell 100. (See also...) Figure 1 The DP SRAM cell 100 includes a cross-coupled first inverter 101 and a second inverter 102. For example... Figure 2As shown, the first inverter 101 includes a first pull-up device (PU-1) 142 formed by a p-type field-effect transistor (pFET), a first pull-down device (PD-1) 146 formed by an n-type field-effect transistor (nFET), and a second pull-down device (PD-2) 148 formed by an nFET. The first pull-down device (PD-1) 146 and the second pull-down device (PD-2) 148 are configured in parallel mode. Specifically, the drains of the first pull-down device (PD-1) 146 and the second pull-down device (PD-2) 148 are electrically connected together, their corresponding sources are electrically connected together, and their corresponding gates are electrically connected together. The second inverter 101 includes a second pull-up device (PU-2) 144 formed by a pFET, a third pull-down device (PD-3) 150 formed by an nFET, and a fourth pull-down device (PD-4) 152 formed by an nFET. The third pull-down device (PD-3) 150 and the fourth pull-down device (PD-4) 152 are configured in parallel mode.

[0128] The drains of the first pull-up device (PU-1) 142, the first pull-down device (PD-1) 146, and the second pull-down device (PD-2) 148 are electrically connected together, defining a first drain node (also referred to as the first node or node 1). The drains of the second pull-up device (PU-2) 144, the third pull-down device (PD-3) 150, and the fourth pull-down device (PD-4) 152 are electrically connected together, defining a second drain node (also referred to as the second node or node 2). The gates of the first pull-up device (PU-1) 142, the first pull-down device (PD-1) 146, and the second pull-down device (PD-2) 148 are electrically connected and coupled to the second node. The gates of the second pull-up device (PU-2) 144, the third pull-down device (PD-3) 150, and the fourth pull-down device (PD-4) 152 are electrically connected and coupled to the first node. The sources of the first pull-up device (PU-1) 142 and the second pull-up device (PU-2) 144 are electrically connected to the power supply line (Vdd or CVdd). The sources of the first pull-down device (PD-1) 146, the second pull-down device (PD-2) 148, the third pull-down device (PD-3) 150, and the fourth pull-down device (PD-4) 152 are electrically connected to the complementary power supply line (Vss or CVss).

[0129] The DP SRAM cell 100 further includes a first terminal (terminal A) 112 and a second terminal (terminal B) 114. In one embodiment, terminal A 112 and terminal B 114 include at least four transmission gate devices, referred to as a first transmission gate device (PG-1) 104, a second transmission gate device (PG-2) 106, a third transmission gate device (PG-3) 108, and a fourth transmission gate device (PG-4) 110. Terminal A 112 includes the first transmission gate device (PG-1) 104 and the second transmission gate device (PG-2) 106. Terminal B 114 includes the third transmission gate device (PG-3) 108 and the fourth transmission gate device (PG-4) 110. The drain of the first transmission gate device (PG-1) 104 is electrically connected to the first bit line 122 (referred to as BL-A). The source of the first transmission gate device (PG-1) 104 is electrically connected to the first node. The gate of the first transmission gate device (PG-1) 104 is electrically connected to the first word line 112 (referred to as terminal A WL). The drain of the second transmission gate device (PG-2) 106 is electrically connected to the first complementary bit-line bar 124 (BL-A bar). The source of the second transmission gate device (PG-2) 106 is electrically connected to the second node. The gate of the second transmission gate device (PG-2) 106 is electrically connected to the first word line 112 (terminal A WL). The drain of the third transmission gate device (PG-3) 108 is electrically connected to the second bit line 132 (BL-B). The source of the third transmission gate device (PG-3) 108 is electrically connected to the first node. The gate of the third transmission gate device (PG-3) 108 is electrically connected to the second word line 114 (terminal B WL). The drain of the fourth transmission gate device (PG-4) 110 is electrically connected to the second complementary bit line 134 (BL-B bar). The source of the fourth transmission gate device (PG-4) 110 is electrically connected to the second node. The gate of the fourth transmission gate device (PG-4) 110 is electrically connected to the second word line 114 (terminal B WL). It should be noted that, for ease of reference, terminal A and terminal A WL share the same reference symbol 112, while terminal B and terminal B WL share the same reference symbol 114. Figure 2 As can be seen, the DP SRAM cell 100 includes two pull-up devices (PU-1 and PU-2), four pull-down devices (PD-1, PD-2, PD-3 and PD-4), and four transmission gate devices (PG-1, PG-2, PG-3 and PG-4), which can be implemented using 10 transistors (10T), such as 10 planar FETs or 10 multi-gate FETs.

[0130] Figure 3 This is a schematic diagram of the DP SRAM device 10. (See diagram below.) Figure 3As shown, the DP SRAM device 10 includes an SRAM array 12 composed of 4×4 or more dual-ended SRAM cells, each cell having Figure 1 and Figure 2 The circuit layout is shown. The first word line (WL-A) of the dual-ended SRAM cell in SRAM array 12 is connected to and controlled by the first word line (WL-A) driver / selector 14, while the second word line (WL-B) of the dual-ended SRAM cell in SRAM array 12 is connected to and controlled by the second word line (WL-B) driver / selector 16. According to various foregoing embodiments, the first word line (WL-A) and the second word line (WL-B) of the dual-ended SRAM cell in SRAM array 12 are formed in the same or different metal layers, such as a second metal layer (M2) and / or a fourth metal layer (M4). For example, the first word line (WL-A) is formed in the second metal layer (M2), while the second word line (WL-B) is formed in the fourth metal layer (M4). For another example, the first character line (WL-A) and the second character line (WL-B) are both formed in the second metal layer (M2). Different metal layers are drawn on... Figure 5 and Figure 6 This will be described in more detail below.

[0131] Still refer to Figure 3The first word line (BL-A) and the first complementary bit line (BL-A bar) of the dual-ended SRAM cell in SRAM array 12 are connected to the first Y multiplexer (MUX) and the sensing amplifier 18. When the first word line (WL-A) is selected, the first word line (BL-A) and the first complementary bit line (BL-A bar) of the SRAM cell can be selected, and the data transmitted by the SRAM cell can be read and sensed (or written) by the first Y multiplexer (MUX) and the sensing amplifier 18. The second bit line (BL-B) and the second complementary bit line (BL-B bar) of the dual-ended SRAM cell in SRAM array 12 are connected to the second Y multiplexer (MUX) and the sensing amplifier 20. When the second word line (WL-B) is selected, the second bit line (BL-B) and the second complementary bit line (BL-B bar) of the SRAM cell can be selected, and the data transmitted by the SRAM cell can be read and sensed (or written) by the second Y multiplexer (MUX) and the sense amplifier 20. According to various embodiments based on this disclosure, the first bit line (BL-A), the first complementary bit line (BL-A bar), the second bit line (BL-B), and the second complementary bit line (BL-B bar) of the dual-port SRAM cell can be formed in the same metal layer, such as the first metal layer (M1), as shown in... Figure 5 and Figure 6 .

[0132] To explain Figure 1 and Figure 2 The routing features in the DP SRAM cell 100 shown are illustrated in the schematic layout of the DP SRAM cell. Figure 4A and Figure 4B .because Figure 4A and Figure 4B The schematic layout in the diagram shows a larger proportion than Figure 1 and Figure 2 Further features of the circuit diagram in the image, therefore for Figure 4A and Figure 4B Different reference symbols are used. However, it should be noted that although in Figure 1 , Figure 2 , Figure 4A and Figure 4B Different reference symbols can be used in the features, but... Figure 1 and Figure 2 The devices and nodes marked in the middle Figure 4A and Figure 4B The corresponding part still exists. For example, although... Figure 1 and Figure 2The DP SRAM cells, PG-1, PG-2, PG-3, PG-4, PD-1, PD-2, PD-3, PD-4, PU-1, PU-2, WL-A, WL-B, BL-A, BL-B, BL-A bar, BL-B bar, Vss, and Vdd correspond to... Figure 4A or Figure 4B They have similar features, but their reference signs are not the same. (The last two sentences appear to be fragments and don't form a coherent sentence.) Figure 4A Compared to the schematic layout in the diagram, Figure 4B The schematic layout shown is simplified to illustrate an example of the inventive features of this disclosure.

[0133] First refer to Figure 4A . Figure 1 and Figure 2 The DP SRAM cell 100 shown can be implemented as Figure 4A The DP SRAM cell 200 is shown. The DP SRAM cell 200 can be fabricated on a substrate 202. In some embodiments, the substrate 202 may include a semiconductor material, such as silicon or silicon-germanium. In some alternative embodiments, the substrate 202 may be silicon-on-insulator (SOI), including an insulating layer on a supporting bulk wafer for isolation and a silicon layer on the insulating layer. Different techniques can be used to form the SOI substrate, including separation by implanted oxygen (SIMOX), bonding and etched-back SOI (BESOI), and zone melting and recrystallization (ZMR) SOI. The substrate 202 may include different doped regions. Figure 4AIn the illustrated embodiment, with respect to the DP SRAM cell 200, the substrate 202 may include an n-type well 1000 and a first p-type well 2000-1 and a second p-type well 2000-2, wherein the n-type well 1000 is doped with an n-type dopant, such as phosphorus (P) and arsenic (As), while the first p-type well 2000-1 and the second p-type well 2000-2 are doped with a p-type dopant, such as boron (B). As will be described below, n-type devices will be formed on the first p-type well 2000-1 and the second p-type well 2000-2, and p-type devices will be formed on the n-type well 1000. In some embodiments, when considering crossing the boundary of the DP SRAM cell 200, the first p-type well 2000-1 and the second p-type well 2000-2 may be different regions of the same p-type well 2000. Regarding DP SRAM cell 200, n-type well 1000 is sandwiched between the first p-type well 2000-1 and the second p-type well 2000-2.

[0134] The DP SRAM cell 200 includes a first active region 204-1, a second active region 204-2, a third active region 204-3, a fourth active region 204-4, a fifth active region 204-5, and a sixth active region 204-6. Each active region extends lengthwise along the Y direction. Figure 4A In some embodiments shown, each of the first active region 204-1, the second active region 204-2, the fifth active region 204-5, and the sixth active region 204-6 includes two fin structures or two vertically stacked channel members, while each of the third active region 204-3 and the fourth active region 204-4 includes a single fin structure or a single vertically stacked channel member. Other numbers of active regions, arrangements, and implementations are also possible, and are fully contemplated in this disclosure. In some embodiments, a first pull-up device (PU-1) 206 is formed on a third active region 204-3, a second pull-up device (PU-2) 208 is formed on a fourth active region 204-4, a first transmission gate device (PG-1) 210 and a first pull-down device (PD-1) 218 ​​are formed on a first active region 204-1, a second transmission gate device (PG-2) 212 and a second pull-down device (PD-2) 220 are formed on a second active region 204-2, a third pull-down device (PD-3) 222 and a third transmission gate device (PG-3) 214 are formed on a fifth active region 204-5, and a fourth pull-down device (PD-4) 224 and a fourth transmission gate device (PG-4) 216 are formed on a sixth active region 204-6. Figure 4AIn some of the examples shown, each of the first transmission gate device (PG-1) 210, the second transmission gate device (PG-2) 212, the third transmission gate device (PG-3) 214, and the fourth transmission gate device (PG-4) 216 has its own gate structure that extends longitudinally along the X direction, where the X direction is perpendicular to the Y direction. The first pull-down device (PD-1) 218, the second pull-down device (PD-2) 220, and the first pull-down device (PU-1) 206 share a gate structure that also extends longitudinally along the X direction. The third pull-down device (PD-3) 222, the fourth pull-down device (PD-4) 224, and the second pull-up device (PU-2) 208 share a gate structure that also extends longitudinally along the X direction.

[0135] The DP SRAM cell 200 includes a gate via and a source / drain contact, forming the gate structure and source / drain connection to the transistors in the DP SRAM cell 200. (Refer to...) Figure 4A In some embodiments, the DP SRAM cell 200 includes a first gate via 252, a second gate via 254, a third gate via 256, and a fourth gate via 258. The first gate via 252 is disposed on and electrically coupled to the gate structure of the second transmission gate device (PG-2) 212. Along the X direction, the first gate via 252 is disposed on an isolation feature between the second active region 204-2 and the third active region 204-3. The isolation feature may be a shallow trench isolation (STI) feature, and is typically shown in... Figure 5In the middle, a first gate via 252 electrically couples the gate structure of the second transmission gate device (PG-2) 212 to a first WL-B landing pad 228-1. The first WL-B landing pad 228-1 extends longitudinally along the Y direction and is located between the second active region 204-2 and the third active region 204-3. A second gate via 254 is disposed on and electrically coupled to the gate structure of the third transmission gate device (PG-3) 214. Along the X direction, the second gate via 254 is disposed on an isolation feature (e.g., an STI feature) between the fourth active region 204-4 and the fifth active region 204-5. The second gate via 254 electrically couples the gate structure of the third transmission gate device (PG-3) 214 to the second WL-B landing pad 228-2. The second WL-B landing pad 228-2 extends longitudinally along the Y direction and is located between the fourth active region 204-4 and the fifth active region 204-5. A third gate via 256 is disposed on and electrically coupled to the gate structure of the first transmission gate device (PG-1) 210. Along the X direction, the third gate via 256 is disposed at the end or boundary of the DP SRAM cell 200. The third gate via 256 electrically couples the gate structure of the first transmission gate device (PG-1) 210 to the first WL-A landing pad 226-1. The first WL-A landing pad 226-1 extends longitudinally along the Y direction and is located at the end or boundary of the DP SRAM cell 200. A fourth gate via 258 is disposed on and electrically coupled to the gate structure of the fourth transmission gate device (PG-4) 216. Along the X direction, the fourth gate via 258 is disposed at the other end or boundary of the DP SRAM cell 200. The fourth gate via 258 electrically couples the gate structure of the fourth transmission gate device (PG-4) 216 to the second WL-A landing pad 226-2. The second WL-A landing pad 226-2 extends longitudinally along the Y direction and is located at the other end or boundary of the DP SRAM cell 200. Along the Z direction, each gate via may have a circular, elliptical, racetrack-shaped, square, or rectangular shape. In some embodiments, because the third gate via 256 and the fourth gate via 258 are located at the boundary of the DP SRAM cell 200, they can be enlarged to reduce resistance and improve the performance of the DP SRAM cell 200. Conversely, the first gate via 252 and the second gate via 254 are located within the active region of the DP SRAM cell 200, and the space to enlarge them may be limited. Thus, in those embodiments, the XY plane projected area of ​​the third gate via 256 and the fourth gate via 258 is larger than the XY plane projected area of ​​the first gate via 252 and the second gate via 254.

[0136] The drains (or drain characteristics) of the first pull-down device (PD-1) 218, the second pull-down device (PD-2) 220, and the first pull-up device (PU-1) 206 are electrically coupled to a first long contact 240. The first long contact 240 extends longitudinally along the X direction in the first active region 204-1, the second active region 204-2, and the third active region 204-3. For example... Figure 4A As shown, the first long contact 240 is disposed between the gate structure of the first transmission gate device (PG-1) 210 and the common gate structure of the first pull-down device (PD-1) 218, the second pull-down device (PD-2) 220, and the first pull-up device (PU-1) 206. Similarly, the first long contact 240 is disposed between the gate structure of the second transmission gate device (PG-2) 212 and the common gate structure of the first pull-down device (PD-1) 218, the second pull-down device (PD-2) 220, and the first pull-up device (PU-1) 206. The first long contact 240 is disposed between the common gate structure of the first pull-down device (PD-1) 218, the second pull-down device (PD-2) 220, and the first pull-up device (PU-1) 206 and the common gate structure of the third pull-down device (PD-3) 222, the fourth pull-down device (PD-4) 224, and the second pull-up device (PU-2) 208. Figure 4A As shown, because the first long contact 240 extends along the X direction to cross over the first WL-B landing pad 228-1 (which extends longitudinally along the Y direction), the first gate via 252 may be adjacent to the first long contact 240. As used herein, a long contact refers to a contact feature that physically crosses more than one source / drain region. For example, the first long contact 240 physically crosses over the first pull-down device (PD-1) 218, the second pull-down device (PD-2) 220, and the first pull-up device (PU-1) 206. Alternatively, a long contact refers to a contact feature that physically crosses more than one active region. For example, the first long contact 240 physically crosses over the first active region 204-1, the second active region 204-2, and the third active region 204-3.

[0137] The drains (or drain characteristics) of the third pull-down device (PD-3) 222, the fourth pull-down device (PD-4) 224, and the second pull-up device (PU-2) 208 are electrically coupled to the second long contact 242. The second long contact 242 extends longitudinally along the X direction in the fourth active region 204-4, the fifth active region 204-5, and the sixth active region 204-6. For example... Figure 4AAs shown, the second long contact 242 is disposed between the gate structure of the fourth transmission gate device (PG-4) 216 and the common gate structure of the third pull-down device (PD-3) 222, the fourth pull-down device (PD-4) 224, and the second pull-up device (PU-2) 208. Similarly, the second long contact 242 is disposed between the gate structure of the third transmission gate device (PG-3) 214 and the common gate structure of the third pull-down device (PD-3) 222, the fourth pull-down device (PD-4) 224, and the second pull-up device (PU-2) 208. The second long contact 242 is disposed between the common gate structure of the first pull-down device (PD-1) 218, the second pull-down device (PD-2) 220, and the first pull-up device (PU-1) 206 and the common gate structure of the third pull-down device (PD-3) 222, the fourth pull-down device (PD-4) 224, and the second pull-up device (PU-2) 208. Figure 4A As shown, because the second long contact 242 extends along the X direction to cross over the second WL-B landing pad 228-2 (which extends longitudinally along the Y direction), the second gate via 254 may be adjacent to the second long contact 242.

[0138] The sources (or source characteristics) of the first pull-down device (PD-1) 218 ​​and the second pull-down device (PD-2) 220 are electrically coupled to the third long contact 244. The third long contact 244 extends longitudinally along the X direction on the first active region 204-1 and the second active region 204-2. The sources (or source characteristics) of the third pull-down device (PD-3) 222 and the fourth pull-down device (PD-4) 224 are electrically coupled to the fourth long contact 246. The fourth long contact 246 extends longitudinally along the X direction on the fifth active region 204-5 and the sixth active region 204-6.

[0139] In addition to the first, second, third, and fourth long contacts, the first transmission gate device (PG-1) 210 has a first source contact 272, the second transmission gate device (PG-2) 212 has a second source contact 274, the first pull-up device (PU-1) 206 has a fourth source contact 278, the second pull-up device (PU-2) has a third source contact 276, the third transmission gate device (PG-3) has a fifth source contact 280, and the fourth transmission gate device (PG-4) has a sixth source contact 282. For example... Figure 4AAs shown, via a contact via, the first source contact 272 is electrically coupled to the first bit line (BL-A) 230-1. Similarly, the second source contact 274 is electrically coupled to the second bit line (BL-B) 230-2, the sixth source contact 282 is electrically coupled to the first complementary bit line (BL-A bar) 232-1, and the fifth source contact 280 is electrically coupled to the second complementary bit line (BL-B bar) 232-2. via a contact via, the third source contact 276 and the fourth source contact 278 are electrically coupled to the power line (Vdd) 238. via a first Vss via 260, the third long contact 244 is electrically coupled to the first complementary power line (1... st Vss)234. The fourth long contact 246 is electrically coupled to the second complementary power line (2) via the second Vss through-hole 262. nd Vss)236.

[0140] Still refer to Figure 4A First WL-A landing pad 226-1, first primary line (BL-A) 230-1, first complementary power line (1 st Vss)234, Second bit line (BL-B)230-2, First WL-B landing pad 228-1, Power line (Vdd)238, Second WL-B landing pad 228-2, Second complementary bit line (BL-B bar)232-2, Second complementary power line (2 nd Each of Vss)236, the first complementary bit line (BL-Abar)232-1, and the second WL-A landing pad 226-2 extends longitudinally along the Y direction and is parallel to the longitudinal direction of the active region (204-1 to 204-6). In some embodiments, the first WL-A landing pad 226-1, the first bit line (BL-A)230-1, and the first complementary power line (1 st Vss)234, Second bit line (BL-B)230-2, First WL-B landing pad 228-1, Power line (Vdd)238, Second WL-B landing pad 228-2, Second complementary bit line (BL-B bar)232-2, Second complementary power line (2 nd Vss)236, the first complementary bit line (BL-A bar)232-1, and the second WL-A landing pad 226-2 are disposed in the first metal layer (M1).

[0141] Reference Figure 4BWhen viewed along the Z-direction, the DP SRAM cell 200 is rectangular in shape and extends along the X-direction. In some embodiments, the DP SRAM cell 200 includes a length L along the X-direction and a width W along the Y-direction. The ratio of length L to width W can be between approximately 4 and approximately 7. A smaller width W reduces the line length of the bit lines and complementary bit lines, thereby reducing the ohmic drop (i.e., IR drop) along the length of the bit lines and complementary bit lines. By disposing the first WL-B landing pad 228-1 between the n-type second active region 204-2 and the p-type third active region 204-3, the spacing between the n-type second active region 204-2 and the p-type third active region 204-3 is increased. Similarly, by placing the second WL-B landing pad 228-2 between the n-type fifth active zone 204-5 and the p-type fourth active zone 204-4, the spacing between the n-type fifth active zone 204-5 and the p-type fourth active zone 204-4 is also increased. In this way, the first spacing S1 between adjacent n-type active zones is smaller than the second spacing S2 between an n-type active zone and an adjacent p-type active zone. For example, the n-type first active zone 204-1 and second active zone 204-2 are separated by the first spacing S1 along the X direction. The n-type fifth active zone 204-5 and sixth active zone 204-6 are also separated by the first spacing S1 along the X direction. The n-type second active zone 204-2 and the p-type third active zone 204-3 are separated by the second spacing S2. The n-type fifth active zone 204-5 and the p-type fourth active zone 204-4 are separated by the second spacing S2. As mentioned above Figure 4A Each of the first active region 204-1, the second active region 204-2, the fifth active region 204-5, and the sixth active region 204-6 includes two fin structures or two vertically stacked channel members, while each of the third active region 204-3 and the fourth active region 204-4 includes a single fin structure or a single vertically stacked channel member. Therefore, the first interval S1 refers to the smallest fin-to-fin or stack-to-stack interval between the fins / stacks in the first active region 204-1 and the fins / stacks in the second active region 204-2, or the smallest fin-to-fin or stack-to-stack interval between the fins / stacks in the fifth active region 204-5 and the fins / stacks in the sixth active region 204-6. Similarly, the second interval S2 refers to the smallest fin-to-fin or stack-to-stack interval between the fins / stacks in the second active region 204-2 and the fins / stacks in the third active region 204-3, or the smallest fin-to-fin or stack-to-stack interval between the fins / stacks in the fifth active region 204-5 and the fins / stacks in the fourth active region 204-4.

[0142] In some embodiments, the ratio of the second interval S2 to the first interval S1 may be between about 1.05 and about 2.00. A larger second interval S2 can provide benefits. For example, a larger second interval S2 allows for a larger spacing between the n-type well 1000 and the p-type well 2000 (including the first p-type well 2000-1 and the second p-type well 2000-2), resulting in reduced well isolation leakage and increased immunity to latch-up and soft-error rate. As another example, a larger second interval S2 can free up space for larger n-type wells, which can result in more balanced performance characteristics of the DP SRAM cell 200. (As in...) Figure 4A and Figure 4B As can be seen, in the DP SRAM cell 200, the p-type well 2000 (including the first p-type well 2000-1 and the second p-type well 2000-2) has a larger area than the n-type well 1000. Increasing the area of ​​the n-type well helps to balance the performance of the DP SRAM cell 200. Furthermore, because the first complementary power line (1... st Vss)234 and the second complementary power line (2 nd Vss)236 is the only metal wire located between adjacent n-type active regions (between the first active region 204-1 and the second active region 204-2, or between the fifth active region 204-5 and the sixth active region 204-6), therefore the first complementary power line (1 st Vss)234 and the second complementary power line (2 nd Vss 236 can be wider to make room for the larger first Vss via 260 and second Vss via 262, which can bring improved performance to the DP SRAM cell 200. The first Vss via 260 and the second Vss via 262 have larger dimensions compared to the gate vias (first gate via 252, second gate via 254, third gate via 256, and fourth gate via 258). For example, when both the gate via and the Vss via are substantially rectangular, the gate via has a first dimension D1 along one isolated side, while the Vss via has a second dimension D2. In some embodiments, the ratio of the second dimension D2 to the first dimension D1 may be between about 1.1 and about 4.

[0143] The various metal layers and contact vias of the DP SRAM cell 200 are shown in Figure 5 and Figure 6 . Figure 5 This is a schematic diagram of the metal layer viewed along the Y direction. Figure 6 This is a schematic diagram of the metal layer viewed along the X direction. For simplicity, in... Figure 5 and Figure 6 In the middle, the first, second, third, fourth, fifth and sixth active regions (in Figure 4A The reference symbols in the text are 204-1 to 6, which can be representatively shown as the active region 204; 10 transistors (in Figure 4A The gate structures shown as PU-1, PU-2, PG-1~4 and PD-1~4 can be representatively shown as gate structure G; the first, second, third and fourth gate vias (in Figure 4A Reference symbols 252, 254, 256, and 258 can be representatively shown as gate vias (GV); source contacts (in...) Figure 4A The reference symbols are 272, 274, 276, 278, 280, and 282; long contacts (in...) Figure 4A The reference symbols are 240, 242, 244, and 246. Figure 6 The source / drain contact via is typically represented as contact C; the source / drain contact via is typically represented as via V0; and the n-type well 1000 and p-type well 2000 (including the first p-type well 2000-1 and the second p-type well 2000-2) are typically represented as well SW. Isolation layers 205, such as shallow trench isolation (STI) layers, can be disposed between adjacent active regions 204 to provide isolation. Each active region 204 can be disposed in, such as... Figure 4A On the n-type well 1000, or such as Figure 4A On the p-type well 2000 (including the first p-type well 2000-1 and the second p-type well 2000-2). The metal wire in the first metal layer (M1) extends longitudinally along the Y direction. The metal wire in the second metal layer (M2) extends longitudinally along the X direction. The metal wire in the third metal layer (M3) extends longitudinally along the Y direction. The metal wire in the fourth metal layer (M4) extends longitudinally along the X direction. The first through-hole (V1) is electrically coupled to the first metal layer (M1) and the second metal layer (M2). The second through-hole (V2) is electrically coupled to the second metal layer (M2) and the third metal layer (M3). The third through-hole (V3) is electrically coupled to the third metal layer (M3) and the fourth metal layer (M4). As described above, the first WL-A landing pad 226-1, the first element line (BL-A) 230-1, and the first complementary power line (1 st Vss)234, Second bit line (BL-B)230-2, First WL-B landing pad 228-1, Power line (Vdd)238, Second WL-B landing pad 228-2, Second complementary bit line (BL-Bbar)232-2, Second complementary power line (2 nd Vss)236, the first complementary bit line (BL-A bar)232-1, and the second WL-A landing pad 226-2 can be disposed in the first metal layer (M1).

[0144] Because the metal lines in the first metal layer (M1), second metal layer (M2), third metal layer (M3), and fourth metal layer (M4) extend along the X direction or along the perpendicular Y direction, the metal lines in the DP SRAM cell 200 do not include complex shapes, thus resulting in increased yield. Figure 3 , Figure 5 and Figure 6 As shown, the second metal layer (M2) and the fourth metal layer (M4) extending in the X direction can be used as the first word line (WL-A) and the second word line (WL-B) to be coupled to the first word line (WL-A) driver / selector 14 and the second word line (WL-B) driver / selector 16. The first bit line (BL-A), the first complementary bit line (BL-Abar), the second bit line (BL-B), and the second complementary bit line (BL-Bbar) extending in the Y direction can be coupled to the first Y multiplexer (MUX) and sense amplifier 18 or the second Y multiplexer (MUX) and sense amplifier 20.

[0145] Figure 7 In some embodiments shown, both the first character line (WL-A) and the second character line (WL-B) can be implemented in the second metal layer (M2). In these embodiments, the first character line (WL-A) can be coupled to the first WL-A landing pad 226-1 and the second WL-A landing pad 226-2 via the paths of the two first vias V1; while the second character line (WL-B) can be coupled to the first WL-B landing pad 228-1 and the second WL-B landing pad 228-2 via the paths of the two first vias V1.

[0146] exist Figure 8 In some alternative embodiments shown, the second word line (WL-B) may be implemented in the second metal layer (M2), while the first word line (WL-A) may be implemented in the fourth metal layer (M4). Because the first word line (WL-A) and the second word line (WL-B) are fabricated in different metal layers, a first metal jog feature 290 can be formed in the second metal layer (M2) to increase the width of the second word line (WL-B) and reduce the ohmic voltage drop (i.e., IR drop). Figure 8In some embodiments shown, the second character line (WL-B) has a first width W1, and the first metal micro-motion feature 290 can increase the width to a second width W2. The second width W2 is greater than the first width W1. In these embodiments, the second character line (WL-B) can be coupled to the first WL-B landing pad 228-1 and the second WL-B landing pad 228-2 via the paths of the two first through holes V1. The first character line (WL-A) can be coupled to the first WL-A landing pad 226-1 and the second WL-A landing pad 226-2 via the paths of the two first through holes V1, the two contact pads 294 and 296 in the second metal layer (M2), the two second through holes V2, the two contact pads 302 and 304 in the third metal layer (M3), and the two third through holes V3. The two contact pads 294 and 296 in the second metal layer (M2), the two second through holes V2, the two contact pads 302 and 304 in the third metal layer (M3), and the two third through holes V3 help to reroute the signal path between the fourth metal layer (M4) and the first WL-A landing pad 226-1 and the second WL-A landing pad 226-2.

[0147] Further embodiments of the metal layer can be shown in Figure 9 In the middle. And Figure 8 Compared to the metal layer structure shown, Figure 9 The metal layer structure also includes a power mesh feature, which can be incorporated into... Figure 8 In the metal layer structure shown, this is to reduce the ohmic voltage drop (i.e., IR drop). For example... Figure 9 As shown, the first complementary power line (1) st Vss)234 can be routed to the fourth metal layer (M4) via the path of the first through-hole V1, the contact pad 295 in the second metal layer (M2), the second through-hole V2, the contact pad 306 in the third metal layer (M3), and the third through-hole V3. Similarly, the second complementary power line (2 nd Vss)236 can be routed to the fourth metal layer (M4) via the path of the first through-hole V1, the contact pad 297 in the second metal layer (M2), the second through-hole V2, the contact pad 308 in the third metal layer (M3), and the third through-hole V3. Because the contact pads 295 and 297 occupy the space in the second metal layer (M2), the second metal layer (M2) in Figure 9 The second metal micro-motion feature 291 in the image may be smaller than that in the image. Figure 8 The first metal micro-motion feature 290 in the middle.

[0148] While not intended to be limiting, one or more embodiments of this disclosure provide benefits. For example, an embodiment of the 10T SRAM cell provided in this disclosure includes two pull-up devices (PU-1 and PU-2), four pull-down devices (PD-1, PD-2, PD-3, and PD-4), and four transmission gate devices (PG-1, PG-2, PG-3, and PG-4). The SRAM cell of this disclosure includes word line contact pads disposed between n-type and p-type devices to increase the spacing between them. The increased spacing allows for reduced latch-up and a lower soft error rate, thus improving performance. Furthermore, the increased spacing between the n-type and p-type devices allows space to be used for larger n-type wells, resulting in a more balanced performance for the SRAM cell. To simplify the routing structure and increase scalability, metal lines in one metal layer are orthogonal to metal lines in adjacent metal layers. The SRAM cell disclosed herein includes a first long contact and a second long contact. The first long contact is coupled to the drains of a first pull-down device (PD-1), a second pull-down device (PD-2), and a first pull-up device (PU-1), while the second long contact is coupled to the drains of a third pull-down device (PD-3), a fourth pull-down device (PD-4), and a second pull-up device (PU-2). The implementation of the long contacts simplifies the routing structure.

[0149] Therefore, in one embodiment, this disclosure provides an SRAM cell. The SRAM cell includes a first pull-down device (PD-1), a second pull-down device (PD-2), a first transmission gate device (PG-1), and a second transmission gate device (PG-2), disposed in a first p-well on a substrate, wherein the active regions of the second transmission gate device (PG-2) and the second pull-down device (PD-2) are aligned along a first direction; a third pull-down device (PD-3), a fourth pull-down device (PD-4), a third transmission gate device (PG-3), and a fourth transmission gate device (PG-4) are disposed in a second p-well on the substrate, wherein the third transmission gate device... The active regions of the transmission gate device (PG-3) and the aforementioned third pull-down device (PD-3) are aligned along a first direction; a first pull-up device (PU-1) and a second pull-up device (PU-2) are disposed in an n-well, which is located between a first p-well and a second p-well, wherein the active region of the first pull-up device (PU-1) extends along the first direction; and a first landing pad is disposed between the second pull-down device (PD-2) and the first pull-up device (PU-1), wherein the first landing pad is electrically coupled to a gate structure of the second transmission gate device (PG-2) via a path of a first gate via.

[0150] In some embodiments, a first gate via is disposed between a second pull-down device (PD-2) and a first pull-up device (PU-1).

[0151] In some embodiments, the SRAM cell may further include a second landing pad disposed between the third pull-down device (PD-3) and the second pull-up device (PU-2), and the second landing pad is electrically coupled to the gate structure of the second transmission gate device (PG-2) via the path of the second gate via.

[0152] In some embodiments, the second gate via is disposed between the third pull-down device (PD-3) and the second pull-up device (PU-2).

[0153] In some embodiments, the drain of the first pull-down device (PD-1), the drain of the second pull-down device (PD-2), and the drain of the first pull-up device (PU-1) are electrically coupled to a first long contact.

[0154] In some embodiments, the drain of the third pull-down device (PD-3), the drain of the fourth pull-down device (PD-4), and the drain of the second pull-up device (PU-2) are electrically coupled to the first long contact.

[0155] In some embodiments, the source of the first pull-down device (PD-1) and the source of the second pull-down device (PD-2) are electrically coupled to a third long contact.

[0156] In some embodiments, the source of the third pull-down device (PD-3) and the source of the fourth pull-down device (PD-4) are electrically coupled to a third long contact.

[0157] In another embodiment, this disclosure provides an SRAM cell. The SRAM cell may include a first pull-down device (PD-1), a second pull-down device (PD-2), a first transmission gate device (PG-1), and a second transmission gate device (PG-2), disposed in a first p-well on a substrate; a third pull-down device (PD-3), a fourth pull-down device (PD-4), a third transmission gate device (PG-3), and a fourth transmission gate device (PG-4), disposed in a second p-well on the substrate; and a first pull-up device (PU-1) and a second pull-up device (PU-2), disposed in an n-well, the n-well being located between the first p-well and the second p-well. The first pull-down device (PD-1), the second pull-down device (PD-2), and the first pull-up device (PU-1) share a gate structure extending along a first direction, and the drain of the first pull-down device (PD-1), the drain of the second pull-down device (PD-2), and the drain of the first pull-up device (PU-1) are electrically coupled to a first long contact.

[0158] In some embodiments, the SRAM cell may further include a first landing pad disposed between the second pull-down device (PD-2) and the first pull-up device (PU-1), and the first landing pad is electrically coupled to the gate structure of the second transmission gate device (PG-2) via the path of the first gate via.

[0159] In some embodiments, the first gate via is disposed adjacent to the first long contact.

[0160] In some embodiments, the drain of the third pull-down device (PD-3), the drain of the fourth pull-down device (PD-4), and the drain of the second pull-up device (PU-2) are electrically coupled to the second long contact.

[0161] In some embodiments, the SRAM cell may further include a second landing pad disposed between the third pull-down device (PD-3) and the second pull-up device (PU-2). The second landing pad is electrically coupled to the gate structure of the second transmission gate device (PG-2) via a path of the second gate via.

[0162] In some embodiments, the second gate via is disposed adjacent to the second long contact.

[0163] In another embodiment, this disclosure provides an SRAM cell. The SRAM cell includes a first pull-down device (PD-1), a second pull-down device (PD-2), a first transmission gate device (PG-1), and a second transmission gate device (PG-2), disposed in a first p-well on a substrate; a third pull-down device (PD-3), a fourth pull-down device (PD-4), a third transmission gate device (PG-3), and a fourth transmission gate device (PG-4), disposed in a second p-well on the substrate; and a first pull-up device (PU-1) and a second pull-up device (PU-2), disposed in an n-well, the n-well being located between the first p-well and the second p-well. The first transmission gate device (PG-1) and the first pull-down device (PD-1) share a first active region extending along a first direction. The second transmission gate device (PG-2) and the second pull-down device (PD-2) share a second active region extending along the first direction. The third active region of the first pull-up device (PU-1) extends along the first direction. The first active region and the second active region are separated from each other by a first interval. The second active region and the third active region are separated from each other by a second interval that is greater than the first interval.

[0164] In some embodiments, the ratio of the second interval to the first interval is between 1.05 and 2.

[0165] In some embodiments, the first active region includes two fin structures, the second active region includes two fin structures, and the third active region includes a single fin structure.

[0166] In some embodiments, the SRAM cell may further include a first landing pad disposed between the second pull-down device (PD-2) and the first pull-up device (PU-1). The first landing pad is electrically coupled to the gate structure of the second transmission gate device (PG-2) via a path of the first gate via, and the first landing pad extends in a first direction.

[0167] In some embodiments, the SRAM cell may further include a first long contact. The drain of the first pull-down device (PD-1), the drain of the second pull-down device (PD-2), and the drain of the first pull-up device (PU-1) are electrically coupled to the first long contact.

[0168] In some embodiments, the first long contact extends in a second direction perpendicular to the first direction, and the first landing pad extends over the first long contact.

[0169] The foregoing outlines the features of several embodiments or examples. Those skilled in the art will understand that they can readily design or modify other processes and structures based on this disclosure to achieve the same purpose and / or attain the same advantages as the embodiments or examples described herein. Those skilled in the art will also understand that these equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to this disclosure without departing from its spirit and scope.

Claims

1. A static random access memory (SRAM) cell, comprising: A first pull-down device, a second pull-down device, a first transmission gate device, and a second transmission gate device are disposed in a first p-well on a substrate, wherein the first transmission gate device and the first pull-down device share a first active area extending along a first direction, and wherein the second transmission gate device and a second active area of ​​the second pull-down device are aligned along the first direction. A third pull-down device, a fourth pull-down device, a third transmission gate device, and a fourth transmission gate device are disposed in a second p-well on the substrate, wherein a third active area of ​​the third transmission gate device and the third pull-down device are aligned along the first direction. A first pull-up device and a second pull-up device are disposed in an n-well, wherein the n-well is located between the first p-well and the second p-well, wherein a fourth active region of the first pull-up device extends along the first direction, wherein the first active region and the second active region are separated from each other by a first interval; and wherein the second active region and the fourth active region are separated from each other by a second interval greater than the first interval; and A first landing pad is disposed between the second pull-down device and the first pull-up device, wherein the first landing pad is electrically coupled to a gate structure of the second transmission gate device via a path of a first gate via.

2. The static random access memory cell as claimed in claim 1, wherein the first gate via is disposed between the second pull-down device and the first pull-up device.

3. The static random access memory unit as described in claim 1, further comprising: A second landing pad is disposed between the third pull-down device and the second pull-up device, wherein the second landing pad is electrically coupled to a gate structure of a third transmission gate device via a path of a second gate via.

4. The static random access memory cell as claimed in claim 3, wherein the second gate via is disposed between the third pull-down device and the second pull-up device.

5. The static random access memory cell as claimed in claim 1, wherein the drain of the first pull-down device, the drain of the second pull-down device, and the drain of the first pull-up device are electrically coupled to a first long contact.

6. The static random access memory cell as claimed in claim 1, wherein the drain of the third pull-down device, the drain of the fourth pull-down device, and the drain of the second pull-up device are electrically coupled to a first long contact.

7. The static random access memory cell as claimed in claim 1, wherein the source of the first pull-down device and the source of the second pull-down device are electrically coupled to a third long contact.

8. The static random access memory cell as claimed in claim 1, wherein the source of the third pull-down device and the source of the fourth pull-down device are electrically coupled to a third long contact.

9. A static random access memory (SRAM) cell, comprising: A first pull-down device, a second pull-down device, a first transmission gate device, and a second transmission gate device are disposed in a first p-well on a base plate; A third pull-down device, a fourth pull-down device, a third transmission gate device, and a fourth transmission gate device are disposed in a second p-well on the aforementioned substrate; and A first pull-up device and a second pull-up device are disposed in an n-well, wherein the n-well is disposed between the first p-well and the second p-well; The first pull-down device, the second pull-down device, and the first pull-up device mentioned above share a gate structure extending along a first direction; The drains of the first pull-down device, the second pull-down device, and the first pull-up device are electrically coupled to a first long contact.

10. The static random access memory unit of claim 9, further comprising: A first landing pad is disposed between the second pull-down device and the first pull-up device, wherein the first landing pad is electrically coupled to a gate structure of the second transmission gate device via a path of a first gate via.

11. The static random access memory cell of claim 10, wherein the first gate via is disposed adjacent to the first long contact.

12. The static random access memory cell of claim 9, wherein the drain of the third pull-down device, the drain of the fourth pull-down device, and the drain of the second pull-up device are electrically coupled to a second long contact.

13. The static random access memory unit of claim 12, further comprising: A second landing pad is disposed between the third pull-down device and the second pull-up device, wherein the second landing pad is electrically coupled to a gate structure of the third transmission gate device via a path of a second gate via.

14. The static random access memory cell of claim 13, wherein the second gate via is disposed adjacent to the second long contact.

15. A static random access memory (SRAM) cell, comprising: A first pull-down device, a second pull-down device, a first transmission gate device, and a second transmission gate device are disposed in a first p-well on a substrate, wherein the first transmission gate device and the first pull-down device share a first active area extending along a first direction, and the second transmission gate device and the second pull-down device share a second active area extending along the first direction. A third pull-down device, a fourth pull-down device, a third transmission gate device, and a fourth transmission gate device are disposed in a second p-well on the aforementioned substrate; and A first pull-up device and a second pull-up device are disposed in an n-well, wherein the n-well is disposed between the first p-well and the second p-well, wherein a third active area of ​​the first pull-up device extends along the first direction; The first active region and the second active region are separated from each other by a first interval; The second active region and the third active region are separated from each other by a second interval that is larger than the first interval.

16. The static random access memory cell of claim 15, wherein the ratio of the second interval to the first interval is between 1.05 and 2.

17. The static random access memory cell of claim 15, wherein: The aforementioned first active region includes two fin structures; The aforementioned second active region includes two fin structures; and The aforementioned third active region includes a single fin structure.

18. The static random access memory unit of claim 15, further comprising: A first landing pad is disposed between the second pull-down device and the first pull-up device; The first landing pad is electrically coupled to a gate structure of the second transmission gate device via a first gate via. The first landing pad extends in the first direction.

19. The static random access memory unit of claim 18, further comprising: A first long contact, wherein the drain of the first pull-down device, the drain of the second pull-down device, and the drain of the first pull-up device are electrically coupled to the first long contact.

20. The static random access memory cell of claim 19, wherein: The aforementioned first long contact extends in a second direction perpendicular to the aforementioned first direction; and The aforementioned first landing pad spans over the aforementioned first long contact point.

21. A semiconductor device structure, comprising: A substrate includes an n-well disposed along a first direction between a first p-well and a second p-well; A first active zone and a second active zone are disposed above the aforementioned n-well and extend along a second direction perpendicular to the aforementioned first direction; A third active zone and a fourth active zone are disposed above the first p-well and extend along the second direction. A fifth active zone and a sixth active zone are disposed above the second p-well and extend along the second direction. A first gate structure extends along the first direction to cover the third active region, the fourth active region, and the first active region, wherein the third active region and the fourth active region are separated from each other by a first interval; and the fourth active region and the first active region are separated from each other by a second interval greater than the first interval; and A second gate structure extends along the first direction to cover the second active region, the fifth active region, and the sixth active region.

22. The semiconductor device structure as claimed in claim 21, wherein: Each of the aforementioned first active region and the aforementioned second active region comprises a single fin; and Each of the aforementioned third active zone, fourth active zone, fifth active zone, and sixth active zone comprises two fins.

23. The semiconductor device structure of claim 21, wherein the ratio of the second interval to the first interval is between 1.05 and 2.

00.

24. The semiconductor device structure as claimed in claim 21, wherein: The aforementioned third active region includes a first source / drain region, a second source / drain region, a third source / drain region, a first channel region disposed between the first source / drain region and the second source / drain region, and a second channel region disposed between the second source / drain region and the third source / drain region. The aforementioned fourth active region includes a fourth source / drain region, a fifth source / drain region, a sixth source / drain region, a third channel region disposed between the fourth source / drain region and the fifth source / drain region, and a fourth channel region disposed between the fifth source / drain region and the sixth source / drain region. as well as The aforementioned first active region includes a fifth channel region located between a seventh source / drain region and an eighth source / drain region.

25. The semiconductor device structure of claim 24, wherein the first gate structure covers the first channel region of the third active region, the third channel region of the fourth active region, and the fifth channel region of the first active region.

26. The semiconductor device structure of claim 24, further comprising: A first long contact is disposed above the second source / drain contact of the third active region, the fifth source / drain region of the fourth active region, and the eighth source / drain region of the first active region.

27. The semiconductor device structure of claim 26, further comprising: A second long contact is disposed above the first source / drain contact in the third active region and above the fourth source / drain contact in the fourth active region.

28. A semiconductor device structure, comprising: A substrate includes an n-well disposed along a first direction between a first p-well and a second p-well; A first active zone and a second active zone are disposed above the aforementioned n-well and extend along a second direction perpendicular to the aforementioned first direction; A third active zone and a fourth active zone are disposed above the first p-well and extend along the second direction. A fifth active zone and a sixth active zone are disposed above the second p-well and extend along the second direction. A first gate structure is disposed above the aforementioned third active region; A second gate structure is disposed above the aforementioned fourth active region; A third gate structure is disposed above the aforementioned fifth active region; as well as A fourth gate structure is disposed above the aforementioned sixth active region; The first gate structure and the fourth gate structure are electrically coupled together via a path of a first word line disposed in a first metal layer. The second gate structure and the third gate structure are electrically coupled together via a path of a second word line disposed in a second metal layer. The second metal layer is different from the first metal layer. The third active region and the fourth active region are separated from each other by a first interval. The fourth active region and the first active region are separated from each other by a second interval greater than the first interval.

29. The semiconductor device structure of claim 28, wherein the first metal layer is disposed above the second metal layer.

30. The semiconductor device structure as claimed in claim 28, wherein: The aforementioned first character line and the aforementioned second character line extend longitudinally along the aforementioned first direction; The aforementioned first character line includes a first width along the aforementioned second direction which is perpendicular to the aforementioned first direction; The aforementioned second character line includes a second width along the aforementioned second direction; and The first width mentioned above is greater than the second width mentioned above.

31. The semiconductor device structure of claim 30, wherein a portion of the second character line includes a metal micro-motion feature to increase the second width of the portion of the second character line.

32. The semiconductor device structure as claimed in claim 30, wherein: The first gate structure and the second gate structure are aligned along the first direction; and The aforementioned third gate structure and the aforementioned fourth gate structure are aligned along the aforementioned first direction.

33. The semiconductor device structure of claim 32, further comprising: A first common gate structure covers the first active region, the second active region, and the third active region above it; as well as A second common gate structure covers the fourth active region, the fifth active region, and the sixth active region. The first common gate structure extends parallel to the first gate structure and the second gate structure. The second common gate structure extends parallel to the third gate structure and the fourth gate structure.

34. The semiconductor device structure as claimed in claim 33, wherein: The first common gate structure is aligned with the third gate structure and the fourth gate structure along the first direction; and The second common gate structure is aligned with the first gate structure and the second gate structure along the first direction.

35. A static random access memory (SRAM) cell, comprising: A first pull-down device, a second pull-down device, a first transmission gate device, and a second transmission gate device are disposed in a first p-well on a substrate, wherein the first transmission gate device and the first pull-down device share a first active area extending along a first direction, and the second transmission gate device and the second pull-down device share a second active area extending along the first direction. A third pull-down device, a fourth pull-down device, a third transmission gate device, and a fourth transmission gate device are disposed in a second p-well on the aforementioned substrate; and A first pull-up device and a second pull-up device are disposed in an n-well, wherein the n-well is disposed between the first p-well and the second p-well, wherein a third active area of ​​the first pull-up device extends along the first direction, wherein the first active area and the second active area are separated from each other by a first interval; and the second active area and the third active area are separated from each other by a second interval greater than the first interval. The drains of the first pull-down device, the second pull-down device, and the first pull-up device are electrically coupled together via a first long contact path. The source terminals of the first pull-down device and the second pull-down device are electrically coupled together via a path of a second long contact.

36. The static random access memory cell of claim 35, wherein the ratio of the second interval to the first interval is between 1.05 and 2.

37. The static random access memory cell of claim 35, wherein: The aforementioned first active zone includes two fins; The aforementioned second active zone includes two fins; and The aforementioned third active zone includes a single fin.

38. The static random access memory cell of claim 35, wherein the first pull-down device, the second pull-down device, and the first pull-up device share a common gate structure.

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