Low density parity check coding device and method

Abstract

The present application relates to the field of 5G technology, and specifically discloses a low-density parity check coding device and method. The device includes: a remainder generation module for generating the remainder result of each matrix element in the check matrix to the lifting factor; an external storage module for storing the remainder result generated by the remainder generation module; an on-chip access control module for obtaining the remainder result at a preset time; and a cyclic accumulation module for performing a cyclic shift operation on the input data according to the remainder result. Since the remainder operation of each matrix element in the check matrix to the lifting factor is performed in advance by the remainder generation module outside the chip, when the cyclic accumulation module needs to perform a cyclic shift operation on the input data, it only needs to go through two levels of access through the external storage module and the on-chip access control module to obtain the remainder result. The whole process does not need to consume a large amount of resources and logic in the chip, thereby avoiding the overall layout and wiring congestion, while also taking into account the demand for high processing speed, thereby improving the computing rate.

Description

Technical Field

[0001] The present invention relates to the field of 5G technology, and in particular to a low-density parity check coding device and method. Background Art

[0002] LDPC (Low Density Parity Check Code) coding technology is a popular coding technology in the current local area network and metropolitan area network, wired data service interface and mobile communication fields.

[0003] LDPC codes are defined based on the parity check matrix, and the encoding and decoding processes of LDPC codes are based on the parity check matrix. In 5G LDPC coding, it is necessary to take the modulus of the lifting factor for each element in the parity check matrix, and then use the remainder to perform a cyclic shift operation on the input data. However, on-chip storage resources are very valuable, and the remainder operation consumes valuable resources and requires more additional logic, resulting in overall layout and routing congestion, which reduces the computing speed. Summary of the invention

[0004] Based on this, it is necessary to provide a low-density parity check coding device, method, electronic device and computer-readable storage medium to address the problem that in 5G LDPC coding, the operation of taking the remainder of each element in the check matrix consumes on-chip resources and additional logic, resulting in overall layout and wiring congestion and reducing the operation rate.

[0005] A low-density parity check encoding device, the device comprising:

[0006] A remainder generation module is used to generate the remainder result of each matrix element in the check matrix with respect to the lifting factor;

[0007] An external storage module, connected to the remainder generation module, and used to store the remainder result generated by the remainder generation module;

[0008] An on-chip access control module connected to the external storage module and configured to obtain the remainder result at a preset time;

[0009] The cyclic accumulation module is connected to the on-chip memory access control module and is used to perform a cyclic shift operation on the input data according to the modulo result.

[0010] In one embodiment, there are several lifting factors, and the remainder generation module is used to generate several groups of remainder results of each matrix element in the check matrix with respect to different lifting factors, and the remainder results of each matrix element in the check matrix with respect to the same lifting factor are one group of remainder results.

[0011] In one embodiment, the modulus of each matrix element in the check matrix with respect to the lifting factor is a remainder table formed by remainders obtained by modulo each matrix element with respect to the lifting factor, and the row and column arrangement order of the remainder table corresponds one-to-one to the row and column arrangement order of each matrix element in the check matrix.

[0012] In one of the embodiments, the external storage module includes an external storage unit and a storage controller;

[0013] The external storage unit includes a DDR, which is used to store the remainder result generated by the remainder generation module;

[0014] The storage controller is used to control the external storage unit to access the modulo result.

[0015] In one of the embodiments, the storage controller is used to store the remainder result generated by the remainder generation module into the external storage unit at power-on time, and is also used to retrieve the remainder result corresponding to the updated lifting factor stored in the external storage unit when the lifting factor is updated, and store it into the on-chip access control module.

[0016] In one of the embodiments, the on-chip memory access control module is used to obtain the modulo result corresponding to the updated lifting factor from the external storage module when the lifting factor is updated, and is used to store the modulo result into the loop accumulation module in a preset manner, and the preset manner includes a column-by-column storage manner.

[0017] In one embodiment, the cyclic accumulation module is used to cyclically shift the input data left n times, where n is the remainder value in the remainder table.

[0018] A low density parity check coding method, the method comprising:

[0019] Pre-generate the modulo result of each matrix element in the check matrix with respect to the lifting factor;

[0020] At the time of power-on, the modulo result of each matrix element in the check matrix with respect to the lifting factor is stored in an external storage module;

[0021] At the time of updating the boost factor configuration, obtaining the modulo result corresponding to the updated boost factor from the external storage module;

[0022] A cyclic shift operation is performed on the input data according to the modulo result.

[0023] An electronic device comprises a memory and a processor, wherein the memory stores a computer program, and the processor implements the above-mentioned low-density parity check coding method when executing the computer program.

[0024] A computer-readable storage medium stores computer instructions, and when the computer instructions are executed by a processor, the low-density parity check encoding method as described above is implemented.

[0025] The low-density parity check coding device provided by the present application includes a remainder generation module, an external storage module, an on-chip access control module and a cyclic accumulation module, wherein the remainder generation module is used to pre-generate the remainder results of each matrix element in the check matrix to the lifting factor, the external storage module is used to store the remainder results generated by the remainder generation module, the on-chip access control module is used to obtain the remainder results at a preset time, and the cyclic accumulation module performs a cyclic shift operation on the input data according to the remainder results. Since the remainder operations of each matrix element in the check matrix to the lifting factor are pre-performed by the remainder generation module outside the chip, when the cyclic accumulation module needs to perform a cyclic shift operation on the input data, it only needs to obtain the remainder results through two-level access through the external storage module and the on-chip access control module, and the whole process does not need to consume a large amount of resources and logic in the chip, thereby avoiding the overall layout and wiring congestion, while also taking into account the demand for high processing speed, thereby improving the computing rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A schematic diagram of the structure of a low-density parity-check encoding device provided in Embodiment 1 of the present application;

[0027] Figure 2 A schematic structural diagram of another implementation of the low-density parity-check encoding device provided in Example 1 of the present application;

[0028] Figure 3 A method for storing the check matrix HBG1 in an external storage unit in the low-density parity-check coding device provided in Embodiment 1 of the present application;

[0029] Figure 4 A method for storing the check matrix HBG2 in an external storage unit in the low-density parity-check coding device provided in Embodiment 1 of the present application;

[0030] Figure 5 A schematic diagram of a writing method of a chip memory access control module in a specific example;

[0031] Figure 6 A flowchart of a low-density parity-check coding method provided in Embodiment 2 of the present application;

[0032] Figure 7 This is a schematic diagram of the structure of an electronic device provided in Example 3 of the present application.

[0033] Description of reference numerals:

[0034] 100, remainder generation module; 200, external storage module; 210, external storage unit; 220, storage controller; 300, on-chip memory access control module; 400, loop accumulation module; 500, memory; 600, processor. DETAILED DESCRIPTION

[0035] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are given in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to understand the disclosure of the present invention more thoroughly and comprehensively.

[0036] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0037] The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0039] As described in the background technology, the encoding and decoding processes of LDPC codes are both based on the check matrix. For example, during the encoding process, it is necessary to perform a modulus operation on the lifting factor for each matrix element in the check matrix, and then use the remainder to perform a cyclic shift operation on the input byte data. However, since the on-chip storage resources are limited and valuable, the remainder operation will consume a large amount of on-chip resources and require a large amount of additional logic, resulting in overall layout and wiring congestion and reducing the computing speed.

[0040] To solve the above problems, the present application provides a low-density parity check coding device, method, electronic device, and computer-readable storage medium.

[0041] Embodiment 1

[0042] An embodiment of the present application provides a low-density parity-check coding device for performing low-density parity-check coding.

[0043] Reference Figure 1 The low-density parity-check coding device provided in this embodiment includes a remainder generation module 100 , an external storage module 200 , an on-chip access control module 300 , and a cyclic accumulation module 400 .

[0044] Among them, the remainder generation module 100 is used to generate the remainder result of each matrix element in the check matrix with respect to the lifting factor; the external storage module 200 is connected to the remainder generation module 100, and is used to store the remainder result generated by the remainder generation module 100; the on-chip access control module 300 is connected to the external storage module 200, and is used to obtain the remainder result at a preset time; the cyclic accumulation module 400 is connected to the on-chip access control module 300, and is used to perform a cyclic shift operation on the input data according to the remainder result.

[0045] In the low-density parity-check coding device provided in this embodiment, since the modulo operation of each matrix element in the check matrix with respect to the lifting factor is pre-performed by the off-chip remainder generation module 100, when the cyclic accumulation module 400 needs to perform a cyclic shift operation on the input data, it only needs to obtain the modulo result through two levels of access through the external storage module 200 and the on-chip access control module 300. The entire process does not need to consume a large amount of resources and logic within the chip, thereby avoiding the overall layout and wiring congestion, while also taking into account the demand for high processing speed, thereby improving the computing rate.

[0046] Among them, the remainder generation module 100 is arranged outside the chip, and the outside of the chip is the outside of the integrated circuit of the chip, that is, the remainder generation module 100 is an external device independent of the chip, and it does not occupy the internal resources of the chip. The external storage module 200 can also be arranged outside the chip to save the internal resources of the chip. The chip used in the low-density parity check encoding device in this embodiment can be selected from FPGA, that is, the remainder generation module 100 and the external storage module 200 are arranged outside the FPGA, and the on-chip access control module 300 is arranged inside the FPGA. During the encoding process, after the two-level access process of the external storage module 200 and the on-chip access control module 300, the remainder is obtained into the cyclic accumulation module, so that the cyclic accumulation module 400 performs a cyclic shift operation according to the remainder. In this process, the FPGA does not need to perform a remainder operation, which saves a lot of resources, and when there is no need for cyclic shift, the remainder pre-generated by the remainder generation module 100 will not occupy the FPGA chip resources.

[0047] In one embodiment, there are several lifting factors, and the remainder generation module 100 is used to generate several groups of remainder results of each matrix element in the check matrix with respect to different lifting factors, and the remainder results of each matrix element in the check matrix with respect to the same lifting factor are one group of remainder results.

[0048] Specifically, there can be several lifting factors. In practical applications, there can be 51 lifting factors, assuming that they can include 2, 3, 5, 7, 9, 11, etc., which are not listed here one by one. For lifting factor 2, the remainder generation module 100 will generate the remainder results of each matrix element in the check matrix to the lifting factor 2, and form a group of remainder results; for lifting factor 3, the remainder generation module 100 will generate the remainder results of each matrix element in the check matrix to the lifting factor 3, and form a group of remainder results; for lifting factor 5, the remainder generation module 100 will generate the remainder results of each matrix element in the check matrix to the lifting factor 5, and form a group of remainder results; and so on, for different lifting factors, the remainder generation module 100 will pre-generate the remainder results of the matrix elements in the check matrix to different lifting factors, and form different groups of remainder results corresponding to different lifting factors.

[0049] Obtaining several groups of remainder results for several different lifting factors in advance helps to quickly retrieve the remainder result corresponding to the currently used lifting factor from the several groups of remainder results when determining the lifting factor used for the current encoding later, thereby improving encoding efficiency.

[0050] In one embodiment, the modulus of each matrix element in the check matrix with respect to the lifting factor is a remainder table formed by remainders obtained by modulo each matrix element with respect to the lifting factor, and the row and column arrangement order of the remainder table corresponds one-to-one to the row and column arrangement order of each matrix element in the check matrix.

[0051] Among them, the elements in the check matrix are arranged in a matrix form, and each matrix element performs a modulus operation on the lifting factor to obtain a remainder, and finally obtains the same number of remainders as the matrix elements. One remainder corresponds to one matrix element, and these remainders are formed into a remainder table according to the row and column arrangement order of the matrix elements. For example, the matrix element in the 1st row and 1st column of the check matrix, the remainder obtained by taking the modulus of the lifting factor is also located in the 1st row and 1st column in the remainder table, and the matrix element in the 2nd row and 3rd column of the check matrix, the remainder obtained by taking the modulus of the lifting factor is also located in the 2nd row and 3rd column in the remainder table.

[0052] In addition, the number of check matrices may be one or two or more. When there are multiple check matrices, the above-mentioned modulo operation is performed on each check matrix, so that when the current check matrix and the lifting factor are determined during encoding, the modulo result corresponding to the current check matrix and the lifting factor can be quickly obtained.

[0053] The remainder generation module 100 is described with a specific example:

[0054] There are two check matrices, HBG1 and HBG2. HBG1 is a matrix of 46 rows and 26 columns, with 46*26 matrix elements, and HBG2 is a matrix of 42 rows and 14 columns, with 42*14 matrix elements. There are 51 lifting factors.

[0055] The 46*26 matrix elements in HBG1 are modulo 51 lifting factors to obtain 51 remainder tables. The result of taking the remainder of the 46*26 matrix elements with the same lifting factor is a remainder table with 46 rows and 26 columns. The order of the remainders in the remainder table corresponds to the order of the matrices of the corresponding matrix factors.

[0056] The 42*14 matrix elements in HBG2 are modulo 51 lifting factors to obtain 51 remainder tables. The result of taking the remainder of the 42*14 matrix elements with the same lifting factor is a remainder table with 42 rows and 14 columns. The order of the remainders in the remainder table corresponds to the matrix order of the corresponding matrix factors.

[0057] That is, a total of 102 remainder tables are generated by the remainder generation module 100 for use by subsequent modules.

[0058] In one embodiment, referring to Figure 2 , the external storage module 200 includes an external storage unit 210 and a storage controller 220;

[0059] The external storage unit 210 includes a DDR, which is used to store the remainder result generated by the remainder generation module 100;

[0060] The storage controller 220 is used to control the external storage unit 210 to access the modulo result.

[0061] DDR is a storage unit external to the FPGA chip, and has a large storage space. The advantage of the large storage space of DDR is used to store the modulo result generated by the modulo generation module 100. The storage controller 220 is used to control the access of the external storage unit 210 to the modulo result, that is, the storage controller 220 can be controlled by the FPGA chip, and obtain the generated modulo result from the modulo generation module 100 at an appropriate time, and can also send the stored modulo result to the next level access module, that is, the on-chip access control module 300 at an appropriate time. The storage controller 220 can be located inside the FPGA chip.

[0062] Take a specific example to explain the data storage structure of the modulo result inside DDR:

[0063] There are two check matrices, HBG1 and HBG2. Figure 3 is the storage method of the remainder table corresponding to the check matrix HBG1, Figure 4 This is the storage method of the remainder table corresponding to the check matrix HBG2. Figure 3 and 4 In , j represents the column number of the check matrix. For the check matrix HBG1, it has 26 columns, and the column numbers are from 0 to 25; for the check matrix HBG2, it has 14 columns, and the column numbers are from 0 to 13. Figure 3 and 4 In the formula, P stands for remainder, and the subscript consists of two numbers, the first number stands for the row number, and the second number stands for the column number, for example, P 00 Represents the remainder corresponding to the 0th row and 0th column element, P 450 Represents the remainder corresponding to the element in row 45 and column 0.

[0064] In addition, since each remainder is 9 bits wide, in order to be compatible with the 32-bit AXI bus in DDR, each 32-bit data is divided into two 16-bit data, two remainders are stored, and the upper 7 bits of each 16-bit data are padded with zeros. For the check matrix HBG1, corresponding to a lifting factor, it has a 46-row 26-row remainder table, and the size of each remainder table is 46*26 / 2*32 / 8=2392Byte. Corresponding to 51 kinds of lifting factors, 51 such remainder tables are stored. For the check matrix HBG2, corresponding to a lifting factor, it has a 42-row 14-column remainder table, but in order to be compatible with the remainder table of HBG1, 4 rows of 0 are added at the end, and the size of each remainder table is 46*14 / 2*32 / 8=1288Byte. Corresponding to 51 kinds of lifting factors, 51 such remainder tables are stored.

[0065] In one embodiment, the storage controller 220 is used to store the remainder result generated by the remainder generation module 100 into the external storage unit 210 at power-on time, and is also used to retrieve the remainder result corresponding to the updated lifting factor stored in the external storage unit 210 when the lifting factor is updated, and store it into the on-chip memory access control module 300.

[0066] That is, the storage controller 220 stores all the remainder results generated by the remainder generation module 100 in the external storage unit 210 (i.e., the first-level storage space) at the time of power-on for subsequent quick calls. When the boost factor is updated in each time slot, the remainder result corresponding to the updated boost factor is taken out from the remainder result in the external storage unit 210 and stored in the on-chip access control module 300 (i.e., the second-level storage space). Among them, time slot is a term in the 5G physical layer, which refers to a set of configured minimum time intervals. The data of each time slot corresponds to a set of parameters, that is, the boost factor needs to be updated once for each time slot. Assuming that the boost factor updated in the current time slot is 2, the remainder table obtained by performing a modulus operation on the boost factor 2 of the current check matrix is ​​taken out from the external storage unit 210.

[0067] Reference Figure 2 The on-chip access control module 300 may include a BRAM, and the modulo result corresponding to the updated lifting factor may be retrieved and stored in the BRAM.

[0068] Specifically, the method of taking out the modulo result corresponding to the updated lifting factor from the external storage unit 210 to the on-chip access control module 300 can be: 26*46 9-bit registers are set in the on-chip access control module 300, and 2 remainders are taken out from the DDR for each clock (this is because the FPGA takes data from the DDR through the AXI bus, and the data bit width used by the AXI bus of the DDR interface is 32 bits. According to the above text, 32 bits of data contain 2 remainders) and written into the register, and only the valid remainder bits in the DDR are taken out (that is, the data of the filled 0 part is removed). In this embodiment, the method of intercepting the valid bits din<={tdata[24:16], tdata[8:0]} can be adopted. For the check matrix HBG1, 26*46 / 2=598 valid clocks are required, and for the check matrix HBG2, 14*46 / 2=322 valid clocks are required.

[0069] In one of the embodiments, the on-chip memory access control module 300 is used to obtain the modulo result corresponding to the updated lifting factor from the external storage module 200 when the lifting factor is updated, and is used to store the modulo result into the loop accumulation module 400 in a preset manner, and the preset manner includes a column-by-column storage manner.

[0070] For a description of the on-chip access control module 300 acquiring the modulo result corresponding to the updated lifting factor from the external storage module 200 at the time of updating the lifting factor, please refer to the above content.

[0071] The on-chip access control module 300 can also take out the remainder result in a preset manner and send it to the cyclic accumulation module 400. In this embodiment, the column-by-column storage method is selected. Specifically, taking the remainder table with 46 rows and 26 columns as an example, 46 remainder values ​​can be taken out per clock, that is, a column of remainder values ​​is taken out at the same time, and parallel operation is realized. In this way, relatively cheap LUT resources can be used in exchange for 46 times the rate. The cyclic accumulation module 400 can perform cyclic shift operations on 46 data at the same time. It takes a total of 26 clocks to transmit the remainder table with 46 rows and 26 columns.

[0072] In one embodiment, the cyclic accumulation module 400 is used to cyclically left-shift the input data n times, where n is the remainder value in the remainder table.

[0073] The original input data is input in a single bit-by-bit manner. In practical applications, it is necessary to combine Zc (i.e., the lifting factor) input bits as the subsequent input data to be processed. According to Zc, 46 Zc_outs can be converted, such as Zc_out0, Zc_out1, Zc_out2...Zc_out45. When the on-chip access control module 300 takes out the 46 remainder values ​​of the first column at the first effective clock, the 46 input data Zc_out can be respectively subjected to the first cyclic left shift operation according to the 46 remainder values, and the number of cyclic left shifts is the corresponding remainder value; at the second effective clock, the 46 remainder values ​​of the second column are taken out, and the 46 data obtained after the last cyclic left shift are continued to be cyclically shifted to the left according to the 46 remainder values ​​of the second column, and so on, to realize the cyclic shift and accumulation operation of the input data. Among them, there can be 46 cyclic accumulation modules 400, and one cyclic accumulation module 400 is responsible for the cyclic shift operation of one input data.

[0074] The principle of the above-mentioned low-density parity check encoding device is explained below with reference to a specific example:

[0075] Taking the lifting factor Zc of the above configuration as 4 and the check matrix HBG1 as an example, the specific implementation is as follows:

[0076] At the time of booting, 102 remainder tables generated by the remainder generation module 100 are stored in the DDR, and each remainder table corresponds to a base address and a storage length.

[0077] For example, at the beginning of the current time slot, the upper layer software configures Zc as 4, and the check matrix selects HBG1. First, find the base address corresponding to the remainder table corresponding to the lifting factor Zc of 4 and the check matrix HBG1, and use the storage controller 220 to retrieve the data of length 2392Byte from the base address.

[0078] 26*46 9-bit registers are pre-defined in FPGA, namely P 00 ,P 10 ,…,P 440 ,P 450 ,P 01 ,P 11 ,…,P 4425 ,P 4525 . Write 2 remainders for each clock, and only take the valid bits in DDR. Here, the method of intercepting the valid bits is adopted, and the first clock gets P 00 ,P 10 The value of P 00 The lower 9 bits of the input data (P 00 <=tdata[8:0]), P 10 The lower 9 bits of the upper 16 bits of the input data (P 00 <=tdata[24:16]); the second clock gets P 20 ,P 30 The value of P 20 The lower 9 bits of the input data (P 20 <=tdata[8:0]), P 30 The lower 9 bits of the upper 16 bits of the input data (P 30 <=tdata[24:16]); and so on. Figure 5 As shown, HBG1 requires 26*46 / 2=598 effective clocks.

[0079] Read out: Divide into 26 read clocks rd_clk transmission, each clock transmits 46 remainder elements. Read out P at the first clock 00 ,P 10 ,…,P 450 , the second clock reads P 01 ,P 11 ,…,P 451 , and so on, the last clock (the 26th clock) reads out the last 46 remainders P 025 ,P 125 ,…,P 4525 .

[0080] Embodiment 2

[0081] The present application embodiment provides a low density parity check coding method, referring to Figure 6, the method comprises the following steps:

[0082] Step S100, pre-generate the modulo result of each matrix element in the check matrix with respect to the lifting factor;

[0083] Step S300, at the time of booting, storing the modulo result of each matrix element in the check matrix with respect to the lifting factor into the external storage module 200;

[0084] Step S500: when the lifting factor configuration is updated, a modulo result corresponding to the updated lifting factor is obtained from the external storage module 200;

[0085] Step S700: performing a cyclic shift operation on the input data according to the modulo result.

[0086] Since the modulo operation of each matrix element in the check matrix with respect to the lifting factor is performed off-chip in advance, when a cyclic shift operation is required on the input data, only two levels of access are required through the external storage module 200 and the on-chip access control module 300 to obtain the modulo result. The entire process does not require consuming a large amount of resources and logic within the chip, thereby avoiding overall layout and wiring congestion. At the same time, it also takes into account the demand for high processing speed and improves the computing speed.

[0087] The low-density parity check coding method provided in this embodiment and the low-density parity check coding device provided in Embodiment 1 belong to the same inventive concept. For the specific steps of the low-density parity check coding method, please refer to the corresponding description in Embodiment 1, which will not be repeated here.

[0088] Embodiment 3

[0089] The present application embodiment provides an electronic device, such as Figure 7 As shown, the memory 500 and the processor 600 are connected to each other in a communication manner and can be connected via a bus or other means. Figure 7 The example of connecting through bus is taken in the following.

[0090] The processor 600 may be a central processing unit (CPU). The processor 600 may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or a combination of the above chips.

[0091] The memory 500 is a non-transitory computer-readable storage medium that can be used to store non-transitory software programs, non-transitory computer executable programs and modules, such as program instructions corresponding to the low-density parity check coding method in the embodiment of the present invention. The processor 600 executes various functional applications and data processing of the processor 600, that is, the low-density parity check coding method, by running the non-transitory software programs, instructions and modules stored in the memory 500.

[0092] The memory 500 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required by at least one function; the data storage area may store data created by the processor 600, etc. In addition, the memory 500 may include a high-speed random access memory, and may also include a non-transitory memory, such as at least one disk storage device, a flash memory device, or other non-transitory solid-state storage device. In some embodiments, the memory 500 may optionally include a memory remotely arranged relative to the processor 600, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0093] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, the storage medium can be a disk, an optical disk, a read-only memory (ROM), a random access memory (RAM), a flash memory, a hard disk drive (HDD) or a solid-state drive (SSD), etc.; the storage medium can also include a combination of the above-mentioned types of memory.

[0094] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0095] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A low-density parity check coding device, characterized in that: The device comprises: A remainder generation module, used for generating a remainder result of each matrix element in the check matrix with respect to the lifting factor, wherein the remainder generation module is arranged outside the chip; An external storage module, connected to the remainder generation module, and used to store the remainder result generated by the remainder generation module; An on-chip access control module connected to the external storage module and configured to obtain the remainder result at a preset time; A cyclic accumulation module, connected to the on-chip memory access control module, configured to perform a cyclic shift operation on the input data according to the remainder result; Wherein, the external storage module includes an external storage unit and a storage controller; the external storage unit includes a DDR for storing the remainder result generated by the remainder generation module; the storage controller is used to control the access of the external storage unit to the remainder result; The storage controller is used to store the remainder result generated by the remainder generation module into the external storage unit at the time of power-on, and is also used to retrieve the remainder result corresponding to the updated lifting factor stored in the external storage unit at the time of updating the lifting factor, and store it into the on-chip access control module; The on-chip access control module is used to obtain the modulo result corresponding to the updated lifting factor from the external storage module when the lifting factor is updated, and is used to store the modulo result into the cyclic accumulation module in a preset manner, wherein the preset manner includes a column-by-column storage manner.

2. The low-density parity-check coding device according to claim 1, characterized in that: There are several lifting factors, and the remainder generation module is used to generate several groups of remainder results of each matrix element in the check matrix with respect to different lifting factors. The remainder results of each matrix element in the check matrix with respect to the same lifting factor are one group of remainder results.

3. The low-density parity-check coding device according to claim 1, characterized in that: The modulo result of each matrix element in the check matrix with respect to the lifting factor is a remainder table formed by the remainders obtained by modulo each matrix element with respect to the lifting factor, and the row and column arrangement order of the remainder table corresponds one-to-one to the row and column arrangement order of each matrix element in the check matrix.

4. The low-density parity-check coding device according to claim 3, characterized in that: The cyclic accumulation module is used for cyclically shifting the input data to the left n times, where n is the remainder value in the remainder table.

5. The low-density parity-check coding device according to claim 3, characterized in that: The boosting factors include 51 types.

6. The low-density parity-check coding device according to claim 1, characterized in that: The storage controller is arranged inside the chip.

7. The low-density parity-check coding device according to claim 1, characterized in that: The chip memory access control module includes a BRAM.

8. A low density parity check coding method, characterized in that: The method is applied to the low-density parity-check coding device according to claim 1, and the method comprises: Pre-generate the modulo result of each matrix element in the check matrix with respect to the lifting factor; At the time of power-on, the modulo result of each matrix element in the check matrix with respect to the lifting factor is stored in an external storage module; At the time of updating the boost factor configuration, obtaining the modulo result corresponding to the updated boost factor from the external storage module; A cyclic shift operation is performed on the input data according to the modulo result.

9. An electronic device, characterized in that: The method comprises a memory and a processor, wherein the memory stores a computer program, and wherein the processor implements the low-density parity-check coding method as claimed in claim 8 when executing the computer program.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and when the computer instructions are executed by a processor, the low-density parity-check encoding method according to claim 8 is implemented.

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