Managing memory operations to reduce power

Abstract

The present application relates to managing reduced power memory operations. A memory device includes a hardware suspend mechanism configured to place a component of a memory controller in a lower power mode upon completion of a memory operation. A timer is provided to wake the CPU out of the lower power mode; and a hardware interrupt may be used in determining entry into or wakeup from the lower power mode. A memory monitoring circuit system is provided to estimate the duration of a memory operation; and a timer is provided to wake up the component without a hardware interrupt or additional command.

Description

Technical Field

[0001] Embodiments described herein generally relate to systems and methods for reducing energy consumption of a memory device during memory operations by causing at least a portion of a memory controller to enter a low power mode while waiting for the memory operations to complete. Background Art

[0002] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic devices. There are many different types of memory, including volatile memory and non-volatile memory. Volatile memory requires power to maintain its data and includes various forms of random access memory (RAM), such as dynamic random access memory (DRAM) or synchronous dynamic random access memory (SDRAM), etc. Non-volatile memory can retain stored data when power is not applied (in some cases it can be implemented as read-only memory (ROM)), and can include one or more storage technologies, such as flash memory (e.g., NAND or NOR flash memory), electrically erasable programmable ROM (EEPROM), static RAM (SRAM), ferroelectric RAM (FeRAM), erasable programmable ROM (EPROM), resistance variable memory, such as phase change random access memory (PCRAM), resistance random access memory (RRAM), magnetoresistive random access memory (MRAM), or 3D XPoint TM Memory, etc.

[0003] Flash memory is used as non-volatile memory for a wide range of electronic applications. Flash memory devices typically include one or more groups of single transistor, floating gate, or charge trapping memory cells that allow high memory density, high reliability, and low power consumption. Two common types of flash memory array architectures include NAND and NOR architectures, which are named after the logical form in which the basic memory cells of each architecture are arranged. The memory cells of the memory array are typically arranged in a matrix. In an example, the gate of each floating gate memory cell in a row of the array is coupled to an access line (e.g., a word line). In the NOR architecture, the drain of each memory cell in a column of the array is coupled to a data line (e.g., a bit line). In the NAND architecture, the drain of each memory cell in a string of the array is coupled in series in a source-to-drain manner between a source line and a bit line.

[0004] Power consumption of memory devices is a common problem as memory devices are increasingly found in a variety of power-sensitive environments, such as cellular phones, tablet computers, Internet of Things (IoT) devices, and various other devices. Therefore, improvements that help increase the efficiency of power usage of memory devices can provide significant technical and practical advantages. Summary of the invention

[0005] One aspect of the present application relates to a memory device, comprising: a memory array; and a memory controller configured to receive a command from a host device, the memory controller including a processing circuit system, the processing circuit system including one or more processors, and configured to perform operations, the operations including: starting a first memory management operation in the memory array; placing at least one component in the memory controller in a lower power mode during the first memory management operation; setting a wake-up time based on a predicted completion time of the first memory management operation; and switching the memory controller out of the lower power mode when at least one of a wake-up event and expiration of the wake-up time occurs.

[0006] Another aspect of the present application relates to a method for managing power usage of a memory device, the memory device comprising a memory array and a memory controller, the memory controller being configured to receive instructions from a host device, the method comprising: initiating a first memory management operation in the memory array; placing at least one component in the memory controller in a lower power mode during the first memory management operation; setting a wake-up time based on a predicted completion time of the first memory management operation; and switching the memory controller out of the lower power mode when at least one of a wake-up event and expiration of the wake-up time occurs.

[0007] Yet another aspect of the present application relates to at least one device-readable storage medium comprising instructions which, when executed by one or more processors of a memory controller, cause the one or more processors to perform operations comprising: initiating a first memory management operation in a memory array; placing at least one component in the memory controller in a lower power mode during the first memory management operation; setting a wake-up time based on a predicted completion time of the first memory management operation; and switching the memory controller out of the lower power mode when at least one of a wake-up event and expiration of the wake-up time occurs.

[0008] Yet another aspect of the present application relates to a machine-readable medium of a machine storing instructions that, when executed, cause the machine to perform the method of managing power usage of a memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In the drawings, which are not necessarily drawn to scale, the same reference numerals may describe similar components in different views. The same numerals with different letter suffixes may represent different instances of similar components. The drawings generally illustrate various embodiments discussed in this document by way of example and not limitation.

[0010] Figure 1 A conceptual diagram illustrating an example of an environment that includes a memory device.

[0011] Figures 2 to 3is a schematic diagram showing an example of a NAND architecture semiconductor memory array.

[0012] Figure 4 is a block diagram illustrating an example of a memory module.

[0013] Figure 5 Depicted is a timing diagram illustrating programming of an example NAND device in a sample embodiment.

[0014] Figure 6 A schematic diagram depicting an example embodiment of system suspend hardware.

[0015] Figure 7 A schematic diagram depicting an example embodiment of system wakeup hardware.

[0016] Figure 8 Diagram depicting an example of suspending hardware for a multi-core system.

[0017] Fig. 9 A diagram depicting an example of waking up hardware for a multi-core system.

[0018] Fig. 10A to B show such as Figure 6 and 7 Flowchart of an example operation of the system suspend / wake hardware.

[0019] Fig.11 is a block diagram depicting an example of a machine that may incorporate the described system suspend / wake hardware and / or methods. DETAILED DESCRIPTION

[0020] The mobile device market is particularly sensitive to the overall energy consumption of mobile devices due to the limited battery capacity of mobile devices. As a result, high expectations are placed on the energy efficiency of the operation of storage devices associated with mobile devices. Various techniques have been proposed to more efficiently use energy to complete a specific set of host commands and services for data requests to and from storage devices. The systems and methods described herein provide efficient energy usage of storage devices by providing system suspend / wake operations that reduce energy consumption during time-consuming memory operations (e.g., memory programming and erase operations).

[0021] For example, programming a NAND component may require several milliseconds, depending on the number of bits per cell to be programmed; and a data erase operation may take longer, such as up to 30ms. During these operations, the physical circuitry in the memory controller, which will typically include one or more processors, may not do anything except wait for the completion of the NAND operation, which causes the memory controller to consume unnecessary energy.

[0022] Techniques for saving energy during such times when a memory device is not performing other operations except waiting for a memory operation to complete are described herein. During such "wait" times, some physical circuitry in a memory controller, in some instances a processor (or a portion of a processor, such as a core), may be placed in a lower power mode and awakened when the memory operation is completed. Such techniques will be described below in the example context of a NAND memory device.

[0023] A memory device includes a separate memory die, which may, for example, include a storage area containing one or more memory cell arrays implementing one (or more) selected storage technologies. This memory die typically includes support circuitry for operating the memory array (s). Other examples, sometimes commonly referred to as "managed memory devices," include an assembly of one or more memory dies associated with a memory controller functionality configured to control the operation of the one or more memory dies. This memory controller functionality can simplify interoperability with external devices such as a "host" discussed later herein, and further facilitate the management of (typically) multiple discrete memory devices. In such managed memory devices, the controller functionality may be implemented on one or more dies that are also incorporated into the memory array or on a separate die. In other memory devices, one or more memory devices may be combined with the memory controller functionality to form a solid-state drive (SSD) storage volume.

[0024] Example embodiments of the present disclosure are described in the example of managed memory devices implementing NAND flash memory cells referred to as "managed NAND" devices. However, these examples do not limit the scope of the present disclosure, which may be implemented by memory devices implementing other memory storage technologies, such as the non-limiting examples previously discussed herein. Managed NAND devices may be used as primary or secondary memory in various forms of electronic devices and are commonly used in mobile devices.

[0025] Each flash memory cell in a NOR or NAND architecture semiconductor memory array can be programmed to two or more programming states. For example, a single-level cell (SLC) can represent one of two programming states (e.g., 1 or 0), representing one data bit. Flash memory cells can also represent more than two programming states, allowing the manufacture of higher density memories without increasing the number of memory cells, because each cell can represent more than one binary digit (e.g., more than one bit). Such cells may be referred to as multi-state memory cells, multi-bit cells, or multi-level cells (MLC). In some instances, MLC may refer to a memory cell that can store two bits of data per cell (e.g., one of four programming states), TLC may refer to a memory cell that can store three bits of data per cell (e.g., one of eight programming states), and QLC may store four bits of data per cell. MLC is used herein in its broader context to refer to any memory cell that can store more than one bit of data per cell (i.e., it can represent more than two programming states; therefore, the term MLC is used herein in a broader context to be generally applicable to memory cells that store 2, 3, 4 or more bits of data per cell).

[0026] The managed memory device may be configured and operated in accordance with recognized industry standards. For example, the managed NAND device may be, as a non-limiting example, a Universal Flash Storage (UFS) TM ) device, embedded MMC device (eMMC TM ) and the like. For example, in the case of the above example, the UFS device may be configured according to a Joint Electronic Device Engineering Council (JEDEC) standard (e.g., JEDEC standard JESD223D, entitled “JEDEC UFS Flash Storage 3.0”, and / or an update or subsequent version of this standard). Similarly, the identified eMMC device may be configured according to JEDEC standard JESD84-A51, entitled “JEDEC eMMC standard 5.1”, and / or an update or subsequent version of this standard. The identified standards are provided only as example environments in which the described methods and structures may be utilized, but such methods and structures may be utilized in a variety of environments outside of the identified standards (or any other actual or proposed standards), unless expressly indicated herein.

[0027] SSDs can be used as primary storage for computers, etc. and offer advantages over traditional hard disk drives with moving parts in terms of, for example, performance, size, weight, durability, operating temperature range, and power consumption. For example, SSDs can have reduced seek times, latency, or other delays relative to conventional disk drives. SSDs use non-volatile memory cells, such as flash memory cells, allowing the drive to be more versatile and compact.

[0028] Both SSDs and managed memory devices may include several memory devices, including several die or logical units (e.g., logical unit numbers or LUNs), and typically include a memory controller that includes a processing circuit system that typically includes one or more processors that perform logical functions to operate the memory devices or interface with external systems. Such SSDs and managed memory devices may include one or more flash memory die that include several memory arrays and peripheral circuit systems. The flash memory array may include several blocks of memory cells organized into several physical pages. In some instances, the SSD may also include DRAM or SRAM (or other forms of memory die or other memory structures), for example as part of the controller. Similarly, a managed NAND device may include one or more arrays of volatile and / or non-volatile memory separate from the NAND storage array and within or separate from the controller. Both the SSD and the managed NAND device can receive commands associated with memory operations from the host, such as read or write operations to transfer data (e.g., user data and associated integrity data, such as error data and address data, etc.) between the memory device and the host, or erase operations to erase data from one or more memory devices.

[0029] The present embodiments will be described primarily with reference to managed NAND devices constructed and operated in accordance with the UFS standard. Although such managed NAND devices and the UFS standard represent only relevant example configurations; and the present methods and structures may be implemented with memory devices implementing other storage technologies and / or implementing other standards or operating protocols.

[0030] The present description sets forth examples of memory devices, methods, and machine-readable media for managing a memory device, the memory device including a memory controller configured to receive instructions from a host device. The memory controller is configured to perform operations including placing the memory controller in a lower power mode during a memory management operation, and in many instances, setting a wake-up time based on a predicted completion time of the memory management operation (which may be provided, for example, by a memory communication interface that communicates with a memory array). The memory controller also operates to switch the memory controller out of the lower power mode when, for example, at least one of: receiving another memory management operation; expiration of the wake-up time; and receiving an interrupt from one or more selected hardware resources. In an example embodiment, the memory array is a NAND memory array, and the memory management operation is one of: programming a portion of the NAND memory array, erasing a portion of the NAND memory array, and reading from the NAND memory array.

[0031] Figure 1 An example of environment 100 is shown, which includes a host device 105 and a memory device 110, configured to communicate via a communication interface 111. The host device 105 or the memory device 110 can be included in a variety of products 150, such as Internet of Things (IoT) devices (e.g., refrigerators or other appliances, sensors, motors or actuators, mobile communication devices, cars, drones, etc.) to support processing, communication, or control of the product 150.

[0032] Memory device 110 includes memory controller 115 and memory array 120, which includes, for example, several individual memory dies (e.g., a stack of 3D NAND dies). In an example, memory device 110 can be a discrete memory or storage device component of host device 105. In other examples, memory device 110 can be part of an integrated circuit (e.g., a system on a chip (SOC) or the like) that is stacked or otherwise included with one or more other components of host device 105. In these examples, memory device 110 communicates with host device 105 components via communication interface 111. Therefore, as described herein, even when memory device 110 is integrated into host device 105, the host or host device 105 operation is different from the operation of memory device 110.

[0033] Various forms of communication interfaces may be used to transfer data between the memory device 110 and one or more other components of the host device 105, such as a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Universal Flash Storage (UFS) interface, an eMMC interface, or a SATA 3 interface. TMinterface or one or more other connectors or interfaces. Host device 105 may include a host system, an electronic device, a processor, a memory card reader, or one or more other electronic devices external to memory device 110. In some examples, host 105 may be a Fig.11 The machine 1100 may be a machine having some or all of the components discussed above.

[0034] The memory controller 115 may receive instructions from the host 105 and may communicate with the memory array 120, such as transferring (e.g., writing) data to or from (e.g., reading) or erasing data in one or more of the memory cells, planes, sub-blocks, blocks, or pages of the memory array 120. For example, the memory controller 115 includes processing circuitry that may include one or more processors that, when present, operate to execute instructions stored in the memory devices. For purposes of this example, the instructions will be discussed as firmware, although the instructions may also be presented as software; and all or some portions of the described functionality may also be implemented in circuitry including one or more components or integrated circuits.

[0035] For example, the memory controller 115 may include one or more memory control units, circuits, or components configured to control access across the memory array 120 and provide a translation layer between the host 105 and the memory device 110. In addition, the memory controller may include a memory interface to interface with an associated memory device. In some examples, the memory interface may be an open NAND flash interface (ONFI). Although the memory controller 115 is shown herein as part of the memory device 110 package, other configurations may be employed, such as the memory controller 115 being a component of the host 105 (e.g., as a discrete package on a system on a chip of the host 105 that is separate from the memory device 110), or even implemented via a central processing unit (CPU) of the host 105.

[0036] The memory manager 125 may include a plurality of components or integrated circuits and / or instructions, etc., for performing associated with various memory management functions. In some embodiments, the functions of the memory manager 125 are implemented by a controller (or processor) executing firmware instructions, which in some instances will be stored within the memory controller 115. In other instances, the memory manager 125 may be implemented at least in part by one or more processors within the memory controller 115, which may execute instructions stored in the memory array 120. Similarly, the management table 130 may be stored in the memory controller 115 or the memory array 120. In such instances, the instructions and / or management table 130 may be stored in certain blocks of the NAND die of the memory array 120 and loaded into the working memory of the memory controller 115 during operation.

[0037] For purposes of this specification, example memory operations and management functions will be described in the context of NAND memory. Those skilled in the art will recognize that other forms of non-volatile memory may have similar memory operations or management functions. Such NAND management functions include wear leveling, garbage collection, recycling, error detection or correction, block retirement, or one or more other memory management functions. The memory manager 125 may parse or format host commands (e.g., commands received from a host) into device commands (e.g., commands associated with operation of the memory array 120, etc.), or generate device commands for the array controller 135 or one or more other components of the memory device 110 (e.g., to implement various memory management functions). Such internally generated operations, such as garbage collection, wear leveling, etc., may result in operations that may provide opportunities for power management operations as described herein being performed in the same manner as those provided by externally directed memory operations.

[0038] The memory manager 125 may include a set of management tables 130 configured to maintain various information associated with one or more components of the memory device 110 (e.g., various information related to a storage array or one or more storage units coupled to the storage controller 115). For example, the management table 130 may include information about a block age, a block erase count, an error history, or one or more error counts (e.g., a write operation error count, a read bit error count, a read operation error count, an erase error count, etc.) of one or more blocks of memory units coupled to the memory controller 115. In some instances, if the number of errors detected for one or more of the error counts is above a threshold, the bit error may be referred to as an uncorrectable bit error. The management table 130 may maintain counts of correctable or uncorrectable bit errors, etc. In an example, the management table 130 may include a translation table or a logical to physical (L2P) mapping.

[0039] Array controller 135 may include power management circuitry 145, which may include at least a portion of the processor of memory controller 115, and in selected embodiments, may include additional hardware circuitry configured to perform the power management functions described herein. As will be discussed in more detail below, these power management functions may include placing circuitry, such as a processor or processor core, into a lower power mode while NAND memory operations are being performed; and switching system circuitry out of a lower power mode in response to an event identified external to this circuitry.

[0040] The array controller 135 may also include circuitry or components configured to control operations related to writing data to, reading data from, or erasing one or more memory cells coupled to the memory controller 115 of the memory device 110. The memory operations may be based on host commands received from the host 105, for example, or generated internally by the memory manager 125 (e.g., associated with wear leveling, error detection, or correction).

[0041] The array controller 135 may also include an error correction code (ECC) component 140, which may include an ECC engine or other circuitry configured to detect or correct errors associated with writing data to or reading data from one or more memory cells of the memory device 110 coupled to the memory controller 115. The memory controller 115 may be configured to actively detect and recover from error occurrences (e.g., bit errors, operation errors, etc.) associated with various operations or storage of data based on ECC data maintained by the array controller 135. This enables the memory controller 115 to maintain the integrity of data transferred between the host 105 and the memory device 110 or to maintain the integrity of stored data. Part of this integrity maintenance may include removing (e.g., retiring) failed memory resources (e.g., memory cells, memory arrays, pages, blocks, etc.) to prevent future errors.

[0042] The memory array 120 may include a number of memory cells arranged in, for example, devices, planes, sub-blocks, blocks, or pages. As an example, a 48GB TLC NAND memory device may include 18,592 bytes (B) of data (16,384+2208 bytes) per page, 1536 pages per block, 548 blocks per plane, and 4 or more planes per device. As another example, a 32GB MLC memory device (storing two bits of data per cell (i.e., 4 programmable states)) may include 18,592 bytes (B) of data (16,384+2208 bytes) per page, 1024 pages per block, 548 blocks per plane, and 4 planes per device, but the required write time is reduced by half and the program / erase (P / E) cycle is increased by two times compared to the corresponding TLC memory device. Other examples may include other numbers or arrangements. In some examples, the memory device or a portion thereof may selectively operate in SLC mode or in a desired MLC mode (e.g., TLC, QLC, etc.).

[0043] In operation, data is typically written to or read from the NAND memory device 110 in units of pages, and erased in units of blocks. However, one or more memory operations (e.g., read, write, erase, etc.) may be performed on larger or smaller groups of memory cells as desired. The data transfer size of the NAND memory device 110 is typically referred to as a page, while the data transfer size of the host is typically referred to as a sector.

[0044] In some examples, the memory array may include several NAND dies, and one or more functions of the memory controller 115 for a particular NAND die may be implemented on an on-die controller on that particular die. Other organizations and depictions of control functions may also be utilized, such as a controller for each die, plane, superblock, block, page, etc.

[0045] Although a data page may include several bytes of user data (e.g., a data payload including several data sectors) and its corresponding metadata, the size of a page generally refers only to the number of bytes used to store the user data. For example, a data page with a page size of 4KB may include 4KB of user data (e.g., 8 sectors assuming a sector size of 512B) and several bytes (e.g., 32B, 54B, 224B, etc.) of metadata corresponding to the user data, such as integrity data (e.g., error detection or correction code data), address data (e.g., logical address data, etc.), or other metadata associated with the user data.

[0046] Different types of memory cells or memory arrays 120 may provide different page sizes or may require different amounts of metadata associated therewith. For example, different memory device types may have different bit error rates, which may result in different amounts of metadata necessary to ensure the integrity of a page of data (e.g., a memory device with a higher bit error rate may require more bytes of error correction code data than a memory device with a lower bit error rate). For example, an MLC NAND flash device may have a higher bit error rate than a corresponding SLC NAND flash device. As such, an MLC device may require more bytes of metadata for error data than a corresponding SLC device.

[0047] Figure 2 It is shown Figure 1 Schematic diagram of an example of a 3D NAND architecture semiconductor memory array 200 of a NAND memory device 110 of the type shown in FIG. 1 , including blocks (e.g., block A 201A, block B 201B, etc.) and sub-blocks (e.g., sub-block A0 201A0, sub-block A1 201A1, sub-block A2 201B, etc.) n 201A n , sub-block B0 201B0, sub-block B n 201B n etc.) are organized into a plurality of memory cell strings (eg, first to third A0 memory strings 205A0 to 207A0, first to third A n Storage string 205A n To 207A n , the first to third B0 storage strings 205B0 to 207B0, the first to third B n Storage string 205B n To 207B n Memory array 200 represents a portion of a larger number of similar structures typically found in a block, device or other unit of a memory device.

[0048] Each string of memory cells includes a source line (SRC) 235 or a source side select gate (SGS) (eg, first to third A0 SGS 231A0 to 233A0, first to third A n SGS 231A n To 233A n , 1st to 3rd B0 SGS 231B0 to 233B0, 1st to 3rd B n SGS 231B n To 233B n etc.) and the drain side select gate (SGD) (eg, the first to third A0 SGD 226A0 to 228A0, the first to third A n SGD 226A n To 228A n, 1st to 3rd B0 SGD 226B0 to 228B0, 1st to 3rd B n SGD 226B n To 228B n In the 3D memory array, a plurality of charge storage transistor layers (e.g., floating gate transistors, charge trap structures, etc.) are stacked from source to drain along the Z direction. Each string of memory cells in the 3D memory array can be arranged as a data line (e.g., bit lines (BL) BL0 to BL2 220 to 222) along the X direction and as a physical page along the Y direction.

[0049] Within a physical page, each layer represents a row of memory cells, and each memory cell string represents a column. A sub-block may include one or more physical pages. A block may include several sub-blocks (or physical pages) (e.g., 128, 256, 384, etc.). Although shown herein as having two blocks, each block has two sub-blocks, each sub-block has a single physical page, each physical page has three memory cell strings, and each string has 8 layers of memory cells. In other examples, the memory array 200 may include more or fewer blocks, sub-blocks, physical pages, memory cell strings, memory cells, or layers. For example, each memory cell string may include more or fewer layers (e.g., 16, 32, 64, 128, etc.) as needed, as well as one or more additional semiconductor material layers (e.g., select gates, data lines, etc.) above or below the charge storage transistors. For example, a 48GB TLC NAND memory device may include 18,592 bytes (B) of data per page (16,384 + 2208 bytes), 1536 pages per block, 548 blocks per plane, and 4 or more planes per device.

[0050] Each memory cell in the memory array 200 includes a control gate (CG) coupled to (e.g., electrically coupled or otherwise operably connected to) an access line (e.g., word lines (WL) WL00 to WL70 210A to 217A, WL01 to WL71 210B to 217B, etc.) that couple the control gate (CG) together across a particular layer or portion of a layer as needed. A corresponding access line may be used to access or control a particular layer in the 3D memory array, and thus a particular memory cell in a string. Various select lines may be used to access select gate groups. For example, the first to third A0 SGD 226A0 to 228A0 may be accessed using the A0 SGD line SGDA0 225A0, and the first to third A0 SGD 226A0 to 228A0 may be accessed using the A0 SGD line SGDA0 225A0. n SGD 226A n To 228A n You can use the SGD line SGDA n 225A nThe first to third B0 SGD 226B0 to 228B0 can be accessed using the B0 SGD line SGDB0 225B0, and the first to third B n SGD 226B n To 228B n You can use B n SGD LineSGDB n 225B n To access. First to third A0 SGS231A0 to 233A0 and first to third A n SGS 231A n To 233A n The first to third B0 SGS 231B0 to 233B0 and the first to third B0 SGS 231B0 to 233B0 can be accessed using the gate select line SGS0 230A. n SGS 231B n To 233B n Access is possible via gate select line SGS1230B.

[0051] In an example, the memory array 200 may include several layers of semiconductor material (e.g., polysilicon, etc.) configured to couple a control gate (CG) of each memory cell or a select gate (or a portion of a CG or a select gate) of a corresponding layer of the array. A combination of a bit line (BL) and a select gate, etc., may be used to access, select, or control a particular string of memory cells in the array, and one or more access lines (e.g., WL) may be used to access, select, or control a particular memory cell at one or more levels in the particular string.

[0052] Figure 3 An example schematic diagram showing a portion of a NAND architecture semiconductor memory array 300 including a plurality of memory cells 302 arranged in a two-dimensional array of strings (e.g., first through third strings 305 through 307) and layers (e.g., shown as respective word lines (WL) WL0 through WL7 310 through 317, drain side select gate (SGD) lines 325, source side select gate (SGS) lines 330, etc.), and a sense amplifier or similar device 360. For example, the memory array 300 may show, for example, Figure 2 An example schematic diagram of a portion of one physical page of memory cells of a 3D NAND architecture semiconductor memory device is shown in FIG.

[0053] Each string of memory cells is coupled to a source line (SRC) 335 using a corresponding source side select gate (SGS) 330 (e.g., first to third SGS 331 to 333) and is coupled to a corresponding data line (e.g., first to third bit lines (BL) BL0 to BL2 320 to 322) using a corresponding drain side select gate (SGD) (e.g., first to third SGD 326 to 328). Figure 3 The example is illustrated with eight layers (e.g., using word lines (WL) WL0 to WL7 310 to 317) and three data lines (BL0 to BL2 326 to 328), but other examples may include memory cell strings with more or fewer layers or more or fewer data lines as desired.

[0054] In a NAND architecture semiconductor memory array, such as the example memory array 300, the state of a selected memory cell 302 can be accessed by sensing a current or voltage change associated with a particular data line containing the selected memory cell. The memory array 300 can be accessed using one or more drivers (e.g., by a control circuit, one or more processors, digital logic, etc.). In an example, the one or more drivers can activate a particular memory cell or group of memory cells by driving a particular potential to one or more data lines (e.g., bit lines BL0 to BL2), access lines (e.g., word lines WL0 to WL7), or select gates, depending on the type of operation desired to be performed on the particular memory cell or group of memory cells.

[0055] In order to program or write data to a memory cell, a programming voltage (Vpgm) (e.g., one or more programming pulses, etc.) may be applied to a selected word line (e.g., WL4), and thus to the control gate of each memory cell coupled to the selected word line (e.g., the first to third control gates (CG) 341 to 343 of the memory cells coupled to WL4). The programming pulses may start at, for example, 15V or close to 15V, and in some instances may increase in magnitude during each programming pulse application. When the programming voltage is applied to the selected word line, a potential, such as a ground potential Vss, may be applied to a data line (e.g., a bit line) and a substrate (and thus, a channel between a source and a drain) of a memory cell that is a target of programming, resulting in charge transfer (e.g., direct injection or Fowler to Nordheim (FN) tunneling, etc.) from the channel to the floating gate of the target memory cell.

[0056] In contrast, the pass voltage (V PASS) is applied to one or more word lines having memory cells that are not targeted for programming, or an inhibit voltage (e.g., Vcc) may be applied to data lines (e.g., bit lines) having memory cells that are not targeted for programming, for example, to inhibit charge transfer from the channel of such non-target memory cells to the floating gate. The pass voltage may be variable, depending on, for example, the proximity of the applied pass voltage to the word lines that are targeted for programming. The inhibit voltage may include a power supply voltage (Vcc), such as a voltage relative to ground potential Vss from an external source or power supply (e.g., a battery, an AC to DC converter, etc.).

[0057] For example, if a programming voltage (e.g., 15V or higher) is applied to a particular word line, such as WL4, a pass voltage of 10V may be applied to one or more other word lines, such as WL3, WL5, etc., to inhibit programming of non-target memory cells or retain values ​​stored on such memory cells that are not targeted for programming. As the distance between the applied programming voltage and the non-target memory cells increases, the pass voltage required to inhibit programming of the non-target memory cells may decrease. For example, where a programming voltage of 15V is applied to WL4, a pass voltage of 10V may be applied to WL3 and WL5, a pass voltage of 8V may be applied to WL2 and WL6, a pass voltage of 7V may be applied to WL1 and WL7, etc. In other examples, the pass voltage or number of word lines, etc. may be higher or lower, or more or less.

[0058] A sense amplifier 360 coupled to one or more of the data lines (eg, first, second or third bit lines (BL0 to BL2) 320 to 322) can detect the state of each memory cell in the corresponding data line by sensing the voltage or current on the particular data line.

[0059] Between applying one or more programming pulses (e.g., Vpgm), a verify operation may be performed to determine whether the selected memory cell has reached its intended programming state. If the selected memory cell has reached its intended programming state, it may be inhibited from further programming. If the selected memory cell has not reached its intended programming state, additional programming pulses may be applied. If the selected memory cell has not reached its intended programming state after a certain number of programming pulses (e.g., a maximum number), the selected memory cell or a string, block, or page associated with the selected memory cell may be marked as defective.

[0060] To erase a memory cell or a group of memory cells (e.g., erasure is typically performed in blocks or sub-blocks), an erase voltage (Vers) (e.g., typically Vpgm) may be applied to the substrate (and therefore the channel, between the source and drain) of the erase target memory cell (e.g., using one or more bit lines, select gates, etc.), while the word lines of the target memory cells are maintained at a potential such as ground Vss, resulting in charge transfer from the floating gates of the target memory cells to the channels (e.g., direct injection or Fowler to Nordheim (FN) tunneling, etc.).

[0061] Figure 4 It is shown Figure 1 4 is a block diagram of an example of a memory device 400 of the type shown in , which includes a memory array 402 having a plurality of memory cells 404 and one or more circuits or components to provide communication with or perform one or more memory operations on the memory array 402. The memory device 400 may include a row decoder 412, a column decoder 414, a sense amplifier 420, a page buffer 422, a selector 424, an input / output (I / O) circuit 426, and a memory control unit 430.

[0062] The memory cells 404 of the memory array 402 may be arranged into blocks, such as a first block 402A and a second block 402B. Each block may include sub-blocks. For example, the first block 402A may include first and second sub-blocks 402A0, 402A1, 402A2, 402A3, 402A4, 402A5, 402A6, 402A7, n , and the second block 402B may include first and second sub-blocks 402B0, 402B n Each sub-block may include a number of physical pages, each page including a plurality of memory cells 404. Although shown herein as having two blocks, each block having two sub-blocks, and each sub-block having a number of memory cells 404, in other examples, the memory array 402 may include more or fewer blocks, sub-blocks, memory cells, etc. In other examples, the memory cells 404 may be arranged into a number of rows, columns, pages, sub-blocks, blocks, etc., and accessed using, for example, an access line 406, a first data line 410, or one or more select gates, source lines, etc.

[0063] The memory control unit 430 may control the memory operation of the memory device 400 according to one or more signals or instructions received on the control line 432, including, for example, one or more clock signals or control signals indicating the desired operation (e.g., write, read, erase, etc.), or address signals (A0 to AX) received on one or more address lines 416. One or more devices external to the memory device 400 may control the value of the control signal on the control line 432 or the address signal on the address line 416. Examples of devices external to the memory device 400 may include, but are not limited to, a host, a storage controller, a processor, or Figure 4 One or more circuits or components not shown.

[0064] The memory device 400 can use the access line 406 and the first data line 410 to transfer data to (e.g., write or erase) or from (e.g., read) one or more of the memory cells 404. The memory control unit 430 may include a state machine 431 coupled to the row decoder 412, the column decoder 414, and the I / O circuit 426. The state machine 431 may also output state data of the flash memory, such as READY / BUSY or PASS / FAIL. In some designs, the state machine 431 may be configured to manage the programming process. The row decoder 412 and the column decoder 414 may receive and decode the address signal (A0 to AX) from the address line 416, determine which of the memory cells 404 will be accessed, and provide the signal to one or more of the access line 406 (e.g., one or more of the plurality of word lines (WL0 to WLm)) or the first data line 410 (e.g., one or more of the plurality of bit lines (BL0 to BLn)), as described above.

[0065] The memory device 400 may include sensing circuitry, such as sense amplifiers 420, configured to determine (e.g., read) data values ​​on the memory cells 404 or determine the values ​​of data to be written using the first data line 410. For example, in a selected string of memory cells 404, one or more of the sense amplifiers 420 may read a logic level in the selected memory cell 404 in response to a read current flowing in the memory array 402 through the selected string to the data line 410.

[0066] One or more devices external to the memory device 400 may communicate with the memory device 400 using the I / O lines (DQ0 to DQN) 408, the address lines (A0 to AX) 416, or the control lines 432. Input / output (I / O) circuits 426 may transfer data values ​​into or out of the memory device 400, e.g., using the I / O lines 408, e.g., into or out of the page buffers 422 or the memory array 402 according to the control lines 432 and the address lines 416. The page buffers 422 may store data received from the one or more devices external to the memory device 400 before programming the data into the associated portions of the memory array 402, or may store data read from the memory array 402 before transmitting the data to the one or more devices external to the memory device 400.

[0067] Column decoder 414 may receive address signals (A0 to AX) 416 and decode them into one or more column select signals (CSEL1 to CSELn). Selector 424 (e.g., selection circuit) may receive column select signals (CSEL1 to CSELn) and select data in page buffer 422 representing the value of data to be read from or programmed into memory cells 404. The selected data may be transferred between page buffer 422 and I / O circuit 426 using second data line 418. In some examples, a flash translation layer (not shown) may map an address provided by a host to a physical memory address used by row decoder 412 and column decoder 414 to read data in memory array 402.

[0068] The memory control unit 430 may receive positive and negative power signals, such as a power supply voltage Vcc 434 and a ground potential Vss 436, from an external source or power supply (e.g., an internal or external battery, an AC to DC converter, etc.). In some examples, the memory control unit 430 may include a regulator 428 to provide the positive or negative power signals internally.

[0069] As described above, the systems and methods described herein provide efficient energy usage of storage devices by providing system suspend / wake-up operations that reduce energy consumption during NAND operations, especially those operations that take a lot of time, such as NAND program and NAND erase operations. For example, Figure 5 The diagram shows that in a sample embodiment, Figure 1A timing diagram 500 for programming a region of TLC memory cells of a memory device of the type described is shown. As shown, the processor (CPU) of the memory controller 115 (or at least a portion of the processor overseeing the programming operation) is substantially inactive while the NAND component performs a first pass 510 for programming a first level of TLC memory cells, waiting for completion of the NAND operation at 520. As known to those skilled in the art, programming can be accomplished in different ways, including programming through one or more pass processes for each of multiple programmed levels of MLC cells.

[0070] In many instances, once the processor has initiated a programming operation, for example, by Figure 4 The memory control unit 430 of the example memory device will process the programming to the individual NAND memory devices, which will then perform the specific physical (electrical) operations of programming on the selected areas of the memory array. Similarly, when the NAND memory device performs a second pass 530 for programming the second level of TLC cells, the processor (or portion thereof) is also substantially inactive, waiting for the NAND operation to complete at 540. Programming of a NAND page may take up to 3ms for a TLC array and up to 10ms for a QLC array; and may take up to 30ms for a data erase operation. During these operations 520 and 540, the associated processor (or portion thereof) of the NAND memory controller 115 is substantially inactive, which causes the processor of the memory controller 115 to consume unnecessary energy on the ICCQ. According to the present description, during this "wait" time, a portion of the memory controller (in many instances, at least a portion of the processor) is placed in a lower power mode and awakened when the operation is expected to complete or when another event occurs that requires the "attention" of the memory controller.

[0071] As described herein, a "lower power mode" may be any of several low power states supported by a particular memory technology and / or operating protocol. For example, the JEDEC UFS v3.0 specification supports several power states, including power-on and lower (reduced) power states, including pre-activation, activation, idle, pre-power-off, power-off, pre-sleep, and sleep. In different memory technologies, lower power states may also be referred to as dormancy, stagnation, sleep, deep stagnation, or deep sleep states. Sleep mode may include multiple low power modes, each of which uses a gradually decreasing amount of power at the expense of increased wake-up time. Similarly, a lower power mode may include a clock gating mode, in which only a portion (usually a small portion) of the entire memory controller will remain on and the rest of the memory controller may be disconnected. Therefore, as used herein, a "lower power mode" includes any condition in which one or more memory controller resources are disabled to reduce power consumption. Some lower power modes may include changing the clock rate or another performance parameter of a processor or other component.

[0072] Figure 6 A hardware diagram showing system suspend hardware 600 in an example embodiment, which may be implemented, for example, as Figure 1 The system suspend hardware 600 is used to suspend the operation of the processor (CPU 620) within the memory controller 115. The wake-up function will refer to Figure 7 Although the system suspend hardware 600 and the system wakeup hardware 700 are circuits that complement each other (and may share some components as described below), for clarity, the circuits that implement complementary functions are discussed separately with respect to these figures.

[0073] In the illustrative example, the system suspend hardware 600 includes one or more timing control units 695 to provide timing and control functions for the operating system suspend hardware 600 and the system wakeup hardware 700. The timing control unit (TCU) 695 can be implemented in a circuit system or by using a processor to execute instructions from software or firmware. In selected embodiments, the timing control unit 695 can be implemented at least in part by using a processor within a memory controller; it can be a dedicated processor / controller, or in some embodiments, a portion of the CPU 620 is not affected by the suspend operation of the system hardware 600. As described below, the TCU will typically include one or more timers that are functionally at least partially responsive to communication with the NAND communication interface 690 and the NAND status register 720, which can be, for example, a register within the NAND communication interface, but this is not required.

[0074] The system suspend hardware 600 also includes an AND gate 610 that sends a suspend signal to the memory controller's CPU 620 to suspend selected operations of the CPU and / or switch the CPU 620 to a lower power mode under selected conditions. In one example embodiment, when inputs A, B, and C are all logic 1s to the AND gate 610, an output is provided indicating that: (i) no other memory management operations have been received; (ii) the wake-up time has not expired; and (iii) no interrupts have been received from the hardware resource selected to switch the memory controller 115 into (or out of) a lower power mode during the memory management operation. In an example embodiment: (i) input A is an indication signal from the UFS interface 630 indicating that no new protocol commands have been received for the memory device 110 to process; (ii) input B is an idle register set signal 640, which is set by the TCU 695 of the system suspend hardware 600 to enable suspend operations; and (iii) input C is an input from the mask register 650 indicating that all hardware modules, such as the voltage detector 660, the universal asynchronous receiver / transmitter (UART) 670, the temperature sensor 680, and the NAND communication interface 690 are idle a, d / or in a non-error state, and the mask register 650 has not received a NAND error signal from the NAND communication interface 690. The mask register 650 can be set by a set signal 685, which is provided by the system suspend hardware 600 to select hardware resource(s) to switch the memory controller 115 into and out of a lower power mode during memory management operations. Thus, for the system suspend hardware 600 to switch the CPU 620 to a lower power mode, no new NAND commands should be received at input A, the idle register should be set at input B, and the selected hardware module(s) should be inactive at input C. Additionally, based on the predicted latency from the NAND communication interface 690 (communicating with the one or more NAND devices that are performing operations), the CPU (and / or other hardware) can be placed in an appropriate low power mode. For example, the more time there is until the next event (or if there is no event), the more aggressive the power saving mode can be.

[0075] In an example embodiment, the wake-up time of AND gate 610 is provided by TCU 695 of system suspend hardware 600, which in turn is established based on the NAND command being executed. For example, NAND communication interface 690 provides a corresponding signal to system suspend hardware 600 to determine whether the minimum sleep time has been exceeded so that there is enough time for CPU 620 to enter a lower power mode. When such time is available, TCU 695 sets a timer to establish a wake-up time for CPU 620 to return to normal operation. In an example embodiment, the wake-up timer is established by using the NAND communication interface in response to the NAND die operation of NAND memory array 120.

[0076] Those skilled in the art will appreciate that gate 610 need not be an AND gate. For example, a NAND gate may be used to output a suspend signal when each of the following is true:

[0077] a) No other memory operation: the signal will be true until the command arrives and then becomes false; b) The timer has not expired: the signal will be true until the timer expires and then becomes false; and c) There is no interrupt: the signal will be true until an interrupt occurs and then becomes false. On the other hand, each of these sub-signals can be represented in an affirmative way, most likely each is an interrupt signal: a) There is a memory operation - the signal will be false until the command arrives and then will become true; b) The timer has expired - the signal will be false until the timer is started and then becomes true; and c) There is an interrupt - the signal will be false until an interrupt occurs and then becomes true. In the latter case, an OR gate is used to issue a suspend signal. Other variations are clear to those skilled in the art.

[0078] In an example embodiment, the system suspend hardware 600TCU 695 manages the system suspend hardware 600. For example, after switching the NAND long consuming operation at input A to indicate that a time consuming NAND operation (i.e., program / erase / copy back) is being processed, if no other tasks need to be run, if the idle register is set at input B, and if no other hardware is active, the CPU 620 is placed in an idle state. The system suspend hardware 600 also configures a timer to set a wakeup time from the hardware suspend state based on a prediction of the NAND operation time provided by the NAND communication interface 690. The system suspend hardware 600 also sets a hardware mask register 650 to select the source of the hardware whose busy state gates the system suspend hardware 600 to switch the CPU 620 to a lower power mode. The system suspend hardware 600 also sets a mask register 650 to specify the source of the hardware whose interrupt should wake up the CPU 620 at the end of the lower power mode. For example, an interrupt may be a new protocol command arriving at input A, error correction (ECU) data decode completed, a UART serial communication port / protocol; a Joint Test Action Group tag (JTAG); and / or a general purpose input / output (GPIO) peripheral signal toggled at input C, a voltage level detection, etc. Hardware mask register 650 is shared with system wakeup hardware 700, as described below.

[0079] Figure 7 A hardware diagram illustrating an example implementation of system wake-up hardware 700, which in an example embodiment is provided as a memory controller 115 ( Figure 1). In the depicted example, system wake-up hardware 700 includes an OR gate 710 that wakes up CPU 620 when a timer within TCU 695 expires at input C, a new protocol command is received at input B, or a hardware interrupt is received from mask register 650 at input A indicating that any of the selected hardware components has become active and generated an interrupt. Thus, if any of the indicated conditions are met, CPU 620 is woken up and switched from a lower power mode to normal operation.

[0080] Once CPU 620 is awakened, wake-up system 700 checks whether the timer has expired or whether CPU 620 has been awakened by a hardware interrupt at input A. If CPU 620 is awakened by a timer, the CPU checks NAND status register 720 to determine whether the NAND operation has been completed. On the other hand, if CPU 620 is awakened by a hardware interrupt at input A, the 620 CPU processes the task requested by the hardware. Thereafter, CPU 620 checks whether the waiting time is still greater than the predicted remaining NAND operation time. If so, similar system hardware can be configured to re-enter system suspend mode. If there is no pending NAND operation, CPU 620 can be awakened by a hardware event.

[0081] Figure 8 A hardware diagram of an example implementation of system suspend hardware 800 for multiple processor cores (identified as CPU1 and CPU2) is shown. The system suspend hardware 800 Figure 6 The system suspend hardware 600 is combined with additional suspend circuitry, generally indicated at 805, to control the operation of CPU2 820, which may be, for example, a second processor core, but in other examples may be a second processor. In the example embodiment, the processor cores may sleep independently. Also, one processor / core may control the sleep operation of another processor / core. In the illustrated embodiment, the sleep operation of the processor / core may be controlled by the processor core. Figure 6Embodiments of the present invention replicate or share components (e.g., AND gate 810 corresponds to AND gate 610 and idle register set signal 840 corresponds to idle register set signal 640). However, the hardware state relates to the hardware state of the elements that provide input to the respective core processor, CPU 620 (CPU1) or CPU2 820. In addition, in this embodiment, multiple timers may be provided for each of the cores in response to multiple memory operations that each respective core may have initiated on the NAND memory array 120. In some instances, these multiple timers may be included within a single TCU 695; or, as depicted in the depicted example, by a separate TCU 895. Moreover, in this embodiment, the wake-up system 700 checks whether CPU1 620 is still needed after the NAND operation is started. If not, CPU1 620 enters a suspended / lower power mode. The wake-up system 700 also sets corresponding timers in the TCU 695, 895, where the desired wake-up timing is set based on the prediction of the completion of the corresponding NAND operation(s) of each core. For example, for a NAND array including four NAND dies, CPU1 may initiate a first programming operation on a first die and an erase operation on a second die; and CPU2 may initiate a second programming operation on a third die. CPU1 may receive timer settings from the NAND communication interface 690 to set multiple timers in the TCU 695, such as a first timer for the first programming operation being set to 2ms and a second timer for the erase operation being set to 10ms. However, if the second programming operation on the third die initiated by CPU2 includes substantially more data being programmed, the timer in the TCU 895 may be established at eight 8ms in response to the communication from the NAND communication interface 690. The system suspend hardware 800 may also configure the system suspend hardware 800 input mask registers 650 and 850 to select source hardware for each processor, and for each processor, the BUSY state will automatically enable the system suspend hardware 600 and 805 to enter a lower power mode. The system suspend hardware 800 can also configure the output mask register of the system suspend hardware so that the suspend signal will pass through the output mask register to select the hardware (e.g., CPU, ECU, peripheral device, etc.) that will be placed in the lower power mode. Its activity can generate an interrupt to reduce the hardware of dynamic power and set the register bit of the system suspend hardware 600 / 800 to identify that the CPU 620 / 820 and / or other components have been released and are ready to enter the lower power mode. For example, in the case where the lower power mode is a clock gating mode, the system can gate the clock to slow down or stop to save power. In this case, the "suspend" signal slows down or stops the clock or sends a signal to CPU 620 and / or CPU 830 to stop.Thus, only a small portion of the core or a portion of the memory controller external to the core will remain in the "always on" power domain, and the core can be in a lower power mode.

[0082] Fig. 9 A hardware diagram of an example system wakeup hardware 900 for a multi-core environment is shown. The system wakeup hardware 900 includes Figure 7 The system wake-up hardware 700 includes an additional wake-up hardware circuit 905. In addition, the hardware circuit includes a second OR gate 910 to provide a wake-up instruction to CPU2 820. In this embodiment, the components are duplicated or combined with Figure 7 As previously described, the mask registers 650 and 850 of the system suspend hardware 800 are each shared with the system wakeup hardware 900. In the depicted example embodiment, a single timer in the TCU 695 may be coupled to provide a corresponding timer signal as an input to each of the OR gates 710 and 910. However, in other embodiments, such as reference Figure 8 As discussed, separate timers in separate TCUs 695 and 895 may be used to provide timer signals to respective OR gates 710, 910 (or to other logic or circuitry configured to generate a wake-up signal to each CPU 620 / 820).

[0083] Fig. 10A B to B show an embodiment in which the memory controller 115 ( Figure 1 ) is an operational flow chart of a suspend / wake system implemented in accordance with an embodiment of the present invention. The depicted example is configured to place a portion of a processor in a lower power state. Although not explicitly described for clarity, additional components may be similarly placed in a lower power state by the same operation. Similarly, in lieu of a processor, other circuitry within a memory controller rather than the processor may be placed in a lower power state.

[0084] At 1000, the memory controller 115 checks whether a time-consuming NAND operation (i.e., program / erase / copy back) is being performed. This information can be used as a prediction of the NAND operation time provided by the NAND communication interface 690 for any ongoing operation. If such an operation is being processed, the memory controller 115 checks at 1010 whether any other processor tasks need to be run (such as can be implemented by executing software or firmware in this example). The determination as to whether another task needs to be run can be made relative to the entire processor, or, for example, relative to a selected core of the processor. For example, where a multi-core processor is used, in some examples, operations performed on individual memory dies in the array can be assigned to separate cores of the processor.

[0085] If no other tasks need to be run, the CPU 620 is placed in an idle state (lower power mode) at 1020 (which may result in changing the operating parameters of the entire processor, or just a portion thereof); and the (TCU 695) timer is configured at 1030 to set the wakeup time from the lower power state based on a prediction of the NAND operation time, such as may be provided by the NAND communication interface 690. As described above, based on the predicted delay in the NAND communication interface 690, the CPU 620 may be placed in an appropriate low power mode. For example, the more time there is to the next event (or if no event is pending), the more aggressive the low power mode may be. Optionally, the system mask register 650 / 850 is also set at 1040 to select a source of hardware whose busy state gates the system suspend hardware 600 to switch the CPU 620 to a lower power mode; and also optionally, may be configured at 1050 to specify a hardware source whose interrupt should wake up the CPU 620 at the end of the lower power mode. Both of these operations are optional, as in some systems the mask registers may be set independently of any individual NAND operations, such as at system boot. And / or such hardware resource(s) may be pre-established or the CPU 620 and / or TCU 695, such as at system boot or at device manufacturing.

[0086] The system wake-up hardware is monitored at 1055 (e.g., by Figure 7 The system wakeup hardware will wake up the CPU 620 upon receiving a hardware interrupt or a new NAND operation, as shown at 1060. Once awakened, the CPU 620 will identify the wakeup mechanism by determining at 1065 whether the timer has expired; and if not, determine at 1070 what hardware interrupt or new operation was received; and will process the interrupt or new operation at 1075.

[0087] If it is determined at 1065 that the timer has expired, the CPU 620 will check to determine if the NAND operation has completed, as indicated at 1080. Similarly, when the processing of the hardware interrupt or new operation is completed at 1075, the CPU will check at 1080 whether the NAND operation has completed. If it is determined that the NAND operation has completed, the CPU 620 remains awake, as indicated at 1055. If it is determined that the NAND operation has not yet completed, the CPU 620 will determine at 1090 whether the remaining time of the memory operation is greater than the remaining time on the timer (established by the TCU 695), and if so, will continue the low power mode as indicated at 1095, returning to operation 1020. If the remaining time of the memory operation is not greater than the remaining time on the timer, the CPU 620 will remain awake, as shown at 1085. It will be clear to those skilled in the art who have the benefit of this disclosure that the above method can be modified. For example, determining any type of wake-up event at 1055 can cause the CPU to be awakened at 1060.

[0088] Therefore, in an example embodiment, a hardware suspend mechanism is provided to place the processor (CPU 620) of the memory controller 115 in a lower power mode when the NAND operation is completed, rather than simply waiting for the NAND operation to complete when the processor is idle. A timer is provided to wake up the CPU 620 from the lower power mode, and a hardware mask selection enables the suspend system hardware to respond to a gating condition that affects the need for resources of the CPU 20. Therefore, by reducing the idle time of the processor and / or other processing circuit systems, the suspend system and the wake-up system cooperate to save CPU energy during NAND operations. It will also be understood that by setting a timer to predict NAND busy operations at a known duration, sleep / wake-up time and power savings can be further optimized. Similarly, where possible, the NAND system can decode and store data in a buffer and release associated resources before waking up the CPU 620, thereby allowing the CPU 620 to sleep for a longer duration.

[0089] In an example embodiment, there may be a single (or two) processors or processor cores within the memory controller 115 that execute instructions to perform operations such as Fig. 10A Some example embodiments may have a power management processor - perhaps implemented as a separate, possibly smaller processor or logic block within the memory controller 115; or alternatively implemented as a small power management core of the processor. In such an embodiment, the memory controller 115 is able to execute instructions while the main processor (which directly controls memory operations) is in a low power mode. In such an example, the main processor (e.g., CPU 620) will not be awakened unless awakened by the power management processor (or other logic structure).

[0090] Fig.11 A block diagram of an example machine 1100, such as a memory controller, on which any one or more of the techniques (e.g., methods) discussed herein may be performed is shown. For example, any memory system (main memory 1104, static memory 1106, and mass storage device 1121) within the machine 1100 may implement the above with respect to Figures 6 to 10A B to the type of memory device suspend and wake-up method described. In an alternative embodiment, the machine 1100 can be operated as an independent machine or can be connected (e.g., networked) to other machines. In a network deployment, the machine 1100 can operate in the server-client network environment with the capabilities of a server machine, a client machine, or both. In an example, the machine 1100 can act as a peer machine in a peer-to-peer (P2P) (or other distributed) network environment. The machine 1100 can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile phone, a network device, an IoT device, an automotive system, or any machine capable of executing instructions (in sequence or otherwise) specifying the actions to be taken by the machine. In addition, although only a single machine is shown, the term "machine" should also be considered to include any machine collection that executes an instruction set (or multiple instruction sets) alone or in combination to perform any one or more methods discussed herein, such as cloud computing, software as a service (SaaS), and other computer cluster configurations.

[0091] As described herein, an example may include logic, components, devices, packages or mechanisms, or may be operated by them. A circuit system is a collection of circuits (e.g., a group of circuits) implemented in a tangible entity including hardware (e.g., simple circuits, gates, logic, etc.). The membership of the circuit system may change flexibly over time and with potential hardware variability. The circuit system includes members that can perform specific tasks individually or in combination when operating. In an example, the hardware of the circuit system may be designed to perform specific operations (e.g., hardwired) invariably. In an example, the hardware of the circuit system may include variably connected physical components (e.g., execution units, transistors, simple circuits, etc.), which include computer-readable media that are physically modified (e.g., magnetic, electrical, particles of constant mass can be removably placed, etc.) to encode instructions for specific operations. When the physical components are connected, the basic electrical properties of the hardware components will change, such as from an insulator to a conductor, and vice versa. The instructions enable the participating hardware (e.g., execution units or loading mechanisms) to create members of the circuit system in hardware via variable connections to perform a part of a specific task when operating. Thus, when the apparatus is operating, the computer-readable medium is communicatively coupled to other components of the circuit system. In an example, any physical component can be used in more than one member of more than one circuit system. For example, in operation, an execution unit can be used in a first circuit of a first circuit system at one point in time, and can be reused by a second circuit in the first circuit system or a third circuit in the second circuit system at a different time.

[0092] The machine (e.g., computer system) 1100 (e.g., host device 105, memory device 110, etc.) may include a hardware processor 1102 (e.g., a CPU, a graphics processing unit (GPU), a hardware processor core, or any combination thereof, such as a memory controller 115, etc.), a main memory 1104, and a static memory 1106, some or all of which may communicate with each other via an interconnect (e.g., a bus) 1108. The machine 1100 may also include a display unit 1110, an alphanumeric input device 1112 (e.g., a keyboard), and a user interface (UI) navigation device 1114 (e.g., a mouse). In an example, the display unit 1110, the input device 1112, and the UI navigation device 1114 may be a touch screen display. The machine 1100 may also include a signal generating device 1118 (e.g., a speaker), a network interface device 1120, and one or more sensors 1116, such as a global positioning system (GPS) sensor, a compass, an accelerometer, or other sensors. The machine 1100 may include an output controller 1128, such as a serial (e.g., USB, parallel or other wired or wireless (e.g., infrared (IR), near field communication (NFC)), etc.) connection to communicate with or control one or more peripheral devices (e.g., a printer, a card reader, etc.).

[0093] The machine 1100 may include a machine-readable medium 1122 on which is stored one or more sets of data structures or instructions 1124 (e.g., firmware or software) that embody or are used by any one or more of the techniques or functions described herein. During execution of the instructions 1124 by the machine 1100, the instructions may also reside, in whole or in part, within the main memory 1104, within the static memory 1106, or within the hardware processor 1102. In an example, one or any combination of the hardware processor 1102, the main memory 1104, or the static memory 1106 may constitute the machine-readable medium 1122.

[0094] Although the machine-readable medium 1122 is illustrated as a single medium, the term “machine-readable medium” may include a single medium or multiple media (eg, a centralized or distributed database, or associated caches and servers) configured to store one or more instructions 1124 .

[0095] The term "machine-readable medium" may include any medium capable of storing or encoding instructions for execution by the machine 1100 and causing the machine 1100 to perform any one or more techniques of the present disclosure, or any medium capable of storing, encoding, or carrying data structures used by or associated with such instructions. Non-limiting examples of machine-readable media include solid-state memory and optical and magnetic media. In an example, a mass machine-readable medium comprises a machine-readable medium having a plurality of particles with a constant (e.g., stationary) mass. Therefore, a mass machine-readable medium is not a transient propagating signal. Specific examples of mass machine-readable media may include: non-volatile memory, such as semiconductor memory devices (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)) and flash memory devices; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

[0096] Instructions 1124 (e.g., software, programs, operating systems (OS), etc.) or other data are stored on storage 1121 and can be accessed by memory 1104 for use by processor 1102. Memory 1104 (e.g., DRAM) is typically fast, but volatile, and is therefore a different type of storage device (e.g., SSD) than mass storage 1121, which is suitable for long-term storage, including in an "off" state. Instructions 1124 or data used by a user or machine 1100 are typically loaded into memory 1104 for use by processor 1102. When memory 1104 is full, virtual space from mass storage 1121 can be allocated to supplement memory 1104; however, because mass storage 1121 devices are typically slower than memory 1104, and write speeds are typically at least twice as slow as read speeds, the use of virtual memory can significantly reduce the user experience due to storage device latency (compared to memory 1104, such as DRAM). Furthermore, using the mass storage device 1121 for virtual memory may significantly reduce the useful life of the mass storage device 1121 .

[0097] Compared to virtual memory, in order to avoid paging of mass storage device 1121, virtual memory compression (e.g. The kernel feature "ZRAM") uses part of the memory as compressed block storage. Paging is done in compressed blocks until such data must be written to the mass storage device 1121. Virtual memory compression increases the available size of the memory 1104 while reducing wear on the mass storage device 1121.

[0098] Storage devices optimized for mobile electronic devices, or removable storage, traditionally include MMC solid-state storage devices (e.g., micro Secure Digital (microSD TM ) card, etc.). MMC devices include several parallel interfaces (e.g., 8-bit parallel interfaces) with the host device and are usually removable and separate components from the host device. In contrast, eMMC TM The device is attached to the circuit board and is considered a component of the host device, with read speeds comparable to Serial ATA based SSD devices. TM (Serial AT (Advanced Technology) Connection or SATA). However, the demand for mobile device performance continues to increase, such as to fully enable virtual devices or augmented reality devices, take advantage of increased network speeds, etc. In response to this demand, storage devices have moved from parallel communication interfaces to serial communication interfaces. UFS devices, including controllers and firmware, communicate with host devices using a low voltage differential signaling (LVDS) serial interface with dedicated read / write paths, further promoting higher read / write speeds.

[0099] The instructions 1124 may also be transmitted or received over the communication network 1126 using a transmission medium via the network interface device 1120 using any of a number of transmission protocols (e.g., frame relay, Internet Protocol (IP), transmission control protocol (TCP), user datagram protocol (UDP), hypertext transfer protocol (HTTP), etc.). Example communication networks may include a local area network (LAN), a wide area network (WAN), a packet data network (e.g., the Internet), a mobile telephone network (e.g., a cellular network), a plain old telephone (POTS) network, and a wireless data network (e.g., a wireless network called a cellular network). The Institute of Electrical and Electronics Engineers (IEEE) 802.11 series of standards, known as 16 series of standards), IEEE 802.15.4 family of standards, P2P networks, etc. In an example, the network interface device 1120 may include one or more physical jacks (e.g., Ethernet, coaxial, or telephone jacks) or one or more antennas to connect to the communication network 1126. In an example, the network interface device 1120 may include multiple antennas to use at least one of single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO) technology for wireless communication.

[0100] The term "transmission medium" shall be taken to include any intangible medium that is capable of storing, encoding or carrying instructions to be executed by the machine 1100, and includes digital or analog communications signals or other intangible medium to facilitate communication of such software.

[0101] In order to better illustrate the methods and apparatus described herein, a set of non-limiting example embodiments are listed below as numerically identified examples.

[0102] Example 1 is a memory device comprising: a memory array; and a memory controller configured to receive a command from a host device, the memory controller including a processing circuit system, the processing circuit system including one or more processors and configured to perform operations, the operations including: initiating a first memory management operation in the memory array; placing at least one component in the memory controller in a lower power mode during the first memory management operation; setting a wake-up time based on a predicted completion time of the first memory management operation; and switching the memory controller out of the lower power mode when at least one of a wake-up event and expiration of the wake-up time occurs.

[0103] In Example 2, the subject matter of Example 1, wherein the memory array is a NAND memory array, and the memory management operation is a NAND memory management operation.

[0104] In Example 3, the subject matter of Example 2, wherein the NAND memory management operation is one of programming of the NAND memory array, erasing of the NAND memory array, and reading of the NAND memory array.

[0105] In Example 4, the subject matter of any one or more of Examples 1-3, wherein the wake event includes: requesting a second memory operation at the memory controller.

[0106] In example 5, the subject matter of example 4, wherein the request for a second memory operation is received at the memory controller from a host.

[0107] In Example 6, the subject matter of any one or more of Examples 4-5, wherein the request by the memory controller for a second memory operation is generated in the memory controller.

[0108] In Example 7, any one or more of the subject matter of Examples 1-6, wherein the wake event comprises a hardware interrupt from a specified hardware component.

[0109] In Example 8, the subject matter of any one or more of Examples 1-7, wherein placing the memory controller in the lower power mode includes: providing a suspend signal to the memory controller when no other memory management operations are received and no interrupts are received from hardware resources designated to switch the memory controller into and out of the lower power mode.

[0110] In Example 9, the subject matter of any one or more of Examples 1 to 8, wherein placing the memory controller in the lower power mode includes: outputting a suspend signal to the memory controller from a gate that receives at input at least an indication of whether another memory management operation has been received, an indication of whether the wake-up time has expired, and an indication of whether an interrupt has been received from the hardware resource designated to switch the memory controller into and out of the lower power mode.

[0111] In Example 10, the subject matter of any one or more of Examples 1 to 9, wherein setting the wake-up time includes: receiving the predicted completion time of the memory management operation from an interface that communicates with the memory array; and entering a selected power saving mode based on the predicted completion time of the memory management operation.

[0112] In example 11, the subject matter of example 10, wherein the selected power saving mode is selected from a plurality of possible power saving modes responsive at least in part to the predicted completion time of the first memory management operation.

[0113] In Example 12, the subject matter of any one or more of Examples 1-11, wherein switching the memory controller out of the lower power mode upon receiving at least one of the wake-up event or timer expiration includes: providing a wake-up signal to the component of the memory controller in the lower power mode.

[0114] In Example 13, the subject matter of Example 12, wherein switching the memory controller out of the lower power mode includes: outputting the wake-up signal to the memory controller from an OR gate that receives at input at least an indication of whether another memory management operation has been received, an indication of whether the wake-up time has expired, and an indication of whether an interrupt has been received from a hardware resource designated to switch the memory controller into and out of the lower power mode.

[0115] In Example 14, any one or more of the subject matter of Examples 1-13 optionally includes a status register indicating a status of the first memory management operation.

[0116] In Example 15, the subject matter of Example 14, wherein the memory controller operation further includes: determining whether the wake-up time has expired, and checking the status register to determine whether the first memory management operation has been completed; and, when the wake-up time expires or the first memory management operation is completed, switching at least one component in the memory controller out of the lower power mode.

[0117] In Example 16, the subject matter of Example 15, wherein when the memory controller determines whether the interrupt has been received, the memory controller also executes instructions to process the task requested by the interrupt, and then checks whether the memory management operation has been completed, and when completed, switches the memory controller out of the lower power mode.

[0118] In Example 17, the subject matter of any one or more of Examples 1-16, wherein the memory controller includes at least two processors, wherein a first processor executes instructions to perform suspend / wake operations of the at least two processors.

[0119] Example 18 is a method for managing power usage of a memory device, the memory device comprising a memory array and a memory controller, the memory controller being configured to receive instructions from a host device, the method comprising: initiating a first memory management operation in the memory array; placing at least one component in the memory controller in a lower power mode during the first memory management operation; setting a wake-up time based on a predicted completion time of the first memory management operation; and switching the memory controller out of the lower power mode when at least one of a wake-up event and expiration of the wake-up time occurs.

[0120] In Example 19, the subject matter of Example 18, wherein the memory array is a NAND memory array, and placing the memory controller in a lower power mode during memory management operations includes placing the memory controller in a lower power mode during one of programming of the NAND memory array, erasing of the NAND memory array, and reading of the NAND memory array.

[0121] In Example 20, the subject matter of any one or more of Examples 18-19, wherein placing the memory controller in a lower power mode includes: providing a suspend signal to the memory controller during the memory management operation when no other memory management operations are received, the wake-up time has not expired, and no interrupts are received from a hardware resource selected to switch the memory controller into and out of the lower power mode.

[0122] In Example 21, the subject matter of Example 20, wherein placing the memory controller in the lower power mode includes: during the memory management operation, outputting the suspend signal to the memory controller from a gate that receives at input at least an indication of whether another memory management operation has been received, an indication of whether the wake-up time has expired, and an indication of whether an interrupt has been received from the hardware resource selected to switch the memory controller into and out of the lower power mode.

[0123] In Example 22, the subject matter of any one or more of Examples 18 to 21, wherein setting the wake-up time includes: receiving the predicted completion time of the memory management operation from a memory communication interface that communicates with the memory array, and based on the predicted completion time of the memory management operation, entering a more aggressive power saving mode during a longer predicted completion time of the memory management operation.

[0124] In Example 23, the subject matter of any one or more of Examples 18-22, wherein the memory array comprises a plurality of memory die, and wherein setting the wake-up time based on the predicted completion time of the memory management operation comprises: setting separate wake-up times for different memory operations being performed by the respective memory dies.

[0125] In Example 24, the subject matter of any one or more of Examples 18 to 23, wherein switching the memory controller out of the lower power mode upon at least one of receiving another memory management operation, expiring the wake-up time, and receiving an interrupt from a hardware resource selected to switch the memory controller into and out of the lower power mode includes: during the memory management operation, when another memory management operation has been received, the wake-up time has expired, and an interrupt has been received from a hardware resource selected to switch the memory controller into and out of the lower power mode, providing a wake-up signal to the memory controller.

[0126] In Example 25, the subject matter of Example 24, wherein switching the memory controller out of the lower power mode includes: during the memory management operation, outputting the wake-up signal to the memory controller from an OR gate that receives at input at least an indication of whether another memory management operation has been received, an indication of whether the wake-up time has expired, and an indication of whether an interrupt has been received from a hardware resource selected to switch the memory controller into and out of the lower power mode.

[0127] In Example 26, the subject matter of any one or more of Examples 24 to 25 optionally includes: when the wake-up time has expired, checking a status register indicating the status of the memory management operation to determine whether the memory management operation has been completed, and when completed, switching the memory controller out of the lower power mode.

[0128] In Example 27, the subject matter of any one or more of Examples 24 to 26 optionally includes: when an interrupt has been received, processing the task requested by the interrupt, then checking whether the memory management operation has been completed, and when completed, switching the memory controller out of the lower power mode.

[0129] Example 28 is at least one non-transitory device-readable storage medium comprising instructions that, when executed by one or more processors of a memory controller, cause the one or more processors to perform operations comprising: initiating a first memory management operation in a memory array; placing at least one component in the memory controller in a lower power mode during the first memory management operation; setting a wake-up time based on a predicted completion time of the first memory management operation; and switching the memory controller out of the lower power mode when at least one of a wake-up event and expiration of the wake-up time occurs.

[0130] In Example 29, according to the subject matter of Example 28, wherein the storage system includes a NAND memory array, the medium further includes instructions for placing the memory controller in a lower power mode during the memory management operation by placing the memory controller in a lower power mode during one of programming the NAND memory array, erasing the NAND memory array, and reading the NAND memory array.

[0131] In Example 30, the subject matter of any one or more of Examples 28 to 29 may optionally include instructions for placing the memory controller in the lower power mode by providing a suspend signal to the memory controller during the memory management operation when no other memory management operations are received, the wake-up time has not expired, and no interrupts are received from hardware resources selected to switch the memory controller into and out of the lower power mode.

[0132] In Example 31, the subject matter of any one or more of Examples 29 to 30 optionally includes instructions for placing the memory controller in the lower power mode by outputting the suspend signal to the memory controller from a gate that receives at input at least an indication of whether another memory management operation has been received, an indication of whether the wake-up time has expired, and an indication of whether an interrupt has been received from the hardware resource selected to switch the memory controller into and out of the lower power mode.

[0133] In Example 32, the subject matter of any one or more of Examples 28 to 31 optionally includes instructions for receiving the predicted completion time of the memory management operation from a memory communication interface that communicates with the memory array, and for setting the wake-up time by entering a more aggressive power saving mode at a longer predicted completion time of the memory management operation based on the predicted completion time of the memory management operation.

[0134] In Example 33, according to the subject matter of any one or more of Examples 28 to 32, wherein the storage system includes multiple memory tube cores, the subject matter further includes instructions for setting the wake-up time based on the predicted completion time of the memory management operation by setting separate wake-up times for different memory operations being performed by the corresponding memory tube cores.

[0135] In Example 34, the subject matter of any one or more of Examples 28 to 33 optionally includes instructions for switching the memory controller out of the lower power mode when at least one of another memory management operation has been received, the wake-up time has expired, and an interrupt has been received from a hardware resource selected to switch the memory controller into and out of the lower power mode is received by providing a wake-up signal to the memory controller during the memory management operation to switch the memory controller out of the lower power mode when at least one of another memory management operation has been received, the wake-up time has expired, and an interrupt has been received from a hardware resource selected to switch the memory controller into and out of the lower power mode.

[0136] In Example 35, the subject matter of Example 34 may optionally include instructions for switching the memory controller out of the lower power mode by outputting the wake-up signal to the memory controller from an OR gate that receives at input at least an indication of whether another memory management operation has been received, an indication of whether the wake-up time has expired, and an indication of whether an interrupt has been received from a hardware resource selected to switch the memory controller into and out of the lower power mode during the memory management operation.

[0137] In Example 36, the subject matter of any one or more of Examples 34 to 35 optionally includes instructions for, when a wake-up time has expired, checking a status register indicating a status of the memory management operation to determine whether the memory management operation has been completed, and when completed, switching the memory controller out of the lower power mode.

[0138] In Example 37, the subject matter of any one or more of Examples 34 to 36 may optionally include instructions for, when an interrupt has been received, processing a task requested by the interrupt, then checking whether the memory management operation has been completed, and when completed, switching the memory controller out of the lower power mode.

[0139] In Example 38, the memory device of any of Examples 1-17 may incorporate structure, features, or functionality found in one or more other examples of Examples 1-17.

[0140] In Example 39, the memory device of any of Examples 1-17 may be configured to perform any of the methods of Examples 18-27.

[0141] In Example 40, the memory device of any of Examples 1-17 may be incorporated into any of the machine-readable media of Examples 28-37.

[0142] In Example 41, any of the methods of Examples 18 to 27 may be adapted to be performed by using a memory device according to any of Examples 1 to 17.

[0143] Example 42, any method of implementing 18-27 may be adapted to include operations or functions identified in one or more other examples of examples 18-27.

[0144] In Example 43, the machine-readable medium of any of Examples 28 to 37 may be suitable for performing any of the methods of Examples 18 to 27.

[0145] In Example 44, any memory device of Examples 1-17 may include the non-transitory device-readable storage medium of Examples 28-37 configured to store instructions executable to perform one or more operations of the memory device.

[0146] In Example 45, any memory device of Examples 1-17 can be incorporated into an electronic system that also includes a host processor and a communication bus extending between the host processor and the memory device.

[0147] In Example 46, any of the methods of Examples 18 to 27 may be performed by an electronic system including a host processor and a communication interface extending between the host processor and the memory device.

[0148] The above detailed description includes reference to the accompanying drawings, which form a part of the detailed description. The accompanying drawings show by way of illustration specific embodiments in which the systems and methods described herein can be practiced. These embodiments are also referred to as "examples" herein. Such examples may include elements other than those shown or described. However, the inventors have also contemplated that only examples of those elements shown or described are provided. In addition, the inventors also contemplate using any combination or permuted examples of those elements (or one or more aspects thereof) shown or described relative to the specific examples (or one or more aspects thereof) shown or described herein, or relative to other examples (or one or more aspects thereof).

[0149] In this document, as commonly used in patent documents, the terms "a" or "an" are used to include one or more than one, independent of any other instances or uses of "at least one" or "one or more". In this document, unless otherwise stated, the term "or" is used to refer to a non-exclusive or, such that "A or B" may include "A but not B", "B but not A", and "A and B". In the appended claims, the terms "including" and "among which" are used as the plain English equivalents of the respective terms "comprising" and "wherein". In addition, in the appended claims, the terms "including" and "comprising" are open-ended, that is, systems, devices, articles, or processes that include elements other than those listed after the term in the claim are still considered to fall within the scope of the claim. In addition, in the appended claims, the terms "first", "second", and "third", etc. are used merely as labels and are not intended to impose numerical requirements on their objects.

[0150] In various examples, the components, controllers, processors, units, engines, or tables described herein may include physical circuitry or firmware stored on a physical device, etc. As used herein, "processor" means any type of computing circuit, such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor (DSP), or any other type of processor or processing circuit, including a group of processors or a multi-core device.

[0151] Various embodiments according to the present disclosure and described herein include memories utilizing memory cells (e.g., NAND strings of memory cells) in vertical structures. As used herein, orientation adjectives are applied relative to the surface of the substrate on which the memory cells are formed (i.e., the vertical structures are considered to extend away from the substrate surface, the bottom of the vertical structures are considered to be the end closest to the substrate surface, and the top of the vertical structures are considered to be the end farthest from the substrate surface).

[0152] As used herein, operating a memory cell includes reading from the memory cell, writing to the memory cell, or erasing the memory cell. The operation of placing a memory cell in a desired state is referred to herein as "programming" and may include writing to a memory cell and / or clearing from a memory cell (e.g., a memory cell may be programmed to an erased state).

[0153] According to one or more embodiments of the present disclosure, a memory controller (e.g., a processor, a controller, firmware, etc.) located inside or outside a memory device is capable of determining (e.g., selecting, setting, adjusting, calculating, changing, clearing, communicating, adapting, deriving, defining, utilizing, modifying, applying, etc.) the number of wear cycles or the wear state (e.g., recording the wear cycles, counting the operations of the memory device when the wear cycles occur, tracking the operations of the memory system initiated by them, evaluating the characteristics of the memory device corresponding to the wear state, etc.).

[0154] According to one or more embodiments of the present disclosure, a memory access device may be configured to provide wear cycle information to a memory device with each memory operation. A memory device control circuit system (e.g., control logic) may be programmed to compensate for memory device performance changes corresponding to the wear cycle information. The memory device may receive the wear cycle information and determine one or more operating parameters (e.g., values, characteristics) in response to the wear cycle information.

[0155] It should be understood that when an element is referred to as being "on," "connected to," or "coupled to" another element, it can be directly on, connected to, or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element, there are no intervening elements or layers. If two elements are shown as being connected by a line in a drawing, the two elements may be coupled or directly coupled unless otherwise indicated.

[0156] The method examples described herein may be implemented at least in part by a machine or computer. Some examples may include a computer-readable medium or machine-readable medium encoded with instructions, which are operable to configure an electronic device to perform the methods described in the above examples. The embodiments of these methods may include codes such as microcode, assembly language code, high-level language code, etc. This code may include computer-readable instructions for performing various methods. The code may form part of a computer program product. In addition, the code may be tangibly stored on one or more volatile or non-volatile tangible computer-readable media, such as during execution or at other times. Examples of these tangible computer-readable media may include, but are not limited to, hard disks, removable disks, removable optical disks (e.g., CDs and DVDs), cassettes, memory cards or sticks, RAM, ROM, SSDs, UFS devices, eMMC devices, etc.

[0157] The above description is intended to be illustrative, not restrictive. For example, the above examples (or one or more aspects thereof) can be used in combination with each other. Other embodiments may be used, as used by those of ordinary skill in the art when reading the above description. It should be understood that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the above detailed description, various features may be combined together to simplify the present disclosure. This should not be interpreted as meaning that the disclosed features that are not claimed for protection are essential to any claim. On the contrary, the subject matter of the invention may be less than all the features of a specific disclosed embodiment. Therefore, the attached claims are thus incorporated into the specific detailed description, wherein each claim is independently used as a separate embodiment, and it is expected that such embodiments can be combined with each other in various combinations or arrangements. The scope of the present invention should be determined with reference to the attached claims and the full scope of equivalents given by these claims.

Claims

1. A memory device, comprising: NAND memory array; and A memory controller configured to receive commands from a host device, the memory controller comprising processing circuitry including one or more processors and configured to perform operations comprising: initiating a first NAND memory management operation in the NAND memory array, the first NAND memory management operation comprising at least one of: programming a portion of the NAND memory array, erasing a portion of the NAND memory array, and reading from the NAND memory array; After initiating the first NAND memory management operation, determining whether other memory operations are pending; placing at least one component in the memory controller in a lower power mode during the first NAND memory management operation upon determining that no other memory operations are pending; Setting a wake-up time based on a predicted completion time of the first NAND memory management operation comprises: receiving a predicted completion time of said first NAND memory management operation from an interface in communication with said NAND memory array; as well as entering a selected power saving mode based on the predicted completion time of the first NAND memory management operation; as well as When at least one of a wake-up event and expiration of the wake-up time occurs, the at least one component in the memory controller is switched out of the lower power mode.

2. The memory device of claim 1, wherein the wake event comprises: requesting a second memory operation at the memory controller.

3. The memory device of claim 2, wherein the request for a second memory operation is received at the memory controller from a host. 4 . The memory device of claim 2 , wherein the request by the memory controller for a second memory operation is generated in the memory controller.

5. The memory device of claim 1, wherein the wake event comprises a hardware interrupt from a specified hardware component.

6. The memory device of claim 1 , wherein placing the memory controller in the lower power mode comprises providing a suspend signal to the memory controller when no other memory management operations are received and no interrupts are received from a hardware resource designated to switch the memory controller into and out of the lower power mode.

7. The memory device of claim 1 , wherein placing the memory controller in the lower power mode comprises: outputting a suspend signal to the memory controller from a gate that receives at least the following signals at input: whether an indication of another memory management operation has been received, an indication of whether the wake-up time has expired, and An indication of whether an interrupt has been received from a hardware resource designated to switch the at least one component in the memory controller into and out of the lower power mode.

8. The memory device of claim 1, wherein the selected power saving mode is selected from a plurality of possible power saving modes responsive at least in part to the predicted completion time of the first NAND memory management operation.

9. The memory device of claim 1, further comprising: a status register indicating a status of the first NAND memory management operation.

10. The memory device of claim 9, wherein the memory controller operations further comprise: determining whether the wake-up time has expired, and checking the status register to determine whether the first NAND memory management operation has completed; and, Upon expiration of the wake-up time or completion of the first NAND memory management operation, switching the at least one component in the memory controller out of the lower power mode.

11. The memory device of claim 10, wherein when the memory controller determines whether an interrupt has been received, the memory controller also executes instructions to process a task requested by the interrupt and then checks whether the first NAND memory management operation has been completed, and when completed, switches the at least one component in the memory controller out of the lower power mode.

12. A method of managing power usage of a memory device, the memory device comprising a NAND memory array and a memory controller, the memory controller being configured to receive instructions from a host device, the method comprising: Initiating a first memory management operation in the NAND memory array, the first memory management operation comprising at least one of: programming the NAND memory array, erasing the NAND memory array, and reading the NAND memory array; placing at least one component in the memory controller into a lower power mode during the first memory management operation; Setting a wake-up time based on a predicted completion time of the first memory management operation comprises: receiving the predicted completion time of the first memory management operation from a memory communication interface in communication with the NAND memory array, and based on the predicted completion time of the first memory management operation, entering one of a plurality of power saving modes in response to a length of the predicted completion time of the first memory management operation; as well as When at least one of a wake-up event and expiration of the wake-up time occurs, the at least one component in the memory controller is switched out of a lower power mode.

13. The method of claim 12 , wherein placing the memory controller in the lower power mode comprises providing a suspend signal to the memory controller during the first memory management operation when no other memory management operations are received, the wake-up time has not expired, and no interrupts are received from a hardware resource selected to switch the at least one component in the memory controller into and out of the lower power mode.

14. The method of claim 13 , wherein placing the memory controller in the lower power mode comprises, during the first memory management operation, outputting the suspend signal to the memory controller from a gate that receives at input at least an indication of whether another memory management operation has been received, an indication of whether the wake-up time has expired, and an indication of whether an interrupt has been received from the hardware resource selected to switch the at least one component in the memory controller into and out of the low power mode.

15. The method of claim 12, wherein the NAND memory array comprises a plurality of memory dies, and wherein setting a wake-up time based on a predicted completion time of the first memory management operation comprises setting separate wake-up times for different memory operations being performed by respective memory dies.

16. At least one non-transitory device-readable storage medium comprising instructions that, when executed by one or more processors of a memory controller, cause the one or more processors to perform operations comprising: initiating a first NAND memory management operation in a NAND memory array, the first NAND memory management operation comprising at least one of: programming the NAND memory array, erasing the NAND memory array, and reading the NAND memory array; Placing at least one component in the memory controller into a lower power mode during the first NAND memory management operation, comprising: receiving a predicted completion time of the first NAND memory management operation from a memory communication interface in communication with the NAND memory array, and entering one of a plurality of power saving modes in response to a length of the predicted completion time of the first NAND memory management operation based on the predicted completion time of the first NAND memory management operation; setting a wake-up time based on a predicted completion time of the first NAND memory management operation; and When at least one of a wake-up event and expiration of the wake-up time occurs, the at least one component in the memory controller is switched out of the lower power mode.

17. The medium of claim 16 further comprising instructions for placing the memory controller in the lower power mode by providing a suspend signal to the memory controller during the first NAND memory management operation when no other memory management operations are received, the wake-up time has not expired, and no interrupts are received from a hardware resource selected to switch the at least one component in the memory controller into and out of the lower power mode.

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