Restoration of damaged storage components in memory devices

Abstract

Devices and techniques for recovering damaged storage portions in a memory device are described herein. During a garbage collection operation on a collection of storage portions (e.g., pages) in a memory array, a failure event is detected. Here, members of the collection of storage portions are moved from previous physical locations to new physical locations by the garbage collection operation. In response to the failure event, a reference to the previous physical location of a potentially damaged storage portion in the collection of storage portions can be retrieved. Here, as part of the garbage collection operation, the potentially damaged storage portion has been written to the new physical location. The potentially damaged storage portion can then be overwritten at the new physical location using data from the previous physical location.

Description

Technical Field

[0001]

[0014] Embodiments described herein generally relate to recovering data from a memory device.The following examples generally address data corruption that results when valid data from one block is being moved to another block during garbage collection. Background Art

[0002] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic devices.There are many different types of memory, including volatile and non-volatile memory.

[0003] Volatile memory requires power to maintain its data and includes random access memory (RAM), dynamic random access memory (DRAM), or synchronous dynamic random access memory (SDRAM), among others.

[0004] Non-volatile memory can retain stored data when not powered, and includes flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), static RAM (SRAM), erasable programmable ROM (EPROM), resistance variable memory such as phase-change random access memory (PCRAM), resistive random access memory (RRAM), magnetoresistive random access memory (MRAM), or 3D XPoint TM Memory, etc.

[0005] Memory is typically described and organized by virtual logical blocks and physical blocks. While a physical block refers to a physical structure (e.g., location) in a memory device (e.g., its address), a logical block is conceptually similar in that it provides a flexible interface for the physical block. Thus, for example, if a memory device moves data from one physical block to another, such as to garbage collect a first physical block, the relationship from the first physical block to the corresponding logical block can be transferred without interrupting host operations that access data via the logical block. The relationship between the physical block and the logical block is typically maintained in a data structure, which may be referred to as a logical-to-physical (L2P) mapping (e.g., a table, list, dictionary, or other data structure). As the size and complexity of the physical structure of the memory device increases, the size and complexity of the L2P mapping typically also increases. Summary of the Invention

[0006] According to one aspect of the present application, a memory controller for damaged storage portion recovery in a memory device is provided. The memory controller includes: a memory device containing instructions; and processing circuitry configured by the instructions, when in operation, to: detect a failure event during a garbage collection operation on a set of storage portions in a memory array, members of the set of storage portions being moved from previous physical locations to new physical locations by the garbage collection operation; in response to the failure event, retrieve a reference to the previous physical location of a potentially damaged storage portion in the set of storage portions, the potentially damaged storage portion having been written to the new physical location; and rewrite the potentially damaged storage portion at the new physical location using data from the previous physical location.

[0007] According to another aspect of the present application, a method for recovering damaged storage portions in a memory device is provided. The method includes: detecting a failure event during a garbage collection operation on a set of storage portions in a memory array, members of the set of storage portions being moved from previous physical locations to new physical locations by the garbage collection operation; in response to the failure event, retrieving a reference to the previous physical location of a potentially damaged storage portion in the set of storage portions, the potentially damaged storage portion having been written to the new physical location; and rewriting the potentially damaged storage portion at the new physical location using data from the previous physical location.

[0008] According to another aspect of the present disclosure, a machine-readable medium is provided, wherein the machine-readable medium includes instructions that, when executed by a circuit system, cause the circuit system to implement any method of the present application.

[0009] According to another aspect of the present application, a system is provided, comprising components for implementing any method of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In the drawings, which are not necessarily drawn to scale, like reference numerals may describe similar components in different views. Like reference numerals with different letter suffixes may represent different instances of similar components. The drawings generally illustrate various embodiments discussed in this document by way of example and not limitation.

[0011] Figure 1 An example of an environment including a memory device is shown.

[0012] Figure 2 An example representation of pages and corresponding spare areas is shown.

[0013] Figure 3 Shows an example of a page that is potentially damaged during a program failure.

[0014] Figure 4 An example of a page potentially damaged during an asynchronous power failure during programming is shown.

[0015] Figure 5 An example storage structure showing addresses used to restore pages.

[0016] Figure 6 An example storage structure showing addresses used to restore pages.

[0017] Figure 7 An example of recovering data during an asynchronous power loss event using a storage structure for recovering page addresses is shown.

[0018] Figure 8 An example of recovering data during a program failure event using a storage structure for recovering addresses of pages is shown.

[0019] Figure 9 A flow chart illustrating an example of a method for damaged storage portion recovery in a memory device.

[0020] Figure 10 is a block diagram illustrating an example of a machine upon which one or more embodiments may be implemented. DETAILED DESCRIPTION

[0021] Various memory technologies, such as NAND or storage-class memory (e.g., 3D XPoint™), perform maintenance operations, such as garbage collection. These maintenance operations typically involve moving good data to new locations and reclaiming bad data (e.g., data marked as no longer current, erased by the host, etc.) via an erase operation or similar operation. Once the bad data is reclaimed, the storage structure can typically be used to store new data. In managed memory devices, the memory device includes a controller to perform such maintenance operations, rather than, for example, a host performing these operations.

[0022] A problem that can occur in some memory devices (e.g., NAND devices) is the potential corruption of data during failures, such as program (e.g., write) failures to a page, asynchronous power loss to the device during a write, and other failures. Traditional techniques for addressing such failures include increasing the level of error correction code (ECC) on the page (e.g., the number of ECC bits); relying on ECC to recover the data after the failure. While increased ECC has the potential to provide a good level of data protection, the gradual reduction in memory geometries and the increase in controller complexity have made it difficult to implement more complex ECC protection. This is exacerbated by the limited working memory (e.g., static random access memory (SRAM)) typically included with the managed memory controller. In this environment, data redundancy often results in expensive products that can suffer performance penalties, or simply wastes storage space due to data redundancy.

[0023] Writing data during garbage collection presents a failure scenario where data recovery techniques can be used instead of providing additional storage areas for data redundancy or complex ECC schemes. In a garbage collection operation, as described above, data is moved from a first physical location (e.g., a page) to a second physical location, and then the data in the first location is reclaimed. Because reclaiming typically occurs after the move, if data corruption occurs while writing the data to the new location, the unreclaimed "old" data can serve as a redundant backup for the new data. However, when managing such data movement, the logical-to-physical (L2P) mapping is updated during the write. Therefore, the old address of the data before the corruption may be lost. To address this issue, the old address of the data can be written to a spare area (e.g., extra bits) in a NAND page or equivalent page in other memory technologies.

[0024] The spare area used to store the old address is not the same page as the data being written, because a failure on the written data will likely cause a failure of the spare area as well. Instead, spare areas of other pages are used. Several criteria can be placed on which pages store the previous addresses of other pages, depending on performance or failure conditions. Examples may include constraints on spare areas for one page on different planes or on different page lines (such as word lines) in different dies. Each of these locations can provide protection during asynchronous power failures, program failures, or die failures, respectively. In any case, the spare area uses a relationship with the page being written so that the spare area is calculated when possible corruption is identified for that page. Under failure conditions, this spare area is accessed to retrieve the previous address of the page, and then the data is reread from the original physical location before being reclaimed and used to overwrite the page.

[0025] Using a spare area to store the previous physical address of data provides several benefits beyond ready recovery of that data during a failure. For example, this solution does not impact over-provisioning (e.g., dedicating additional storage resources to maintenance operations rather than user data) and does not impact memory device performance. Additionally, the complexity of recovering from asynchronous power loss or program failures is reduced in the hardware or in the software (e.g., firmware) running on it. Additional details and examples are provided below.

[0026] The following notes provide context for the discussion herein. A memory device comprises individual memory dies, which may, for example, comprise a storage region comprising one or more memory cell arrays, thereby implementing one (or more) selected storage technologies. Such memory dies will typically include support circuitry for operating the memory arrays. Other examples, sometimes commonly referred to as "managed memory devices," include an assembly of one or more memory dies associated with controller functionality configured to control the operation of the one or more memory dies. Such controller functionality can simplify interoperability with external devices acting as "hosts," as discussed later herein. In such managed memory devices, the controller functionality can be implemented on one or more dies that also incorporate the memory arrays, or on a separate die. In other examples, one or more memory devices can be combined with controller functionality to form a solid-state drive (SSD) memory volume. The term "memory system" is used herein to include one or more memory dies and any controller functionality for such memory dies (when present); and thus includes individual memory devices, managed memory devices, and SSDs.

[0027] Embodiments of the present disclosure are described in the context of examples of managed memory devices implementing NAND flash memory cells, referred to as "managed NAND" devices. However, these examples do not limit the scope of the present disclosure, which may be implemented in other forms of memory devices and / or with other forms of storage technology.

[0028] Each flash memory cell in a NOR or NAND architecture semiconductor memory array can be individually or collectively programmed to one or more programmed states. For example, a single-level cell (SLC) can represent one of two programmed states (e.g., 1 or 0), thereby representing one data bit. Flash memory cells can also represent more than two programmed states, allowing the manufacture of higher density memories without increasing the number of memory cells because each cell can represent more than one binary digit (e.g., more than one bit). Such cells may be referred to as multi-state memory cells, multi-digit cells, or multi-level cells (MLCs). In some examples, an MLC may refer to a memory cell that can store two data bits per cell (e.g., one of four programmed states), a triple-level cell (TLC) may refer to a memory cell that can store three data bits per cell (e.g., one of eight programmed states), and a quad-level cell (QLC) may store four data bits per cell. MLC is used herein in its broader context to refer to any memory cell that can store more than one data bit per cell (i.e., can represent more than two programmed states).

[0029] The managed memory device may be configured and operated according to recognized industry standards. For example, the managed NAND device may be, as a non-limiting example, a Universal Flash Storage (UFS) TM ) devices or embedded MMC devices (eMMC TM ) and the like. For example, in the case of the above example, the UFS device can be configured according to the Joint Electron Device Engineering Council (JEDEC) standard (e.g., JEDEC standard JESD223D, entitled "JEDEC UFS Flash Storage 3.0", etc.) and / or an update or subsequent version of such a standard. Similarly, the identified eMMC device can be configured according to the JEDEC standard JESD84-A51 entitled "JEDEC eMMC standard 5.1" (also, and / or an update or subsequent version of such a standard). The identified standards are provided merely as example environments in which the described methods and structures can be utilized. Such methods and structures can be used in a variety of environments other than the identified standards (or any other actual or proposed standards), unless expressly indicated herein.

[0030] SSDs are particularly useful as primary storage devices for computers, offering advantages over traditional hard disk drives with moving parts, such as performance, size, weight, robustness, operating temperature range, and power consumption. For example, SSDs can have reduced seek times, latency, or other delays (e.g., electromechanical, etc.) associated with magnetic disk drives. SSDs use non-volatile memory cells, such as flash memory cells, to avoid internal battery power requirements, thereby allowing the drives to be more versatile and compact. Managed memory devices, such as managed NAND devices, can be used as primary or secondary memory in various electronic devices and are commonly used in mobile devices.

[0031] Both SSDs and managed memory devices may include several memory devices having several dies or logical units (e.g., logical unit numbers or LUNs), and may include one or more processors or other controllers that perform the logic functions required to operate the memory devices or interface with external systems. Such SSDs and managed memory devices may include one or more flash memory dies containing multiple memory arrays and peripheral circuitry. The flash memory arrays may include multiple blocks of memory cells organized into multiple physical pages. In some examples, SSDs may also include DRAM or SRAM (or other forms of memory dies or other memory structures). Similarly, managed NAND devices may include one or more arrays of volatile and / or non-volatile memory separate from the NAND storage arrays and within or separate from the controller. Both SSDs and managed NAND devices may receive commands from a host associated with memory operations, such as read or write operations to transfer data (e.g., user data and associated integrity data, such as error data and address data) between the memory device and the host, or erase operations to erase data from the memory device.

[0032] Figure 1 An example of an environment 100 is shown that includes a host device 105 and a memory device 110 configured to communicate via a communication interface. The host device 105 or the memory device 110 may be included in a variety of products 150, such as Internet of Things (IoT) devices (e.g., refrigerators or other appliances, sensors, motors or actuators, mobile communication devices, cars, drones, etc.), to support processing, communication, or control of the product 150.

[0033] Memory device 110 includes a memory controller 115 and a memory array 120, which includes, for example, multiple individual memory dies (e.g., a stack of three-dimensional (3D) NAND dies). In 3D architecture semiconductor memory technology, vertical structures are stacked, thereby increasing the number of levels, physical pages, and therefore the density of memory devices (e.g., memory devices). In one example, memory device 110 can be a discrete memory or memory device component of host device 105. In other examples, memory device 110 can be part of an integrated circuit (e.g., a system on a chip (SoC), etc.) that is stacked or otherwise included with one or more other components of host device 105.

[0034] Data may be transferred between the memory device 110 and one or more other components of the host device 105 using one or more communication interfaces, such as a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a UFS interface, an eMMC™ interface, or one or more other connectors or interfaces. The host device 105 may include a host system, an electronic device, a processor, a memory card reader, or one or more other electronic devices external to the memory device 110. In some examples, the host 105 may be a host computer with a reference Figure 10 The machine 1000 may include some or all of the components discussed above.

[0035] The memory controller 115 may receive instructions from the host 105 and may communicate with the memory array 120 to transfer data to (e.g., write or erase) or transfer data from (e.g., read) one or more of the memory cells, planes, sub-blocks, blocks, or pages of the memory array 120. For example, the memory controller 115 may include one or more memory control units, circuits, or components configured to control access across the memory array 120 and provide a translation layer between the host 105 and the memory device 110.

[0036] Memory controller 115 includes processing circuitry, which may include one or more processors that, when present, operate to execute instructions stored in the memory devices and may include additional circuitry or components. For the purposes of this disclosure, the instructions will be discussed as firmware, but they may also exist as software; and all or some portion of the described functionality may also be implemented in circuitry including one or more components or integrated circuits. In some examples, the functions of memory controller 115 are implemented by a processor executing instructions of firmware, which in some examples will be stored within memory controller 115. In other examples, one or more processors within memory controller 115 may execute instructions stored in memory array 120. Similarly, management tables 130 used by the controller may be stored on memory controller 115 or in memory array 120. In such examples, the instructions and / or management tables 130 may be stored in certain blocks of the NAND die of memory array 120 and loaded into the working memory of memory controller 115 during operation. Memory controller 115 may include circuitry or firmware, including one or more components or integrated circuits, among other things.

[0037] The memory manager 125 may include, among other things, circuitry or firmware, such as several components or integrated circuits associated with various memory management functions. For purposes of the present description, example memory operation and management functions will be described in the context of NAND memory. Those skilled in the art will recognize that other forms of non-volatile memory may have similar memory operation or management functions. Such NAND management functions include wear leveling (e.g., garbage collection or reclamation), error detection or correction, block retirement, or one or more other memory management functions. The memory manager 125 may parse or format host commands (e.g., commands received from a host device) into device commands (e.g., commands associated with operation of a memory array, etc.), or generate device commands for the device controller 135 or one or more other components of the memory device 110 (e.g., to implement various memory management functions).

[0038] The memory manager 125 may include a set of management tables 130 configured to maintain various information associated with one or more components of the memory device 110 (e.g., various information associated with a memory array or one or more memory cells coupled to the memory controller 115). For example, the management tables 130 may include information about block age, block erase counts, error history, or one or more error counts (e.g., write operation error counts, read bit error counts, read operation error counts, erase error counts, etc.) for one or more memory cell blocks coupled to the memory controller 115. In some examples, if the number of errors detected for one or more of the error counts is above a threshold, the bit error may be referred to as an uncorrectable bit error. The management tables 130 may, among other things, maintain counts of correctable or uncorrectable bit errors. In an example, the management tables 103 may include a translation table or an L2P map.

[0039] The array controller 135 may include, among other things, circuitry or components configured to control memory operations associated with writing data to, reading data from, or erasing one or more memory cells of the memory device 110 coupled to the memory controller 115. The memory operations may be based on host commands (e.g., associated with wear leveling, error detection or correction, etc.), such as those received from the host 105 or generated internally by the memory manager 125.

[0040] The array controller 135 may include an error correction code (ECC) component 140, which may include, among other things, an ECC engine or other circuitry configured to detect or correct errors associated with writing data to or reading data from one or more memory cells of the memory device 110 coupled to the memory controller 115. The memory controller 115 may be configured to actively detect and recover from error occurrences (e.g., bit errors, operational errors, etc.) associated with various operations or data storage, while maintaining the integrity of data transferred between the host 105 and the memory device 110, or maintaining the integrity of stored data (e.g., using redundant RAID storage, etc.), and may remove (e.g., retire) failed memory resources (e.g., memory cells, memory arrays, pages, blocks, etc.) to prevent future errors.

[0041] As described above, the memory controller 115 (e.g., through the memory manager 125, array controller 135, or other circuitry) is configured to handle both garbage collection and error correction. The memory controller 115 is also configured to perform damaged storage portion recovery. Although the following discussion of damaged storage portion recovery is from the perspective of the memory controller 115, the same techniques can be applied in unmanaged memory devices (e.g., where the controller is external to the memory device 110).

[0042] The memory controller 115 is configured to detect a failure event during a garbage collection operation on a set of storage portions in the memory array 120. Here, members of the set of storage portions are being moved from a previous physical location to a new physical location by a garbage collection operation. In one example, moving a storage portion involves writing data to the new physical location, updating the L2P map to associate the storage portion's logical identifier with the new physical location, and ultimately erasing the previous (e.g., previous, old, etc.) physical location. As mentioned herein, in NAND devices, erasure is a block-level erase, and the storage portion being moved can be as small as a page. Therefore, erasure is typically delayed until good data has been completely written to the new physical location.

[0043] Detecting a failure event may include direct observation of the event by sensors of memory controller 115, or it may include a message generated by another device (e.g., array controller 135 or other device involved in writing data to memory array 120). In one example, the failure event is an asynchronous power loss during a program of a member of a memory portion set. The impact of an asynchronous power loss when writing data to a new physical location may depend on the geometry of the device. Generally speaking, an asynchronous power loss when writing a page line in a NAND device may damage another page line. Figure 4 Show this relationship.

[0044] In one example, the failure event is a program failure of a member of a memory portion set. In a NAND device, this failure can potentially damage already written pages within the same plane of the same die. Figure 3 An example of this situation is shown. In one example, the failure event is a die failure. A die failure covers a situation where the entire NAND die becomes inaccessible (eg, reading or writing is no longer possible).

[0045] Upon detecting a failure event, the memory controller 115 is configured to retrieve a reference to the previous physical location of the potentially corrupted storage portion in the set of storage portions. Here, the potentially corrupted storage portion has already been written to a new physical location. Thus, generally speaking, a failure occurs when a storage portion, after garbage collection, is written to a different storage portion than the one potentially corrupted due to the failure. The storage portion may (e.g., potentially) be corrupted because a failure during programming can lead to corruption of a previously written storage portion, even though the storage portion may not actually be corrupted. This corruption possibility typically requires an error recovery process to address potential data loss. Because garbage collection has not yet completed, an uncorrupted version of the data exists at the previous physical address of the potentially corrupted storage portion. Therefore, as further explained below, the required error correction or even verification of existing errors is unnecessary. In fact, known good data at the previous physical location can be reread and used to establish an uncorrupted version of the data at the new physical location or a second new physical location (e.g., in the case of a die failure, on a different die).

[0046] In one example, to retrieve a reference to the previous physical location of the potentially corrupted storage portion, the memory controller 115 is configured to identify the second storage portion based on a physical relationship between the new physical location of the potentially corrupted storage portion and the new physical location of the second storage portion. The previous physical location of the potentially corrupted storage portion is then read from the new physical location of the second storage portion. In these examples, a defined relationship between the potentially corrupted storage portion and other storage locations that accommodate previous physical addresses is used to avoid mapping or other translations. Therefore, the second storage location for the potentially corrupted storage portion is calculated using the defined relationship. In one example, when the storage portion is a NAND page, the previous physical address is stored in a spare area of ​​the second page. Here, reading the previous physical location of the potentially corrupted storage portion from the new physical location of the second storage portion includes reading the spare area of ​​the NAND page, which is the new physical location of the second storage portion. Therefore, when writing to the second storage portion, the previous physical address of the first storage portion (the potentially corrupted storage portion) is written with the second storage portion. Because these are all in the new physical location, no mapping back to the previous physical storage device portion is required.

[0047] In one example, the memory controller 115 is configured to identify the second storage portion during the original write of the potentially corrupted storage portion for a garbage collection operation based on a physical relationship between the new physical location of the potentially corrupted storage portion and the new physical location of the second storage portion. Here, the defined relationship is used to identify the previous physical address of the physical portion to which the physical portion will be written when the physical portion is written to the new physical address. Therefore, as part of the criteria for writing to the new physical location, the previous physical location will be written according to the defined relationship. Thus, the previous physical location of the potentially corrupted storage portion is written to the new physical location of the second storage portion in the context of the potentially corrupted storage location for subsequent retrieval, as described in detail above.

[0048] As described above, the storage portion can be a NAND page. And, in one example, the set of storage portions can be a block in a NAND device. In one example, to identify the second storage portion based on a physical relationship between the new physical location of the potentially damaged storage portion and the new physical location of the second storage portion, for example, using a defined relationship to calculate the second physical portion from the potentially damaged physical portion, the memory controller 115 is configured to add an offset to the page line of the new physical address of the potentially damaged storage portion. Thus, if the potentially damaged page is on page line z, then the second page is on z+1 or z-1 (z+(-1)). This offset ensures that the previous physical address will be available in the event that the entire page line is potentially damaged, such as during an asynchronous power loss event.

[0049] In one example, to identify the second storage portion based on a physical relationship between the new physical location of the possibly damaged storage portion and the new physical location of the second storage portion, e.g., using a defined relationship to calculate the second physical location from the possibly damaged physical location, the memory controller 115 is configured to add an offset to the NAND die of the new physical address of the possibly damaged storage portion. In one example, identifying the second storage portion based on the physical relationship between the new physical location of the possibly damaged storage portion and the new physical location of the second storage portion includes using the same plane in the offset NAND die. Combining these offsets yields a storage pattern for the previous physical address, e.g., Figure 5 and Figure 6 These defined relationships ensure that the previous physical address is available during possible corruption in a NAND plane, NAND die, or NAND page line.

[0050] Once the memory controller 115 has retrieved the previous physical location of the potentially corrupted memory portion, the memory controller 115 is configured to read the data at the previous physical location. This good, or uncorrupted, data is then rewritten at the new physical location. Rewriting the good data is an efficient technique for ensuring that the data at the new physical location is not corrupted, regardless of whether it was actually damaged by the failure event. In one example, the new physical location has been changed to an operational memory array element. Thus, if the new physical location originally pointed to a NAND cell located on a failed die, it is remapped to a cell in an operational die.

[0051] The damaged storage portion recovery techniques described herein offer several advantages over current methods. For example, these techniques do not rely on over-provisioned resources in the memory array 120 to store good copies of the data. Instead, they exploit the presence of good data at previous physical locations prior to the completion of garbage collection. Furthermore, because extensive error correction is not used, the performance of the memory device 110 is not affected, while the complexity of the memory device 110 is reduced. Consequently, a simpler, higher-performance memory device 110 is achieved that is more robust to data corruption.

[0052] Memory array 120 may include a number of memory cells arranged, for example, in a number of devices, planes, sub-blocks, blocks, or pages. As an example, a 48GB TLC NAND memory device may include 18,592 bytes (B) of data per page (16,384 + 2208 bytes), 1536 pages per block, 548 blocks per plane, and four or more planes per device. As another example, a 32GB MLC memory device (storing two data bits per cell (i.e., four programmable states)) may include 18,592 bytes (B) of data per page (16,384 + 2208 bytes), 1024 pages per block, 548 blocks per plane, and four planes per device, but require half the write time and twice the program / erase (P / E) cycles of a corresponding TLC memory device. Other examples may include other numbers or arrangements. In some examples, a memory device or portion thereof can be selectively operated in an SLC mode or in a desired MLC mode (eg, TLC, QLC, etc.).

[0053] In operation, for example, when the memory array is a NAND array, data is typically written to or read from the memory device 110 in pages and erased in blocks. However, one or more memory operations (e.g., read, write, erase, etc.) may be performed on larger or smaller groups of memory cells as desired. The data transfer size of the memory device 110 is typically referred to as a page; while the data transfer size of the host is typically referred to as a sector.

[0054] Although a data page may include several bytes of user data (e.g., a data payload comprising several data sectors) and corresponding metadata, the size of a page generally refers only to the number of bytes used to store the user data. As an example, a data page with a 4KB page size may include 4KB of user data (e.g., assuming 8 sectors with a sector size of 512B) and several bytes (e.g., 32B, 54B, 224B, etc.) of metadata corresponding to the user data, such as integrity data (e.g., error detection or correction code data), address data (e.g., logical address data, etc.), or other metadata associated with the user data.

[0055] Different types of memory cells or memory arrays 120 may provide different page sizes or may require different amounts of metadata associated therewith. For example, different memory device types may have different bit error rates, which may result in different amounts of metadata being required to ensure the integrity of a page of data (e.g., a memory device with a higher bit error rate may require more bytes of error correction code data than a memory device with a lower bit error rate). For example, a multi-level cell (MLC) NAND flash device may have a higher bit error rate than a corresponding single-level cell (SLC) NAND flash device. Therefore, an MLC device may require more bytes of metadata for error data than a corresponding SLC device.

[0056] Figure 2 Show that if Figure 1 An example representation of a page and corresponding spare area implemented by system 100 is shown. Figure 2 The example of provides a NAND memory device scenario for partial recovery of damaged storage. Here is a memory arranged as pages in blocks in planes in a die. Although a plane in a die generally contains several blocks, as illustrated, the pages in a plane are in a single block. Here, a page line is a homologous page belonging to a plane (shown as a row). Note that individual pages are shown as having two spare regions, but these can be contiguous regions with space (e.g., bits) representing two physical page addresses. The structure shown is for the following description of Figures 3 to 8 The discussion provides the above context.

[0057] Figure 3 An example of a page potentially damaged during a program failure is shown. Here, the diagonally cross-hatched page belonging to plane N-1 has a program failure due to a memory program (e.g., writing to a NAND cell). This failure can potentially damage many pages, shown by the horizontal and vertical cross-hatching within the same plane.

[0058] Figure 4An example of potentially damaged pages during an asynchronous power failure during programming is shown. Here, due to the internal memory geometry, an asynchronous power loss event during programming of any page in page line N-1 (shown with diagonal cross-hatching) can potentially damage pages in page line Z (shown with horizontal and vertical cross-hatching).

[0059] Figure 5 and Figure 6 An example mode is shown in which the data recovery described herein is performed by storing the previous physical address. Furthermore, redundancy is achieved using the data stored at the old address. These old addresses are stored in a spare area of ​​other (e.g., adjacent) pages (e.g., virtual pages) within the block.

[0060] Figure 5 An example storage structure for recovering the addresses of pages is shown. The arrows indicate which spare area holds the address of a given page. The arrows are solid to indicate cross-page line relationships and dashed for intra-page line relationships. As shown, both spare areas for most pages in a block are used to store previous physical addresses. Taking page 5 as an example, the spare areas provide the previous address of page 1 and the previous address of page 6. The first spare area provides page line corruption protection (e.g., under asynchronous power failures), and the second spare area provides plane corruption protection (e.g., under program failures). Thus, for asynchronous power loss, an address pointer to the previous page line is used to retrieve good data, and for program failures, a pointer on the same page line is used to retrieve good data from the previous physical location of page 5.

[0061] Figure 6 An example storage structure for restoring addresses of pages is shown. For clarity only, arrows are solid in one direction and dashed in the other direction. Figure 6 The pattern shown is Figure 5 The model to the alternative. Different from Figure 5 The horizontal and vertical arrangements shown in the defined relationship show a diagonal physical relationship. Therefore, here, the adjacent page is the page on the previous page line, in the same plane, and on the next die. Therefore, page 5 stores the previous address of page 3 because page 5 is in the next page line (page line 0 + 1 = page line 1), in the same plane (plane 1), and in the next die (die 1 + 1 modulo 2 = die 0).

[0062] Figure 6 The model shown provides advantages over Figure 5 For example, half of the spare area is in Figure 6 Because the spare area holds a single previous physical address instead of two. Also, in the event of a die failure due to die offset in a defined relationship, Figure 6 mode provides protection.

[0063] This mode can provide an extension to ECC to protect against asynchronous power loss events on single or multi-layer NAND blocks, as well as NAND program failure events that may damage more than one page line. For example, in the event of asynchronous power loss, reading the spare area of ​​the pages in page line Z+1 provides the previous physical addresses to restore all pages of page line Z. For a program failure, reading the spare area of ​​the pages of Die 0 Plane 1 makes it possible to recover the previous physical addresses of all pages of Die 1 Plane 1. And if the entire die becomes inaccessible, reading the spare area of ​​the pages of Die 0 makes it possible to recover the previous physical addresses of all pages of Die 1. Therefore, damaged rows and damaged columns are fully recoverable.

[0064] Figure 7 An example of recovering data during an asynchronous power loss event using a storage structure for recovering page addresses is shown. Figure 6 After the writing of page line 3, page line 1 is Figure 7 Here, reading the spare area of ​​the page in page line 2 (page line 1+1) yields the previous physical addresses of the page in page line 1. These previous physical addresses are used to read the undamaged data and rewrite the page in page line 1.

[0065] Figure 8 An example of recovering data during a program failure event using a storage structure for recovering page addresses is shown. Here, after a program failure of page 13, pages in plane 1 of die 0 may be corrupted. To recover the previous addresses of these pages, a spare area in the same plane in an adjacent die provides the previous physical addresses of the potentially corrupted pages. Similarly, if the entire die 0 is inaccessible, reading the spare area of ​​the pages in die 1 will yield the previous physical addresses of the pages in die 0.

[0066] Figure 9 A flow chart illustrating an example of a method 900 for recovering a damaged storage portion in a memory device. The operations of the method 900 are performed by computing hardware. Examples of such computing hardware may include the Figure 1 The memory controller 115 or other processing circuitry of the memory device 110 is depicted, such as other computer components such as an external memory controller.

[0067] At operation 905, a failure event is detected on a set of storage portions in a memory array during a garbage collection operation. Here, members of the set of storage portions are being moved from a previous physical location to a new physical location by the garbage collection operation. In one example, the failure event is an asynchronous power loss during a program of a member of the set of storage portions. In another example, the failure event is a program failure of a member of the set of storage portions. In another example, the failure event is a die failure.

[0068] At operation 910, in response to a failure event, a reference to a previous physical location of a potentially corrupted storage portion in a set of storage portions is retrieved. Here, the potentially corrupted storage portion has been written to a new physical location. In one example, retrieving the reference to the previous physical location of the potentially corrupted storage portion includes identifying the second storage portion based on a physical relationship between the new physical location of the potentially corrupted storage portion and the new physical location of a second storage portion. The previous physical location of the potentially corrupted storage portion is then read from the new physical location of the second storage portion. In one example, reading the previous physical location of the potentially corrupted storage portion from the new physical location of the second storage portion includes reading a spare area of ​​a NAND page, which is the new physical location of the second storage portion. In one example, method 900 is expanded to include identifying the second storage portion based on the physical relationship between the new physical location of the potentially corrupted storage portion and the new physical location of the second storage portion during the original write of the potentially corrupted storage portion for a garbage collection operation. The previous physical location of the potentially corrupted storage portion is then written to the new physical location of the second storage portion.

[0069] In one example, the storage portion is a page. In one example, the set of storage portions is a block in a NAND device. In one example, based on a physical relationship between the new physical location of the potentially damaged storage portion and the new physical location of the second storage portion, the second storage portion is identified as including a page line that adds an offset to the new physical address of the potentially damaged storage portion. In one example, based on a physical relationship between the new physical location of the potentially damaged storage portion and the new physical location of the second storage portion, the second storage portion is identified as including a NAND die that adds an offset to the new physical address of the potentially damaged storage portion. In one example, based on the physical relationship between the new physical location of the potentially damaged storage portion and the new physical location of the second storage portion, the second storage portion is identified as including using the same plane in an offset NAND die.

[0070] At operation 915, the potentially damaged portion of storage is rewritten at the new physical location using data from the previous physical location. Thus, the data is efficiently recovered. This efficiency can be observed in several scenarios. Using the old addresses of potentially damaged data in a spare area of ​​the storage array results in less working memory usage, does not consume storage resources (e.g., NAND cells set aside for this purpose), does not impact memory device performance, reduces hardware or software complexity, and increases memory device resilience to failures.

[0071] Figure 10A block diagram of an example machine 1000 is shown on which any one or more of the techniques (e.g., methods) discussed herein may be executed. For example, any of the memory systems within the machine 1100 (main memory 1104, static memory 1106, and mass storage device 1121) may implement the techniques described herein with respect to Figures 1 to 9 The damaged storage portion is partially restored. In alternative embodiments, machine 1000 may operate as a standalone device or may be connected (e.g., networked) to other machines. In a networked deployment, machine 1000 may operate in the capacity of a server machine, a client machine, or both in a server-client network environment. In one example, machine 1000 may operate as a peer machine in a peer-to-peer (P2P) (or other distributed) network environment. Machine 1000 may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile phone, a network appliance, an IoT device, an automotive system, or any other machine capable of executing (sequentially or otherwise) instructions that specify actions to be taken by the machine. Further, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or collectively execute one (or more) sets of instructions to perform any one or more of the methodologies discussed herein (e.g., cloud computing, software as a service (SaaS), other computer cluster configurations).

[0072] As described herein, an example may include logic, components, devices, packages, or mechanisms, or may be operated by logic, components, devices, packages, or mechanisms. A circuit system is a collection of circuits (e.g., a set) implemented in a tangible entity that includes hardware (e.g., simple circuits, gates, logic, etc.). Circuit system members can be flexible over time and with the variability of the underlying hardware. A circuit system includes components that can perform specific tasks individually or in combination when operated. In one example, the hardware of the circuit system can be designed to perform specific operations (e.g., hard-wired). In one example, the hardware of the circuit system can include variably connected physical components (e.g., execution units, transistors, simple circuits, etc.), which include computer-readable media that are physically modified (e.g., magnetic properties of fixed centralized particles, electrically movable placement, etc.) to encode instructions for specific operations. When the physical components are connected, the underlying electrical properties of the hardware components change, for example, from an insulator to a conductor or vice versa. The instructions enable participating hardware (e.g., an execution unit or a loading mechanism) to generate components of the circuit system in the hardware via variable connections to perform portions of a specific task when in operation. Thus, when the device is operating, the computer-readable medium is communicatively coupled to other components of the circuit system. In an example, any one of the physical components can be used in more than one component in more than one circuit system. For example, in operation, an execution unit can be used in a first circuit in a first circuit system at one point in time and reused by a second circuit in the first circuit system, or reused by a third circuit in the second circuit system at a different time.

[0073] A machine (e.g., a computer system) 1000 (e.g., a host device 105, a memory device 110, etc.) may include a hardware processor 1002 (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a hardware processor core, or any combination thereof, such as a memory controller 115, etc.); a main memory 1004 and a static memory 1006, some or all of which may communicate with each other via an interconnection (e.g., a bus) 1008. The machine 1000 may also include a display unit 1010, an alphanumeric input device 1012 (e.g., a keyboard), and a user interface (UI) navigation device 1014 (e.g., a mouse). In one example, the display unit 1010, the input device 1012, and the UI navigation device 1014 may be a touch screen display. The machine 1000 may also include a memory device (e.g., a drive unit) 1021, a signal generating device 1018 (e.g., a speaker), a network interface device 1020, and one or more sensors 1016, such as a global positioning system (GPS) sensor, a compass, an accelerometer, or other sensors. The machine 1000 may include an output controller 1028, such as a serial (e.g., Universal Serial Bus (USB)), parallel, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connection to communicate with or control one or more peripheral devices (e.g., a printer, a card reader, etc.).

[0074] The storage device 1016 may include a machine-readable medium 1022 on which one or more sets of data structures or instructions 1024 (e.g., software) embodying or utilized by any one or more of the techniques or functions described herein are stored. The instructions 1024 may also reside, completely or at least partially, within the main memory 1004, within the static storage 1006, or within the hardware processor 1002 during execution thereof by the machine 1000. In one example, one or any combination of the hardware processor 1002, the main memory 1004, the static storage 1006, or the storage device 1016 may constitute the machine-readable medium 1022.

[0075] Although machine-readable medium 1022 is shown as a single medium, the term "machine-readable medium" may include a single medium or multiple media (eg, a centralized or distributed database, or associated caches and servers) configured to store one or more instructions 1024.

[0076] The term "machine-readable medium" may include any medium capable of storing, encoding, or carrying instructions for execution by the machine 1000 and causing the machine 1000 to perform any one or more of the techniques of the present disclosure, or any medium capable of storing, encoding, or carrying data structures used by or associated with such instructions. Non-limiting examples of machine-readable media may include solid-state memory and optical and magnetic media. In one example, a bulk machine-readable medium includes a machine-readable medium having a plurality of particles having a constant (e.g., stationary) mass. Thus, a bulk machine-readable medium is a non-transitory propagating signal. Specific examples of bulk machine-readable media may include: non-volatile memory, such as semiconductor memory devices (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)) and flash memory devices; magnetic disks, such as internal hard disks and removable magnetic disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

[0077] Instructions 1024 (e.g., software, programs, operating system (OS), etc.) or other data are stored on storage device 1021 and can be accessed by memory 1004 for use by processor 1002. Memory 1004 (e.g., DRAM) is typically fast but volatile, and therefore a different type of storage device than storage device 1021 (e.g., SSD), which is suitable for long-term storage (including in "power-off" conditions). Instructions 1024 or data for use by a user or machine 1000 are typically loaded into memory 1004 for use by processor 1002. When memory 1004 is full, virtual space from storage device 1021 can be allocated to supplemental memory 1004. However, because storage 1021 devices are typically slower than memory 1004, with write speeds typically at least twice as slow as read speeds, the use of virtual memory can significantly reduce the user experience due to memory device latency (compared to memory 1004, such as DRAM). Furthermore, the use of storage device 1021 for virtual memory can significantly reduce the useful life of storage device 1021.

[0078] Compared to virtual memory, virtual memory compression (e.g. A kernel feature ("ZRAM") uses portions of memory stored as compressed blocks to avoid paging to memory device 1021. Paging occurs in compressed blocks until it is necessary to write such data to memory device 1021. Virtual memory compression increases the available size of memory 1004 while reducing wear and tear on memory device 1021.

[0079] Memory devices optimized for mobile electronic devices or mobile memory devices have traditionally included MMC solid-state memory devices (e.g., micro Secure Digital (microSD) TM) card, etc.). MMC devices include several parallel interfaces (e.g., 8-bit parallel interfaces) with the host device and are often detachable and separable components from the host device. In contrast, eMMC TM The device is attached to the board and is seen as a component of the host device, with read speeds comparable to Serial ATA-based TM (Serial AT (Advanced Technology) Attachment, or SATA) SSD devices. However, the demand for performance in mobile devices continues to increase, for example to fully enable virtual or augmented reality devices, take advantage of increased network speeds, etc. In response to this demand, storage devices have transitioned from parallel to serial communication interfaces. Universal Flash Storage (UFS) devices, which include a controller and firmware, use a low-voltage differential signaling (LVDS) serial interface with dedicated read / write paths to communicate with the host device, further promoting higher read / write speeds.

[0080] The instructions 1024 may further be transmitted or received over the communication network 1026 via the network interface device 1020 using a transmission medium utilizing any of a number of transmission protocols (e.g., Frame Relay, Internet Protocol (IP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), Hypertext Transfer Protocol (HTTP), etc.). Example communication networks may include a local area network (LAN), a wide area network (WAN), a packet data network (e.g., the Internet), a mobile telephone network (e.g., a cellular network), a plain old telephone (POTS) network, and a wireless data network (e.g., the Institute of Electrical and Electronics Engineers (IEEE) 802.11 standard system, known as IEEE 802.16 standard system, known as ), IEEE 802.15.4 standard system, peer-to-peer (P2P) networks, and the like. In one example, the network interface device 1020 may include one or more physical jacks (e.g., Ethernet, coaxial, or telephone jacks) or one or more antennas to connect to the communication network 1026. In one example, the network interface device 1020 may include multiple antennas to enable wireless communication using at least one of single-input, multiple-output (SIMO), multiple-input, multiple-output (MIMO), or multiple-input, single-output (MISO) technology. The term "transmission media" shall be construed to include any intangible medium capable of storing, encoding, or carrying instructions for execution by the machine 1000, and includes digital or analog communication signals or other intangible media used to facilitate communication of such software.

[0081] Additional examples:

[0082] Example 1 is a memory controller for recovering damaged storage portions in a memory device, the memory controller comprising: a memory device containing instructions; and a processing circuit system that, when in operation, is configured by the instructions to: detect a failure event during a garbage collection operation on a set of storage portions in a memory array, members of the set of storage portions being moved from previous physical locations to new physical locations through the garbage collection operation; retrieve a reference to a previous physical location of a potentially damaged storage portion in the set of storage portions in response to the failure event, the potentially damaged storage portion having been written to the new physical location; and rewrite the potentially damaged storage portion at the new physical location using data from the previous physical location.

[0083] In Example 2, the subject matter of Example 1, wherein, in order to retrieve a reference to a previous physical location of a potentially damaged storage portion, the processing circuit system is configured by the instructions to: identify the second storage portion based on a physical relationship between the new physical location of the potentially damaged storage portion and the new physical location of the second storage portion; and read the previous physical location of the potentially damaged storage portion from the new physical location of the second storage portion.

[0084] In Example 3, the subject matter of Example 2, wherein the processing circuit system is configured by the instructions to: during an original write of the potentially corrupted storage portion for a garbage collection operation, identify the second storage portion based on a physical relationship between the new physical location of the potentially corrupted storage portion and the new physical location of the second storage portion; and write the previous physical location of the potentially corrupted storage portion into the new physical location of the second storage portion.

[0085] In example 4, the subject matter of any of examples 2-3, wherein the storage portion is a page, and wherein the set of storage portions is a block in a NAND device.

[0086] In Example 5, the subject matter of Example 4, wherein, in order to identify the second storage portion based on a physical relationship between the new physical location of the potentially damaged storage portion and the new physical location of the second storage portion, the processing circuit system is configured by the instruction to add an offset to the page line of the new physical address of the potentially damaged storage portion.

[0087] In Example 6, the subject matter of Examples 4 to 5, wherein, in order to identify the second storage portion based on a physical relationship between the new physical location of the potentially damaged storage portion and the new physical location of the second storage portion, the processing circuit system is configured by the instructions to add an offset to the NAND die of the new physical address of the potentially damaged storage portion.

[0088] In Example 7, the subject matter of Example 6, wherein in order to identify the second storage portion based on a physical relationship between the new physical location of the potentially damaged storage portion and the new physical location of the second storage portion, the processing circuit system is configured by the instructions to use the same plane in the offset NAND die.

[0089] In Example 8, the subject matter of any of Examples 4 to 7, wherein in order to read the previous physical location of the potentially damaged storage portion from the new physical location of the second storage portion, the processing circuit system is configured by the instructions to read a spare area of ​​the NAND page, which is the new physical location of the second storage portion.

[0090] In example 9, the subject matter of any of examples 1-8, wherein the failure event is an asynchronous power loss during a program of a member of a storage portion set.

[0091] In example 10, the subject matter of any of examples 1 to 9, wherein the failure event is a failure of a program of a member of the storage portion set.

[0092] Example 11 is a method for recovering damaged storage portions in a memory device, the method comprising: detecting a failure event during a garbage collection operation on a set of storage portions in a memory array, members of the set of storage portions being moved from previous physical locations to new physical locations through the garbage collection operation; retrieving a reference to a previous physical location of a potentially damaged storage portion in the set of storage portions in response to the failure event, the potentially damaged storage portion having been written to the new physical location; and rewriting the potentially damaged storage portion at the new physical location using data from the previous physical location.

[0093] In Example 12, the subject matter of Example 11, wherein retrieving a reference to a previous physical location of a potentially damaged storage portion comprises: identifying the second storage portion based on a physical relationship between a new physical location of the potentially damaged storage portion and a new physical location of the second storage portion; and reading the previous physical location of the potentially damaged storage portion from the new physical location of the second storage portion.

[0094] In Example 13, the subject matter of Example 12 includes: during an original write of the potentially corrupted storage portion for a garbage collection operation, identifying a second storage portion based on a physical relationship between a new physical location of the potentially corrupted storage portion and a new physical location of the second storage portion; and writing the previous physical location of the potentially corrupted storage portion to the new physical location of the second storage portion.

[0095] In Example 14, the subject matter of any of Examples 12-13, wherein the storage portion is a page, and wherein the set of storage portions is a block in a NAND device.

[0096] In Example 15, the subject matter of Example 14, wherein the second storage portion is identified based on a physical relationship between the new physical location of the potentially damaged storage portion and the new physical location of the second storage portion, including a page line that adds an offset to the new physical address of the potentially damaged storage portion.

[0097] In Example 16, the subject matter of any of Examples 14-15, wherein the second storage portion is identified based on a physical relationship between the new physical location of the potentially damaged storage portion and the new physical location of the second storage portion, and the second storage portion includes a NAND die that adds an offset to the new physical address of the potentially damaged storage portion.

[0098] In Example 17, the subject matter of Example 16, wherein identifying the second storage portion based on a physical relationship between the new physical location of the potentially damaged storage portion and the new physical location of the second storage portion includes using the same plane in the offset NAND die.

[0099] In Example 18, the subject matter of any of Examples 14-17, wherein reading the previous physical location of the potentially damaged storage portion from the new physical location of the second storage portion includes reading a spare area of ​​the NAND page, which is the new physical location of the second storage portion.

[0100] In example 19, the subject matter of any of examples 11-18, wherein the failure event is an asynchronous power loss during a program of a member of a storage portion set.

[0101] In example 20, the subject matter of any of examples 11 to 19, wherein the failure event is a failure of a program of a member of the storage portion set.

[0102] Example 21 is a machine-readable medium comprising instructions for recovery of damaged storage portions in a memory device, which, when executed by a processing circuit system, causes the processing circuit system to perform operations comprising: detecting a failure event during a garbage collection operation on a set of storage portions in a memory array, members of the set of storage portions being moved from previous physical locations to new physical locations by the garbage collection operation; retrieving a reference to a previous physical location of a potentially damaged storage portion in the set of storage portions in response to the failure event, the potentially damaged storage portion having been written to the new physical location; and rewriting the potentially damaged storage portion at the new physical location using data from the previous physical location.

[0103] In Example 22, the subject matter of Example 21, wherein retrieving a reference to a previous physical location of a potentially damaged storage portion comprises: identifying the second storage portion based on a physical relationship between a new physical location of the potentially damaged storage portion and a new physical location of the second storage portion; and reading the previous physical location of the potentially damaged storage portion from the new physical location of the second storage portion.

[0104] In Example 23, the subject matter of Example 22, wherein the operation includes: during the original write of the potentially corrupted storage portion for a garbage collection operation, identifying the second storage portion based on a physical relationship between the new physical location of the potentially corrupted storage portion and the new physical location of the second storage portion; and writing the previous physical location of the potentially corrupted storage portion to the new physical location of the second storage portion.

[0105] In Example 24, the subject matter of any of Examples 22-23, wherein the storage portion is a page, and wherein the set of storage portions is a block in a NAND device.

[0106] In Example 25, the subject matter of Example 24, wherein the second storage portion is identified based on a physical relationship between the new physical location of the potentially damaged storage portion and the new physical location of the second storage portion to include a page line that adds an offset to the new physical address of the potentially damaged storage portion.

[0107] In Example 26, the subject matter of Examples 24-25, wherein the second storage portion is identified based on a physical relationship between the new physical location of the potentially damaged storage portion and the new physical location of the second storage portion, and the second storage portion includes a NAND die that adds an offset to the new physical address of the potentially damaged storage portion.

[0108] In Example 27, according to the subject matter of Example 26, identifying the second storage portion based on a physical relationship between a new physical location of the potentially damaged storage portion and a new physical location of the second storage portion includes using the same plane in the offset NAND die.

[0109] In Example 28, the subject matter of any of Examples 24-27, wherein reading the previous physical location of the potentially damaged storage portion from the new physical location of the second storage portion includes reading a spare area of ​​the NAND page that is the new physical location of the second storage portion.

[0110] In Example 29, the subject matter of any of Examples 21-28, wherein the failure event is an asynchronous power loss during a program of a member of a storage portion set.

[0111] In example 30, the subject matter of any of examples 21 to 29, wherein the failure event is a failure of a program of a member of the storage portion set.

[0112] Example 31 is a system for recovering damaged storage portions in a memory device, the system comprising: a component for detecting a failure event during a garbage collection operation on a set of storage portions in a memory array, members of the set of storage portions being moved from previous physical locations to new physical locations through the garbage collection operation; a component for retrieving a reference to a previous physical location of a potentially damaged storage portion in the set of storage portions in response to the failure event, the potentially damaged storage portion having been written to a new physical location; and a component for rewriting the potentially damaged storage portion at the new physical location using data from the previous physical location.

[0113] In Example 32, the subject matter of Example 31, wherein the means for retrieving a reference to a previous physical location of a potentially damaged storage portion comprises: a means for identifying a second storage portion based on a physical relationship between a new physical location of the potentially damaged storage portion and a new physical location of the second storage portion; and a means for reading the previous physical location of the potentially damaged storage portion from the new physical location of the second storage portion.

[0114] In Example 33, the subject matter of Example 32 includes: a component for identifying a second storage portion based on a physical relationship between a new physical location of the potentially corrupted storage portion and a new physical location of the second storage portion during an original write of the potentially corrupted storage portion for a garbage collection operation; and a component for writing the previous physical location of the potentially corrupted storage portion to the new physical location of the second storage portion.

[0115] In Example 34, the subject matter of any of Examples 32-33, wherein the storage portion is a page, and wherein the set of storage portions is a block in a NAND device.

[0116] In Example 35, the subject matter of Example 34, wherein the means for identifying the second storage portion based on a physical relationship between the new physical location of the potentially damaged storage portion and the new physical location of the second storage portion includes means for adding an offset to a page line of the new physical address of the potentially damaged storage portion.

[0117] In Example 36, the subject matter of Examples 34-35, wherein the means for identifying the second storage portion based on a physical relationship between the new physical location of the potentially damaged storage portion and the new physical location of the second storage portion includes means for adding an offset to the NAND die of the new physical address of the potentially damaged storage portion.

[0118] In Example 37, the subject matter of Example 36, wherein the means for identifying the second storage portion based on a physical relationship between the new physical location of the potentially damaged storage portion and the new physical location of the second storage portion includes means for using a same plane in offset NAND dies.

[0119] In Example 38, the subject matter of any of Examples 34 to 37, wherein the means for reading the previous physical location of the possibly damaged storage portion from the new physical location of the second storage portion includes means for reading a spare area of ​​the NAND page, the spare area being the new physical location of the second storage portion.

[0120] In Example 39, the subject matter of any of Examples 31-38, wherein the failure event is an asynchronous power loss during a program of a member of a storage portion set.

[0121] In example 40, the subject matter of any of examples 31 to 39, wherein the failure event is a failure of a program of a member of the storage portion set.

[0122] Example 41 is at least one machine-readable medium comprising instructions that, when executed by processing circuitry, cause the processing circuitry to operate to implement any of Examples 1-40.

[0123] Example 42 is a device comprising means for implementing any of Examples 1-40.

[0124] Example 43 is a system for implementing any of Examples 1-40.

[0125] Example 44 is a method of implementing any of Examples 1-40.

[0126] The above detailed description includes reference to the accompanying drawings, which form part of the detailed description. The figures illustrate specific embodiments that can put the present invention into practice by means of diagrams. These embodiments are also referred to as "examples" in this article. Such examples may include elements other than those shown or described. However, the inventors of the present invention also contemplate examples in which only those elements shown or described are provided. In addition, the inventors of the present invention also contemplate examples (or one or more aspects thereof) of any combination or arrangement of those elements shown or described with respect to a particular example (or one or more aspects thereof) or with respect to other examples (or one or more aspects thereof) shown or described herein.

[0127] In this document, the terms "a" and "an" are used as is common in patent literature to include one or more than one, independent of any other examples or uses of "at least one" or "one or more." In this document, the term "or" is used to refer to non-exclusivity, or such that "A or B" may include "A but not B," "B but not A," and "A and B," unless otherwise indicated. In the appended claims, the terms "including" and "in which" are used as the concise English equivalents of the corresponding terms "comprising" and "wherein." Furthermore, in the appended claims, the terms "comprising" and "including" are open-ended, that is, systems, devices, articles, or processes that include elements in addition to the elements listed after the term in the claim are still considered to fall within the scope of the appended claims. In addition, in the appended claims, the terms "first," "second," and "third," etc. are used merely as labels and are not intended to impose numerical requirements on their objects.

[0128] In various examples, the components, controllers, processors, units, engines, or tables described herein may include, among other things, physical circuitry or firmware stored on a physical device. As used herein, "processor" refers to any type of computing circuit, such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor (DSP), or any other type of processor or processing circuit, including groups of processors or multi-core devices.

[0129] As used in this document, the term "horizontal" is defined as a plane parallel to the conventional plane or surface of a substrate, such as the plane underlying a wafer or die, regardless of the actual orientation of the substrate at any point in time. The term "vertical" refers to a direction perpendicular to horizontal as defined above. Prepositions such as "up," "above," and "below" are defined relative to a conventional plane or surface on the top or exposed surface of a substrate, regardless of the orientation of the substrate; and while "up" is intended to indicate direct contact of one structure relative to another structure "above" (in the absence of an expression indicating the contrary), the terms "above" and "below" are expressly intended to identify the relative placement of structures (or layers, features, etc.), which expressly includes, but is not limited to, direct contact between the identified structures unless specifically indicated as such. Similarly, the terms "above" and "below" are not limited to horizontal orientation, as a structure may be "above" a reference structure if it is the outermost portion of the construction in question at a certain point in time, even if such structure extends vertically rather than in a horizontal orientation relative to the reference structure.

[0130] The terms "wafer" and "substrate" are used herein to generally refer to any structure on which an integrated circuit is formed, and also to refer to such structures during the various stages of integrated circuit fabrication. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the various embodiments is defined solely by the appended claims, along with the full scope of equivalents to which such claims are entitled.

[0131] Various embodiments according to the present disclosure and described herein include memories utilizing a vertical structure of memory cells (e.g., a NAND string of memory cells). As used herein, adjectives will be used that are directional relative to the surface of the substrate on which the memory cells are formed (i.e., a vertical structure will be considered to extend away from the substrate surface, a bottom end of the vertical structure will be considered to be the end closest to the substrate surface, and a top end of the vertical structure will be considered to be the end farthest from the substrate surface).

[0132] As used herein, directional adjectives such as horizontal, vertical, orthogonal, parallel, perpendicular, etc. may refer to relative orientations and, unless otherwise indicated, are not intended to require strict adherence to specific geometric properties. For example, as used herein, a vertical structure need not be exactly perpendicular to the surface of the substrate, but may instead be substantially perpendicular to the surface of the substrate and may form an acute angle (e.g., between 60 and 120 degrees, etc.) with the surface of the substrate.

[0133] In some embodiments described herein, different doping profiles may be applied to a source-side select gate (SGS), a control gate (CG), and a drain-side select gate (SGD), each of which, in this example, may be formed of or at least include polysilicon. As a result, these layers (e.g., polysilicon, etc.) may exhibit different etch rates when exposed to an etching solution. For example, during the formation of a monolithic pillar in a 3D semiconductor device, the SGS and CG may be recessed, while the SGD may remain less recessed or even not recessed. These doping profiles may thus enable selective etching into different layers (e.g., the SGS, CG, and SGD) in a 3D semiconductor device using an etching solution (e.g., tetramethylammonium hydroxide (TMCH)).

[0134] As used herein, operating a memory cell includes reading from the memory cell, writing to the memory cell, or erasing the memory cell. The operation of placing a memory cell in a given state is referred to herein as "programming" and can include writing to a memory cell or erasing from a memory cell (e.g., a memory cell can be programmed to an erased state).

[0135] According to one or more embodiments of the present disclosure, a memory controller (e.g., a processor, controller, firmware, etc.) located inside or outside a memory device is capable of determining (e.g., selecting, setting, adjusting, calculating, changing, clearing, transferring, adapting, deriving, defining, utilizing, modifying, applying, etc.) a certain number of wear cycles or wear states (e.g., recording wear cycles, counting operations of the memory device as they occur, tracking the operations of the memory device from which they originate, evaluating characteristics of the memory device corresponding to the wear states, etc.).

[0136] According to one or more embodiments of the present disclosure, a memory access device may be configured to provide wear cycle information to a memory device with each memory operation. Memory device control circuitry (e.g., logic control) may be programmed to compensate for changes in memory device performance corresponding to the wear cycle information. The memory device may receive the wear cycle information and determine one or more operating parameters (e.g., values, characteristics) in response to the wear cycle information.

[0137] It will be understood that when an element is referred to as being "on," "connected to," or "coupled to" another element, it can be directly on, directly connected to, or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element, there are no intervening elements or layers present. If two elements are shown in the drawings as being connected by a line, then the two elements may be coupled or directly coupled unless otherwise specified.

[0138] The method examples described herein may be implemented at least in part by a machine or computer. Some examples may include a computer-readable medium or machine-readable medium encoded with instructions that can be used to configure an electronic device to perform the methods described in the above examples. Implementations of such methods may include code, such as microcode, assembly language code, high-level language code, or the like. Such code may include computer-readable instructions for performing various methods. The code may form part of a computer program product. In addition, the code may be tangibly stored on one or more volatile or non-volatile tangible computer-readable media, for example, during execution or at other times. Examples of these tangible computer-readable media may include, but are not limited to: a hard disk, a removable magnetic disk, a removable optical disk (e.g., a compact disc and a digital video disc), a cassette tape, a memory card or stick, a random access memory (RAM), a read-only memory (ROM), a solid-state drive (SSD), a universal flash storage (UFS) device, an embedded MMC (eMMC) device, and the like.

[0139] The above description is intended to be illustrative and not restrictive. For example, the examples described above (or one or more aspects thereof) may be used in combination with each other. For example, a person of ordinary skill in the art may use other embodiments after consulting the above description. It should be understood that the summary of the invention will not be used to interpret or limit the scope or meaning of the claims. In addition, in the above detailed description, various features may be grouped together to simplify the present disclosure. This should not be interpreted as intending that the disclosed features that are not claimed for protection are essential to any claim. In fact, the subject matter of the present invention may be less than all the features of a particular disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed description, wherein each claim exists independently as a separate embodiment, and it is expected that these embodiments can be combined with each other in various combinations or arrangements. The scope of the present invention should be determined by reference to the appended claims and the full scope of equivalents given by the claims.

Claims

1. A memory controller for recovering a damaged storage portion in a memory device, the memory controller comprising: a memory device containing instructions; as well as processing circuitry that, when in operation, is configured by the instructions to: detecting a failure event during a garbage collection operation on a set of storage portions in a memory array, members of the set of storage portions being moved from a previous physical location to a new physical location by the garbage collection operation; In response to the failure event, retrieving a reference to a previous physical location of a potentially corrupted storage portion in the set of storage portions, the potentially corrupted storage portion having been written to a new physical location; as well as The potentially corrupted storage portion is overwritten at the new physical location using data from the previous physical location.

2. The memory controller of claim 1 , wherein to retrieve the reference to the previous physical location of the potentially corrupted storage portion, the processing circuitry is configured by the instructions to: identifying a second storage portion based on a physical relationship between the new physical location of the potentially damaged storage portion and a new physical location of the second storage portion; and The previous physical location of the potentially corrupted storage portion is read from the new physical location of the second storage portion.

3. The memory controller of claim 2 , wherein the processing circuitry is configured by the instructions to: identifying, during an original write of the potentially corrupted storage portion for the garbage collection operation, the second storage portion based on the physical relationship between the new physical location of the potentially corrupted storage portion and the new physical location of the second storage portion; and The previous physical location of the potentially corrupted storage portion is written to the new physical location of the second storage portion.

4. The memory controller of claim 2, wherein the storage portion is a page, and wherein the set of storage portions is a block in a NAND device.

5. The memory controller of claim 4 , wherein, in order to identify the second storage portion based on the physical relationship between the new physical location of the potentially corrupted storage portion and the new physical location of the second storage portion, the processing circuit system is configured by the instruction to add an offset to a page line of the new physical address of the potentially corrupted storage portion.

6. The memory controller of claim 4 , wherein, to identify the second storage portion based on the physical relationship between the new physical location of the potentially corrupted storage portion and the new physical location of the second storage portion, the processing circuit system is configured by the instruction to add an offset to the NAND die of the new physical address of the potentially corrupted storage portion.

7. The memory controller of claim 6 , wherein the processing circuitry is configured by the instructions to use a same plane in the offset NAND die in order to identify the second storage portion based on the physical relationship between the new physical location of the potentially damaged storage portion and the new physical location of the second storage portion.

8. A memory controller according to claim 4, wherein in order to read the previous physical location of the possibly damaged storage portion from the new physical location of the second storage portion, the processing circuit system is configured by the instruction to read a spare area of ​​a NAND page, which is the new physical location of the second storage portion.

9. The memory controller of claim 1, wherein the fault event is an asynchronous power loss during a program of a member of the set of memory portions.

10. The memory controller of claim 1, wherein the failure event is a failure of a program of a member of the set of memory portions.

11. A method for recovering a damaged storage portion in a memory device, the method comprising: detecting a failure event during a garbage collection operation on a set of storage portions in a memory array, members of the set of storage portions being moved from a previous physical location to a new physical location by the garbage collection operation; In response to the failure event, retrieving a reference to a previous physical location of a potentially corrupted storage portion in the set of storage portions, the potentially corrupted storage portion having been written to a new physical location; as well as The potentially corrupted storage portion is overwritten at the new physical location using data from the previous physical location.

12. The method of claim 11 , wherein retrieving the reference to the previous physical location of the potentially corrupted storage portion comprises: identifying a second storage portion based on a physical relationship between the new physical location of the potentially damaged storage portion and a new physical location of the second storage portion; and The previous physical location of the potentially corrupted storage portion is read from the new physical location of the second storage portion.

13. The method according to claim 12, comprising: identifying, during an original write of the potentially corrupted storage portion for the garbage collection operation, the second storage portion based on the physical relationship between the new physical location of the potentially corrupted storage portion and the new physical location of the second storage portion; as well as The previous physical location of the potentially corrupted storage portion is written to the new physical location of the second storage portion.

14. The method of claim 12, wherein the storage portion is a page, and wherein the set of storage portions is a block in a NAND device.

15. The method of claim 14 , wherein the second storage portion is identified based on the physical relationship between the new physical location of the potentially corrupted storage portion and the new physical location of the second storage portion, comprising adding an offset to a page line of the new physical address of the potentially corrupted storage portion.

16. The method of claim 14 , wherein the second storage portion is identified based on the physical relationship between the new physical location of the potentially damaged storage portion and the new physical location of the second storage portion as comprising a NAND die that adds an offset to the new physical address of the potentially damaged storage portion.

17. The method of claim 16, wherein identifying a second storage portion based on the physical relationship between the new physical location of the potentially damaged storage portion and the new physical location of the second storage portion includes using a same plane in the offset NAND die.

18. The method of claim 14, wherein reading the previous physical location of the potentially damaged storage portion from the new physical location of the second storage portion comprises reading a spare area of ​​a NAND page that is the new physical location of the second storage portion.

19. The method of claim 11, wherein the fault event is an asynchronous loss of power during a program of a member of the set of storage portions.

20. The method of claim 11, wherein the failure event is a failure of a program that is a member of the set of storage portions.

21. A machine-readable medium comprising instructions that, when executed by circuitry, cause the circuitry to perform the method of any one of claims 11 to 20.

22. A system for recovering a damaged storage portion in a memory device, comprising means for implementing the method according to any one of claims 11 to 20.

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