Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device includes: a substrate including an active region and a device isolation region; a flat plate structure formed on the substrate; an oxide semiconductor layer covering a top surface of the flat plate structure in the active region and the device isolation region and continuously provided on a top surface of the substrate; a gate structure provided on the oxide semiconductor layer and including a gate dielectric layer and a gate electrode; and source / drain regions provided on both sides of the gate structure and formed in the oxide semiconductor layer, wherein when observed from a side cross-section, an extending direction of the flat plate structure and an extending direction of the gate structure cross each other.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10 - 2020 - 0005599, filed with the Korean Intellectual Property Office on January 15, 2020, the entire contents of which are incorporated herein by reference. Technical field

[0003] The present inventive concept relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device including an oxide semiconductor layer and a method of manufacturing the same. Background art

[0004] With the rapid development of the electronics industry and the increasing user demands, electronic devices have become more and more compact and lightweight. Therefore, semiconductor devices are required as key devices in modern electronic devices with high integration, and at the same time, more stringent design rules may require continuous reduction of device feature sizes. In addition, the demand for high - speed semiconductor devices is also increasing. To meet the requirements of high integration and high speed of such semiconductor devices, various studies have been conducted. Summary of the invention

[0005] The present inventive concept provides a semiconductor device and a method of manufacturing the semiconductor device, in which an oxide semiconductor layer is continuously formed across a plurality of active regions of a substrate without etching it, and each transistor is electrically separable.

[0006] The problems to be solved by the technical idea of the present inventive concept are not limited to the above problems, and other problems not mentioned can be clearly understood by those of ordinary skill in the art from the following description.

[0007] According to an exemplary embodiment of the present inventive concept, there is provided a semiconductor device including: a substrate including active regions and device isolation regions; a flat plate structure formed on the substrate; an oxide semiconductor layer covering a top surface of the flat plate structure in the active regions and the device isolation regions and continuously disposed on a top surface of the substrate; a gate structure disposed on the oxide semiconductor layer and including a gate dielectric layer and a gate electrode; and source / drain regions disposed on both sides of the gate structure and formed in the oxide semiconductor layer, wherein when viewed from a side cross - section, an extending direction of the flat plate structure and an extending direction of the gate structure cross each other.

[0008] According to an exemplary embodiment of the inventive concept, a semiconductor device is provided, including: a substrate configured to define a plurality of active regions; an insulating layer covering a top surface of the substrate; a gate electrode formed on the insulating layer and extending in a first direction; a gate dielectric layer covering the insulating layer and the gate electrode; an oxide semiconductor layer disposed on the gate dielectric layer and configured to form a channel region in each of the plurality of active regions; a plurality of contact structures electrically connected to the oxide semiconductor layer; and an upper gate metal layer formed between every two adjacent ones of the plurality of active regions, wherein a device isolation insulating layer is not formed between every two adjacent ones of the plurality of active regions.

[0009] According to an exemplary embodiment of the inventive concept, a semiconductor device is provided, including: a substrate including a device isolation region configured to define a plurality of active regions; a first insulating layer formed on the substrate; a lower gate metal layer covering all of the plurality of active regions and the device isolation region of the substrate, on the first insulating layer, and configured for device isolation; a second insulating layer formed on the lower gate metal layer; an oxide semiconductor layer disposed on the second insulating layer and configured to form a channel region in each of the plurality of active regions; a plurality of gate structures, each of the plurality of gate structures being disposed on a channel region in a corresponding one of the plurality of active regions; source / drain regions disposed on both sides of each of the plurality of gate structures and formed in the oxide semiconductor layer; contact structures electrically connected to the source / drain regions; and a lower gate metal layer contact portion electrically connected to the lower gate metal layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Exemplary embodiments of the inventive concept will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0011] Figure 1A is a plan view of a semiconductor device according to an exemplary embodiment of the inventive concept, Figure 1B is along Figure 1A a cross-sectional view of the semiconductor device taken along line B-B′;

[0012] Figures 2 to 4 are all views of a semiconductor device according to an exemplary embodiment of the inventive concept;

[0013] Figure 5A is a plan view showing a semiconductor device according to an exemplary embodiment of the inventive concept, Figure 5B is along Figure 5A a cross-sectional view of the semiconductor device taken along line BB-BB′, Figure 5C is along Figure 5AA cross-sectional view of the semiconductor device taken along line CC-CC′;

[0014] Figures 6 to 8 are diagrams of semiconductor devices according to exemplary embodiments of the inventive concept;

[0015] Figure 9 is a flowchart of a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept;

[0016] Figures 10A to 10E is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to a process sequence according to an exemplary embodiment of the inventive concept;

[0017] Figure 11 is a flowchart of a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept;

[0018] Figures 12A to 12C , Figures 13A to 13C , Figures 14A to 14C , Figures 15A to 15C , Figures 16A to 16C as well as Figures 17A to 17C is a diagram illustrating a method of manufacturing a semiconductor device according to a process sequence according to an exemplary embodiment of the inventive concept; and

[0019] Figure 18 is a configuration diagram of a system of a semiconductor module according to an exemplary embodiment of the inventive concept.

[0020] because Figures 1A to 18 The drawings in the drawings are for illustrative purposes only, and thus the elements in the drawings are not necessarily drawn to scale. For example, some elements may be enlarged or enlarged for clarity. DETAILED DESCRIPTION

[0021] Hereinafter, exemplary embodiments of the inventive concept are described in detail with reference to the accompanying drawings.

[0022] Figure 1A is a plan view of a semiconductor device 10 according to an exemplary embodiment of the present inventive concept, Figure 1B is along Figure 1A 1 is a cross-sectional view of the semiconductor device 10 taken along line BB′.

[0023] refer to Figure 1A and Figure 1B The semiconductor device 10 includes a plate structure 110 , an oxide semiconductor layer 120 , a gate structure 130 , a contact plug 150 , and a gate contact 160 disposed on a substrate 100 .

[0024] The substrate 100 may include a wafer, and the wafer includes, for example, silicon (Si). In an exemplary embodiment of the inventive concept, the substrate 100 may include a wafer including a semiconductor element (e.g., germanium (Ge)), or a compound semiconductor (e.g., silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), gallium antimonide (GaSb), indium antimonide (InSb), indium arsenide (InAs), indium phosphide (InP), indium gallium arsenide (InGaAs), cadmium selenide (CdSe), cadmium sulfide (CdS), cadmium telluride (CdTe), zinc oxide (ZnO), zinc selenide (ZnSe), zinc sulfide (ZnS), or zinc telluride (ZnTe)). The substrate 100 may have a silicon-on-insulator (SOI) structure. The substrate 100 may include a conductive region, e.g., a well doped with an impurity or a structure doped with an impurity. Additionally, the substrate 100 may include one or more semiconductor layers or structures and may include an active or operable portion of a semiconductor device.

[0025] The flat structure 110 may be formed on the substrate 100. The flat structure 110 may include a first insulating layer 112, a lower gate metal layer 114, and a second insulating layer 116 sequentially stacked on the substrate.

[0026] To serve as a physical barrier layer and as an electrical insulating layer, both the first insulating layer 112 and the second insulating layer 116 may include an inorganic insulating material. For example, both the first insulating layer 112 and the second insulating layer 116 may include at least one of silicon oxide (SiO2), silicon nitride (Si3N4), or aluminum oxide (Al2O3). For example, the first insulating layer 112 or the second insulating layer 116 may serve as a buffer layer to reduce stress caused by a lattice constant difference between the material constituting the substrate 100 and the material constituting the oxide semiconductor layer 120. In addition, the first insulating layer 112 or the second insulating layer 116 may prevent impurities such as hydrogen (H) atoms from diffusing from the substrate 100 into the interior of the oxide semiconductor layer 120 and may serve as a barrier layer to prevent current flowing inside the oxide semiconductor layer 120 from leaking into the substrate 100. In an exemplary embodiment of the inventive concept, since silane (SiH4) gas and ammonia (NH3) gas may be used to form silicon nitride (Si3N4), and hydrogen (H) atoms may be included in the silicon nitride (Si3N4) film, the second insulating layer 116 in direct contact with the oxide semiconductor layer 120 may not include silicon nitride (Si3N4) and may include, for example, silicon oxide (SiO2) and / or aluminum oxide (Al2O3). The second insulating layer 116 including silicon oxide (SiO2) and / or aluminum oxide (Al2O3) may prevent or inhibit any hydrogen (H) atoms from moving upward into the oxide semiconductor layer 120.

[0027] The lower gate metal layer 114 may be interposed between the first insulating layer 112 and the second insulating layer 116. The lower gate metal layer 114 may include, for example, doped polysilicon (p-Si), metal, metal nitride, metal silicide, or a combination thereof. In an exemplary embodiment of the inventive concept, the lower gate metal layer 114 may include at least one of, for example, nickel (Ni), cobalt (Co), or ruthenium (Ru). As will be described later, when a specific voltage is applied via the lower gate metal layer contact 170, the lower gate metal layer 114 may locally operate the oxide semiconductor layer 120 in an insulating state. Thus, although the oxide semiconductor layer 120 is formed without isolation, the transistor may be electrically isolated by applying a voltage to the lower gate metal layer 114 via the lower gate metal layer contact 170.

[0028] The top surface of the lower gate metal layer 114 may have a planar structure, and the lower gate metal layers 114 may be continuously connected to each other above the substrate 100. In other words, the lower gate metal layer 114 may be formed to have the same thickness over the active region AR and the device isolation region IR of the substrate 100.

[0029] The oxide semiconductor layer 120 may be formed on the second insulating layer 116 of the flat plate structure 110. The oxide semiconductor layer 120 may have a flat top surface, may be configured for device isolation, and may be continuously formed to cover the top surface of the flat plate structure 110 in the active region AR and the device isolation region IR. The height of the top surface of the oxide semiconductor layer 120 may be higher than the height of the top surface of the substrate 100.

[0030] The oxide semiconductor layer 120 may include a conductive oxide, such as a homologous oxide. In this case, the homologous oxide may refer to an oxide having the formula RAO3(MO) ma material, where R is an element selected from, for example, scandium (Sc), ytterbium (Yb), lutetium (Lu), and indium (In); A is an element selected from, for example, gallium (Ga), aluminum (Al), iron (Fe), and indium (In); M is an element selected from, for example, zinc (Zn) and magnesium (Mg); and m is an integer). However, the elements R, A, and M that can be included in the homologous oxide are not limited thereto. For example, the oxide semiconductor layer 120 may include at least one of, for example, indium gallium zinc oxide (InGaZnO), indium gallium silicon oxide (InGaSiO), indium tin zinc oxide (InSnZnO), indium zinc oxide (InZnO), and hafnium indium zinc oxide (HfInZnO). For example, in an exemplary embodiment of the inventive concept, the oxide semiconductor layer 120 may include indium gallium zinc oxide (InGaZnO) (also referred to as IGZO) formed of indium (In), gallium (Ga), zinc (Zn), and oxygen (O), or a-IGZO in an amorphous form (In2Ga2ZnO7) or a crystalline form (InGaZnO4).

[0031] In an exemplary embodiment of the inventive concept, the oxide semiconductor layer 120 may have an amorphous structure or a c-axis oriented crystalline structure. For example, when the oxide semiconductor layer 120 includes an indium gallium zinc oxide (InGaZnO) layer having a c-axis oriented crystalline structure, the oxide semiconductor layer 120 may have a YbFeO-type crystalline structure. This c-axis oriented crystalline structure makes the out-of-plane direction (along the c-axis) and the in-plane direction (within the a-b plane) two different crystalline directions. In the YbFeO-type crystalline structure, an InO layer having a hexagonal arrangement may be disposed in a layered structure along the c-axis direction, and a (Ga, Zn)O layer may be between two adjacent InO layers. However, the crystalline structure of the oxide semiconductor layer 120 is not limited thereto.

[0032] In an exemplary embodiment of the inventive concept, at least one impurity such as fluorine (F), hydrogen (H), nitrogen (N), magnesium (Mg), yttrium (Y), ruthenium (Ru), or arsenic (As) may be doped into the oxide semiconductor layer 120. By doping with p-type or n-type impurities, the oxide semiconductor layer 120 can increase its conductivity. For example, since donor energy levels are formed above the conduction band, many crystalline oxide semiconductors can be doped with hydrogen (H) to achieve high conductivity. For example, in order to dope impurities into the oxide semiconductor layer 120, the impurities may be doped in-situ during the process of forming the oxide semiconductor layer 120, or ion implantation of impurity ions may be performed after the oxide semiconductor layer 120 is formed.

[0033] The active region AR may be defined in the oxide semiconductor layer 120. For example, the oxide semiconductor layer 120 may include an active region AR constituting a first transistor TR1, and the oxide semiconductor layer 120 may include an active region AR constituting a second transistor TR2. The first transistor TR1 and the second transistor TR2 may be formed in different active regions AR. In an exemplary embodiment of the inventive concept, the first transistor TR1 may include an NMOS transistor, and the second transistor TR2 may include a PMOS transistor, but the inventive concept is not limited thereto.

[0034] The first transistor TR1 and the second transistor TR2 may be partial components of a volatile semiconductor memory device or may be included as partial components of a non-volatile semiconductor memory device, such as a dynamic random access memory (RAM) (DRAM) or a static RAM (SRAM) for the volatile semiconductor memory device, and a phase change RAM (PRAM), a magnetoresistive RAM (MRAM), a ferroelectric RAM (FeRAM), or a resistive RAM (RRAM) for the non-volatile semiconductor memory device.

[0035] As shown, the semiconductor device 10 according to an exemplary embodiment of the inventive concept has been described as a planar transistor, but the inventive concept is not limited thereto. For example, the semiconductor device 10 according to an exemplary embodiment of the inventive concept may include, for example, a fin-type transistor including a fin-type active region, a tunneling field effect transistor (FET), a transistor including a nanowire, a transistor including a nanosheet (i.e., a multi-bridge channel FET ) or various three-dimensional (3D) transistors.

[0036] The top surface of the oxide semiconductor layer 120 may have a planar structure, and the oxide semiconductor layers 120 may be continuously connected to each other above the substrate 100. In other words, the oxide semiconductor layer 120 may be formed to have the same thickness over the active region AR and the device isolation region IR of the substrate 100.

[0037] The semiconductor device 10 of the inventive concept may not include physical components such as a device isolation structure (i.e., a device isolation layer or a device isolation trench) in the device isolation region IR. When a specific voltage is applied via the lower gate metal layer contact portion 170 electrically connected to the lower gate metal layer 114, the oxide semiconductor layer 120 may operate in an insulating state. Accordingly, although the oxide semiconductor layer 120 is formed without isolation, the active region AR may be electrically isolated by applying a voltage to the lower gate metal layer 114 via the lower gate metal layer contact portion 170.

[0038] The gate structures 130 may be spaced apart from each other in a first direction (X direction) on the oxide semiconductor layer 120 and may extend in a second direction (Y direction). In an exemplary embodiment of the inventive concept, each gate structure 130 may be planar, but the inventive concept is not limited thereto. The gate structure 130 may include a gate dielectric layer 132, a gate electrode 134, a gate capping layer 136, and a gate spacer 138. When viewed from Figure 1B the side cross-sectional view shown, the flat plate structure 110 extends in a first direction (X direction), which may intersect the extending direction of the gate structure 130 (e.g., the second direction (Y direction)).

[0039] The gate dielectric layer 132 may be formed on the oxide semiconductor layer 120. The gate dielectric layer 132 may include, for example, a silicon oxide (SiO2) layer, a silicon oxynitride (SiON) layer, a high-k (high dielectric constant) layer having a dielectric constant higher than that of the silicon oxide (SiO2) layer, or a combination thereof. The high-k layer may include a metal oxide or a metal oxynitride. For example, the high-k layer that may be used as the gate dielectric layer 132 may include, for example, hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), hafnium aluminum oxide (HfAlO), zirconium oxide (ZrO2), titanium oxide (TiO2), yttrium oxide (Y2O3), tantalum oxide (Ta2O5), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO), lanthanum hafnium oxide (LaHfO), aluminum oxide (Al2O3), or a combination thereof, but the inventive concept is not limited thereto.

[0040] The gate electrode 134 may be formed on the gate dielectric layer 132. The gate electrode 134 may cover the top surface of the gate dielectric layer 132 and may extend in the second direction (Y direction). The gate electrode 134 may include, for example, doped polysilicon (p-Si), a metal, or a combination thereof. For example, the gate electrode 134 may include a metal having at least one of the following: for example, tungsten (W), aluminum (Al), cobalt (Co), titanium (Ti), tantalum (Ta), copper (Cu), molybdenum (Mo), or a metal alloy thereof. For example, the gate electrode 134 may include a metal silicide material, such as nickel silicide (NiSi2), titanium silicide (TiSi2), tungsten silicide (WSi2), or cobalt silicide (CoSi2).

[0041] The gate capping layer 136 may be formed on the gate electrode 134. The gate capping layer 136 may cover the top surface of the gate electrode 134 and may extend in the second direction (Y direction). For example, the gate capping layer 136 may include, for example, silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbon oxynitride (SiCON), or silicon nitride (Si3N4).

[0042] The gate spacer 138 may be formed on two sidewalls of the gate dielectric layer 132, the gate electrode 134, and the gate capping layer 136, and may extend in the second direction (Y direction). The gate spacer 138 may include, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), or a combination thereof.

[0043] In an exemplary embodiment of the inventive concept, the gate spacer 138 may include a plurality of layers including materials different from each other. Although the gate spacer 138 is shown in Figure 1B as including a single layer, the inventive concept is not limited thereto. For example, in an exemplary embodiment of the inventive concept, the gate spacer 138 may include a first spacer layer, a second spacer layer, and a third spacer layer formed in sequence. The first spacer layer and the third spacer layer may include, for example, silicon nitride (Si3N4), silicon oxide (SiO2), or silicon oxynitride (SiON). The second spacer layer may include an insulating material having a lower dielectric constant than the first spacer layer, and may include, for example, an air gap.

[0044] The source / drain regions SD may be formed inside the oxide semiconductor layer 120 on both sides of the gate structure 130. In other words, two source / drain regions SD may be formed inside the oxide semiconductor layer 120, where one source / drain region SD is located on one side of the gate structure 130, and the other source / drain region SD is located on the opposite side of the gate structure 130. In addition, the channel region CH may be formed inside the oxide semiconductor layer 120 and disposed under the gate structure 130, where the top surface of the oxide semiconductor layer 120 has a planar structure. A p-type impurity or an n-type impurity may be doped in the source / drain regions SD.

[0045] The interlayer insulating layer 140 may be formed on the oxide semiconductor layer 120 to cover the gate structure 130. The interlayer insulating layer 140 may include, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tetraethyl orthosilicate (TEOS), or a low-k dielectric material having a low dielectric constant of about 2.2 to 2.4. As an example, the low-k dielectric material may include carbon-doped silicon oxide, such as SiCOH.

[0046] The contact plug 150 may penetrate the interlayer insulating layer 140 and may be electrically connected to the source / drain region SD. In addition, the gate contact 160 may penetrate the interlayer insulating layer 140 and the gate capping layer 136 and may be electrically connected to the gate electrode 134.

[0047] The contact plug 150 and the gate contact 160 may include, for example, doped polysilicon (p-Si), metal, metal nitride, metal silicide, or a combination thereof. In an exemplary embodiment of the inventive concept, the contact plug 150 and the gate contact 160 may be formed as a bilayer structure including a metal buried layer and a conduction barrier layer surrounding side and bottom surfaces of the metal buried layer.

[0048] The metal buried layer may include, for example, at least one of cobalt (Co), tungsten (W), nickel (Ni), ruthenium (Ru), copper (Cu), aluminum (Al), its silicide, or its alloy. Additionally, the conduction barrier layer may include, for example, titanium (Ti), tantalum (Ta), ruthenium (Ru), titanium nitride (TiN), tantalum nitride (TaN), or a combination thereof, but the inventive concept is not limited thereto. Although in Figure 1B one contact plug 150 is shown as being located on both sides of the gate structure 130 (e.g., one contact plug 150 on each side), two or more contact plugs 150 may be on both sides of the gate structure 130.

[0049] In an exemplary embodiment of the inventive concept, in a contact region CR spaced apart from the active region AR in which the gate structure 130 is provided by a certain distance, the lower gate metal layer contact 170 may penetrate the interlayer insulating layer 140 and the second insulating layer 116 and may be electrically connected to the lower gate metal layer 114. The lower gate metal layer contact 170 may not contact the oxide semiconductor layer 120. Accordingly, the height of the bottom surface of the contact plug 150 may be higher than the height of the bottom surface of the lower gate metal layer contact 170. The lower gate metal layer contact 170 may include, for example, doped polysilicon (p-Si), metal, metal nitride, metal silicide, or a combination thereof. In an exemplary embodiment of the inventive concept, similar to the contact plug 150 and the gate contact 160, the lower gate metal layer contact 170 may be formed as a bilayer structure including a metal buried layer and a conduction barrier layer surrounding side and bottom surfaces of the metal buried layer.

[0050] Although in Figure 1B one lower gate metal layer contact 170 is shown as being on one side of the substrate 100, the inventive concept is not limited thereto. Additionally, the position of the lower gate metal layer contact region CR is not limited to Figure 1B the position shown.

[0051] With the rapid development of the electronics industry and the increasing user requirements, electronic devices have become more and more compact and lightweight. Therefore, semiconductor devices are required as key devices in modern electronic devices with high integration, and at the same time, more stringent design rules may require continuous reduction of device feature sizes. In addition, the demand for high-speed semiconductor devices is also increasing. To meet the requirements of high integration and high speed of semiconductor devices, various studies have been conducted.

[0052] The technology for solving the patterning process problem of oxide semiconductors is also one of various studies. Oxide semiconductors are materials used in semiconductor devices to reduce leakage current in the channel region CH. In the case of oxide semiconductors (e.g., InGaZnO), it is usually difficult to form an array structure with a pitch of about 100 nm or less. This is because in the case of dry etching of oxide semiconductors, etching by-products adhere to the wall surface of the processing chamber and are not removed from the wall surface of the processing chamber, so there may be a problem that the oxide semiconductor may be contaminated. Therefore, it may be difficult to dry-etch the oxide semiconductor to have a small pitch during the manufacturing process of the array structure and to form a device isolation structure within the small pitch.

[0053] To solve the above problems, the semiconductor device 10 according to an exemplary embodiment of the inventive concept can provide a structure in which electrical insulation can be formed between gate structures 130 without etching the oxide semiconductor layer 120. It has been confirmed that when a specific negative bias is applied to the oxide semiconductor layer 120, the cut-off state (I off ) of the leakage current of the oxide semiconductor layer 120 is measured to be about 1e-20 A / μm.

[0054] I off The fact that it is about 1e-20 A / μm can be interpreted as meaning that the oxide semiconductor layer 120 works like an insulating material (e.g., silicon oxide (SiO2)). Therefore, the semiconductor device 10 according to an exemplary embodiment of the inventive concept can realize an array structure having the same feature size as that of a general semiconductor device without using the oxide semiconductor layer 120.

[0055] A specific negative bias voltage can be applied to the oxide semiconductor layer 120 via the flat plate structure 110 (e.g., via the lower gate metal layer 114 of the flat plate structure 110). When a voltage of approximately -0.5V to approximately -1V (e.g., about -0.7V) is applied to the oxide semiconductor layer 120 via the lower gate metal layer 114 of the flat plate structure 110, the oxide semiconductor layer 120 can operate in an insulating state. Alternatively, when the lower gate metal layer 114 of the flat plate structure 110 includes a p-type metal (e.g., nickel (Ni), cobalt (Co), or ruthenium (Ru)) having a work function of about 4.5eV or higher, the oxide semiconductor layer 120 can operate in an insulating state even without applying a negative bias voltage to the oxide semiconductor layer 120.

[0056] When a specific operating voltage is applied to the gate electrode 134 for the operation of the first transistor TRl and the second transistor TR2, the oxide semiconductor layer 120 corresponding to the active region AR can be used as the channel region CH. For example, a portion of the oxide semiconductor layer 120 that vertically overlaps with the gate electrode 134 in the active region AR can be used as the channel region CH of the first transistor TR1 or the second transistor TR2.

[0057] In the semiconductor device 10 according to an exemplary embodiment of the inventive concept, the first transistor TR1 and the second transistor TR2 can operate independently by allowing the device isolation region IR to substantially maintain an electrically insulating state between the active regions, while omitting the process of forming a device isolation structure by etching the oxide semiconductor layer 120. For example, the oxide semiconductor layer 120 according to this exemplary embodiment can maintain an insulating state in the device isolation region IR and can be used as the channel region CH in the active region AR at the same time.

[0058] Since the manufacturing process of the semiconductor device 10 according to the inventive concept is simplified, the productivity and economic efficiency of the semiconductor device 10 can be improved.

[0059] Figures 2 to 4 are diagrams of semiconductor devices 20, 30, and 40 according to exemplary embodiments of the inventive concept, respectively.

[0060] Most of the components constituting the semiconductor devices 20, 30, and 40 and the materials of the components described below can be substantially the same as or similar to those described above with reference to Figure 1A and Figure 1B Therefore, for ease of description, the differences from the above-described semiconductor device (refer to Figure 1B 10 therein) will be mainly described.

[0061] Refer to Figure 2, the semiconductor device 20 may include a flat structure 110, an oxide semiconductor layer 120, a gate structure 130A, and a contact plug 150 disposed on a substrate 100.

[0062] The gate structure 130A may include a gate dielectric layer 132A, a gate electrode 134A, a gate capping layer 136A, and a gate spacer 138A. The gate dielectric layer 132A may surround two side surfaces and a bottom surface of the gate electrode 134A, and may be formed between the gate electrode 134A and the oxide semiconductor layer 120 and between the gate electrode 134A and the gate spacer 138A.

[0063] The gate electrode 134A may include at least one of, for example, a metal, a metal nitride, or a metal carbide. For example, the gate electrode 134A may include, for example, aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), titanium nitride (TiN), tungsten nitride (WN), titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), tantalum carbonitride (TaCN), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), or a combination thereof, but the inventive concept is not limited thereto. In an exemplary embodiment of the inventive concept, the gate electrode 134A may include a work function metal-containing layer and a gap-fill metal layer.

[0064] The work function metal-containing layer may include at least one metal of, for example, titanium (Ti), tungsten (W), ruthenium (Ru), niobium (Nb), molybdenum (Mo), hafnium (Hf), nickel (Ni), cobalt (Co), platinum (Pt), ytterbium (Yb), terbium (Tb), dysprosium (Dy), erbium (Er), or palladium (Pd). Alternatively, the work function metal-containing layer may include at least one of, for example, titanium nitride (TiN), tungsten nitride (WN), titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), titanium carbide (TiC), tantalum carbide (TaC), titanium aluminum carbide (TiAlC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), or a combination thereof. The gap-fill metal layer may include, for example, tungsten (W) or aluminum (Al). In an exemplary embodiment of the inventive concept, the gate electrode 134A may have a stacked structure such as TiAlC / TiN / W, TiN / TaN / TiAlC / TiN / W, or TiN / TaN / TiN / TiAlC / TiN / W, but the inventive concept is not limited thereto.

[0065] The interlayer insulating layer 140 may have a top surface at the same height as the top surface of the gate structure 130A. The interlayer insulating layer 140 may surround sidewalls of the gate spacer 138A.

[0066] In an exemplary embodiment of the inventive concept, an upper interlayer insulating layer 142 may be further formed on the interlayer insulating layer 140 and the gate structure 130A, and the contact plug 150 may penetrate the upper interlayer insulating layer 142 and the interlayer insulating layer 140 and may be electrically connected to the top surface of the source / drain region SD. Since the manufacturing process of the semiconductor device 20 according to the present exemplary embodiment is simplified, the productivity and economic efficiency of the semiconductor device 20 may be improved.

[0067] Referring Figure 3 , the semiconductor device 30 may include a first transistor TR1 and a third transistor TR3 disposed on a substrate 100.

[0068] An active region AR may be defined in the oxide semiconductor layer 120. The oxide semiconductor layer 120 may include the active region AR constituting the first transistor TR1, and in addition, may include the active region AR constituting the third transistor TR3. The first transistor TR1 and the third transistor TR3 may be formed in different active regions AR and may be separated by a device isolation region IR. For example, the first transistor TR1 may include an NMOS transistor, and the third transistor TR3 may include a PMOS transistor, but the inventive concept is not limited thereto.

[0069] The semiconductor device 30 of the inventive concept may not include physical components such as a device isolation structure (i.e., a device isolation layer or a device isolation trench) in the device isolation region IR.

[0070] The first transistor TR1 and the third transistor TR3 may be arranged to have increased degrees of freedom. In other words, since a device isolation structure for partitioning the active region AR is not required, the first transistor TR1 and the third transistor TR3 may be freely arranged at desired positions. In Figure 3 , the first transistor TR1 and the third transistor TR3 are shown in directions perpendicular to each other, but the inventive concept is not limited thereto. For example, the first transistor TR1 and the third transistor TR3 may be arranged at a specific angle rather than a right angle. Since the manufacturing process of the semiconductor device 30 according to the present exemplary embodiment is simplified, the productivity and economic efficiency of the semiconductor device 30 may be improved.

[0071] Referring Figure 4 , the semiconductor device 40 may include a planar structure 110A, an oxide semiconductor layer 120, a gate structure 130, and a contact plug 150 disposed on a substrate 100.

[0072] The planar structure 110A may be formed on the substrate 100. The planar structure 110A may include a first insulating layer 112A, a lower gate metal layer 114A, a second insulating layer 116A, and a third insulating layer 118A.

[0073] Each of the first insulating layer 112A, the second insulating layer 116A, and the third insulating layer 118A may include at least one of, for example, silicon oxide (SiO2), silicon nitride (Si3N4), or aluminum oxide (Al2O3). In an exemplary embodiment of the inventive concept, the first insulating layer 112A, the second insulating layer 116A, or the third insulating layer 118A may serve as a buffer layer to reduce stress caused by a lattice constant difference between the material constituting the substrate 100 and the material constituting the oxide semiconductor layer 120. Additionally, the first insulating layer 112A, the second insulating layer 116A, or the third insulating layer 118A may prevent impurities such as hydrogen (H) atoms in the substrate 100 from diffusing into the oxide semiconductor layer 120 and may serve as a barrier layer to prevent current flowing inside the oxide semiconductor layer 120 from leaking into the interior of the substrate 100. Since hydrogen (H) atoms may be contained in the silicon nitride (Si3N4) film, in an embodiment of the inventive concept, the second insulating layer 116A in direct contact with the oxide semiconductor layer 120 may not include silicon nitride (Si3N4) and may include, for example, silicon oxide (SiO2) and / or aluminum oxide (Al2O3). The second insulating layer 116A including silicon oxide (SiO2) and / or aluminum oxide (Al2O3) may prevent or inhibit any hydrogen (H) atoms from moving upward into the oxide semiconductor layer 120.

[0074] The side surface of the lower gate metal layer 114A may be surrounded by the third insulating layer 118A between the first insulating layer 112A and the second insulating layer 116A. The lower gate metal layer 114A may include, for example, doped polysilicon (p-Si), a metal, a metal nitride, a metal silicide, or a combination thereof.

[0075] In an exemplary embodiment of the inventive concept, the lower gate metal layer 114A may include at least one of, for example, nickel (Ni), cobalt (Co), or ruthenium (Ru). When a specific voltage is applied to the lower gate metal layer 114A via the lower gate metal layer contact portion (refer to 170 in Figure 1B , the isolation region IS of the oxide semiconductor layer 120 corresponding to the lower gate metal layer 114A may operate in an insulating state.

[0076] The lower gate metal layer 114A may be formed only in the device isolation region IR of the substrate 100. In other words, the lower gate metal layer 114A may not be formed in the active region AR of the substrate 100. However, since the third insulating layer 118A is formed on the side surfaces of the lower gate metal layer 114A, the top surface of the flat plate structure 110A may be flat on the entire surface of the substrate 100 or on a plurality of active regions AR. Therefore, although the oxide semiconductor layer 120 is formed without isolation, the active regions AR can be electrically isolated by applying a voltage to the lower gate metal layer 114A located in the device isolation region IR of the substrate 100. Since the manufacturing process of the semiconductor device 40 according to the present exemplary embodiment is simplified, the productivity and economic efficiency of the semiconductor device 40 can be improved.

[0077] Figure 5A is a plan view of a semiconductor device 50 according to an exemplary embodiment of the inventive concept, Figure 5B is along Figure 5A a cross-sectional view of the semiconductor device 50 taken along line BB-BB', and Figure 5C is along Figure 5A a cross-sectional view of the semiconductor device 50 taken along line CC-CC'.

[0078] Referring together to Figures 5A to 5C , the semiconductor device 50 may include a gate structure 210, an oxide semiconductor layer 220, an upper structure 230, and contact plugs 250 disposed on a substrate 200.

[0079] The substrate 200 may include a wafer containing silicon (Si) and may be substantially the same as the above-described substrate (refer to Figure 1B 100 therein). The substrate 200 may include conductive regions, for example, wells doped with impurities or structures doped with impurities. Additionally, the substrate 100 may include one or more semiconductor layers or structures and may include active or working portions of semiconductor devices.

[0080] The gate structure 210 may be formed on the substrate 200. The gate structure 210 may include a lower insulating layer 212, a gate electrode 214, and a gate dielectric layer 216.

[0081] The lower insulating layer 212 may include at least one of, for example, silicon oxide (SiO2), silicon nitride (Si3N4), or aluminum oxide (Al2O3). For example, the lower insulating layer 212 may be used as a buffer layer to reduce stress caused by a lattice constant difference between the material constituting the substrate 200 and the material constituting the oxide semiconductor layer 220. In addition, the lower insulating layer 212 may prevent impurities such as hydrogen (H) atoms from diffusing from the substrate 200 into the oxide semiconductor layer 220, and may be used as a barrier layer to prevent current flowing inside the oxide semiconductor layer 220 from leaking into the substrate 200.

[0082] The gate electrode 214 may be formed on the lower insulating layer 212. The gate electrode 214 may include, for example, doped polysilicon (p-Si), a metal, or a combination thereof. The gate electrode 214 may extend in a first direction (X direction) and may be spaced apart from each other in a second direction (Y direction). In other words, the gate electrode 214 may form a gate line.

[0083] In an exemplary embodiment of the inventive concept, the plurality of gate electrodes 214 may include at least two gate electrodes 214 adjacent to each other and having a first spacing distance Dl in the second direction (Y direction), and at least two gate electrodes 214 adjacent to each other and having a second spacing distance D2 greater than the first spacing distance D1. In other words, the distances between the plurality of gate electrodes 214 may not be the same.

[0084] The gate dielectric layer 216 may conformally cover the top surface of the gate electrode 214. The gate dielectric layer 216 may include, for example, a silicon oxide (SiO2) layer, a silicon oxynitride (SiON) layer, a high-k layer having a dielectric constant higher than that of the silicon oxide (SiO2) layer, or a combination thereof. The high-k layer may include, for example, a metal oxide or a metal oxynitride. For example, the high-k layer that may be used as the gate dielectric layer 216 may include, for example, hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), hafnium aluminum oxide (HfAlO), zirconium oxide (ZrO2), titanium oxide (TiO2), yttrium oxide (Y2O3), tantalum oxide (Ta2O5), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO), lanthanum hafnium oxide (LaHfO), aluminum oxide (Al2O3), or a combination thereof, but the inventive concept is not limited thereto.

[0085] The oxide semiconductor layer 220 may conformally cover the gate dielectric layer 216 of the gate structure 210. The height of the top surface of the oxide semiconductor layer 220 may be higher than the height of the top surface of the substrate 200. The material constituting the oxide semiconductor layer 220 may be the same as the above-mentioned oxide semiconductor layer (referenceFigure 1B The materials in (120) are substantially the same.

[0086] The active region AR can be defined in the oxide semiconductor layer 220. The oxide semiconductor layer 220 can include the active region AR constituting the NMOS transistor, and in addition, can include the active region AR constituting the PMOS transistor. For example, the NMOS transistor and the PMOS transistor can be formed in different active regions AR separated by the device isolation region IR.

[0087] The top surface of the oxide semiconductor layer 220 can have an uneven structure and can be continuously connected to each other on the upper part of the entire surface of the substrate 200 or in a plurality of active regions AR. In other words, the oxide semiconductor layer 220 can be formed without breakage on the active region AR and the device isolation region IR of the substrate 200.

[0088] The semiconductor device 50 according to the inventive concept may not include physical components such as a device isolation structure (e.g., a device isolation layer or a device isolation trench) in the device isolation region IR. Instead, when a specific voltage is applied to the upper gate metal layer 234, the oxide semiconductor layer 220 can operate in a locally insulated state.

[0089] The upper structure 230 can be formed on the oxide semiconductor layer 220. The upper structure 230 can include an upper insulating layer 232 and an upper gate metal layer 234.

[0090] The upper insulating layer 232 can conformally cover the oxide semiconductor layer 220 and can include at least one of, for example, silicon oxide (SiO2), silicon nitride (Si3N4), or aluminum oxide (Al2O3). The upper insulating layer 232 can have a top surface with an uneven structure, and the height of the top surface of the upper insulating layer 232 can be higher than the height of the top surface of the substrate 200.

[0091] The upper gate metal layer 234 can be formed on the upper insulating layer 232 and can include, for example, doped polysilicon (p-Si), a metal, a metal nitride, a metal silicide, or a combination thereof. In an exemplary embodiment of the inventive concept, the upper gate metal layer 234 can include at least one of, for example, nickel (Ni), cobalt (Co), or ruthenium (Ru). When a specific voltage is applied to the upper gate metal layer 234, the oxide semiconductor layer 220 can operate in a locally insulated state.

[0092] The upper gate metal layer 234 may be formed only in the device isolation region IR of the substrate 200. In other words, the upper gate metal layer 234 may not be formed in the active region AR of the substrate 200. For example, the upper gate metal layer 234 may be formed between every two adjacent active regions AR among a plurality of active regions AR, and the device isolation insulating layer may not be formed between every two adjacent active regions AR among the plurality of active regions AR.

[0093] In an exemplary embodiment of the inventive concept, the upper gate metal layer 234 may include a first upper gate metal layer 234-1 formed between gate electrodes 214 and a second upper gate metal layer 234-2 formed on the barrier insulating layer 231.

[0094] The first upper gate metal layer 234-1 may extend in a first direction (X direction) and may be spaced apart from each other in a second direction (Y direction). In addition, the second upper gate metal layer 234-2 may extend in the second direction (Y direction) and may be separated from each other in the first direction (X direction). In other words, the first upper gate metal layer 234-1 and the second upper gate metal layer 234-2 may cross each other perpendicularly.

[0095] In an exemplary embodiment of the inventive concept, the height of the top surface of the first upper gate metal layer 234-1 may be lower than the height of the bottom surface of the second upper gate metal layer 234-2. This may be because the second upper gate metal layer 234-2 is disposed on the barrier insulating layer 231 having a specific thickness. For example, the second upper gate metal layer 234-2 may vertically overlap the barrier insulating layer 231.

[0096] The barrier insulating layer 231 may include at least one of, for example, silicon oxide (SiO2), silicon nitride (Si3N4), or aluminum oxide (Al2O3). The barrier insulating layer 231 may extend in the second direction (Y direction) and may be spaced apart from each other in the first direction (X direction). In other words, the barrier insulating layer 231 and the gate electrodes 214 may cross each other perpendicularly. The barrier insulating layer 231 may be disposed between every two adjacent contact plugs 250 arranged in the first direction (X direction) among a plurality of contact plugs 250 on the gate dielectric layer 216.

[0097] The interlayer insulating layer 240 may cover the upper structure 230 and may include, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tetraethyl orthosilicate (TEOS), or a low-k dielectric material having a low dielectric constant of about 2.2 to 2.4. As an example, the low-k dielectric material may include carbon-doped silicon oxide, such as SiCOH.

[0098] The contact plug 250 can penetrate the interlayer insulating layer 240 and the upper insulating layer 232, and can be electrically connected to the oxide semiconductor layer 220. The contact plug 250 can include, for example, doped polysilicon (p-Si), metal, metal nitride, metal silicide, or a combination thereof. The material constituting the contact plug 250 can be substantially the same as the material of the above contact plug (refer to Figure 1B 150 in

[0099] A detailed description is given of the insulation mechanism that operates between the transistors in the region between adjacent unit cells UC that make up the semiconductor device 50.

[0100] In the interval I between the transistors between adjacent unit cells UC in the first direction (X direction), due to the presence of the barrier insulating layer 231 and the operation of the upper structure 230, device isolation can be achieved by using the local isolation state of the oxide semiconductor layer 220. For example, when a specific voltage is applied to the second upper gate metal layer 234-2, the oxide semiconductor layer 220 can operate in a locally insulating state to isolate adjacent unit cells UC in the first direction (X direction).

[0101] In the interval II between the transistors between adjacent unit cells UC in the fourth direction (K direction), due to the presence of the barrier insulating layer 231 and the operation of the upper structure 230, device isolation can be achieved by using the local isolation state of the oxide semiconductor layer 220. For example, when a specific voltage is applied to the second upper gate metal layer 234-2, the oxide semiconductor layer 220 can operate in a locally insulating state to isolate adjacent unit cells UC in the fourth direction (K direction).

[0102] In the interval III between the transistors between adjacent unit cells UC in the second direction (Y direction), due to the arrangement of the gate electrode 214 and the operation of the upper structure 230, device isolation can be achieved by using the local isolation state of the oxide semiconductor layer 220. For example, when a specific voltage is applied to the first upper gate metal layer 234-1, the oxide semiconductor layer 220 can operate in a locally insulating state to isolate adjacent unit cells UC in the second direction (Y direction).

[0103] In the transistors between adjacent unit cells UC located in all directions, device isolation can be achieved by using the local insulating state of the oxide semiconductor layer 220.

[0104] The semiconductor device 50 according to an exemplary embodiment of the inventive concept can provide a structure capable of electrically insulating between transistors between unit cells UC without etching the oxide semiconductor layer 220. In other words, when a specific negative bias is applied to the oxide semiconductor layer 220 via the upper gate metal layer 234 of the upper structure 230, the oxide semiconductor layer 220 can function as an insulating material like silicon oxide (SiO2). Accordingly, an array structure having the same feature size as that of a general semiconductor device that does not use the oxide semiconductor layer 220 can be implemented.

[0105] A negative bias can be applied to the oxide semiconductor layer 220 via the upper gate metal layer 234 of the upper structure 230. When a voltage of about -0.5V to about -1V (e.g., about -0.7V) is applied to the oxide semiconductor layer 220 via the upper gate metal layer 234, the oxide semiconductor layer 220 can operate in an insulating state.

[0106] In the semiconductor device 50 according to an exemplary embodiment of the inventive concept, each transistor can operate electrically independently while substantially maintaining the electrical isolation state between transistors between unit cells UC, and at the same time, a process of forming a device isolation structure by etching the oxide semiconductor layer 220 is omitted. For example, the oxide semiconductor layer 120 according to the present exemplary embodiment can maintain an insulating state in the device isolation region IR and can simultaneously function as a channel region CH of a transistor of the unit cell UC in the active region AR.

[0107] Since the manufacturing process of the semiconductor device 50 can be simplified, there can be an effect of improving the productivity and economic efficiency of the semiconductor device 50.

[0108] Figures 6 to 8 are diagrams of semiconductor devices 60, 70, and 80 according to exemplary embodiments of the inventive concept, respectively.

[0109] Most components constituting the semiconductor devices 60, 70, and 80 described below and materials constituting most components can be substantially the same as or similar to those described with reference to Figures 5A to 5C Therefore, for ease of description, the description focuses on differences from the above-described semiconductor device (reference Figure 5A of 50).

[0110] Reference Figure 6 shows that the semiconductor device 60 can include a contact plug 250, a capacitor 260, and a bit line 270.

[0111] The contact plug 250 can include a first contact plug 251 connected to the capacitor 260 and a second contact plug 253 connected to the bit line 270.

[0112] The capacitor 260 may form a storage electrode having a cylindrical structure to increase capacitance, and may be arranged in a row along a second direction (Y direction).

[0113] A plurality of bit lines 270 may extend parallel to each other along the second direction (Y direction). A plurality of capacitors 260 may be located between two adjacent ones of the plurality of bit lines 270. The bit lines 270 may extend parallel to the second upper gate metal layer 234-2, and may cross the first upper gate metal layer 234-1.

[0114] Reference Figure 7 ,the semiconductor device 70 may include a contact plug 250, a capacitor 260A, and a bit line 270A.

[0115] The contact plug 250 may include a first contact plug 251 connected to the capacitor 260A and a second contact plug 253 connected to the bit line 270A.

[0116] The capacitor 260A may include a storage electrode having a cylindrical structure to increase static capacitance. The capacitor 260A may be arranged in a zigzag pattern along the second direction (Y direction). In other words, the capacitor 260A may be arranged in a honeycomb structure.

[0117] A plurality of bit lines 270A may extend parallel to each other along the second direction (Y direction). A plurality of capacitors 260A may be formed between two adjacent ones of the plurality of bit lines 270A and on the bit lines 270A. In this case, an insulating layer may be formed between the capacitor 260A and the bit line 270A. The bit line 270A may extend parallel to the second upper gate metal layer 234-2, and may cross the first upper gate metal layer 234-1.

[0118] Reference Figure 8 ,the semiconductor device 80 may include a gate structure 210, an oxide semiconductor layer 220, an upper structure 230, a contact plug 250, and a driver circuit region 280 disposed on a substrate 200.

[0119] The driver circuit region 280 may be a region in which a peripheral circuit or a driver circuit for driving the semiconductor device 80 is provided. The driver circuit region 280 may be formed between the substrate 200 and the gate structure 210.

[0120] In an exemplary embodiment of the inventive concept, the peripheral circuit in the driver circuit region 280 may include a circuit capable of processing data input / output to / from the semiconductor device 80 at high speed. The driver circuit region 280 may include a wiring structure 283 electrically connected to a plurality of transistors 281. The wiring structure 283 may be insulated by an interlayer insulating layer 285 formed in the driver circuit region 280.

[0121] The semiconductor device 80 according to the inventive concept may not include physical components such as a device isolation structure (e.g., a device isolation layer or a device isolation trench) in the device isolation region IR. Instead, when a specific voltage is applied to the upper gate metal layer 234, the oxide semiconductor layer 220 may operate in a locally insulated state. Since the manufacturing process of the semiconductor device 80 according to the present exemplary embodiment is simplified, the productivity and economic efficiency of the semiconductor device 80 can be improved.

[0122] Figure 9 is a flowchart of a method S10 of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept.

[0123] Reference Figure 9 , the method S10 of manufacturing a semiconductor device may include a processing sequence of six operations (S110 to S160).

[0124] When implementing a certain exemplary embodiment differently, a specific processing order may be executed in a different order from that to be described. For example, two consecutively described processes may be executed substantially simultaneously or in an order opposite to the described order. This flexibility can also be applied to the method of manufacturing a semiconductor device described later (reference Figure 11 of S20).

[0125] The method S10 of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept may include: a first operation (S110) of forming a planar structure on a substrate, a second operation (S120) of forming an oxide semiconductor layer on the planar structure, a third operation (S130) of forming a gate dielectric layer, a gate electrode, and a gate capping layer on the oxide semiconductor layer, a fourth operation (S140) of completing the gate structure by forming gate spacers, a fifth operation (S150) of forming an interlayer insulating layer, and a sixth operation (S160) of forming contact plugs penetrating the interlayer insulating layer.

[0126] Later, reference Figures 10A to 10E will be made to detail the technical characteristics of each of the first operation S110 to the sixth operation S160.

[0127] Figures 10A to 10E is a cross-sectional view showing a method of manufacturing a semiconductor device according to a processing sequence according to an exemplary embodiment of the inventive concept. Figures 10A to 10E Each of those in Figure 9 may respectively show

[0128] Reference Figure 10A , a planar structure 110 may be formed on a substrate 100 in which a plurality of active regions AR are defined.

[0129] The flat plate structure 110 may include a first insulating layer 112, a lower gate metal layer 114, and a second insulating layer 116.

[0130] The first insulating layer 112 may be formed on the substrate 100 and may include, for example, silicon oxide (SiO2), silicon nitride (Si3N4), or aluminum oxide (Al2O3). The first insulating layer 112 may be formed by, for example, a chemical vapor deposition (CVD) process, a thermal oxidation process, an atomic layer deposition (ALD) process, etc.

[0131] The lower gate metal layer 114 may be formed on the first insulating layer 112 and may include, for example, doped polysilicon (p-Si), a metal, a metal nitride, a metal silicide, or a combination thereof. In an exemplary embodiment of the inventive concept, the lower gate metal layer 114 may include at least one of, for example, nickel (Ni), cobalt (Co), or ruthenium (Ru). The lower gate metal layer 114 may be formed by a CVD process or a physical vapor deposition (PVD) process.

[0132] The second insulating layer 116 may be formed on the lower gate metal layer 114 and, substantially similarly to the first insulating layer 112, may include, for example, silicon oxide (SiO2), silicon nitride (Si3N4), or aluminum oxide (Al2O3). The second insulating layer 116 may be formed by a CVD process, a thermal oxidation process, an ALD process, etc.

[0133] Referring Figure 10B , an oxide semiconductor layer 120 may be formed on the flat plate structure 110.

[0134] The oxide semiconductor layer 120 may include, for example, indium gallium zinc oxide (InGaZnO), indium gallium silicon oxide (InGaSiO), indium tin zinc oxide (InSnZnO), indium zinc oxide (InZnO), or hafnium indium zinc oxide (HfInZnO). The oxide semiconductor layer 120 may be formed by, for example, a PVD process, a pulsed laser deposition (PLD) process, a CVD process, an ADL process, etc.

[0135] The oxide semiconductor layer 120 may have an amorphous or c-axis oriented crystal structure. In an exemplary embodiment of the inventive concept, a laser annealing process for crystallizing the oxide semiconductor layer 120 may be additionally performed. In an exemplary embodiment of the inventive concept, impurities may be doped onto the oxide semiconductor layer 120. For example, in order to dope impurities onto the oxide semiconductor layer 120, impurities may be doped in-situ during the formation of the oxide semiconductor layer 120, or impurity ions may be implanted after the formation of the oxide semiconductor layer 120. In an exemplary embodiment of the inventive concept, at least one impurity such as fluorine (F), hydrogen (H), nitrogen (N), magnesium (Mg), yttrium (Y), ruthenium (Ru), or arsenic (As) may be doped in the oxide semiconductor layer 120.

[0136] Reference Figure 10C , after a gate insulating layer, a gate conductive layer, and a gate capping layer 136 are sequentially formed on the oxide semiconductor layer 120, a gate electrode 134 and a gate dielectric layer 132 may be formed by using the gate capping layer 136 as an etch mask and patterning the gate conductive layer and the gate insulating layer.

[0137] Source / drain regions SD may be formed inside the oxide semiconductor layer 120 on both sides of the gate dielectric layer 132, the gate electrode 134, and the gate capping layer 136. The source / drain regions SD may be formed by implanting impurity ions into the oxide semiconductor layer 120. For example, p-type impurities or n-type impurities may be doped in the source / drain regions SD. In an exemplary embodiment of the inventive concept, the impurity ion implantation process for forming the source / drain regions SD may be performed after forming the gate spacers (reference Figure 10D 138 in

[0138] Reference Figure 10D , gate spacers 138 may be formed on two sidewalls of the gate dielectric layer 132, the gate electrode 134, and the gate capping layer 136.

[0139] The spacer insulating layer covering the gate dielectric layer 132, the gate electrode 134, and the gate capping layer 136 may be formed by a CVD process or an ALD process, and the gate spacers 138 may be formed by performing an anisotropic etching process on the spacer insulating layer. For example, the gate spacers 138 may include silicon nitride (Si3N4), but the inventive concept is not limited thereto. The gate spacers 138 may include multiple layers having different materials from each other. For example, an air gap may be formed in the gate spacers 138 having multiple layers.

[0140] Here, the gate dielectric layer 132, the gate electrode 134, the gate capping layer 136, and the gate spacers 138 may be referred to as components of the gate structure 130.

[0141] Reference Figure 10E An interlayer insulating layer 140 may be formed over the oxide semiconductor layer 120 and the gate structure 130.

[0142] The interlayer insulating layer 240 may include, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tetraethyl orthosilicate (TEOS), or a low-k dielectric material. As an example, the low-k dielectric material may include carbon-doped silicon oxide such as SiCOH. By forming a mask pattern over the interlayer insulating layer 140 and using the mask pattern as an etching mask, a contact hole 150H that penetrates the interlayer insulating layer 140 and exposes the top surface of the source / drain region SD may be formed.

[0143] The mask pattern may be formed over the interlayer insulating layer 140 by a photolithography process. The mask pattern may be formed by applying a photoresist and patterning the photoresist by an exposure and development process. In this case, the contact hole 150H may be defined by the mask pattern.

[0144] Recently, since design rules defining minimum feature sizes and spaces have been reduced to below the limit of ordinary photolithography processes, a new process using extreme ultraviolet (EUV) rays may be introduced. Thus, the mask pattern may be formed by a process using EUV rays.

[0145] By etching the interlayer insulating layer 140 using the mask pattern as an etching mask, a contact hole 150H that exposes a part of the top surface of the source / drain region SD may be formed. The contact hole 150H may have a tapered profile in which the upper width is greater than the lower width.

[0146] Referring again to Figure 1B ,a contact plug 150 filling the contact hole 150H may be formed by forming a conductive layer filling the contact hole 150H over the interlayer insulating layer 140 and removing an upper portion of the conductive layer by a chemical mechanical polishing (CMP) process until the top surface of the interlayer insulating layer 140 is exposed. The contact plug 150 may include, for example, doped polysilicon (p-Si), a metal, a metal nitride, a metal silicide, or a combination thereof.

[0147] By using such a manufacturing process, a semiconductor device 10 according to an exemplary embodiment of the inventive concept may be manufactured, and since the manufacturing process of the semiconductor device 10 is simplified, the productivity and economic efficiency of the semiconductor device 10 may be improved.

[0148] Referring to the manufacturing process of the semiconductor device 10 described above, those of ordinary skill in the art may easily understand the manufacturing processes of other semiconductor devices 20, 30, and 40.

[0149] Figure 11It is a flowchart of a method (S20) for manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept.

[0150] Referring Figure 11 , the method S20 for manufacturing a semiconductor device may include a processing sequence of seven operations (S210 to S270).

[0151] The method (S20) for manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept may include a first operation (S210) of forming a lower insulating layer and a gate electrode on a substrate, a second operation (S220) of forming a gate dielectric layer and a blocking insulating layer in a direction crossing the gate electrode, a third operation (S230) of conformally forming an oxide semiconductor layer, a fourth operation (S240) of conformally forming an upper insulating layer, a fifth operation (S250) of forming an upper gate metal layer, a sixth operation (S260) of forming an interlayer insulating layer, and a seventh operation (S270) of forming a contact plug penetrating the interlayer insulating layer.

[0152] Referring Figures 12A to 17C The technical features of each of the first operation S210 to the seventh operation S270 will be described in detail.

[0153] Figures 12A to 17C It is a diagram showing a method for manufacturing a semiconductor device according to a processing sequence according to an exemplary embodiment of the inventive concept.

[0154] Figure 12A , Figure 13A , …… and Figure 17A correspond to layouts, Figure 12B , Figure 13B , … and Figure 17B correspond to cross-sectional views taken along line X-X' of Figure 12A , Figure 13A , …… and Figure 17A , and Figure 12C , Figure 13C , … and Figure 17C correspond to cross-sectional views taken along line Y-Y' of Figure 12A , Figure 13A , …… and Figure 17A .

[0155] Referring Figures 12A to 12C , the lower insulating layer 212 and the gate electrode 214 may be formed on the substrate 200.

[0156] The lower insulating layer 212 may include at least one of, for example, silicon oxide (SiO2), silicon nitride (Si3N4), or aluminum oxide (Al2O3). In an exemplary embodiment of the inventive concept, the lower insulating layer 212 may serve as a buffer layer for reducing stress caused by a lattice constant difference of materials constituting other components disposed above and below the lower insulating layer 212. In addition, the lower insulating layer 212 may prevent impurities from diffusing from the substrate 200 into components disposed above the lower insulating layer 212. In addition, the lower insulating layer 212 may serve as a barrier layer for preventing current leakage.

[0157] The gate electrode 214 may be formed on the lower insulating layer 212. The gate electrode 214 may include, for example, doped polysilicon (p-Si), a metal, or a combination thereof. The gate electrode 214 may extend in a first direction (X direction) and may be spaced apart from each other in a second direction (Y direction). In other words, the gate electrode 214 may form a gate line.

[0158] The gate electrode 214 may be formed by using, for example, a double patterning technique (DPT) or a quadruple patterning technique (QPT).

[0159] An ultra-fine pattern beyond the optical limit may be formed by using DPT. In other words, a first mask pattern having a width greater than a minimum feature size may be formed through a photolithography process, and a second mask pattern having a width equal to the minimum feature size may be formed by using the first mask pattern. For each line pattern constituting the first mask pattern, two line patterns constituting the second mask pattern may be formed. By using the second mask pattern as an etching mask, a plurality of gate electrodes 214 each having a width equal to the minimum feature size may be finally formed. This technique may print very fine features by changing the pattern density to twice, four times, or six times by using various deposition and etching schemes.

[0160] In an exemplary embodiment of the inventive concept, the plurality of gate electrodes 214 may include at least two gate electrodes 214 adjacent to each other at a first spacing distance D1, and at least two gate electrodes 214 adjacent to each other in a second direction (Y direction) at a second spacing distance D2 greater than the first spacing distance D1. In other words, the distances between the plurality of gate electrodes 214 may be different from each other. In other words, a gate vacancy region 214D in which no gate electrode 214 is formed may be formed on the lower insulating layer 212. For example, the gate vacancy region 214D may have a width of the gate electrode 214 within the second spacing distance D2.

[0161] Reference Figures 13A to 13C, the gate dielectric layer 216 can be formed to conformally cover the top surfaces of the lower insulating layer 212 and the gate electrode 214, and the blocking insulating layer 231 can be formed to extend in one direction (e.g., in the second direction (Y direction)) to intersect with the gate electrode 214.

[0162] The gate dielectric layer 216 can include, for example, a silicon oxide (SiO2) layer, a silicon oxynitride (SiON) layer, a high-k layer having a dielectric constant higher than that of the silicon oxide (SiO2) layer, or a combination thereof. The high-k layer can include, for example, a metal oxide or a metal oxynitride.

[0163] The lower insulating layer 212, the gate electrode 214, and the gate dielectric layer 216 can be referred to as components of the gate structure 210.

[0164] The blocking insulating layer 231 can include at least one of, for example, silicon oxide (SiO2), silicon nitride (Si3N4), or aluminum oxide (Al2O3). The blocking insulating layer 231 can extend in the second direction (Y direction) and can be spaced apart from each other in the first direction (X direction). In other words, the blocking insulating layer 231 having a specific thickness and the gate electrode 214 can intersect perpendicularly to each other.

[0165] Refer together Figures 14A to 14C , an oxide semiconductor layer 220 can be conformally formed on the gate dielectric layer 216 and the blocking insulating layer 231.

[0166] The oxide semiconductor layer 220 can have a top surface with an uneven structure, and the height of the top surface of the oxide semiconductor layer 220 can be higher than the height of the top surface of the substrate 100.

[0167] The oxide semiconductor layer 220 can include a conductive oxide. For example, the oxide semiconductor layer 220 can include at least one of, for example, indium gallium zinc oxide (InGaZnO), indium gallium silicon oxide (InGaSiO), indium tin zinc oxide (InSnZnO), indium zinc oxide (InZnO), hafnium indium zinc oxide (HfInZnO).

[0168] The oxide semiconductor layer 220 can be continuously connected to each other on the top surface of the entire surface of the substrate 200 or in a plurality of active regions AR. In other words, the oxide semiconductor layer 220 can be formed without interruption on the top surface of the substrate 200, or without disconnection on the active regions AR and the device isolation regions IR of the substrate 200.

[0169] Refer together Figures 15A to 15C , the upper insulating layer 232 can be conformally formed on the oxide semiconductor layer 220.

[0170] The upper insulating layer 232 may include at least one of, for example, silicon oxide (SiO2), silicon nitride (Si3N4), or aluminum oxide (Al2O3). The upper insulating layer 232 may have a top surface with an uneven structure that has substantially the same phase as the oxide semiconductor layer 220, and the height of the top surface of the upper insulating layer 232 may be higher than the height of the top surface of the substrate 200.

[0171] In an exemplary embodiment of the inventive concept, the upper insulating layer 232 may include a relatively flexible insulating material, may cover the oxide semiconductor layer 220, and may have a flat (or gentle) top surface.

[0172] Referring together Figures 16A to 16C to, the upper gate metal layer 234 may be formed on the upper insulating layer 232, extend in one direction (e.g., in the second direction (Y direction)) to cross the gate electrode 214, and also extend in one direction (e.g., in the first direction (X direction)) to be parallel to the gate electrode 214.

[0173] The upper gate metal layer 234 may include, for example, doped polysilicon (p-Si), a metal, a metal nitride, a metal silicide, or a combination thereof. In an exemplary embodiment of the inventive concept, the upper gate metal layer 234 may include at least one of, for example, nickel (Ni), cobalt (Co), or ruthenium (Ru).

[0174] The upper gate metal layer 234 may include a first upper gate metal layer 234-1 formed between the gate electrodes 214 and a second upper gate metal layer 234-2 formed on the barrier insulating layer 231.

[0175] The first upper gate metal layer 234-1 may extend in the first direction (X direction) and may be spaced apart from each other in the second direction (Y direction). Additionally, the second upper gate metal layer 234-2 may extend in the second direction (Y direction) and may be spaced apart from each other in the first direction (X direction). In other words, the first upper gate metal layer 234-1 and the second upper gate metal layer 234-2 may cross each other perpendicularly. For example, the first upper gate metal layer 234-1 may be formed in a gate vacancy region (refer to Figure 12A 214D in) where no gate electrode 214 is formed.

[0176] In an exemplary embodiment of the inventive concept, the height of the top surface of the first upper gate metal layer 234-1 may be lower than the height of the bottom surface of the second upper gate metal layer 234-2. This may be because the second upper gate metal layer 234-2 is disposed on the barrier insulating layer 231 having a specific thickness.

[0177] The upper insulating layer 232 and the upper gate metal layer 234 may be referred to as components of the upper structure 230.

[0178] Referring together Figures 17A to 17C , an interlayer insulating layer 240 may be formed on the upper structure 230.

[0179] The interlayer insulating layer 240 may include, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tetraethyl orthosilicate (TEOS), or a low-k dielectric material. As an example, the low-k dielectric material may include carbon-doped silicon oxide, such as SiCOH. A mask pattern may be formed on the interlayer insulating layer 240, and a contact hole 250H penetrating the interlayer insulating layer 240 may be formed by using the mask pattern as an etching mask.

[0180] The mask pattern may be formed on the interlayer insulating layer 240 by a photolithography process. By applying a photoresist and patterning the photoresist through an exposure and development process, the mask pattern may be formed. In this case, the contact hole 250H may be defined by the mask pattern. In an exemplary embodiment of the inventive concept, the mask pattern may be formed by a process using EUV rays. For example, EUV rays may be used during the exposure process in the process of patterning the photoresist.

[0181] By using the mask pattern as an etching mask to etch the interlayer insulating layer 240, the contact hole 250H may be formed. The contact hole 250H may have a tapered profile in which the upper width is greater than the lower width.

[0182] Referring again Figure 5B , by forming a conductive layer filling the contact hole 250H on the interlayer insulating layer 240 and removing the upper portion of the conductive layer by CMP until the upper surface of the interlayer insulating layer 140 is exposed, a contact plug 250 filling the contact hole 250H may be formed. The contact plug 250 may include, for example, doped polysilicon (p-Si), metal, metal nitride, metal silicide, or a combination thereof.

[0183] By using these manufacturing processes, a semiconductor device 50 according to an exemplary embodiment of the inventive concept may be manufactured, and since the manufacturing process of the semiconductor device 50 is simplified, the productivity and economic efficiency of the semiconductor device 50 may be improved.

[0184] Figure 18 is a configuration diagram of a system 1000 of a semiconductor module according to an exemplary embodiment of the inventive concept.

[0185] Referring Figure 18, system 1000 may include a controller 1010, an input / output (I / O) device 1020, a memory 1030, an interface 1040, and a bus 1050.

[0186] System 1000 may be a mobile system or a system for sending and receiving information. In an exemplary embodiment of the inventive concept, the mobile system may include, for example, a portable computer, a tablet computer, a mobile phone, a smart watch, a digital music player, a memory card, and the like.

[0187] The controller 1010 may be used to control an execution program in the system 1000 and may include, for example, a microprocessor, a digital signal processor, a microcontroller, or a similar device.

[0188] The I / O device 1020 may be used to input or output data of the system 1000. The system 1000 may be connected to an external device, such as a computer or a network, through the I / O device 1020 and may exchange data with the external device. The I / O device 1020 may include, for example, a touchpad, a keyboard, a mouse, or a display.

[0189] The memory 1030 may store data for the operation of the controller 1010 or may store data processed by the controller 1010. According to an exemplary embodiment of the inventive concept, the memory 1030 may include any one of the semiconductor devices 10 to 50 referred to above Figures 1A to 5C described.

[0190] The interface 1040 may be a data transmission path between the system 1000 and an external device. The controller 1010, the I / O device 1020, the memory 1030, and the interface 1040 may communicate with each other via the bus 1050.

[0191] Although the exemplary embodiments of the inventive concept have been described with reference to the accompanying drawings, those of ordinary skill in the art should understand that the inventive concept may be implemented in other specific applications without changing the technical aspects or essential features of the inventive concept. Therefore, the above exemplary embodiments should be understood as exemplary in all aspects and not restrictive.

[0192] Although the inventive concept has been specifically shown and described with reference to the exemplary embodiments of the inventive concept, it should be understood that various changes may be made in form and detail without departing from the spirit and scope of the inventive concept defined by the appended claims.

Claims

1. A semiconductor device, comprising: A substrate including an active region and a device isolation region; A flat plate structure formed on the substrate; An oxide semiconductor layer covering the top surface of the flat plate structure and continuously disposed on the top surface of the substrate in the active region and the device isolation region; A gate structure disposed on the oxide semiconductor layer and including a gate dielectric layer and a gate electrode; Source / drain regions disposed on both sides of the gate structure and formed in the oxide semiconductor layer; And A channel region formed inside the oxide semiconductor layer and disposed under the gate structure; Wherein, when observed from a side cross-section, the extending directions of the flat plate structure and the gate structure cross each other.

2. The semiconductor device according to claim 1, wherein, The flat plate structure includes: A first insulating layer formed on the substrate; A lower gate metal layer formed on the first insulating layer; and A second insulating layer formed on the lower gate metal layer, Wherein the lower gate metal layer is interposed between the first insulating layer and the second insulating layer.

3. The semiconductor device according to claim 2, wherein, The lower gate metal layer includes at least one of nickel (Ni), cobalt (Co), or ruthenium (Ru).

4. The semiconductor device according to claim 2, wherein, The lower gate metal layer is continuously disposed on the top surface of the substrate in the active region and the device isolation region.

5. The semiconductor device according to claim 2, further comprising a lower gate metal layer contact portion electrically connected to the lower gate metal layer.

6. The semiconductor device according to claim 2, wherein, The lower gate metal layer is only disposed in the device isolation region.

7. The semiconductor device according to claim 1, wherein, The oxide semiconductor layer includes at least one of indium gallium zinc oxide (InGaZnO), indium gallium silicon oxide (InGaSiO), indium tin zinc oxide (InSnZnO), indium zinc oxide (InZnO), or hafnium indium zinc oxide (HfInZnO).

8. The semiconductor device according to claim 1, wherein the top surface of the oxide semiconductor layer has a planar structure.

9. The semiconductor device according to claim 1, wherein, The gate dielectric layer surrounds the side surface and the bottom surface of the gate electrode.

10. A semiconductor device, comprising: A substrate configured to define a plurality of active regions; An insulating layer covering the top surface of the substrate; A gate electrode formed on the insulating layer and extending in a first direction; A gate dielectric layer covering the insulating layer and the gate electrode; An oxide semiconductor layer disposed on the gate dielectric layer and configured to form a channel region in each of the plurality of active regions; A plurality of contact structures electrically connected to the oxide semiconductor layer; And An upper gate metal layer formed between every two adjacent active regions among the plurality of active regions, Wherein, no device isolation insulating layer is formed between every two adjacent active regions among the plurality of active regions.

11. The semiconductor device according to claim 10, wherein, The top surface of the oxide semiconductor layer has an uneven structure and continuously extends across the plurality of active regions.

12. The semiconductor device according to claim 10, wherein The oxide semiconductor layer includes at least one of indium gallium zinc oxide (InGaZnO), indium gallium silicon oxide (InGaSiO), indium tin zinc oxide (InSnZnO), indium zinc oxide (InZnO), or hafnium indium zinc oxide (HfInZnO).

13. The semiconductor device according to claim 10 further includes a blocking insulating layer disposed between every two adjacent contact structures among the plurality of contact structures on the gate dielectric layer and extending in a second direction perpendicular to the first direction.

14. The semiconductor device according to claim 13, wherein, A plurality of the gate electrodes are provided, and the plurality of gate electrodes include at least two of the gate electrodes adjacent to each other at a first interval distance in the second direction and at least two of the gate electrodes adjacent to each other at a second interval distance greater than the first interval distance.

15. The semiconductor device according to claim 10, wherein, The upper gate metal layer includes at least one of nickel (Ni), cobalt (Co), or ruthenium (Ru).

16. The semiconductor device according to claim 10, wherein, The height of the bottom surface of each of the contact structures is higher than the height of the top surface of the gate electrode.

17. A semiconductor device, comprising: a substrate including device isolation regions configured to define a plurality of active regions; a first insulating layer formed on the substrate; a lower gate metal layer covering all of the plurality of active regions and the device isolation regions of the substrate, on the first insulating layer, and configured for device isolation; a second insulating layer formed on the lower gate metal layer; an oxide semiconductor layer disposed on the second insulating layer and configured to form a channel region in each of the plurality of active regions; a plurality of gate structures, each of the plurality of gate structures being disposed on the channel region in a corresponding one of the plurality of active regions; source / drain regions disposed on both sides of each of the plurality of gate structures and formed in the oxide semiconductor layer; contact structures electrically connected to the source / drain regions; and a lower gate metal layer contact portion electrically connected to the lower gate metal layer.

18. The semiconductor device according to claim 17, wherein, The height of the bottom surface of the contact structure is higher than the height of the bottom surface of the lower gate metal layer contact portion.

19. The semiconductor device according to claim 17, wherein, When a voltage of -0.5 V to -1 V is applied to the oxide semiconductor layer via the lower gate metal layer, the oxide semiconductor layer is configured to operate in an insulating state.

20. The semiconductor device according to claim 17, wherein The top surface of the lower gate metal layer has a planar structure, the top surface of the oxide semiconductor layer has a planar structure, and each of the plurality of gate structures is planar and includes a gate dielectric layer, a gate electrode, and a gate spacer.

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