Method for manufacturing a semiconductor device and semiconductor device

Abstract

In the method, a first dielectric layer is formed over a semiconductor fin, a second dielectric layer is formed over the first dielectric layer, the second dielectric layer is recessed below the top of each semiconductor, a third dielectric layer is formed over the recessed second dielectric layer, and the third dielectric layer is recessed below the top of the semiconductor fin, thereby forming a fin wall. The fin wall includes the recessed third dielectric layer and the recessed second dielectric layer disposed below the recessed third dielectric layer, the first dielectric layer is recessed below the top of the fin wall to form a fin liner layer, the fin liner layer and the semiconductor fin are recessed, and source / drain epitaxial layers are respectively formed over the recessed semiconductor fins. The source / drain epitaxial layers are separated from each other by the fin wall. Embodiments of the present application also relate to a method of manufacturing a semiconductor device and a semiconductor device.

Description

Technical Field

[0001] Embodiments of the present application relate to methods of manufacturing semiconductor devices and semiconductor devices. Background Art

[0002] As the semiconductor industry enters nanotechnology process nodes in the pursuit of higher device density, higher performance, and lower cost, challenges from manufacturing and design issues have led to the development of three-dimensional designs such as fin field-effect transistors (Fin FETs). Fin FET devices typically include semiconductor fins with a high aspect ratio, and a channel and source / drain regions of a semiconductor transistor device are formed therein. Taking advantage of the increased surface area of the channel and source / drain regions, a gate is formed above and along the sides of the fin structure (e.g., wrapped around) to produce a faster, more reliable, and better-controlled semiconductor transistor device. In some devices, strained materials such as silicon germanium (SiGe), silicon carbide (SiC), and / or silicon phosphide (SiP) can be used in the source / drain (S / D) portion of the Fin FET to enhance carrier mobility. Summary of the Invention

[0003] Some embodiments of the present application provide a method of manufacturing a semiconductor device, the method comprising: forming a first dielectric layer above a semiconductor fin disposed above a semiconductor substrate; forming a second dielectric layer above the first dielectric layer; recessing the second dielectric layer below the top of each semiconductor; forming a third dielectric layer above the recessed second dielectric layer; recessing the third dielectric layer below the top of each semiconductor fin, thereby forming wall fins disposed between the semiconductor fins, the wall fins comprising the recessed third dielectric layer and the recessed second dielectric layer disposed below the recessed third dielectric layer; recessing the first dielectric layer below the top of the wall fins; forming a fin liner layer above the upper portions of each semiconductor fin and the upper portions of the wall fins, the wall fins protruding from the recessed first dielectric layer; etching the fin liner layer and recessing the semiconductor fins; and forming source / drain epitaxial layers above the recessed semiconductor fins, respectively, wherein the source / drain epitaxial layers are separated from each other by the wall fins.

[0004] Some other embodiments of the present application provide a method for manufacturing a semiconductor device, the method comprising: forming a first dielectric layer over a plurality of semiconductor fins disposed above a semiconductor substrate, thereby leaving a first gap between adjacent semiconductor fins; forming a second dielectric layer over the first dielectric layer, such that the first gap is completely filled with the second dielectric layer; recessing the second dielectric layer below the top of each of the plurality of semiconductor fins, thereby forming a second gap over the recessed second dielectric layer between adjacent semiconductor fins covered by the first dielectric layer; forming a third dielectric layer over the recessed second dielectric layer, such that the second gap is completely filled with the third dielectric layer; recessing the third dielectric layer below the top of each of the plurality of semiconductor fins, thereby forming wall fins disposed between adjacent semiconductor fins; recessing the first dielectric layer below the top of each of the wall fins; forming a sacrificial gate structure over an upper portion of each of the plurality of semiconductor fins and an upper portion of each of the wall fins, the wall fins protruding from the recessed first dielectric layer; forming a fin liner layer over an upper portion of each of the plurality of semiconductor fins and an upper portion of each of the wall fins, the wall fins protruding from the recessed first dielectric layer and covered by the sacrificial gate structure; etching the fin liner layer and recessing the plurality of semiconductor fins; forming source / drain epitaxial layers over the plurality of recessed semiconductor fins respectively; and replacing the sacrificial gate structure with a metal gate structure, wherein the source / drain epitaxial layers are separated from each other by the wall fins.

[0005] Some further embodiments of the present application provide a semiconductor device, comprising: a first semiconductor fin and a second semiconductor fin, disposed above a semiconductor substrate and extending in a first direction; an isolation insulating layer, disposed between the first semiconductor fin and the second semiconductor fin; a wall fin, extending in the first direction, wherein a lower portion of the wall fin is embedded in the isolation insulating layer, and an upper portion of the wall fin protrudes from the isolation insulating layer; a gate structure, disposed above a channel region of the first semiconductor fin and a channel region of the second semiconductor fin and extending in a second direction intersecting the first direction; a first source / drain epitaxial layer and a second source / drain epitaxial layer, the first source / drain epitaxial layer being disposed above a source / drain region of the first semiconductor fin, and the second source / drain epitaxial layer being disposed above a source / drain region of the second semiconductor fin, wherein: the first source / drain epitaxial layer and the second source / drain epitaxial layer are separated by the wall fin, the wall fin comprises a lower dielectric layer and an upper dielectric layer disposed above the lower dielectric layer and made of a material different from that of the lower dielectric layer, and the upper dielectric layer comprises a dielectric material having a dielectric constant higher than that of the lower dielectric layer and the isolation insulating layer. Description of the Drawings

[0006] As will be best understood from the following detailed description when read in conjunction with the accompanying drawings, aspects of the present invention can be best understood. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustrative purposes only. In fact, for the sake of clear discussion, the dimensions of the various components can be increased or decreased arbitrarily.

[0007] Figure 1 Shows one of the stages in the sequential manufacturing operations of a semiconductor FET device according to an embodiment of the present disclosure.

[0008] Figure 2 Shows one of the stages in the sequential manufacturing operations of a semiconductor FET device according to an embodiment of the present disclosure.

[0009] Figure 3 Shows one of the stages in the sequential manufacturing operations of a semiconductor FET device according to an embodiment of the present disclosure.

[0010] Figure 4 Shows one of the stages in the sequential manufacturing operations of a semiconductor FET device according to an embodiment of the present disclosure.

[0011] Figure 5 Shows one of the stages in the sequential manufacturing operations of a semiconductor FET device according to an embodiment of the present disclosure.

[0012] Figure 6 Shows one of the stages in the sequential manufacturing operations of a semiconductor FET device according to an embodiment of the present disclosure.

[0013] Figure 7 Shows one of the stages in the sequential manufacturing operations of a semiconductor FET device according to an embodiment of the present disclosure.

[0014] Figure 8A , Figure 8B , Figure 8C , Figure 8D and Figure 8E Shows one of the stages in the sequential manufacturing operations of a semiconductor FET device according to an embodiment of the present disclosure.

[0015] Figure 9 Shows one of the stages in the sequential manufacturing operations of a semiconductor FET device according to an embodiment of the present disclosure.

[0016] Figure 10 Shows one of the stages in the sequential manufacturing operations of a semiconductor FET device according to an embodiment of the present disclosure.

[0017] Figure 11 Shows one of the stages in the sequential manufacturing operations of a semiconductor FET device according to an embodiment of the present disclosure.

[0018] Figure 12A and Figure 12B illustrates one of the stages in the sequential manufacturing operations of a semiconductor FET device according to an embodiment of the present disclosure.

[0019] Figure 13A and Figure 13B illustrates one of the stages in the sequential manufacturing operations of a semiconductor FET device according to an embodiment of the present disclosure.

[0020] Figure 14A and Figure 14B illustrates one of the stages in the sequential manufacturing operations of a semiconductor FET device according to an embodiment of the present disclosure.

[0021] Figure 15A and Figure 15B illustrates one of the stages in the sequential manufacturing operations of a semiconductor FET device according to another embodiment of the present disclosure.

[0022] Figure 16A and Figure 16B illustrates one of the stages in the sequential manufacturing operations of a semiconductor FET device according to another embodiment of the present disclosure.

[0023] Figure 17A and Figure 17B illustrates one of the stages in the sequential manufacturing operations of a semiconductor FET device according to an embodiment of the present disclosure.

[0024] Figure 18A and Figure 18B illustrates one of the stages in the sequential manufacturing operations of a semiconductor FET device according to another embodiment of the present disclosure.

[0025] Figure 19A and Figure 19B illustrates one of the stages in the sequential manufacturing operations of a semiconductor FET device according to another embodiment of the present disclosure.

[0026] Figure 20A and 20B illustrates one of the stages in the sequential manufacturing operations of a semiconductor FET device according to other embodiments of the present disclosure. Detailed Description

[0027] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, the dimensions of the elements are not limited to the disclosed ranges or values, but may depend on the process conditions of the device and / or the desired performance. Additionally, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where additional components may be formed between the first and second components such that the first and second components may not be in direct contact. For simplicity and clarity, the various components may be drawn arbitrarily in different proportions.

[0028] Moreover, for ease of description, spatial relative terms such as "under", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another (or other) element or component as shown in the figures. In addition to the orientation shown in the figures, the spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly. Additionally, the term "made of" may mean "comprising" or "consisting of". In the present disclosure, the phrase "one of A, B, and C" means "A, B, and / or C" (A, B, C, A and B, A and C, B and C, or A, B, and C), unless otherwise specified, and does not mean one element from A, one element from B, and one element from C.

[0029] One of the factors determining the device performance of a field effect transistor (FET) such as a fin FET (FinFET) is the shape of the epitaxial source / drain structure. In particular, when the source / drain regions of the FinFET are recessed and then an epitaxial source / drain layer is formed therein, the etching substantially defines the shape of the epitaxial source / drain structure. Additionally, when two adjacent fin structures are close to each other, the epitaxial layers undesirably merge with each other.

[0030] In the present disclosure, a wall fin structure (dielectric pseudo fin structure) is employed to physically and electrically separate adjacent source / drain epitaxial layers and define the shape of the source / drain epitaxial layers. The optimal source / drain shape can improve the Ion / Ioff current ratio of the FinFET and can improve the device performance.

[0031] Figures 1 to 13B Views showing various stages of a sequential manufacturing operation of a semiconductor device according to the present disclosure are shown. It should be understood that this may be done in Figures 1 to 13BProvide additional operations before, during, and after the process shown. For additional embodiments of the method, some of the operations described below may be replaced or eliminated. The order of operations / processes may be interchanged.

[0032] As Figure 1 shown, one or more fin structures 20 are fabricated over a substrate 10. The substrate 10 is, for example, a p-type silicon substrate having an impurity concentration in the range of about 1×10 15 cm -3 to about 1×10 18 cm -3 . In other embodiments, the substrate 10 is an n-type silicon substrate having an impurity concentration in the range of about 1×10 15 cm -3 to about 1×10 18 cm -3 . Optionally, the substrate 10 may include other elemental semiconductors such as germanium; compound semiconductors including group IV-IV compound semiconductors such as SiC and SiGe, group III-V compound semiconductors such as GaAs, GaP, GaN, InP, InAs, InSb, GaAsP, AlGaN, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. In one embodiment, the substrate 10 is the silicon layer of a SOI (silicon-on-insulator) substrate. Amorphous substrates such as amorphous silicon or amorphous SiC or insulating materials such as silicon oxide may also be used as the substrate 10. The substrate 10 may include various regions that have been appropriately doped with impurities (e.g., p-type or n-type conductivity).

[0033] The fin structures 20 may be patterned by any suitable method. For example, one or more lithography processes including double patterning processes or multiple patterning processes may be used to pattern the fin structures 20. Generally, double patterning or multiple patterning processes combine lithography and self-alignment processes, thereby allowing the creation of patterns having, for example, a pitch smaller than that achievable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate, and the sacrificial layer is patterned using a lithography process. Spacers are formed adjacent to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fin structures 20. In some embodiments, a hard mask pattern 22 for etching the substrate 10 remains on top of the fin structures 20. In some embodiments, the pattern 22 includes one or more layers of silicon oxide, silicon nitride, SiON, and other suitable materials. In certain embodiments, the hard mask pattern 22 includes silicon nitride.

[0034] As Figure 1As shown, four fin structures 20 protrude from the substrate 10 in the Z direction, extend in the Y direction, and are arranged adjacent to each other in the X direction at a constant pitch. However, the number of fin structures is not limited to four. The number can be one, two, three, five or more. Additionally, one or more dummy fin structures can be disposed near both sides of the fin structures 20 to improve pattern fidelity in the patterning process. The width of the fin structures 20 is in the range of about 5 nm to about 40 nm in some embodiments, and in the range of about 7 nm to about 15 nm in certain other embodiments. The height of the fin structures 20 is in the range of about 100 nm to about 300 nm in some embodiments, and in the range of about 50 nm to 100 nm in other embodiments. The spacing between the fin structures 20 is in the range of about 5 nm to about 80 nm in some embodiments, and can be in the range of about 7 nm to 20 nm in other embodiments. The pitch of the fin structures is in the range of about 10 nm to about 120 nm in some embodiments, and in the range of about 14 nm to about 35 nm in other embodiments. However, those skilled in the art will recognize that the dimensions and values described throughout the specification are merely examples and can be varied to suit different scales of integrated circuits. In some embodiments, the finFET device is an n-type finFET. In other embodiments, the finFET device is a p-type finFET.

[0035] As Figure 2 shown, after the fin structures 20 are formed, a first dielectric layer 30 is formed over the fin structures 20. The first dielectric layer 30 includes one or more insulating material layers formed by LPCVD (low-pressure chemical vapor deposition), plasma CVD, or atomic layer deposition (ALD), or any other suitable film-forming method, such as silicon oxide, silicon oxynitride, silicon nitride, SiOC, SiCN, or SiOCN. In certain embodiments, silicon oxide is used as the first dielectric layer 30. In some embodiments, as Figure 2 shown, the first dielectric layer 30 is conformally formed over the fin structures 20 such that a first spacer 25 is formed between adjacent fin structures. The thickness of the first dielectric layer 30 is adjusted such that in some embodiments, the spacer S1 is in the range of about 5 nm to about 40 nm, and in certain embodiments, in the range of about 7 nm to about 15 nm.

[0036] As Figure 3As shown, after forming the first dielectric layer 30, a second dielectric layer 35 is formed over the first dielectric layer 30. The material of the second dielectric layer 35 is different from that of the first dielectric layer 30. In some embodiments, the second dielectric layer 35 includes one or more insulating material layers formed by LPCVD, plasma CVD, or ALD or any other suitable film-forming method, such as silicon oxide, silicon oxynitride, or silicon nitride, SiOC, SiCN, or SiOCN. In some embodiments, the second dielectric layer 35 is made of silicon nitride. As Figure 3 shown, in some embodiments, the second dielectric layer 35 completely fills the first spacer 25 and covers the top of the first dielectric layer 30. In other embodiments, a void is formed in the bottom portion of the first spacer 25. In some embodiments, one or more additional dielectric layers are formed between the first dielectric layer 30 and the second dielectric layer 35. In some embodiments, after forming the second dielectric layer 35, a planarization operation such as an etch-back process or a chemical mechanical polishing (CMP) process is performed to planarize the upper surface of the second dielectric layer 35.

[0037] Next, by using suitable dry and / or wet etching operations, the second dielectric layer 35 is recessed downward below the top of the fin structure 20, as Figure 4 shown. Since the second dielectric layer 35 is made of a material different from that of the first dielectric layer 30, the second dielectric layer 35 is selectively etched relative to the first dielectric layer 30. As Figure 4 shown, a second spacer 37 is formed over the recessed second dielectric layer 35. In some embodiments, the upper surface of the recessed second dielectric layer 35 has a V-shaped or U-shaped profile.

[0038] In addition, as Figure 5 shown, after recessing the second dielectric layer 35, a third dielectric layer 40 is formed over the first dielectric layer 30 and the recessed second dielectric layer 35. The material of the third dielectric layer 40 is different from that of the first dielectric layer 30 and the second dielectric layer 35. In some embodiments, the third dielectric layer 40 includes a material having an etching rate lower than that of the second dielectric layer relative to polysilicon. In some embodiments, the third dielectric layer 40 includes a high-k dielectric material. In some embodiments, the third dielectric layer 40 includes a dielectric material having a dielectric constant (k) higher than that of the second dielectric layer 35 and / or the first dielectric layer 30. When the upper surface of the recessed second dielectric layer 35 has a V-shaped or U-shaped profile, the bottom of the third dielectric layer 40 has a V-shaped or U-shaped profile.

[0039] In some embodiments, the third dielectric layer 40 includes one or more undoped hafnium oxides (e.g., HfO x, where 0 < x ≤ 2), hafnium oxide doped with one or more other elements (e.g., HfSiO, HfSiON, HfTaO, HfTiO, or HfZrO), zirconia, alumina, titanium oxide, and hafnium oxide-alumina (HfO2 - Al2O3) alloy. In certain embodiments, hafnium oxide (HfO x ) is used as the third dielectric layer 40. The third dielectric layer can be formed by LPCVD, plasma CVD, or ALD or any other suitable film-forming method. In some embodiments, the second dielectric layer 35 is made of silicon nitride. As Figure 5 shown, in some embodiments, the third dielectric layer 40 completely fills the second spacer 37 and covers the top of the first dielectric layer 30. In some embodiments, after forming the third dielectric layer 40, a planarization operation such as an etch-back process or a CMP process is performed to planarize the upper surface of the third dielectric layer 40.

[0040] Next, by using appropriate dry and / or wet etching operations, the third dielectric layer 40 is recessed downward below the top of the fin structure 20 to form the wall fin 50 (pseudo-dielectric fin), as Figure 6 shown. Since the third dielectric layer 40 is made of a material different from that of the first dielectric layer 30, the third dielectric layer 40 is selectively etched relative to the first dielectric layer 30. As Figure 6 shown, a third spacer 42 is formed above the wall fin 50 (recessed third dielectric layer 40). As Figure 6 shown, the wall fin 50 includes a recessed third dielectric layer 40 formed on the recessed second dielectric layer 35, as a hybrid fin structure. In some embodiments, the upper surface of the recessed third dielectric layer 30 has a V-shaped or U-shaped.

[0041] Then, by using suitable dry and / or wet etching operations, the first dielectric layer 30 is recessed downward below the top of the fin structure 20, thereby exposing the upper portion of the wall fin 50, as Figure 7 shown. Since the first dielectric layer 30 is made of a material different from that of the second dielectric layer 35 and the third dielectric layer 40, the first dielectric layer 30 is selectively etched relative to the second and third dielectric layers. The recessed first dielectric layer 30 serves as an isolation insulating layer (e.g., shallow trench isolation (STI)) to electrically isolate one fin structure from adjacent fin structures.

[0042] Subsequently, a sacrificial gate structure 60 is formed above the channel regions of the fin structure 20 and the wall fin 50, as Figures 8A to 8C shown. Figure 8B is a plan view, Figure 8A is a cross-sectional view corresponding to Figure 8B along the line X1 - X1, and Figure 8C is corresponding to Figure 8BCross-sectional view of the line Y1-Y1. The sacrificial gate structure 60 includes a sacrificial gate dielectric layer 62 and a sacrificial gate electrode layer 64. In some embodiments, the sacrificial gate structure 60 further includes a hard mask layer located above the sacrificial gate electrode layer 64. In some embodiments, the hard mask layer includes a first hard mask layer 66A and a second hard mask layer 66B.

[0043] A blanket layer for the sacrificial gate dielectric layer and a blanket polysilicon layer are formed over the isolation insulating layer 30, the fin structure 20, and the wall fin structure 50, and then a patterning operation is performed to obtain the sacrificial gate structure 60 as shown in Figure 8A and Figure 8B . In some embodiments, the patterning of the polysilicon layer is performed by using a hard mask including a silicon nitride layer as the first hard mask layer 66A and an oxide layer as the second hard mask layer 66B. In other embodiments, the first hard mask layer 66A may be silicon oxide and the second hard mask layer 66B may be silicon nitride. In some embodiments, the sacrificial gate dielectric layer 62 is formed by oxidation. In other embodiments, the sacrificial gate dielectric layer 62 is formed by CVD, PVD, ALD, electron beam evaporation, or other suitable film deposition processes. In this case, as shown in Figure 8D , the sacrificial gate dielectric layer 62 is also formed on the isolation insulating layer 30 and the wall fin structure 50, and is also formed between the sidewall spacers 65 and the fin structure 20. In some embodiments, the thickness of the sacrificial gate dielectric layer 62 is in the range of about 1 nm to about 5 nm.

[0044] As shown in Figure 8B , two sacrificial gate structures 60 extending in the X direction are disposed adjacent to each other in the Y direction. However, the number of sacrificial gate structures is not limited to two. The number may be one, three, four, five, or more. Additionally, one or more dummy gate structures may be disposed near both sides of the sacrificial gate structure 60 to improve pattern fidelity in the patterning process. In some embodiments, the width of the sacrificial gate structure 60 is in the range of about 5 nm to about 40 nm, and in certain embodiments, it may be in the range of about 7 nm to about 15 nm.

[0045] As shown in Figure 8BAs shown, in some embodiments, the wall fin structure 50 surrounds the fin structure. Depending on the spacing between the fin structures 20 in the Y direction, the width of the wall fin structure 50 in the Y direction is less than, equal to, or greater than the width of the wall fin structure 50 in the X direction. In some embodiments, when the spacing between the fin structures 20 in the Y direction is small, no wall fin structure is formed between the ends of the fin structures. In some embodiments, when the spacing between the fin structures 20 in the Y direction is large, a wall fin structure without one of the second dielectric layer and the third dielectric layer is formed, or no wall fin structure is formed between the ends of the fin structures. In some embodiments, a dummy gate structure is formed above the spacing between the fin structures 20 in the Y direction.

[0046] In addition, as Figure 8B and Figure 8C shown, a gate sidewall spacer 65 is formed on the side surface of the sacrificial gate structure 60. An insulating material layer for the gate sidewall spacer 65 is formed above the sacrificial gate structure 60. The insulating material layer is deposited in a conformal manner such that it is formed to have substantially equal thicknesses on the vertical surfaces, horizontal surfaces, and top of the sacrificial gate structure 60 such as sidewalls. In some embodiments, the thickness of the insulating material layer ranges from about 5 nm to about 20 nm. The insulating material layer includes one or more of SiN, SiON, and SiCN or any other suitable dielectric material. The insulating material layer can be formed by ALD or CVD or any other suitable method. Next, the horizontal portion of the insulating material layer is removed by anisotropic etching to form the gate sidewall spacer 65. In some embodiments, the gate sidewall spacer 65 includes two to four different insulating material layers.

[0047] In addition, in some embodiments, as Figure 8E shown, the sacrificial gate structure 60 is cut into multiple pieces of sacrificial gate structures. An insulating isolation plug 69 is formed between adjacent multiple pieces of sacrificial gate structures. In some embodiments, as Figure 8E shown, the isolation plug 69 covers the wall fin structure 50. In other embodiments, at least the third dielectric layer 40 is removed, and then the isolation plug 69 is formed. In certain embodiments, the third dielectric layer 40 and at least a portion of the second dielectric layer 35 are removed, and then the isolation plug 69 is formed. The isolation plug 69 includes one or more dielectric material layers formed by LPCVD, plasma CVD, or atomic layer deposition (ALD) or any other suitable film-forming method, such as silicon oxide, silicon oxynitride, silicon nitride, SiOC, SiCN, or SiOCN.

[0048] Subsequently, as Figure 9 shown, a fin liner layer 70 is formed above the source / drain regions of the fin structures 20 and the wall fin structure 50. Figure 9 corresponds to Figure 8BCross-sectional view of line X2-X2.

[0049] The fin liner 70 includes one or more insulating material layers formed by LPCVD, plasma CVD, or atomic layer deposition (ALD) or any other suitable film-forming method, such as insulating materials like silicon oxide, silicon oxynitride, silicon nitride, SiOC, SiCN, or SiOCN. In certain embodiments, silicon nitride is used as the fin liner 70. In some embodiments, the thickness of the fin liner 70 ranges from about 5 nm to about 20 nm.

[0050] Then, as Figure 10 shown, the horizontal portions of the fin liner 70 are removed by anisotropic etching. By this etching, the tops of the source / drain regions of the fin structure 20 and the tops of the wall fin structures 50 are exposed, and the fin liner 70 remains on the sides of the fin structure 20 as fin sidewalls.

[0051] Furthermore, as Figure 11 shown, the source / drain regions of the fin structure 20 are recessed by using a suitable etching operation. During the etching operation, the fin sidewalls 70 are also recessed below the tops of the wall fin structures 50, as Figure 11 shown. Since the upper portion of the wall fin structure 50 (the recessed third dielectric layer 40 made of, for example, hafnium oxide) is made of a different material from the fin sidewalls 70 (e.g., silicon nitride), the wall fin structure 50 is not recessed. Although in some embodiments the lower portion (the recessed second dielectric layer 35) is made of the same material as the fin sidewalls 70, the recessed second dielectric layer 35 is substantially not etched because the recessing etching is anisotropic etching.

[0052] Subsequently, as Figure 12A and Figure 12B shown, one or more source / drain epitaxial layers 80 are formed over the recessed fin structure 20. Figure 12B is a cross-sectional view of line Y1-Y1 corresponding to Figure 8B

[0053] In some embodiments, the source / drain epitaxial layer 80 includes one or more of SiP, SiAs, SiCP, SiPA, and SiC for n-type FETs, and SiGe, GeSn, and SiGeSn for p-type FETs. For p-type FETs, in some embodiments, the source / drain epitaxial layer 80 is doped with B (boron). In some embodiments, the source / drain epitaxial layer includes multiple layers. In some embodiments, the source / drain epitaxial layer 80 is epitaxially grown by an LPCVD process, molecular beam epitaxy, atomic layer deposition, or any other suitable method. The LPCVD process is carried out using a silicon source gas such as SiH4, Si2H6, or Si3H8; a germanium source gas such as GeH4 or Ge2H6; a carbon source gas such as CH4 or SiH3CH; and a phosphorus source gas such as PH3 at a temperature of about 400 to 800 °C and a pressure of about 1 to 200 Torr.

[0054] In Figure 11 , H1 is the height of the source / drain region of the fin structure 20 before recess etching from the upper surface of the isolation insulating layer 30, H2 is the height of the fin sidewall 70 after recess etching from the upper surface of the isolation insulating layer, and H3 is the distance between the top of the source / drain region of the fin structure 20 before recess etching and the top of the source / drain region of the fin structure 20 after recess etching. H4 is the height of the wall fin structure 50 from the upper surface of the isolation insulating layer 30, and H5 is the height of the recessed third dielectric layer 40 of the wall fin structure 50. Further, as Figure 10 shown, S2 is the spacing between the fin structure 20 having the fin liner layer 70 and the wall fin structure 50 having the fin liner layer 70.

[0055] In some embodiments, depending on the design and / or process requirements of the semiconductor device, the ratio H2 / H1 is in the range of about 0.13 to 0.17. In some embodiments, the ratio H2 / H1 is in the range of about 0.13 to 0.144 (first case), in the range of about 0.144 to 0.156 (second case), or in the range of about 0.156 to 0.17 (third case). In some embodiments, depending on the design and / or process requirements of the semiconductor device, the ratio H3 / H1 is in the range of about 0.88 to 1.0. In some embodiments, the ratio H3 / H1 is in the range of about 0.88 to 0.92 (first case), in the range of about 0.92 to 0.96 (second case), or in the range of about 0.96 to 1.0 (third case).

[0056] When H2 / H1 and / or H3 / H1 exceed the upper limit, the source / drain epitaxial layer 80 formed on the recessed fin structure has a relatively small volume, and when H2 / H1 and / or H3 / H1 are below the lower limit, it is difficult to control the growth direction of the source / drain epitaxial layer and / or adjacent source / drain epitaxial layers 80 may merge.

[0057] In some embodiments, the ratio H4 / H1 ranges from about 0.6 to about 0.9, and in other embodiments from about 0.7 to 0.8. When H4 / H1 exceeds the upper limit, the volume of the source / drain epitaxial layer 80 becomes smaller, and when H4 / H1 is below the lower limit, adjacent source / drain epitaxial layers 80 may merge.

[0058] In some embodiments, the ratio H4 / S2 ranges from about 1.5 to about 4.5, and in other embodiments from about 2.0 to 3.5. When H4 / S2 exceeds the upper limit, the volume of the source / drain epitaxial layer 80 becomes smaller, and when H4 / H1 is below the lower limit, adjacent source / drain epitaxial layers 80 may merge.

[0059] It should be noted that by controlling the height H4 of the wall fin structure, the height H2 of the fin sidewall can be controlled. As described below, the height H2 affects the volume of the source / drain epitaxial layer 80. In other words, by controlling the wall fin height H4 (e.g., the thickness of the recessed second and / or third dielectric layer), the volume of the source / drain epitaxial layer 80 can be controlled.

[0060] Then, one or more interlayer dielectric (ILD) layers 90 are formed over the source / drain epitaxial layer 80 and the sacrificial gate structure 60. Materials for the ILD layer 90 include compounds containing Si, O, C, and / or H, such as silicon oxide, SiCOH, and SiOC. Organic materials such as polymers can be used for the ILD layer 90. After forming the ILD layer 90, a planarization operation such as CMP is performed to expose the top of the sacrificial gate electrode layer 64. In some embodiments, a contact etch stop layer, such as a silicon nitride layer or a silicon oxynitride layer, is formed before forming the ILD layer 90.

[0061] Then, the sacrificial gate electrode layer 64 and the sacrificial gate dielectric layer 62 are removed to form a gate spacer. Plasma dry etching and / or wet etching can be used to remove the sacrificial gate structure. When the sacrificial gate electrode layer 64 is polysilicon and the ILD layer 90 is silicon oxide, a wet etchant such as a TMAH solution can be used to selectively remove the sacrificial gate electrode layer 64. Thereafter, the sacrificial gate dielectric layer 62 is removed using plasma dry etching and / or wet etching.

[0062] After removing the sacrificial gate electrode layer 64 and the sacrificial gate dielectric layer 62, a metal gate structure 100 is formed in the gate spacer, asFigure 13A and Figure 13B as shown Figure 13B is a cross-sectional view of line Y1-Y1 corresponding to Figure 8B The metal gate structure 100 includes a gate dielectric layer 102 and a metal gate electrode layer 106. In some embodiments, the gate dielectric layer 102 includes one or more dielectric material layers, such as silicon oxide, silicon nitride, or high-k dielectric materials, other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconia, alumina, titanium oxide, hafnium oxide-aluminum oxide (HfO2-Al2O3) alloy, other suitable high-k dielectric materials, and / or combinations thereof. In some embodiments, the gate dielectric layer 102 includes an interface layer formed between the channel layer and the dielectric material by chemical oxidation. The gate dielectric layer 102 can be formed by CVD, ALD, or any suitable method. In one embodiment, a highly conformal deposition process such as ALD is used to form the gate dielectric layer 102 to ensure that a gate dielectric layer with a uniform thickness is formed around each channel layer. In one embodiment, the thickness of the gate dielectric layer 102 is in the range of about 1 nm to about 10 nm.

[0063] Subsequently, a metal gate electrode layer 106 is formed over the gate dielectric layer 102. The gate electrode layer 106 includes one or more conductive material layers, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof. The gate electrode layer 106 can be formed by CVD, ALD, electroplating, or other suitable methods. Materials for the gate dielectric layer 102 and the gate electrode layer 106 are also deposited over the upper surface of the ILD layer 90. Then, the material for the gate electrode layer formed on the ILD layer 90 is planarized by using, for example, CMP until the top surface of the ILD layer 90 is exposed.

[0064] In some embodiments of the present disclosure, one or more work function adjustment layers 104 are inserted between the gate dielectric layer 102 and the gate electrode layer 106, as Figure 13A and Figure 13BAs shown. The work function adjustment layer 104 is made of a single layer such as TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi or a multi-layer of two or more of these materials. For an n-channel FET, one or more of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi and TaSi are used as the work function adjustment layer, and for a p-channel FET, one or more of TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC and Co are used as the work function adjustment layer 104. The work function adjustment layer 104 can be formed by ALD, PVD, CVD, electron beam evaporation or other suitable processes. In addition, the work function adjustment layer 104 can be formed separately for n-channel FETs and p-channel FETs that can use different metal layers.

[0065] In some embodiments, after the planarization operation, the metal gate structure 100 is recessed and a capping insulating layer (not shown) is formed over the recessed gate electrode layer. The capping insulating layer includes one or more layers of a silicon nitride-based material, such as SiN. The capping insulating layer can be formed by depositing an insulating material and subsequent planarization operations.

[0066] It should be understood that the FET undergoes further CMOS processes to form various components, such as contacts / vias, interconnect metal layers, dielectric layers, passivation layers, etc.

[0067] Figures 14A to 16B and Figures 17A to 19B is a comparison between cases where H1, H2 and H3 have different sizes.

[0068] Figure 14A and Figure 14B and Figure 17A and Figure 17B corresponds to the above first case, where the ratio H2 / H1 is in the range of about 0.13 to 0.144 (first case) and the ratio H3 / H1 is in the range of about 0.88 to 0.92. Figure 15A and Figure 15B and Figure 18A and Figure 18B corresponds to the above second case, where H2 / H1 is in the range of about 0.144 to 0.156, and the ratio H3 / H1 is in the range of about 0.92 to 0.96. Figure 16A and Figure 16B and Figure 19A and Figure 19B corresponds to the above third case, where H2 / H1 is in the range of about 0.156 to 0.17, and the ratio H3 / H1 is in the range of about 0.96 to 1.0.

[0069] In the first case, the cross-sectional shape of the source / drain epitaxial layer 80 is substantially a whole circle (e.g., an ellipse) as shown in Figure 17A and has the largest volume among the three cases. In some embodiments, the protrusion amount C1 (i.e., the distance from the top (channel region) of the fin structure 20 to the top of the source / drain epitaxial layer) is in the range of about 1 nm to about 5 nm. The width W1 and height L1 of the source / drain epitaxial layer 80 are the largest among the three cases.

[0070] In the second case, the cross-sectional shape of the source / drain epitaxial layer 80 has an upper elliptical shape and a lower semi-rhombus shape as shown in Figure 18A In some embodiments, the protrusion amount C1 is in the range of about ±1 nm. A negative value of C1 means that the top of the source / drain epitaxial layer is lower than the top of the fin structure 20 (channel region).

[0071] In the third case, the cross-sectional shape of the source / drain epitaxial layer 80 is substantially a rhombus shape as shown in Figure 19A and has the smallest volume among the three cases. In some embodiments, the protrusion amount C1 is in the range of about -5 nm to about -1 nm.

[0072] In some embodiments, the interface between the recessed second dielectric layer 35 and the recessed third dielectric layer 40 in the wall fin structure is located above the upper surface of the recessed first dielectric layer (isolation insulating layer) 30. In other embodiments, as shown in Figure 20A , the interface between the recessed second dielectric layer 35 and the recessed third dielectric layer 40 in the wall fin structure is located below the upper surface of the isolation insulating layer 30. In certain embodiments, as shown in Figure 20B , the interface between the recessed second dielectric layer 35 and the recessed third dielectric layer 40 in the wall fin structure is at the same height (±2 nm) as the upper surface of the recessed first dielectric layer (isolation insulating layer) 30. When the recessed third dielectric layer 40 extends too far above the upper surface of the first dielectric layer 30, the recessed third dielectric layer 40 may bend. When the recessed second dielectric layer is completely embedded in the isolation insulating layer 30, the etching of the liner layer 70 does not affect the wall fin structure.

[0073] According to an embodiment of the present disclosure, by adopting a hybrid wall fin structure having at least two layers made of different materials, it is easier to adjust the height of the wall fin structure. In addition, by using a high-k dielectric material for the third dielectric layer, the wall fin structure can be protected during fin liner etching and / or fin recess etching. By adjusting the height of the wall fin structure, the volume and / or shape of the source / drain epitaxial layer can be controlled.

[0074] It should be understood that not all advantages need to be discussed here, that no particular advantage is required for all embodiments or instances, and that other embodiments or instances may provide different advantages.

[0075] According to one aspect of the present disclosure, in a method of manufacturing a semiconductor device, a first dielectric layer is formed over a semiconductor fin disposed over a semiconductor substrate, a second dielectric layer is formed over the first dielectric layer, the second dielectric layer is recessed below the top of each semiconductor fin, a third dielectric layer is formed over the recessed second dielectric layer, and the third dielectric layer is recessed below the top of each semiconductor fin, thereby forming a fin wall disposed between the semiconductor fins. The fin wall includes the recessed third dielectric layer and the recessed second dielectric layer disposed below the recessed third dielectric layer. The first dielectric layer is recessed below the top of the fin wall, a fin liner layer is formed over an upper portion of each semiconductor fin and an upper portion of the fin wall, the fin wall protrudes from the recessed first dielectric layer, the fin liner layer is recessed and the semiconductor fins are recessed, and source / drain epitaxial layers are formed over the recessed semiconductor fins, respectively. The source / drain epitaxial layers are separated from each other by the fin wall. In one or more of the above or below embodiments, the first dielectric layer, the second dielectric layer, and the third dielectric layer are made of different dielectric materials from each other. In one or more of the above or below embodiments, the third dielectric layer includes hafnium oxide. In one or more of the above or below embodiments, the second dielectric layer includes silicon nitride. In one or more of the above or below embodiments, the first dielectric layer includes silicon oxide. In one or more of the above or below embodiments, when etching the fin liner layer, a portion of the fin liner layer formed over the upper portion of each semiconductor fin is retained. In one or more of the above or below embodiments, when etching the fin liner layer, the fin liner formed over the upper portion of the fin wall is completely removed. In one or more of the above or below embodiments, the fin liner layer includes silicon nitride. In one or more of the above or below embodiments, the source / drain epitaxial layer contacts the recessed third dielectric layer of the fin wall.

[0076] According to another aspect of the present disclosure, in a method of manufacturing a semiconductor device, a first dielectric layer is formed over a plurality of semiconductor fins disposed over a semiconductor substrate, thereby leaving a first gap between adjacent semiconductor fins, a second dielectric layer is formed over the first dielectric layer, thereby completely filling the first gap with the second dielectric layer, the second dielectric layer is recessed below the top of each of the plurality of semiconductor fins, thereby forming a second gap over the recessed second dielectric layer between adjacent semiconductor fins covered by the first dielectric layer, a third dielectric layer is formed over the recessed second dielectric layer, thereby completely filling the second gap with the third dielectric layer, the third dielectric layer is recessed below the top of each of the plurality of semiconductor fins, thereby forming wall fins disposed between adjacent semiconductor fins, the first dielectric layer is recessed below the top of each wall fin, a sacrificial gate structure is formed over the upper portion of each of the plurality of semiconductor fins and over the upper portion of each wall fin, the wall fins protrude from the recessed first dielectric layer, a fin liner layer is formed over the upper portion of each of the plurality of semiconductor fins and over the upper portion of each wall fin, the wall fins protrude from the recessed first dielectric layer and are not covered by the sacrificial gate structure, the fin liner layer is etched and the plurality of semiconductor fins are recessed, source / drain epitaxial layers are respectively formed over the plurality of recessed semiconductor fins, and the sacrificial gate structure is replaced with a metal gate structure. The source / drain epitaxial layers are separated from each other by the wall fins. In one or more of the above or below embodiments, the first dielectric layer, the second dielectric layer, and the third dielectric layer are made of different dielectric materials from each other. In one or more of the above or below embodiments, the third dielectric layer includes at least one selected from the group consisting of hafnium oxide, aluminum oxide, zinc oxide, and zirconium oxide. In one or more of the above or below embodiments, the first dielectric layer includes silicon oxide, and the second dielectric layer includes silicon nitride. In one or more of the above or below embodiments, when etching the fin liner layer, a portion of the fin liner layer formed over the upper portion of each of the plurality of semiconductor fins is retained, and the fin liner formed over the upper portion of each wall fin is completely removed. In one or more of the above or below embodiments, an interface between the recessed second dielectric layer and the recessed third dielectric layer in each of the wall fins is located above an upper surface of the recessed first dielectric layer. In one or more of the above or below embodiments, a hard mask pattern is formed on the top of each of the plurality of semiconductor fins before forming the first dielectric layer. In one or more of the above or below embodiments, the first gap is completely filled with the second dielectric layer.

[0077] According to another aspect of the present disclosure, in a method of manufacturing a semiconductor device, a first dielectric layer is formed over a semiconductor fin disposed over a semiconductor substrate, a second dielectric layer is formed over the first dielectric layer, the second dielectric layer is recessed below the top of each semiconductor fin, a third dielectric layer is formed over the recessed second dielectric layer, and the third dielectric layer is recessed below the top of the semiconductor fin, thereby forming a fin wall disposed between the semiconductor fins. The fin wall includes the recessed third dielectric layer and the recessed second dielectric layer disposed below the recessed third dielectric layer. The first dielectric layer is recessed below the top of the fin wall. A sacrificial gate structure is formed, the semiconductor fins not covered by the sacrificial gate structure are recessed, and source / drain epitaxial layers are respectively formed over the recessed semiconductor fins. The source / drain epitaxial layers are separated from each other by the fin wall. In one or more of the above or below embodiments, the source / drain epitaxial layer contacts the recessed third dielectric layer of the fin wall. In one or more of the above or below embodiments, an interface between the recessed second dielectric layer and the recessed third dielectric layer in the fin wall is located below an upper surface of the recessed first dielectric layer.

[0078] According to one aspect of the present disclosure, a semiconductor device includes: a first semiconductor fin and a second semiconductor fin, disposed above a semiconductor substrate and extending in a first direction; an isolation insulating layer disposed between the first semiconductor fin and the second semiconductor fin; a wall fin extending in the first direction, wherein a lower portion of the wall fin is embedded in the isolation insulating layer and an upper portion of the wall fin protrudes from the isolation insulating layer; a gate structure disposed above a channel region of the first semiconductor fin and a channel region of the second semiconductor fin and extending in a second direction intersecting the first direction; a first source / drain epitaxial layer and a second source / drain epitaxial layer, the first source / drain epitaxial layer being disposed above a source / drain region of the first semiconductor fin and the second source / drain epitaxial layer being disposed above a source / drain region of the second semiconductor fin. The first source / drain epitaxial layer and the second source / drain epitaxial layer are separated by the wall fin. The wall fin includes a lower dielectric layer and an upper dielectric layer disposed above the lower dielectric layer and made of a material different from that of the lower dielectric layer. The upper dielectric layer includes a dielectric material having a dielectric constant higher than those of the lower dielectric layer and the isolation insulating layer. In one or more of the above or below embodiments, the upper dielectric layer includes at least one selected from the group consisting of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconia, alumina, titanium oxide, and hafnium oxide-aluminum oxide (HfO2-Al2O3) alloy. In one or more of the above or below embodiments, the lower dielectric layer includes at least one selected from the group consisting of silicon nitride, silicon oxynitride, SiOC, and SiOCN. In one or more of the above or below embodiments, an interface between the lower dielectric layer and the upper dielectric layer in the wall fin is located above an upper surface of the isolation insulating layer. In one or more of the above or below embodiments, the interface between the lower dielectric layer and the upper dielectric layer in the wall fin is located below a horizontal plane at which at least one of the first source / drain epitaxial layer and the second source / drain epitaxial layer has a widest width in the second direction. In one or more of the above or below embodiments, the interface between the lower dielectric layer and the upper dielectric layer in the wall fin is located below an upper surface of the isolation insulating layer. In one or more of the above or below embodiments, a top of the wall fin is located below a top of a channel region of each of the first semiconductor fin and the second semiconductor fin. In one or more of the above or below embodiments, an interface between a source / drain region of the first semiconductor fin and the first source / drain epitaxial layer is located below an upper surface of the isolation insulating layer.

[0079] According to another aspect of the present disclosure, a semiconductor device includes: a first semiconductor fin and a second semiconductor fin disposed above a semiconductor substrate; an isolation insulating layer disposed between the first semiconductor fin and the second semiconductor fin; a wall fin extending in a first direction, wherein a lower portion of the wall fin is embedded in the isolation insulating layer and an upper portion of the wall fin protrudes from the isolation insulating layer; a gate structure disposed above a channel region of the first semiconductor fin and a channel region of the second semiconductor fin, a first source / drain epitaxial layer and a second source / drain epitaxial layer, the first source / drain epitaxial layer being disposed above a source / drain region of the first semiconductor fin and the second source / drain epitaxial layer being disposed above a source / drain region of the second semiconductor fin; and a first fin liner layer and a second fin liner layer, the first fin liner layer being disposed on a bottom portion of the first source / drain epitaxial layer and the second fin liner layer being disposed on a bottom portion of the second source / drain epitaxial layer. The first source / drain epitaxial layer and the second source / drain epitaxial layer are separated by the wall fin, the wall fin includes a lower dielectric layer and an upper dielectric layer disposed above the lower dielectric layer and made of a material different from that of the lower dielectric layer, and the upper dielectric layer, the lower dielectric layer, and the isolation insulating layer are made of different materials from each other. In one or more of the above or below embodiments, the upper dielectric layer includes doped or undoped hafnium oxide. In one or more of the above or below embodiments, the lower dielectric layer includes silicon nitride. In one or more of the above or below embodiments, the fin liner layer includes silicon nitride. In one or more of the above or below embodiments, an interface between the lower dielectric layer and the upper dielectric layer in the wall fin is located above an upper surface of the isolation insulating layer. In one or more of the above or below embodiments, an interface between the lower dielectric layer and the upper dielectric layer in the wall fin is located above a top of the fin liner layer. In one or more of the above or below embodiments, an interface between the lower dielectric layer and the upper dielectric layer in the wall fin is located below a horizontal plane at which at least one of the first source / drain epitaxial layer and the second source / drain epitaxial layer has a widest width along a gate extending direction. In one or more of the above or below embodiments, the first source / drain epitaxial layer and the second source / drain epitaxial layer are in contact with an upper portion of the wall fin. In one or more of the above or below embodiments, no void is formed under the lower dielectric layer in the wall fin.

[0080] According to another aspect of the present disclosure, a semiconductor device includes: a semiconductor fin disposed above a semiconductor substrate and extending in a first direction; an isolation insulating layer disposed above the semiconductor substrate; a wall fin disposed above the substrate, wherein a lower portion of each wall fin is embedded in the isolation insulating layer and an upper portion of the wall fin protrudes from the isolation insulating layer; a gate structure disposed above a channel region of each semiconductor fin; and source / drain epitaxial layers respectively disposed above source / drain regions of the semiconductor fins. The source / drain epitaxial layers are separated from adjacent source / drain epitaxial layers by the wall fins respectively, and each wall fin includes a lower dielectric layer and an upper dielectric layer disposed above the lower dielectric layer and made of a material different from that of the lower dielectric layer. The upper dielectric layer includes a dielectric material having a dielectric constant greater than that of the lower dielectric layer and the isolation insulating layer. In one or more of the above or below embodiments, the gate structure is disposed above the wall fin. In one or more of the above or below embodiments, the upper dielectric layer includes doped or undoped hafnium oxide.

[0081] The features of several embodiments are outlined above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can readily use the present invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructs do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present invention.

Claims

1. A method of manufacturing a semiconductor device, the method comprising: Forming a first dielectric layer over a semiconductor fin disposed above a semiconductor substrate, the first dielectric layer forming a gap that separates adjacent semiconductor fins; Forming a second dielectric layer over the first dielectric layer; Recessing the second dielectric layer below the top of each semiconductor and filling the gap therewith; Forming a third dielectric layer over the recessed second dielectric layer; Recessing the third dielectric layer below the top of each semiconductor fin and filling the gap therewith, thereby forming a wall fin disposed between the semiconductor fins, the wall fin comprising a recessed third dielectric layer and the recessed second dielectric layer disposed below the recessed third dielectric layer, wherein within the gap, sidewalls of the second dielectric layer, sidewalls of the third dielectric layer are in direct contact with and coplanar with inner walls of the gap; Recessing the first dielectric layer below the top of the wall fin; Forming a fin liner layer over an upper portion of each semiconductor fin and an upper portion of the wall fin, the wall fin protruding from the recessed first dielectric layer; Etching the fin liner layer and recessing the semiconductor fins; and Forming source / drain epitaxial layers over the recessed semiconductor fins respectively, wherein the source / drain epitaxial layers are separated from each other by the wall fins.

2. The method according to claim 1, wherein, The first dielectric layer, the second dielectric layer and the third dielectric layer are made of different dielectric materials from each other.

3. The method according to claim 2, wherein The third dielectric layer comprises hafnium oxide.

4. The method according to claim 3, wherein, The second dielectric layer comprises silicon nitride.

5. The method according to claim 4, wherein The first dielectric layer comprises silicon oxide.

6. The method according to claim 2, wherein When etching the fin liner layer, a part of the fin liner layer formed over an upper portion of each semiconductor fin is retained.

7. The method according to claim 6, wherein, When etching the fin liner layer, the fin liner layer formed over an upper portion of the wall fin is completely removed.

8. The method according to claim 6, wherein The fin liner layer comprises silicon nitride.

9. The method according to claim 2, wherein The source / drain epitaxial layer contacts the recessed third dielectric layer of the wall fin.

10. A method of manufacturing a semiconductor device, the method comprising: Forming a first dielectric layer over a plurality of semiconductor fins disposed above a semiconductor substrate, thereby leaving a first gap between adjacent semiconductor fins; Forming a second dielectric layer over the first dielectric layer, such that the first gap is completely filled by the second dielectric layer; Recessing the second dielectric layer below the top of each of the plurality of semiconductor fins, thereby forming a second gap over the recessed second dielectric layer between adjacent semiconductor fins covered by the first dielectric layer; Forming a third dielectric layer over the recessed second dielectric layer, such that the second gap is completely filled by the third dielectric layer; Recessing the third dielectric layer below the top of each of the plurality of semiconductor fins, thereby forming a wall fin disposed between adjacent semiconductor fins; Recessing the first dielectric layer below the top of each wall fin; Forming a sacrificial gate structure over an upper portion of each of the plurality of semiconductor fins and an upper portion of each wall fin, the wall fin protruding from the recessed first dielectric layer; A fin liner layer is formed above the upper portion of each of the plurality of semiconductor fins and above the upper portion of each of the wall fins, the wall fins protruding from a recessed first dielectric layer and covered by the sacrificial gate structure; The fin liner layer is etched and the plurality of semiconductor fins are recessed; Source / drain epitaxial layers are respectively formed above the plurality of recessed semiconductor fins; And The sacrificial gate structure is replaced with a metal gate structure, wherein the source / drain epitaxial layers are separated from each other by the wall fins.

11. The method according to claim 10, wherein, The first dielectric layer, the second dielectric layer, and the third dielectric layer are made of different dielectric materials from each other.

12. The method according to claim 11, wherein, The third dielectric layer includes at least one selected from the group consisting of hafnium oxide, aluminum oxide, zinc oxide, and zirconium oxide.

13. The method according to claim 12, wherein, The first dielectric layer includes silicon oxide, and the second dielectric layer includes silicon nitride.

14. The method according to claim 10, wherein, When etching the fin liner layer, a part of the fin liner layer formed above the upper portion of each of the plurality of semiconductor fins is retained, and the fin liner layer formed above the upper portion of each of the wall fins is completely removed.

15. The method according to claim 10, wherein, The interface between the recessed second dielectric layer and the recessed third dielectric layer in each of the wall fins is located above the upper surface of the recessed first dielectric layer.

16. The method according to claim 10, wherein, Before forming the first dielectric layer, a hard mask pattern is formed on the top of each of the plurality of semiconductor fins.

17. The method according to claim 10, wherein The first spacer is completely filled with the second dielectric layer.

18. A semiconductor device, comprising: A first semiconductor fin and a second semiconductor fin, disposed above a semiconductor substrate and extending in a first direction; An isolation insulating layer, disposed between the first semiconductor fin and the second semiconductor fin; Wall fins, extending in the first direction, wherein a lower portion of the wall fins is embedded in the isolation insulating layer, and an upper portion of the wall fins protrudes from the isolation insulating layer; A gate structure, disposed above the channel regions of the first semiconductor fin and the second semiconductor fin and extending in a second direction intersecting the first direction; A first source / drain epitaxial layer and a second source / drain epitaxial layer, the first source / drain epitaxial layer being disposed above the source / drain region of the first semiconductor fin, and the second source / drain epitaxial layer being disposed above the source / drain region of the second semiconductor fin, wherein: The first source / drain epitaxial layer and the second source / drain epitaxial layer are separated by the wall fins, The wall fins include a lower dielectric layer and an upper dielectric layer disposed above the lower dielectric layer and made of a material different from that of the lower dielectric layer, and The upper dielectric layer includes a dielectric material having a dielectric constant higher than those of the lower dielectric layer and the isolation insulating layer, wherein the lower dielectric layer is embedded in the spacer of the isolation insulating layer, sidewalls of the lower dielectric layer are in direct contact with inner walls of the spacer, and sidewalls of the upper dielectric layer, sidewalls of the lower dielectric layer, and sidewalls of the spacer are coplanar.

19. The semiconductor device according to claim 18, wherein, The upper dielectric layer includes at least one selected from the group consisting of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconia, alumina, titanium oxide, and hafnium oxide-aluminum oxide (HfO2-Al2O3) alloy.

20. The semiconductor device according to claim 18, wherein, The lower dielectric layer includes at least one selected from the group consisting of silicon nitride, silicon oxynitride, SiOC, and SiOCN.

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