Semiconductor device and method for forming the same

Abstract

A semiconductor device and method are provided. The semiconductor device according to the present invention includes a first transistor in a first region and a second transistor in a second region. The first transistor includes a first gate structure extending longitudinally along a first direction, and a first gate spacer, a second gate spacer, and a third gate spacer above the sidewall of the first gate structure. The second transistor includes a second gate structure extending longitudinally along the first direction, and a first gate spacer and a third gate spacer above the sidewall of the second gate structure. The first gate spacer, the second gate spacer, and the third gate spacer have different compositions, and the third gate spacer is directly located on the first gate spacer in the second region.

Description

Technical Field

[0001] Embodiments of the present application provide a semiconductor device and a method for forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. During the development of ICs, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometric size (i.e., the smallest component (or wire) that can be produced using a manufacturing process) has decreased. Scaling down processes is generally beneficial for increasing production efficiency and reducing associated costs. However, this scaling down is also accompanied by an increase in the complexity of the design and manufacture of the devices that comprise these ICs, and in order to achieve these advances, similar developments in device manufacturing are needed.

[0003] Scaling of semiconductor devices has also reduced the thickness of the gate dielectric layer, which requires a reduction in the gate voltage to avoid device failure. However, the supply voltage of the external circuit has not kept pace with the scaling of semiconductor devices. Although the thickness of the gate dielectric layer has been reduced by several times, the supply voltage has only decreased from about 5 volts to about 2.5 to 3.3 volts. This uneven scaling trend has led to an increasing electric field in the gate dielectric layer near the drain. The increased electric field in turn leads to hot carrier injection (HCI or hot carrier effect (HCE)), which describes the phenomenon that charge carriers (electrons or holes) gain high kinetic energy due to the presence of high electric fields. HCI is undesirable because it degrades device performance and causes leakage. HCI is particularly relevant to input / output (I / O) devices because they interface with external circuits that operate at the supply voltage. HCI issues can prevent multi-gate devices such as fin field effect transistors (FinFETs) from being used as I / O devices. Summary of the invention

[0004] In some embodiments, a semiconductor device includes: a first transistor, the first transistor is in a first region, the first transistor includes: a first gate structure extending longitudinally along a first direction, and a first gate spacer layer, a second gate spacer layer, and a third gate spacer layer above the side wall of the first gate structure; and a second transistor, the second transistor is in a second region, the second transistor includes: a second gate structure extending longitudinally along the first direction, and the first gate spacer layer and the third gate spacer layer above the side wall of the second gate structure, wherein the first gate spacer layer, the second gate spacer layer, and the third gate spacer layer have different compositions, and wherein the third gate spacer layer is directly located on the first gate spacer layer in the second region.

[0005] In some embodiments, a semiconductor device includes: a first transistor, the first transistor is in a first region, the first transistor includes: a first gate structure extending longitudinally along a first direction, and a first gate spacer layer, a second gate spacer layer, a third gate spacer layer, and a fourth gate spacer layer above the side wall of the first gate structure; and a second transistor, the second transistor is in a second region, the second transistor includes: a second gate structure extending longitudinally along the first direction, and the first gate spacer layer, the third gate spacer layer, and the fourth gate spacer layer above the side wall of the second gate structure, wherein the fourth gate spacer layer, the third gate spacer layer, and the second gate spacer layer have different compositions, and wherein the third gate spacer layer is directly located on the first gate spacer layer in the second region.

[0006] In some embodiments, a method includes: depositing a first dummy gate stack over a first region of a substrate, and depositing a second dummy gate stack over a second region of the substrate; depositing a first spacer material layer over the first dummy gate stack and the second dummy gate stack; depositing a second spacer material layer over the first spacer material layer; etching back the second spacer material layer; selectively removing the second spacer material layer in the second region; after selectively removing, depositing a third spacer material layer over the first dummy gate stack and the second dummy gate stack; and etching the first spacer material layer, the second spacer material layer, and the third spacer material layer to form a first gate spacer along the sidewall of the first dummy gate stack and a second gate spacer along the sidewall of the second dummy gate stack, wherein the compositions of the first gate spacer material layer, the second gate spacer material layer, and the third gate spacer material layer are different.

[0007] An embodiment of the present application provides an input / output device. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0009] Figure 1 is a flow chart of a method of manufacturing a semiconductor device according to various aspects of the present invention.

[0010] Figures 2 to 11 According to various aspects of the present invention Figure 1 Partial cross-sectional views of a workpiece during various operations of the method.

[0011] Fig.12 is a flow chart of another method of manufacturing a semiconductor device according to various aspects of the present invention.

[0012] Figures 13 to 22 According to various aspects of the present invention Fig.12 Partial cross-sectional views of a workpiece during various operations of the method.

[0013] Fig.23 is a flow chart of an alternative method of fabricating a semiconductor device according to various aspects of the present invention.

[0014] Figures 24 to 33 According to various aspects of the present invention Fig.23 Partial cross-sectional views of a workpiece during various operations of the method. DETAILED DESCRIPTION

[0015] It should be understood that the following disclosure provides many different embodiments or examples for realizing the different features of various embodiments. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or characters in various examples. This repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0016] Moreover, in the present invention, the formation of a component on another component that is connected to and / or coupled to another component may include an embodiment in which direct contact is formed, and may also include an embodiment in which additional components may be formed between these components so that these components may not be in direct contact. Moreover, for the convenience of the present invention, spatially relative terms such as "lower", "upper", "horizontal", "vertical", "above", "above", "below", "below", "upward", "downward", "top", "bottom" and their derivatives (for example, "horizontally", "downwardly", "upwardly", etc.) may be used herein to describe the relationship between one component and another component. Spatially relative terms are used to cover different orientations of the device including these components.

[0017] In addition, when "about", "approximately", etc. are used to describe a number or a range of numbers, the term is intended to encompass numbers within a reasonable range including the number, such as numbers within + / -10% of the number or other values ​​understood by those skilled in the art. For example, the term "about 5 nm" encompasses a size range from 4.5 nm to 5.5 nm.

[0018] Scaling of semiconductor devices reduces the thickness of the gate dielectric layer and increases the electric field in the gate dielectric layer near the drain. The increased electric field may lead to HCI (or HCE), which describes the phenomenon that charge carriers (electrons or holes) gain high kinetic energy and are injected into the gate dielectric layer due to the presence of a high electric field. HCI is undesirable because it changes the threshold voltage, degrades device performance, and causes leakage. Because the operating voltage of I / O devices (e.g., between about 2.5V and 5.0V) is higher than the operating voltage of core devices, I / O devices are more susceptible to HCI-related failures and performance issues. When forming an I / O FinFET, the source / drain trench or the resulting source / drain features may be undercut on the gate spacer layer, thereby reducing the channel length and the distance between the channel and the drain. The reduction in the distance between the channel and the drain may exacerbate HCI.

[0019] The present invention provides such embodiments, wherein the I / O devices and core devices manufactured on the same substrate have different gate spacer arrangements to meet the switching speed requirements of the core devices and the reduction of HCI of the I / O devices. In these embodiments, the I / O devices include additional boost spacers, while the core devices do not include such additional boost spacers. The additional boost spacers increase the distance between the channel and the drain of the I / O device and reduce the occurrence of HCI. The boost spacers can be formed of silicon oxide and can be protected by gate spacers that are more resistant to etching.

[0020] Various embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. Figure 1 , Fig.12 and Fig.23 Flowcharts showing methods 100, 400 and 500 of forming a semiconductor device on a workpiece 200 are shown. Figure 1 , Fig.12 and Fig.23 Not shown, but Figures 2 to 11 , Figures 13 to 22 and Figures 24 to 33 Methods 100, 400, and 500 are merely examples and are not intended to limit the present invention beyond the scope explicitly described in the claims. For other embodiments of these methods, other operations may be added before, during, and after methods 100, 400, and 500, and some of the operations described may be replaced, eliminated, or moved. Figures 2 to 11Describing method 100, the following is combined with Figures 13 to 22 Method 400 is described below in conjunction with Figures 24 to 33 Method 500 is described. Figures 2 to 11 , Figures 13 to 22 and Figures 24 to 33 Each of the embodiments shows a partial cross-sectional view of the workpiece 200 during various operations of the method 100, the method 400, or the method 500. The present invention is not limited to any particular number of devices or device areas, or any particular device configuration. Other components may be added to the semiconductor device manufactured on the workpiece 200, and some of the components described below may be replaced, modified, or eliminated in other embodiments of the semiconductor device to be manufactured on the workpiece 200. Because a semiconductor device will be formed from the workpiece 200 at the end of the process described in the present invention, the workpiece 200 may be referred to as a semiconductor device 200 as the context requires. The operation of the method 100 is described below, followed by the methods 400 and 500. The methods 400 and 500 have similar operations to the method 100, and similar operations in the methods 400 and 500 may be simplified or omitted for the sake of brevity.

[0021] refer to Figure 1 and Figure 2 , the method 100 includes a block 102 of receiving a workpiece 200. Figure 2 As shown, the workpiece 200 includes a substrate 202, a first fin structure 204-1 above a first region 1000 of the substrate 202, a second fin structure 204-2 above a second region 2000 of the substrate 202, a first dummy gate stack 206-1 above the first fin structure 204-1, and a second dummy gate stack 206-2 above the second fin structure 204-2. In some embodiments, the first region 1000 may be a high voltage device region or an I / O device region, and the second region 2000 may be a logic device region, which includes a logic device, a memory device, or a digital signal processing device. In some implementations, the devices in the first region 1000 operate and are configured to operate at an operating voltage between approximately 2.5V and 5V, and the devices in the second region 2000 operate and are configured to operate at an operating voltage between approximately 0.5V and approximately 1V. Figure 2 As shown, the first fin structure 204-1 and the second fin structure 204-2 may be parallel to each other. Each of the first fin structure 204-1 and the second fin structure 204-2 is connected to and generated from the substrate 202. In addition, each of the first fin structure 204-1 and the second fin structure 204-2 may be referred to as an active region or a fin-shaped active region.

[0022] The substrate 202 may include a basic (single element) semiconductor, such as silicon, germanium, and / or other suitable materials; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or other suitable materials; an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, and / or other suitable materials. The substrate 202 may be a single layer of material having a uniform composition. Alternatively, the substrate 202 may include multiple material layers having similar or different compositions suitable for IC device manufacturing. In one example, the substrate 202 may be a silicon-on-insulator (SOI) substrate having a silicon layer formed on a silicon oxide layer. In another example, the substrate 202 may include a conductive layer, a semiconductor layer, a dielectric layer, other layers, or a combination thereof. In some embodiments, where the substrate 202 includes different types of transistors, various doped regions, such as source / drain regions, are disposed in or on the substrate 202. According to design requirements, the doped region may be doped with a p-type dopant, such as phosphorus or arsenic, and / or an n-type dopant, such as boron or BF2. The doped region may be directly formed on the substrate 202 in a p-type well structure, an n-type well structure, a double well structure, or using a raised structure. The doped region may be formed by implanting dopant atoms, epitaxial growth of in-situ doping, and / or other suitable techniques. For simplicity, the substrate 202 is only shown in FIG. Figure 2 is schematically shown in FIG. 1 and for simplicity Figures 3 to 9 Omitted in .

[0023] The first fin structure 204-1 and the second fin structure 204-2 may be manufactured using a suitable process including a photolithography process and an etching process. The photolithography process may include forming a photoresist layer (resist) covering the substrate 202; exposing the resist to a pattern; performing a post-exposure baking process; and developing the resist to form a mask element (not shown) including the resist. The mask element is then used to etch a groove into the substrate 202, thereby leaving the first fin structure 204-1 and the second fin structure 204-2 on the substrate 202. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. Many other embodiments of the method for forming the first fin structure 204-1 and the second fin structure 204-2 may be suitable. For example, the first fin structure 204-1 and the second fin structure 204-2 may be patterned using a double patterning process or a multiple patterning process. Typically, a double patterning process or a multiple patterning process combines a photolithography process with a self-alignment process, allowing the formation of patterns with, for example, a pitch smaller than that obtainable using a single direct photolithography process. For example, in one embodiment, a material layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned material layer using a self-aligned process. The material layer is then removed, and the remaining spacers or mandrels can then be used to pattern multiple fin structures 204. The first fin structure 204-1 and the second fin structure 204-2 extend in length along the X direction.

[0024] Despite Figure 2 It is not explicitly shown in the figure, but the first fin structure 204-1 and the second fin structure 204-2 can be separated from the adjacent fin structure by an isolation component, which can include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric material and / or other suitable materials. The isolation component may include a shallow trench isolation component. In one embodiment, the isolation component can be formed by etching a trench in the substrate 202 during the formation of the first fin structure 204-1 and the second fin structure 204-2. Then, the trench can be filled with the above-mentioned isolation material through a deposition process, and then a chemical mechanical planarization (CMP) process is used. Other isolation structures, such as field oxide layers, local oxidation of silicon (LOCOS) and / or other suitable structures can also be implemented as isolation components. The isolation component can be deposited by any suitable method, such as chemical vapor deposition (CVD), flow CVD (FCVD), spin-on glass (SOG), other suitable methods or combinations thereof.

[0025] like Figure 2As shown, the first dummy gate stack 206-1 is disposed above the first channel region C1 of the first fin structure 204-1 in the first region 1000. The first channel region C1 is sandwiched between the two first source / drain regions SD1 of the first fin structure 204-1. Similarly, the second dummy gate stack 206-2 is disposed above the second channel region C2 of the second fin structure 204-2 in the second region 2000. The second channel region C2 is sandwiched between the two second source / drain regions SD2 of the second fin structure 204-2. In some embodiments, the first dummy gate stack 206-1 and the second dummy gate stack 206-2 may include polysilicon. For patterning purposes, the workpiece 200 may also include a gate top hard mask 208 above the first dummy gate stack 206-1 and the second dummy gate stack 206-2. The gate top hard mask 208 may be a single layer or multiple layers. In some examples, when the gate top hard mask 208 is multi-layered, the gate top hard mask 208 includes a pad oxide layer and a pad nitride layer above the pad oxide layer. The first dummy gate stack 206-1 and the second dummy gate stack 206-2 extend longitudinally along a Y direction perpendicular to the X direction. Although not explicitly shown, before forming the first dummy gate stack 206-1 and the second dummy gate stack 206-2, a dummy gate dielectric layer may be deposited over the first fin structure 204-1 and the second fin structure 204-2. The dummy gate dielectric layer may be formed of silicon oxide. As shown in FIG. Figure 2 As shown, the first width W1 of the first dummy gate stack 206 - 1 is greater than the second width W2 of the second dummy gate stack 206 - 2 to provide a longer channel length in the first region 1000 .

[0026] refer to Figure 1 and Figure 2 , the method 100 includes a block 104 of depositing a first spacer material layer 210 over the workpiece 200. In some embodiments, the first spacer material layer 210 may include silicon, oxygen, carbon, and nitrogen. In one embodiment, the first spacer material layer 210 may include silicon oxycarbonitride (SiOCN). The dielectric constant of the first spacer material layer 210 may be similar to the dielectric constant of a silicon oxide layer. In some implementations, the first spacer material layer 210 may be deposited over the first dummy gate stack 206-1 and the second dummy gate stack 206-2 using a CVD process, a sub-atmospheric CVD (SACVD) process, an ALD process, a PVD process, or other suitable process. In some implementations, the thickness of the first spacer material layer 210 may be between about 2.5 nm and about 3.0 nm.

[0027] refer to Figure 1 and Figure 3, the method 100 includes a block 106 of performing an implantation process 300. In some embodiments, the implantation process 300 is performed to form an LDD region (not shown) above the first source / drain region SD1 and the second source / drain region SD2. The implantation process 300 may be used for an n-type field effect transistor (NFET), such as phosphorus (P) or arsenic (As), or a p-type dopant, such as boron (B) or indium (In), for a p-type field effect transistor (PFET). For example, the operation at block 106 may implant an n-type dopant into the first source / drain region SD1 and the second source / drain region SD2. The LDD region is self-aligned with the first dummy gate stack 206-1 and the second dummy gate stack 206-2. In some implementations, the first spacer material layer 210 is used as a shielding layer or a protective layer to control the thickness of the LDD region and reduce surface damage. Although not explicitly shown in the figure, after the implantation process 300, the workpiece 200 is annealed to activate the implanted ions in the LDD region.

[0028] refer to Figure 1 and Figure 4 , the method 100 includes a block 108 of depositing a second spacer material layer 211 over the first spacer material layer 210. In some embodiments, the second spacer material layer 211 and the first spacer material layer 210 may have the same composition. In these embodiments, the second spacer material layer 211 may include silicon, oxygen, carbon, and nitrogen. In one embodiment, the second spacer material layer 211 may include silicon oxycarbonitride (SiOCN). The dielectric constant of the second spacer material layer 211 may be similar to the dielectric constant of a silicon oxide layer. In some embodiments, the second spacer material layer 211 may be deposited over the first spacer material layer 210 using a CVD process, a SACVD process, an ALD process, a PVD process, or other suitable process. In some implementations, the second spacer material layer 211 may have a thickness similar to the thickness of the first spacer material layer 210. In some examples, the thickness of the second spacer material layer 211 may be between about 2.5 nm and about 3.0 nm.

[0029] refer to Figure 1 and Figure 5, the method 100 includes a block 110 of depositing a third spacer material layer 212 over the second spacer material layer 211. The third spacer material layer 212 is formed of a dielectric material different from the fin structure, the first spacer material layer 210, the second spacer material layer 211, and the fourth spacer material layer 214 (described below). As such, their different compositions allow the third spacer material layer 212 to be selectively removed without damaging adjacent structures. In some embodiments, the third spacer material layer 212 may include silicon, carbon, or oxygen. In one embodiment, the third spacer material layer 212 may include silicon oxide. In some implementations, the third spacer material layer 212 may be porous and have a dielectric constant less than that of silicon oxide. In some implementations, the third spacer material layer 212 may be deposited over the second spacer material layer 211 using a CVD process, a SACVD process, an ALD process, a PVD process, or other suitable processes. According to the present invention, the thickness of the third spacer material layer 212 is greater than the thickness of the second spacer material layer 211, so that the third spacer material layer 212 can be used as a thickness booster. In this regard, the third spacer material layer 212 may also be referred to as a thickness boosting layer. In some examples, the thickness of the third spacer material layer 212 may be between about 8 nm and about 20 nm. By design of the present invention, the third spacer material layer 212 has a low dielectric constant so that the thickness can be increased without increasing the dielectric constant.

[0030] refer to Figure 1 and Figure 6 , the method 100 includes a block 112 of etching back the third spacer material layer 212. In some embodiments, at block 112, an anisotropic dry etching process, such as reactive ion etching (RIE), may be performed on the workpiece 200. The anisotropic dry etching process at block 112 may remove portions of the third spacer material layer 212 deposited on the top surface of the second spacer material layer 211. The different composition of the third spacer material layer 212 allows for selective etching thereof without substantially damaging the second spacer material layer 211. Figure 6 As shown, the operation at block 112 leaves the third spacer material layer 212 (and the gate top hard mask 208 thereon) along the sidewalls of the first dummy gate stack 206-1 (and the gate top hard mask 208 thereon) and the second dummy gate stack 206-2. In some implementations, the anisotropic dry etching process at block 112 may use a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBR3), an iodine-containing gas, oxygen, hydrogen, other suitable gases and / or plasmas, and / or combinations thereof.

[0031] refer to Figure 1 and Figure 7 , the method 100 includes a block 114 of selectively removing the third spacer material layer 212 in the second region 2000. Figure 7 In some embodiments shown, a photoresist mask 213 is formed over the workpiece 200, covering the first region 1000 but exposing the second region 2000. In an exemplary process, a photoresist layer is blanket deposited over the workpiece 200 and patterned using a photolithography process. In the exemplary process, after the photoresist layer is deposited, the photoresist layer is soft-baked, exposed to radiation reflected from or transmitted through the photomask, baked in a post-baking process, and developed in a developer solution. In the case where the photoresist mask 213 protects the first region 1000, a selective wet etching process, a selective dry etching process, or a suitable selective etching process can be used to selectively remove the third spacer material layer 212 in the second region 2000. An exemplary selective wet etching process may include the use of dilute hydrofluoric acid (DHF) or buffered hydrofluoric acid (BHF). BHF may include hydrofluoric acid (HF) and ammonia (NH3) here.

[0032] refer to Figure 1 and Figure 8, the method 100 includes a block 116, in which a fourth spacer material layer 214 is deposited over the workpiece 200. In some embodiments, the fourth spacer material layer 214 is more etch-resistant than the first spacer material layer 210, the second spacer material layer 211, and the third spacer material layer 212. It can be seen that the etch resistance is generally positively correlated with the dielectric constant. That is, the dielectric constant of the fourth spacer material layer 214 is greater than the dielectric constant of the first spacer material layer 210, the second spacer material layer 211, or the third spacer material layer 212. The fourth spacer material layer 214 may include silicon and nitrogen and may not contain oxygen. In one embodiment, the fourth spacer material layer 214 may be formed of silicon nitride (SiN). In some implementations, the fourth spacer material layer 214 may be deposited over the second spacer material layer 211 (in the first region 1000 and the second region 2000) and the third spacer material layer 212 (in the first region 1000) using a CVD process, a SACVD process, an ALD process, a PVD process, or other suitable processes. In some examples, the thickness of the fourth spacer material layer 214 is between about 4.5 nm and about 6 nm. Among the first spacer material layer 210, the second spacer material layer 211, the third spacer material layer 212 and the fourth spacer material layer 214, the fourth spacer material layer 214 has the greatest etching resistance and dielectric constant. Although its high etching resistance may be desirable, the high dielectric constant of the fourth spacer material layer 214 may cause an increase in parasitic capacitance between the gate structure and the adjacent source / drain contact. For these reasons, the thickness of the fourth spacer material layer 214 of the present invention is minimized and selected to meet process attributes, such as etchant type, etching conditions, etching duration, or desired source / drain trench size.

[0033] refer to Figure 1 and Fig. 9, the method 100 includes block 118, wherein a first source / drain trench 216-1 is formed in the first region 1000, and a second source / drain trench 216-2 is formed in the second region 2000. At block 118, the first source / drain region SD1 and the second source / drain region SD2 that are not protected by the first dummy gate stack 206-1, the second dummy gate stack 206-2, and the spacer material layer are recessed to form the first source / drain trench 216-1 in the first region 1000 and the second source / drain trench 216-2 in the second region 2000. The operation at block 118 may be performed using an anisotropic dry etching process. In some implementations, the anisotropic dry etching process at block 118 may use a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBR3), an iodine-containing gas, oxygen, hydrogen, other suitable gases and / or plasmas, and / or combinations thereof. Fig. 9 As shown, the anisotropic dry etching process not only forms the first source / drain trench 216 - 1 and the second source / drain trench 216 - 2 , but also removes the fourth spacer material layer 214 , the second spacer material layer 211 and the first spacer material layer 210 from the top surface of the gate top hard mask 208 .

[0034] refer to Figure 1 and Fig.10, the method 100 includes a block 120, wherein a first source / drain feature 218-1 is formed in the first source / drain trench 216-1, and a second source / drain feature 218-2 is formed in the second source / drain trench 216-2. The first source / drain feature 218-1 and the second source / drain feature 218-2 may be formed by one or more epitaxial processes. In order to provide a clean surface for epitaxial growth, a cleaning process may be performed to clean the first source / drain trench 216-1 and the second source / drain trench 216-2 with an HF solution or other suitable solution. Subsequently, one or more epitaxial growth processes are performed to grow epitaxial features in the first source / drain trench 216-1 and the second source / drain trench 216-2. The first source / drain component 218-1 and the second source / drain component 218-2 can be suitable for a p-type metal oxide semiconductor (PMOS) device (e.g., including a p-type epitaxial material), or alternatively, an n-type MOS (NMOS) device (e.g., including an n-type epitaxial material). The p-type epitaxial material may include one or more silicon germanium (SiGe) epitaxial layers, wherein the silicon germanium is doped with a p-type dopant, such as boron, germanium, indium, and / or other p-type dopants. The n-type epitaxial material may include one or more silicon (Si) or silicon carbide (SiC) epitaxial layers, wherein the silicon or silicon carbon is doped with an n-type dopant, such as arsenic, phosphorus, and / or other n-type dopant. In some implementations, each epitaxial growth process may include different in-situ doping levels of suitable dopants. The epitaxial growth process forming the first source / drain feature 218 - 1 and the second source / drain feature 218 - 2 may include vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), a cross deposition and etching (CDE) process, molecular beam epitaxy (MBE), and / or other suitable processes.

[0035] refer to Figure 1 and Fig.11 , the method 100 includes a frame 122, wherein the first dummy gate stack 206-1 is replaced by the first gate structure 250, and the second dummy gate stack 206-2 is replaced by the second gate structure 260. In some embodiments, a gate replacement process or a gate-last process is used, and the first dummy gate stack 206-1 and the second dummy gate stack 206-2 are replaced by the first gate structure 250 and the second gate structure 260. The gate replacement process can be performed on all of the first dummy gate stack 206-1 in the first region 1000 and the second dummy gate stack 206-2 in the second region 2000 at the same time. After the gate replacement is completed, the first gate structure 250 is disposed above the first channel region C1 of the first fin structure 204-1 in the first region 1000, and the second gate structure 260 is disposed above the second channel region C2 of the second fin structure 204-2 in the second region 2000.

[0036] To replace the dummy gate stack with the gate structure, an interlayer dielectric (ILD) layer 220 is formed over the workpiece 200, including over the first source / drain feature 218-1 and the second source / drain feature 218-2. A contact etch stop layer (CESL) (not shown) may be deposited over the workpiece 200 before depositing the ILD layer 220. A planarization process is then performed on the workpiece 200 to remove the gate top hard mask 208 and expose the top surfaces of the first dummy gate stack 206-1 and the second dummy gate stack 206-2. In an example where the first dummy gate stack 206-1 and the second dummy gate stack 206-2 are formed of polysilicon, an etching process selective to polysilicon may be used to remove the first dummy gate stack 206-1 and the second dummy gate stack 206-2 to expose the first channel region C1 and the second channel region C2 without substantially damaging the first gate spacer 230, the second gate spacer 240, and the ILD layer 220. In some embodiments, each of the first gate structure 250 and the second gate structure 260 includes a gate dielectric layer 252 and a gate electrode 254. The gate dielectric layer 252 may include an interface layer and one or more high-k dielectric layers (i.e., a dielectric constant greater than that of silicon oxide, about 3.9) above the interface layer. In some implementations, the interface layer may include silicon oxide, and the high-k dielectric layer may include hafnium oxide, zirconium oxide, aluminum oxide, hafnium dioxide-aluminum oxide alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, etc. or a combination thereof. The interface layer is used to enhance the adhesion of the high-k dielectric layer to the first channel region C1 and the second channel region C2. The gate electrode 254 may include at least one work function metal layer and a metal filling layer disposed thereon. Depending on the conductivity type of the device in the first region 1000 and the device in the second region 2000, the work function metal layer may be a p-type or n-type work function metal layer. Exemplary work function materials include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable work function materials, or combinations thereof. The metal fill layer may include copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), other suitable materials, or combinations thereof, and may use physical vapor deposition (PVD), CVD, ALD, or other suitable processes.

[0037] Still reference Fig.11At the end of the operation at box 122, the first transistor 270 and the second transistor 280 are substantially formed. The first transistor 270 may be an I / O FinFET in the first region 1000, and the second transistor 280 may be a core FinFET in the second region 2000. The first transistor 270 includes a first gate spacer 230 disposed along a sidewall of the first gate structure 250. The second transistor 280 includes a second gate spacer 240 disposed along a sidewall of the second gate structure 260 in the second region 2000. Each first gate spacer 230 includes a first spacer material layer 210, a second spacer material layer 211, a third spacer material layer 212, and a fourth spacer material layer 214. Each second gate spacer 240 includes a first spacer material layer 210, a second spacer material layer 211, and a fourth spacer material layer 214. Compared to the first gate spacer 230, the second gate spacer 240 does not include the third spacer material layer 212 as a thickness boosting layer. In the first gate spacer 230 and the second gate spacer 240, the first spacer material layer 210 occupies a first thickness T1, the second spacer material layer 211 occupies a second thickness T2, the third spacer material layer 212 occupies a third thickness T3, and the fourth spacer material layer 214 occupies a fourth thickness T4. The first thickness T1 is similar to the thickness of the first spacer material layer 210 after deposition, and is between about 2.5 nm and about 3.0 nm. The second thickness T2 is similar to the thickness of the second spacer material layer 211 after deposition, and is between about 2.5 nm and about 3.0 nm. The third thickness T3 is less than the thickness of the third spacer material layer 212 after deposition, and is between about 7 nm and about 19 nm. The fourth thickness T4 is less than the thickness of the fourth spacer material layer 214 after deposition, and is between about 4 nm and about 5.5 nm. As a result, the thickness of the first gate spacer 230 along the X direction can be between about 14 nm and about 30 nm, and the thickness of the second gate spacer 240 along the X direction can be between about 9 nm and about 12 nm. As Fig.11As shown, the first channel length L1 can be between about 74 nm and about 6 μm (6000 nm), and the second channel length L2 can be less than 74 nm. The first gate spacer 230 helps to space the first channel region C1 from the first source / drain feature 218-1 by a first distance D1. When the first source / drain feature 218-1 does not undercut the first gate spacer 230, the first distance D1 can be similar to the thickness of the first gate spacer 230. The first distance D1 spans the LDD region formed at frame 116. The second gate spacer 240 helps to space the second channel region C2 from the second source / drain feature 218-2 by a first distance D2. When the second source / drain feature 218-2 does not undercut the second gate spacer 240, the second distance D2 can be similar to the thickness of the second gate spacer 240. The second distance D2 spans the LDD region formed at frame 116. Fig.11 In some examples shown, the second source / drain feature 218-2 undercuts the second gate spacer 240, and the second distance D2 is less than the thickness of the second gate spacer 240. Due to the longer first channel length L1 and the thicker first gate spacer 230, the first transistor 270 can have an operating voltage between about 3.3V and about 5.0V, making it suitable for high voltage or I / O applications.

[0038] refer to Figure 1 , the method 100 includes a block 124 of performing further processes. Such further processes may include depositing a capping layer over the workpiece, forming another interlayer dielectric layer over the capping layer, forming gate contacts in contact with the first gate structure 250 and the second gate structure 260, recesses for the first source / drain feature 218-1 and the second source / drain feature 218-2, forming silicide features over the first source / drain feature 218-1 and the second source / drain feature 218-2, and forming source / drain contacts in contact with the first source / drain feature 218-1 and the second source / drain feature 218-2. These further processes form conductive features that interconnect various nodes and devices in the semiconductor device 200.

[0039] In addition to the method 100, the present invention also provides Fig.12 The alternative method 400 and Fig.23 Alternative method 500 is shown. Similar to method 100, alternative methods 400 and 500 provide different gate spacers for transistors in the first region 1000 and transistors in the second region 2000. For example, the gate spacers in the first region 1000 include a thickness boosting layer, while the gate spacers in the second region 2000 do not include a thickness boosting layer.

[0040] refer to Fig.12 and Fig.13The method 400 includes a block 402 of receiving a workpiece 200. Fig.13 As shown, the workpiece 200 includes a substrate 202, a first fin structure 204-1 above the first region 1000 of the substrate 202, a second fin structure 204-2 above the second region 2000 of the substrate 202, a first dummy gate stack 206-1 above the first fin structure 204-1, and a second dummy gate stack 206-2 above the second fin structure 204-2. Since the workpiece 200 has been described above with respect to block 102 of the method 100, a detailed description of the workpiece 200 is omitted for the sake of brevity. For the sake of brevity, the substrate 202 is only described in detail. Fig.13 is schematically shown in FIG. 1 and for simplicity Figures 14 to 22 Omitted in .

[0041] refer to Fig.12 and 13 , the method 400 includes a frame 404 of depositing a third spacer material layer 212 above the workpiece 200. The third spacer material layer 212 is formed of a dielectric material different from the fin structure, the first spacer material layer 210, the second spacer material layer 211, and the fourth spacer material layer 214. In this way, its different composition allows the third spacer material layer 212 to be selectively removed without damaging adjacent structures. Since the composition and formation of the third spacer material layer 212 have been described above, a detailed description of the third spacer material layer 212 is omitted for the sake of brevity. In the method 400, the third spacer material layer 212 can be used as a thickness booster. In this regard, the third spacer material layer 212 can also be referred to as a thickness booster layer. In some examples, the thickness of the third spacer material layer 212 can be between about 8nm and about 20nm. Through the design of the present invention, the third spacer material layer 212 has a low dielectric constant so as to increase the thickness without increasing the dielectric constant.

[0042] refer to Fig.12 and Fig.14 , the method 400 includes a block 406 of etching back the third spacer material layer 212. In some embodiments, at block 406, an anisotropic dry etching process, such as reactive ion etching (RIE), may be performed on the workpiece 200. The anisotropic dry etching process at block 406 may remove portions of the third spacer material layer 212 deposited on the top-facing surfaces of the first fin structure 204-1 and the second fin structure 204-2. The different composition of the third spacer material layer 212 allows for selective etching thereof without substantially damaging the first fin structure 204-1, the second fin structure 204-2, and the gate top hard mask 208. Fig.14As shown, the operation at block 406 leaves the third spacer material layer 212 along the sidewalls of the first dummy gate stack 206-1 (and the gate top hard mask 208 thereon) and the second dummy gate stack 206-2 (and the gate top hard mask 208 thereon). In some implementations, the anisotropic dry etching process at block 406 may use a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBR3), an iodine-containing gas, oxygen, hydrogen, other suitable gases and / or plasmas, and / or combinations thereof.

[0043] refer to Fig.12 and Fig.15 , the method 400 includes a block 408 of selectively removing the third spacer material layer 212 in the second region 2000. Fig.15 In some embodiments shown, a photoresist mask 213 is formed over the workpiece 200, covering the first region 1000 but exposing the second region 2000. In an exemplary process, a photoresist layer is blanket deposited over the workpiece 200 and patterned using a photolithography process. In the case where the photoresist mask 213 protects the first region 1000, a selective wet etching process, a selective dry etching process, or a suitable selective etching process can be used to selectively remove the third spacer material layer 212 in the second region 2000. An exemplary selective wet etching process may include the use of dilute hydrofluoric acid (DHF) or buffered hydrofluoric acid (BHF). BHF here may include hydrofluoric acid (HF) and ammonia (NH3).

[0044] refer to Fig.12 and Fig.16, the method 400 includes a frame 410 of depositing a first spacer material layer 210 over the workpiece 200. In some embodiments, the first spacer material layer 210 may include silicon, oxygen, carbon, and nitrogen. In one embodiment, the first spacer material layer 210 may include silicon oxycarbonitride (SiOCN). The dielectric constant of the first spacer material layer 210 may be similar to the dielectric constant of the silicon oxide layer. In some implementations, the first spacer material layer 210 may be deposited on the gate top hard mask 208, the surface of the third spacer material layer 212, and the first fin structure 204-1 in the first region 1000. In the second region 2000, the first spacer material layer 210 may be deposited on the surface of the gate top hard mask 208, the sidewall of the second dummy gate stack 206-2, and the surface of the second fin structure 204-2. The first spacer material layer 210 may be deposited using a CVD process, a SACVD process, an ALD process, a PVD process, or other suitable processes. In some implementations, the thickness of the first spacer material layer 210 can be between about 2.5 nm and about 3.0 nm.

[0045] refer to Fig.12 and Fig.17 , the method 400 includes a block 412 of performing the implantation process 300. In some embodiments, the implantation process 300 is performed to form an LDD region (not shown) above the first source / drain region SD1 and the second source / drain region SD2. The implantation process 300 may be used for an n-type field effect transistor (NFET) with an n-type dopant, such as phosphorus (P) or arsenic (As), or a p-type dopant, such as boron (B) or indium (In), for a p-type field effect transistor (PFET). For example, the operation at block 412 may implant an n-type dopant into the first source / drain region SD1 and the second source / drain region SD2. The LDD region is self-aligned with the first dummy gate stack 206-1 and the second dummy gate stack 206-2. In some implementations, the first spacer material layer 210 is used as a shielding layer or a protective layer to control the thickness of the LDD region and reduce surface damage. Although not explicitly shown in the figure, after the implantation process 300, the workpiece 200 is annealed to activate the implanted ions in the LDD region.

[0046] refer to Fig.12 and Fig.18, the method 400 includes a block 414 of depositing a second spacer material layer 211 over the first spacer material layer 210. In some embodiments, the second spacer material layer 211 and the first spacer material layer 210 may have the same composition. In these embodiments, the second spacer material layer 211 may include silicon, oxygen, carbon, and nitrogen. In one embodiment, the second spacer material layer 211 may include silicon oxycarbonitride (SiOCN). The dielectric constant of the second spacer material layer 211 may be similar to the dielectric constant of a silicon oxide layer. In some embodiments, the second spacer material layer 211 may be deposited over the first spacer material layer 210 using a CVD process, a SACVD process, an ALD process, a PVD process, or other suitable process. In some implementations, the second spacer material layer 211 may have a thickness similar to the thickness of the first spacer material layer 210. In some examples, the thickness of the second spacer material layer 211 may be between about 2.5 nm and about 3.0 nm.

[0047] refer to Fig.12 and Fig.19 , the method 400 includes a block 416, wherein a fourth spacer material layer 214 is deposited on the second spacer material layer 211. In some embodiments, the fourth spacer material layer 214 is more etch-resistant than the first spacer material layer 210, the second spacer material layer 211, and the third spacer material layer 212. It can be seen that the etch resistance is generally positively correlated with the dielectric constant. That is, the dielectric constant of the fourth spacer material layer 214 is greater than the dielectric constant of the first spacer material layer 210, the second spacer material layer 211, or the third spacer material layer 212. The fourth spacer material layer 214 may include silicon and nitrogen and may be free of oxygen. In one embodiment, the fourth spacer material layer 214 may be formed of silicon nitride (SiN). In some implementations, the fourth spacer material layer 214 may be deposited over the second spacer material layer 211 using a CVD process, a SACVD process, an ALD process, a PVD process, or other suitable processes. In some examples, the thickness of the fourth spacer material layer 214 is between about 4.5 nm and about 6 nm.

[0048] refer to Fig.12 and Fig. 20, the method 400 includes a block 418, wherein a first source / drain trench 216-1 is formed in the first region 1000, and a second source / drain trench 216-2 is formed in the second region 2000. At block 418, the first source / drain region SD1 and the second source / drain region SD2 that are not protected by the first dummy gate stack 206-1, the second dummy gate stack 206-2, and the spacer material layer are recessed to form the first source / drain trench 216-1 in the first region 1000 and the second source / drain trench 216-2 in the second region 2000. The operation at block 418 may be performed using an anisotropic dry etching process. In some implementations, the anisotropic dry etching process at block 418 may use a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBR3), an iodine-containing gas, oxygen, hydrogen, other suitable gases and / or plasmas, and / or combinations thereof. Fig. 20 As shown, the anisotropic dry etching process not only forms the first source / drain trench 216 - 1 and the second source / drain trench 216 - 2 , but also removes the fourth spacer material layer 214 , the second spacer material layer 211 and the first spacer material layer 210 from the top surface of the gate top hard mask 208 .

[0049] refer to Fig.12 and Fig.21 The method 400 includes block 420, wherein a first source / drain feature 218-1 is formed in the first source / drain trench 216-1, and a second source / drain feature 218-2 is formed in the second source / drain trench 216-2. Since the first source / drain feature 218-1 and the second source / drain feature 218-2 have been described above with respect to block 120, their detailed description is omitted here for the sake of brevity.

[0050] refer to Fig.12 and Fig. 22 The method 400 includes block 422, wherein the first dummy gate stack 206-1 is replaced by the first gate structure 250, and the second dummy gate stack 206-2 is replaced by the second gate structure 260. Since the first gate structure 250 and the second gate structure 260 have been described above with respect to block 122, their detailed descriptions are omitted here for the sake of brevity.

[0051] Still reference Fig. 22At the end of the operation at box 422, the third transistor 272 and the fourth transistor 282 are substantially formed. The third transistor 272 may be an I / O FinFET in the first region 1000, and the fourth transistor 282 may be a core FinFET in the second region 2000. The third transistor 272 includes a third gate spacer 232 disposed along a sidewall of the first gate structure 250. The fourth transistor 282 includes a fourth gate spacer 242 disposed along a sidewall of the second gate structure 260 in the second region 2000. Each third gate spacer 232 includes a first spacer material layer 210, a second spacer material layer 211, a third spacer material layer 212, and a fourth spacer material layer 214. Each fourth gate spacer 242 includes a first spacer material layer 210, a second spacer material layer 211, and a fourth spacer material layer 214. Compared to the third gate spacer 232, the fourth gate spacer 242 does not include the third spacer material layer 212 as a thickness boosting layer. In the third gate spacer 232 and the fourth gate spacer 242, the first spacer material layer 210 occupies a first thickness T1, the second spacer material layer 211 occupies a second thickness T2, the third spacer material layer 212 occupies a third thickness T3, and the fourth spacer material layer 214 occupies a fourth thickness T4. The first thickness T1 is similar to the thickness of the first spacer material layer 210 after deposition, and is between about 2.5 nm and about 3.0 nm. The second thickness T2 is similar to the thickness of the second spacer material layer 211 after deposition, and is between about 2.5 nm and about 3.0 nm. Since the third spacer material layer 212 has been etched back, the third thickness T3 is less than the thickness of the third spacer material layer 212 after deposition and is between about 7 nm and about 19 nm. Since the fourth spacer material layer 214 has been etched, the fourth thickness T4 is less than the thickness of the fourth spacer material layer 214 after deposition and is between about 4 nm and about 5.5 nm. As a result, the thickness of the third gate spacer 232 along the X direction may be between about 14 nm and about 30 nm, and the thickness of the fourth gate spacer 242 along the X direction may be between about 9 nm and about 12 nm. Fig. 22As shown, the first channel length L1 can be between about 74nm and about 6μm (6000nm), and the second channel length L2 can be less than 74nm. The third gate spacer 232 helps to space the first channel region C1 from the first source / drain feature 218-1 by a first distance D1. When the first source / drain feature 218-1 does not undercut the third gate spacer 232, the first distance D1 can be similar to the thickness of the third gate spacer 232. The first distance D1 spans the LDD region formed at frame 412. The fourth gate spacer 242 helps to space the second channel region C2 from the second source / drain feature 218-2 by a second distance D2. When the second source / drain feature 218-2 does not undercut the fourth gate spacer 242, the second distance D2 can be similar to the thickness of the fourth gate spacer 242. The second distance D2 spans the LDD region formed at frame 412. Fig. 22 In some examples shown, the second source / drain feature 218-2 undercuts the fourth gate spacer 242, and the second distance D2 is less than the thickness of the fourth gate spacer 242. Due to the longer first channel length L1 and the thicker third gate spacer 232, the third transistor 272 can have an operating voltage between about 3.3V and about 5.0V, making it suitable for high voltage or I / O applications.

[0052] refer to Fig.12 , the method 400 includes a block 424 of performing further processes. Such further processes have been described above and are omitted here for the sake of brevity.

[0053] Attention is now directed to method 500 .

[0054] refer to Fig.23 and Fig.24 The method 500 includes a block 502 of receiving a workpiece 200. Fig.24 As shown, the workpiece 200 includes a substrate 202, a first fin structure 204-1 above the first region 1000 of the substrate 202, a second fin structure 204-2 above the second region 2000 of the substrate 202, a first dummy gate stack 206-1 above the first fin structure 204-1, and a second dummy gate stack 206-2 above the second fin structure 204-2. Since the workpiece 200 has been described above with respect to block 102 of the method 100, a detailed description of the workpiece 200 is omitted for the sake of brevity. For the sake of brevity, the substrate 202 is only described in detail. Fig.24 is schematically shown in FIG. 1 and for simplicity Figures 25 to 33 Omitted in .

[0055] refer to Fig.23 and Fig.24, the method 500 includes a frame 504 of depositing a first spacer material layer 210 over the workpiece 200. In some embodiments, the first spacer material layer 210 may include silicon, oxygen, carbon, and nitrogen. In one embodiment, the first spacer material layer 210 may include silicon oxycarbonitride (SiOCN). The dielectric constant of the first spacer material layer 210 may be similar to the dielectric constant of the silicon oxide layer. In some implementations, the first spacer material layer 210 may be deposited on the gate top hard mask 208, the sidewalls of the first dummy gate stack 206-1, and the first fin structure 204-1 in the first region 1000. In the second region 2000, the first spacer material layer 210 may be deposited on the surface of the gate top hard mask 208, the sidewalls of the second dummy gate stack 206-2, and the surface of the second fin structure 204-2. The first spacer material layer 210 may be deposited using a CVD process, a SACVD process, an ALD process, a PVD process, or other suitable processes. In some implementations, the thickness of the first spacer material layer 210 can be between about 2.5 nm and about 3.0 nm.

[0056] refer to Fig.23 and Fig.25 , the method 500 includes a block 506 of performing the implantation process 300. In some embodiments, the implantation process 300 is performed to form an LDD region (not shown) above the first source / drain region SD1 and the second source / drain region SD2. The implantation process 300 may be used for an n-type field effect transistor (NFET) with an n-type dopant, such as phosphorus (P) or arsenic (As), or a p-type dopant, such as boron (B) or indium (In), for a p-type field effect transistor (PFET). For example, the operation at block 506 may implant an n-type dopant into the first source / drain region SD1 and the second source / drain region SD2. The LDD region is self-aligned with the first dummy gate stack 206-1 and the second dummy gate stack 206-2. In some implementations, the first spacer material layer 210 is used as a shielding layer or a protective layer to control the thickness of the LDD region and reduce surface damage. Although not explicitly shown in the figure, after the implantation process 300, the workpiece 200 is annealed to activate the implanted ions in the LDD region.

[0057] refer to Fig.23 and Fig.26, the method 500 includes a frame 508 of depositing a third spacer material layer 212 above the workpiece 200. The third spacer material layer 212 is formed of a dielectric material different from the fin structure, the first spacer material layer 210, the second spacer material layer 211, and the fourth spacer material layer 214. In this way, its different composition allows the third spacer material layer 212 to be selectively removed without damaging adjacent structures. Since the composition and formation of the third spacer material layer 212 have been described above, a detailed description of the third spacer material layer 212 is omitted for the sake of brevity. In the method 500, the third spacer material layer 212 can be used as a thickness boosting layer. In this regard, the third spacer material layer 212 can also be referred to as a thickness boosting layer. In some examples, the thickness of the third spacer material layer 212 can be between about 8nm and about 20nm. Through the design of the present invention, the third spacer material layer 212 has a low dielectric constant so as to increase the thickness without increasing the dielectric constant.

[0058] refer to Fig.23 and Fig. 27 , the method 500 includes a block 510 of forming a third spacer material layer 212. In some embodiments, at block 510, the workpiece 200 may be subjected to an anisotropic dry etching process, such as reactive ion etching (RIE), at block 510. The anisotropic dry etching process at block 510 may remove portions of the third spacer material layer 212 that are deposited on the first spacer material layer 210. The different composition of the third spacer material layer 212 allows for selective etching thereof without substantially damaging the first spacer material layer 210. Fig. 27 As shown, the operation at block 510 leaves the third spacer material layer 212 along the sidewalls of the first dummy gate stack 206-1 (and the gate top hard mask 208 thereon) and the second dummy gate stack 206-2 (and the gate top hard mask 208 thereon). In some implementations, the anisotropic dry etching process at block 510 may use a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBR3), an iodine-containing gas, oxygen, hydrogen, other suitable gases and / or plasmas, and / or combinations thereof.

[0059] refer to Fig.23 and Fig.28 , the method 500 includes a block 512 of selectively removing the third spacer material layer 212 in the second region 2000. Fig.28In some embodiments shown, a photoresist mask 213 is formed over the workpiece 200, covering the first region 1000 but exposing the second region 2000. In an exemplary process, a photoresist layer is blanket deposited over the workpiece 200 and patterned using a photolithography process. In the case where the photoresist mask 213 protects the first region 1000, a selective wet etching process, a selective dry etching process, or a suitable selective etching process can be used to selectively remove the third spacer material layer 212 in the second region 2000. An exemplary selective wet etching process may include the use of dilute hydrofluoric acid (DHF) or buffered hydrofluoric acid (BHF). BHF here may include hydrofluoric acid (HF) and ammonia (NH3).

[0060] refer to Fig.23 and Fig.29 , the method 500 includes a block 514 of depositing a second spacer material layer 211 over the first spacer material layer 210 and the third spacer material layer 212. In some embodiments, the second spacer material layer 211 and the first spacer material layer 210 may have the same composition. In these embodiments, the second spacer material layer 211 may include silicon, oxygen, carbon, and nitrogen. In one embodiment, the second spacer material layer 211 may include silicon oxycarbonitride (SiOCN). The dielectric constant of the second spacer material layer 211 may be similar to the dielectric constant of the silicon oxide layer. In some implementations, the second spacer material layer 211 may be deposited using a CVD process, a SACVD process, an ALD process, a PVD process, or other suitable process. In some implementations, the second spacer material layer 211 may have a thickness similar to the thickness of the first spacer material layer 210. In some examples, the thickness of the second spacer material layer 211 may be between about 2.5 nm and about 3.0 nm.

[0061] refer to Fig.23 and Fig.30, the method 500 includes a block 516, wherein a fourth spacer material layer 214 is deposited on the second spacer material layer 211. In some embodiments, the fourth spacer material layer 214 is more etch-resistant than the first spacer material layer 210, the second spacer material layer 211, and the third spacer material layer 212. It can be seen that the etch resistance is generally positively correlated with the dielectric constant. That is, the dielectric constant of the fourth spacer material layer 214 is greater than the dielectric constant of the first spacer material layer 210, the second spacer material layer 211, or the third spacer material layer 212. The fourth spacer material layer 214 may include silicon and nitrogen and may be free of oxygen. In one embodiment, the fourth spacer material layer 214 may be formed of silicon nitride (SiN). In some implementations, the fourth spacer material layer 214 may be deposited over the second spacer material layer 211 using a CVD process, a SACVD process, an ALD process, a PVD process, or other suitable processes. In some examples, the thickness of the fourth spacer material layer 214 is between about 4.5 nm and about 6 nm.

[0062] refer to Fig.23 and Fig.31 , the method 500 includes a block 518, wherein a first source / drain trench 216-1 is formed in the first region 1000, and a second source / drain trench 216-2 is formed in the second region 2000. At block 518, the first source / drain region SD1 and the second source / drain region SD2 that are not protected by the first dummy gate stack 206-1, the second dummy gate stack 206-2, and the spacer material layer are recessed to form the first source / drain trench 216-1 in the first region 1000 and the second source / drain trench 216-2 in the second region 2000. The operation at block 518 may be performed using an anisotropic dry etching process. In some implementations, the anisotropic dry etching process at block 518 may use a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBR3), an iodine-containing gas, oxygen, hydrogen, other suitable gases and / or plasmas, and / or combinations thereof. Fig.31 As shown, the anisotropic dry etching process not only forms the first source / drain trench 216 - 1 and the second source / drain trench 216 - 2 , but also removes the fourth spacer material layer 214 , the second spacer material layer 211 and the first spacer material layer 210 from the top surface of the gate top hard mask 208 .

[0063] refer to Fig.23 and Fig.32The method 500 includes block 520, wherein a first source / drain feature 218-1 is formed in the first source / drain trench 216-1, and a second source / drain feature 218-2 is formed in the second source / drain trench 216-2. Since the first source / drain feature 218-1 and the second source / drain feature 218-2 have been described above with respect to block 120, their detailed description is omitted here for the sake of brevity.

[0064] refer to Fig.23 and Fig.33 The method 500 includes a block 522, in which the first dummy gate stack 206-1 is replaced by the first gate structure 250, and the second dummy gate stack 206-2 is replaced by the second gate structure 260. Since the first gate structure 250 and the second gate structure 260 have been described above with respect to block 122 of the method 100, their detailed descriptions are omitted here for the sake of brevity.

[0065] Still reference Fig.33. At the end of the operation at box 522, the fifth transistor 274 and the sixth transistor 284 are substantially formed. The fifth transistor 274 may be an I / O FinFET in the first region 1000, and the sixth transistor 284 may be a core FinFET in the second region 2000. The fifth transistor 274 includes a fifth gate spacer 234 disposed along the sidewall of the first gate structure 250. The sixth transistor 284 includes a sixth gate spacer 244 disposed along the sidewall of the second gate structure 260 in the second region 2000. Each fifth gate spacer 234 includes a first spacer material layer 210, a second spacer material layer 211, a third spacer material layer 212, and a fourth spacer material layer 214. Each sixth gate spacer 244 includes a first spacer material layer 210, a second spacer material layer 211, and a fourth spacer material layer 214. Compared to the fifth gate spacer 234, the sixth gate spacer 244 does not include the third spacer material layer 212 as a thickness boosting layer. In the fifth gate spacer 234 and the sixth gate spacer 244, the first spacer material layer 210 occupies a first thickness T1, the second spacer material layer 211 occupies a second thickness T2, the third spacer material layer 212 occupies a third thickness T3, and the fourth spacer material layer 214 occupies a fourth thickness T4. The first thickness T1 is similar to the thickness of the first spacer material layer 210 after deposition, and is between about 2.5 nm and about 3.0 nm. The second thickness T2 is similar to the thickness of the second spacer material layer 211 after deposition, and is between about 2.5 nm and about 3.0 nm. Since the third spacer material layer 212 has been etched back, the third thickness T3 is less than the thickness of the third spacer material layer 212 after deposition and is between about 7 nm and about 19 nm. Since the fourth spacer material layer 214 has been etched, the fourth thickness T4 is less than the thickness of the fourth spacer material layer 214 after deposition and is between about 4 nm and about 5.5 nm. As a result, the thickness of the fifth gate spacer 234 along the X direction may be between about 14 nm and about 30 nm, and the thickness of the sixth gate spacer 244 along the X direction may be between about 9 nm and about 12 nm. Fig.33As shown, the first channel length L1 can be between about 74nm and about 6μm (6000nm), and the second channel length L2 can be less than 74nm. The fifth gate spacer 234 helps to space the first channel region C1 from the first source / drain feature 218-1 by a first distance D1. When the first source / drain feature 218-1 does not undercut the fifth gate spacer 234, the first distance D1 can be similar to the thickness of the fifth gate spacer 234. The first distance D1 spans the LDD region formed at frame 506. The sixth gate spacer 244 helps to space the second channel region C2 from the second source / drain feature 218-2 by a second distance D2. When the second source / drain feature 218-2 does not undercut the sixth gate spacer 244, the second distance D2 can be similar to the thickness of the sixth gate spacer 244. The second distance D2 spans the LDD region formed at frame 506. Fig.33 In some examples shown, the second source / drain feature 218-2 is undercut on the sixth gate spacer 244, and the second distance D2 is less than the thickness of the sixth gate spacer 244. Due to the longer first channel length L1 and the thicker fifth gate spacer 234, the operating voltage of the fifth transistor 274 can be between about 3.3V and about 5.0V, making it suitable for high voltage or I / O applications.

[0066] refer to Fig.23 , the method 500 includes a block 524 of performing further processing. Such further processing has been described above and is omitted here for the sake of brevity.

[0067] The first gate spacer 230, the third gate spacer 232, and the fifth gate spacer 234 have similar thicknesses along the X direction. Although the thicknesses are similar, the first gate spacer 230, the third gate spacer 232, and the fifth gate spacer 234 have different structures. Fig.11 As shown, the first gate spacer 230 includes a first spacer material layer 210 adjacent to the first gate structure 250, a second spacer material layer 211 disposed on the first spacer material layer 210, a third spacer material layer 212 disposed on and along the second spacer material layer 211, and a fourth spacer material layer 214 located on the sidewall of the third spacer material layer 212 and the top surface of the second spacer material layer 211. In the first gate spacer 230, the third spacer material layer 212 is disposed between the second spacer material layer 211 and the fourth spacer material layer 214, and the second spacer material layer 211 is sandwiched between the first spacer material layer 210 and the third spacer material layer 212. Fig. 22As shown, the third gate spacer 232 includes a third spacer material layer 212 disposed along the sidewall of the first gate structure 250, a first spacer material layer 210 disposed along the sidewall of the third spacer material layer 212, a second spacer material layer 211 disposed on the first spacer material layer 210, and a fourth spacer material layer 214 on the sidewall and top surface of the second spacer material layer 211. In the third gate spacer 232, the first spacer material layer 210 is disposed between the third spacer material layer 212 and the second spacer material layer 211, and the second spacer material layer 211 is sandwiched between the first spacer material layer 210 and the fourth spacer material layer 214. Fig.33 As shown, the fifth gate spacer 234 includes a first spacer material layer 210 disposed along the sidewalls of the first gate structure 250 and the top surface of the first fin structure 204-1, a third spacer material layer 212 disposed on the first spacer material layer 210, a second spacer material layer 211 disposed on the sidewalls of the third spacer material layer 212, and a fourth spacer material layer 214 disposed on the sidewalls of the second spacer material layer 211. In the fifth gate spacer 234, the third spacer material layer 212 is disposed between the first spacer material layer 210 and the second spacer material layer 211, and the second spacer material layer 211 is sandwiched between the third spacer material layer 212 and the fourth spacer material layer 214.

[0068] The second gate spacer 240, the fourth gate spacer 242, and the sixth gate spacer 244 have similar thicknesses along the X direction. The second gate spacer 240, the fourth gate spacer 242, and the sixth gate spacer 244 also have similar structures. Fig.11 , Fig. 22 and Fig.33 , each of the second gate spacer 240, the fourth gate spacer 242, and the sixth gate spacer 244 includes a first spacer material layer 210 adjacent to the second gate structure 260, a second spacer material layer 211 disposed on the sidewalls and the top surface of the first spacer material layer 210, and a fourth spacer material layer 214 disposed on the sidewalls and the top surface of the second spacer material layer 211. As described above, the second gate spacer 240, the fourth gate spacer 242, and the sixth gate spacer 244 do not include the third spacer material layer 212. Without the thickness boosting layer, the second gate spacer 240, the fourth gate spacer 242, and the sixth gate spacer 244 are thinner than the first gate spacer 230, the third gate spacer 232, and the fifth gate spacer 234, respectively.

[0069] Although not intended to be limiting, one or more embodiments of the present invention provide benefits. For example, the present invention provides different gate spacers in the I / O device region and the core device region of a semiconductor device. These different gate spacers include a multilayer structure. The gate spacers in the I / O device region include a thickness boosting layer, while the gate spacers in the core device region do not include a thickness boosting layer. As a result, the gate spacers in the I / O device are thicker than the gate spacers in the core device region. The thicker gate spacers in the I / O device further separate the gate structure from the source / drain components to reduce the occurrence of HCI-related failures. The material of the thickness boosting layer is selected so that it can be selectively etched or removed relative to other spacer material layers. The present invention also discloses a method for forming different gate spacers in the I / O device region and the core device region of a semiconductor device.

[0070] According to some embodiments, the present invention provides a semiconductor device. The semiconductor device includes a first transistor in a first region and a second transistor in a second region. The first transistor includes a first gate structure extending longitudinally along a first direction, and a first gate spacer, a second gate spacer, and a third gate spacer above the sidewall of the first gate structure. The second transistor includes a second gate structure extending longitudinally along the first direction, and a first gate spacer and a third gate spacer above the sidewall of the second gate structure. The first gate spacer, the second gate spacer, and the third gate spacer have different compositions. The third gate spacer is directly on the first gate spacer in the second region.

[0071] In some embodiments, in the first region, the second gate spacer is disposed above the first gate spacer, and the third gate spacer is disposed above the second gate spacer. In some embodiments, the width of the first gate structure along a second direction perpendicular to the first direction is greater than the width of the second gate structure along the second direction. In some implementations, the second gate spacer includes silicon oxide. In some embodiments, the first gate spacer includes silicon oxycarbonitride. In some instances, the third gate spacer includes silicon nitride. In some embodiments, the third gate spacer includes silicon nitride. In some instances, the first gate spacer has a first thickness, the second gate spacer has a second thickness, and the third gate spacer has a third thickness. The second thickness is greater than the first thickness and the third thickness. In some implementations, the third thickness is greater than the first thickness.

[0072] According to other embodiments, the present invention provides an IC device including a semiconductor device. The semiconductor device includes a first transistor in a first region and a second transistor in a second region. The first transistor includes a first gate structure extending longitudinally along a first direction, and a first gate spacer, a second gate spacer, a third gate spacer, and a fourth gate spacer above the sidewall of the first gate structure. The second transistor includes a second gate structure extending longitudinally along the first direction, and a first gate spacer, a third gate spacer, and a fourth gate spacer above the sidewall of the second gate structure. The fourth gate spacer, the third gate spacer, and the second gate spacer have different compositions. The third gate spacer is directly on the first gate spacer in the second region.

[0073] In some embodiments, in the first region, the second gate spacer is disposed above the first gate spacer, the third gate spacer is disposed above the second gate spacer, and the fourth gate spacer is disposed above the third gate spacer. The first region is an input / output region, and the second region is a core device region. In some embodiments, the width of the first gate structure along a second direction perpendicular to the first direction is greater than the width of the second gate structure along the second direction. In some implementations, the second gate spacer includes silicon oxide. In some instances, the first gate spacer and the third gate spacer include silicon oxycarbonitride. In some instances, the fourth gate spacer includes silicon nitride. In some implementations, the first gate spacer has a first thickness, the second gate spacer has a second thickness, the third gate spacer has a third thickness, and the fourth gate spacer has a fourth thickness. The second thickness is greater than the first thickness, the third thickness, and the fourth thickness.

[0074] According to other embodiments, the present invention provides a method. The method includes depositing a first dummy gate stack over a first region of a substrate and depositing a second dummy gate stack over a second region of the substrate, depositing a first spacer material layer over the first dummy gate stack and the second dummy gate stack, depositing a second spacer material layer over the first spacer material layer, etching back the second spacer material layer, selectively removing the second spacer material layer in the second region, depositing a third spacer material layer over the first dummy gate stack and the second dummy gate stack after selective removal, and etching the first spacer material layer, the second spacer material layer, and the third spacer material layer to form a first gate spacer along the sidewall of the first dummy gate stack, and forming a second gate spacer along the sidewall of the second dummy gate stack. The first spacer material layer, the second spacer material layer, and the third spacer material layer have different compositions.

[0075] In some embodiments, the first spacer material layer includes silicon oxycarbonitride, the second spacer material layer includes silicon oxide, and the third spacer material layer includes silicon nitride. In some implementations, etching back the second spacer material layer includes removing the second spacer material layer on the top surface. In some examples, selectively removing the second spacer material layer includes forming a photoresist mask to cover the first region and expose the second region, and etching the second region using the photoresist mask as an etching mask.

[0076] In some embodiments, a semiconductor device includes: a first transistor, the first transistor is in a first region, the first transistor includes: a first gate structure extending longitudinally along a first direction, and a first gate spacer, a second gate spacer, and a third gate spacer above a sidewall of the first gate structure; and a second transistor, the second transistor is in a second region, the second transistor includes: a second gate structure extending longitudinally along the first direction, and the first gate spacer and the third gate spacer above a sidewall of the second gate structure, wherein the first gate spacer, the second gate spacer, and the third gate spacer have different compositions, wherein the third gate spacer is directly located on the first gate spacer in the second region. In some embodiments, in the first region, the second gate spacer is disposed above the first gate spacer, and the third gate spacer is disposed above the second gate spacer. In some embodiments, the width of the first gate structure along a second direction perpendicular to the first direction is greater than the width of the second gate structure along the second direction. In some embodiments, the second gate spacer includes silicon oxide. In some embodiments, the first gate spacer includes silicon oxycarbonitride. In some embodiments, the third gate spacer includes silicon nitride. In some embodiments, the third gate spacer includes silicon nitride. In some embodiments, the first gate spacer layer has a first thickness, the second gate spacer layer has a second thickness, and the third gate spacer layer has a third thickness, wherein the second thickness is greater than the first thickness and the third thickness. In some embodiments, the third thickness is greater than the first thickness.

[0077] In some embodiments, a semiconductor device includes: a first transistor, the first transistor is in a first region, the first transistor includes: a first gate structure extending longitudinally along a first direction, and a first gate spacer, a second gate spacer, a third gate spacer, and a fourth gate spacer above a sidewall of the first gate structure; and a second transistor, the second transistor is in a second region, the second transistor includes: a second gate structure extending longitudinally along the first direction, and the first gate spacer, the third gate spacer, and the fourth gate spacer above a sidewall of the second gate structure, wherein the fourth gate spacer, the third gate spacer, and the second gate spacer have different compositions, wherein the third gate spacer is directly located on the first gate spacer in the second region. In some embodiments, in the first region, the second gate spacer is disposed above the first gate spacer, the third gate spacer is disposed above the second gate spacer, and the fourth gate spacer is disposed above the third gate spacer, wherein the first region is an input / output region, and the second region is a core device region. In some embodiments, the width of the first gate structure along a second direction perpendicular to the first direction is greater than the width of the second gate structure along the second direction. In some embodiments, the second gate spacer includes silicon oxide. In some embodiments, the first gate spacer layer and the third gate spacer layer include silicon oxycarbon nitride. In some embodiments, the fourth gate spacer layer includes silicon nitride. In some embodiments, the first gate spacer layer has a first thickness, the second gate spacer layer has a second thickness, the third gate spacer layer has a third thickness, and the fourth gate spacer layer has a fourth thickness, wherein the second thickness is greater than the first thickness, the third thickness, and the fourth thickness.

[0078] In some embodiments, a method includes: depositing a first dummy gate stack over a first region of a substrate and depositing a second dummy gate stack over a second region of the substrate; depositing a first spacer material layer over the first dummy gate stack and the second dummy gate stack; depositing a second spacer material layer over the first spacer material layer; etching back the second spacer material layer; selectively removing the second spacer material layer in the second region; depositing a third spacer material layer over the first dummy gate stack and the second dummy gate stack after the selective removal; and etching the first spacer material layer, the second spacer material layer, and the third spacer material layer to form a first gate spacer along a sidewall of the first dummy gate stack and a second gate spacer along a sidewall of the second dummy gate stack, wherein the first gate spacer material layer, the second gate spacer material layer, and the third gate spacer material layer have different compositions. In some embodiments, the first spacer material layer includes silicon oxycarbon nitride, wherein the second spacer material layer includes silicon oxide, and wherein the third spacer material layer includes silicon nitride. In some embodiments, etching back the second spacer material layer includes removing the second spacer material layer on a surface facing the top. In some embodiments, selectively removing the second spacer material layer includes: forming a photoresist mask to cover the first region and expose the second region; and etching the second region using the photoresist mask as an etching mask.

[0079] The features of several embodiments are summarized above. Those skilled in the art will appreciate that they can easily use the present invention as a basis to design or modify other processes and structures for achieving the same purpose and / or achieving the same advantages as the embodiments described herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present invention, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, comprising: A first transistor, the first transistor is in a first region, the first transistor comprising: a first gate structure extending longitudinally along a first direction, and a first gate spacer, a second gate spacer, and a third gate spacer over a sidewall of the first gate structure; and a second transistor, the second transistor being in a second region, the second transistor comprising: a second gate structure extending longitudinally along the first direction, and the second gate spacer layer and the third gate spacer layer above the sidewalls of the second gate structure, wherein the first gate spacer layer, the second gate spacer layer and the third gate spacer layer have different compositions, The first gate spacer layer is in direct contact with the first gate structure, and the thickness of the first gate spacer layer is greater than the thickness of the second gate spacer layer and the third gate spacer layer. The dielectric constant of the first gate spacer layer is smaller than the dielectric constants of the second gate spacer layer and the third gate spacer layer. The third gate spacer layer is directly located on the second gate spacer layer in the second region.

2. The semiconductor device according to claim 1, wherein In the first region, the second gate spacer layer is disposed over the first gate spacer layer, and the third gate spacer layer is disposed over the second gate spacer layer.

3. The semiconductor device according to claim 1, wherein A width of the first gate structure along a second direction perpendicular to the first direction is greater than a width of the second gate structure along the second direction.

4. The semiconductor device according to claim 1, wherein: The first gate spacer layer includes silicon oxide.

5. The semiconductor device according to claim 1, wherein The second gate spacer layer includes silicon oxycarbon nitride.

6. The semiconductor device according to claim 1, wherein The third gate spacer layer includes silicon nitride.

7. The semiconductor device according to claim 1, wherein The third gate spacer layer includes silicon nitride.

8. The semiconductor device according to claim 1, in, The dielectric constant of the third gate spacer layer is greater than the dielectric constant of the second gate spacer layer.

9. The semiconductor device according to claim 8, wherein: The thickness of the third gate spacer layer is greater than the thickness of the second gate spacer layer.

10. A semiconductor device comprising: A first transistor, the first transistor is in a first region, the first transistor comprising: a first gate structure extending longitudinally along a first direction, and a first gate spacer, a second gate spacer, a third gate spacer, and a fourth gate spacer over a sidewall of the first gate structure; and a second transistor, the second transistor being in a second region, the second transistor comprising: a second gate structure extending longitudinally along the first direction, and the first gate spacer, the third gate spacer and the fourth gate spacer above the sidewalls of the second gate structure, an interlayer dielectric layer surrounding the first gate structure and the second gate structure; The fourth gate spacer layer, the third gate spacer layer and the second gate spacer layer have different compositions. wherein the third gate spacer layer is directly located on the first gate spacer layer in the second region, The interlayer dielectric layer is spaced from the first gate structure by a first distance along a second direction perpendicular to the first direction, which is equal to the total width of the first gate spacer layer, the second gate spacer layer, the third gate spacer layer and the fourth gate spacer layer. The interlayer dielectric layer is spaced from the second gate structure along the second direction by a second distance equal to the total width of the first gate spacer layer, the third gate spacer layer and the fourth gate spacer layer, The dielectric constant of the second gate spacer layer is smaller than the dielectric constants of the first gate spacer layer, the third gate spacer layer and the fourth gate spacer layer.

11. The semiconductor device according to claim 10, in, In the first region, the second gate spacer layer is disposed above the first gate spacer layer, the third gate spacer layer is disposed above the second gate spacer layer, and the fourth gate spacer layer is disposed above the third gate spacer layer, Wherein, the first area is an input / output area, and the second area is a core device area.

12. The semiconductor device according to claim 10, wherein: A width of the first gate structure along a direction perpendicular to the second direction is greater than a width of the second gate structure along the second direction.

13. The semiconductor device according to claim 10, wherein: The second gate spacer layer includes silicon oxide.

14. The semiconductor device according to claim 10, wherein: The first gate spacer layer and the third gate spacer layer include silicon oxycarbon nitride.

15. The semiconductor device according to claim 10, wherein The fourth gate spacer layer includes silicon nitride.

16. The semiconductor device according to claim 10, in, The first gate spacer layer has a first thickness, the second gate spacer layer has a second thickness, the third gate spacer layer has a third thickness, and the fourth gate spacer layer has a fourth thickness, The second thickness is greater than the first thickness, the third thickness and the fourth thickness.

17. A method of forming a semiconductor device, comprising: Over a substrate, forming a first active region in a first region of the substrate and forming a second active region in a second region of the substrate; forming a first dummy gate stack over the channel region of the first active region, and forming a second dummy gate stack over the channel region of the second active region; depositing a first spacer material layer over the first dummy gate stack, the source / drain regions of the first active region, the second dummy gate stack, and the source / drain regions of the second active region; Depositing a second spacer material layer on the first spacer material layer, while the first spacer material layer covers the source / drain region of the first active region and the source / drain region of the second active region; Etching back the second spacer material layer to expose the source / drain region of the first active region and the first spacer material layer above the source / drain region of the second active region; selectively removing the second spacer material layer in the second region; depositing a third spacer material layer over the first dummy gate stack and the second dummy gate stack after the selective removal; as well as etching the first spacer material layer, the second spacer material layer, and the third spacer material layer to form a first gate spacer along a sidewall of the first dummy gate stack and a second gate spacer along a sidewall of the second dummy gate stack, The first spacer material layer, the second spacer material layer and the third spacer material layer have different compositions, and the dielectric constant of the second spacer material layer is smaller than the dielectric constants of the first spacer material layer and the third spacer material layer.

18. The method according to claim 17, in, The first spacer material layer includes silicon oxycarbonitride, Wherein, the second spacer material layer comprises silicon oxide, and Wherein, the third spacer material layer includes silicon nitride.

19. The method according to claim 17, wherein: The etching back the second spacer material layer includes removing the second spacer material layer on a top-facing surface.

20. The method according to claim 17, wherein: Selectively removing the second spacer material layer includes: forming a photoresist mask to cover the first region and expose the second region; and The second region is etched using the photoresist mask as an etching mask.

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