Semiconductor device and method of operating the same

Abstract

A semiconductor device and an operating method thereof, wherein the semiconductor device includes a substrate, a first stack and a second stack. The substrate includes a doped region of a first doping concentration extending downward from an upper surface. The first stack is disposed on the upper surface and includes a first insulating layer and a first conductive layer, a first channel layer, a first storage layer, and a first conductive connector that are alternately stacked. The first conductive layer is configured to receive a first voltage. The first conductive connector is disposed on the first channel layer and has a second doping concentration. The second stack disposed on the first stack includes a second insulating layer and a second conductive layer, a second channel layer, a second storage layer, and a second conductive connector that are alternately stacked. The second conductive layer is configured to receive a second voltage. The second conductive connector is disposed on the second channel layer and configured to receive an erase voltage. The first conductive connector electrically connects the first and second channel layers. The first doping concentration is less than the second doping concentration.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and relates to a semiconductor device and an operating method thereof, and in particular to a semiconductor device and an operating method thereof in which a peripheral circuit part and an array part are vertically stacked. Background Art

[0002] Recently, in order to reduce the size of the chip, a semiconductor structure in which a memory array portion is vertically stacked on a peripheral circuit portion (i.e., a circuit under array (CUA)) has become increasingly popular. In this structure, the memory array portion generally includes a semiconductor substrate; a multi-layer stack structure formed by alternately stacking a plurality of insulating layers and polysilicon layers on the semiconductor substrate; a storage layer (e.g., a silicon oxynitride-oxide-nitride-oxide storage layer, an oxide-nitride-oxide-nitride-oxide (BE-SONOS) storage layer, or a charge trapping memory) and a polysilicon channel layer sequentially formed on the sidewalls of a through opening passing through the multi-layer stack structure; and a plurality of storage cells defined on the channel layer, the storage layer, and the polysilicon layer. The storage cell is electrically connected to the semiconductor substrate as a bottom common source line through the channel layer. The semiconductor substrate usually needs to be doped with a high concentration of N-type semiconductor dopants so that the bottom common source line can be used for a block erase operation of the memory array portion.

[0003] However, after the semiconductor device is manufactured through a process (such as a heat treatment process), the N-type dopants in the semiconductor substrate are easily diffused upward through the channel layer, thereby affecting the function of the ground selection line device adjacent to the substrate.

[0004] Therefore, there is a need to provide a vertical channel flash memory device to solve the problems faced by the prior art. Summary of the invention

[0005] The present invention relates to a semiconductor device. Since the N-type doping region of the substrate of the semiconductor device of the present invention has a relatively low doping concentration (for example, less than 5×10 18 cm -3 ), it is possible to reduce the situation where N-type dopants of the substrate of the semiconductor device are dissipated into the channel layer and affect the ground select line device (GSL device), thereby improving the utilization rate of the ground select line device.

[0006] According to one aspect of the present invention, a semiconductor device is provided. The semiconductor device includes a substrate, a first stack and a second stack. The substrate has an upper surface, wherein the substrate includes a doped region extending downward from the upper surface, and the doped region has a first doping concentration. The first stack is arranged on the upper surface, wherein the first stack includes a plurality of first insulating layers and a plurality of first conductive layers stacked alternately, a first channel layer, a first storage layer and a first conductive connection. The first conductive layer is configured to receive a first voltage. The first channel layer passes through the first stack. The first storage layer surrounds the first channel layer. The first conductive connection is arranged on the first channel layer and has a second doping concentration. The second stack is arranged on the first conductive connection and is located above the first stack, wherein the second stack includes a plurality of second insulating layers and a plurality of second conductive layers stacked alternately, a second channel layer, a second storage layer and a second conductive connection, wherein the second conductive layer is configured to receive a second voltage different from the first voltage. The second channel layer passes through the second stack, and the second storage layer surrounds the second channel layer. The second conductive connection is arranged on the second channel layer. The second conductive connection has a third doping concentration and is configured to receive an erase voltage, wherein the first conductive connection is electrically connected to the first channel layer and the second channel layer. The first doping concentration is less than the second doping concentration and the third doping concentration.

[0007] According to another aspect of the present invention, a method for operating a semiconductor device is provided. The method comprises the following steps. First, the semiconductor device is provided. The semiconductor device comprises a substrate, a first stack and a second stack. The substrate has an upper surface, wherein the substrate comprises a doped region extending downward from the upper surface, and the doped region has a first doping concentration. The first stack is disposed on the upper surface, wherein the first stack comprises a plurality of first insulating layers and a plurality of first conductive layers stacked alternately, a first channel layer, a first storage layer and a first conductive connection. The first channel layer passes through the first stack. The first storage layer surrounds the first channel layer. The first conductive connection is disposed on the first channel layer and has a second doping concentration. The second stack is disposed on the first conductive connection and is located above the first stack, wherein the second stack comprises a plurality of second insulating layers and a plurality of second conductive layers stacked alternately, a second channel layer, a second storage layer and a second conductive connection. The second channel layer passes through the second stack, and the second storage layer surrounds the second channel layer. The second conductive connection is disposed on the second channel layer. The second conductive connection has a third doping concentration, wherein the first conductive connection electrically connects the first channel layer and the second channel layer. The first doping concentration is less than the second doping concentration and the third doping concentration. Then, during an erase operation, an erase voltage is applied to the second conductive connection; during the erase operation, a first voltage is applied to the first conductive layer; and during the erase operation, a second voltage is applied to the second conductive layer; wherein the second voltage is greater than the first voltage.

[0008] In order to better understand the above and other aspects of the present invention, embodiments are given below and described in detail with reference to the accompanying drawings: BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 A cross-sectional view of a semiconductor device according to an embodiment of the present invention is shown.

[0010] Figure 2 A cross-sectional view is shown of a method for erasing a semiconductor device according to an embodiment of the present invention.

[0011] Figure 3 FIG. 4 is a waveform diagram showing an erase operation of a semiconductor device according to an embodiment of the present invention.

[0012]

Explanation of symbols

[0013] 10: Semiconductor devices

[0014] 100a: Peripheral circuit part

[0015] 100b: Array part

[0016] 101: Substrate

[0017] 101s: Upper surface

[0018] 101R: Doping region

[0019] 102: First storage layer

[0020] 103: First insulating column

[0021] 104: First channel layer

[0022] 105: Second insulating column

[0023] 106: Second storage layer

[0024] 108: Second channel layer

[0025] 111-113: first conductive layer

[0026] 116: First dielectric layer

[0027] 121~124: First insulation layer

[0028] 131-133: Second conductive layer

[0029] 136: Second dielectric layer

[0030] 141~144: Second insulation layer

[0031] 152: First conductive connection member

[0032] 154: Second conductive connection member

[0033] 156: Internal connection

[0034] 158: Overlay

[0035] C1: Metal Oxide Semiconductor Structure

[0036] M: Storage unit

[0037] S1: First stack

[0038] S2: Second stack

[0039] T G : Ground select line transistor

[0040] T S : Serial Select Line Transistor

[0041] V 1 : First voltage

[0042] V 2 : Second voltage

[0043] V B : Bit line voltage

[0044] V er : Erase voltage

[0045] V L : Voltage of the first conductive layer

[0046] V U : Second conductive layer voltage DETAILED DESCRIPTION

[0047] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0048] Figure 1 A cross-sectional view of a semiconductor device 10 according to an embodiment of the present invention is shown.

[0049] Please refer to Figure 1The semiconductor device 10 includes a peripheral circuit portion 100a and an array portion 100b, wherein the array portion 100b is located on the peripheral circuit portion 100a. The peripheral circuit portion 100a includes a complementary metal-oxide-semiconductor structure C1 and other suitable structures. The array portion 100b includes a substrate 101, a first stack S1, a second stack S2, an internal connection 156 and a cover layer 158. The second stack S2 is disposed on the first stack S1. The substrate 101 has an upper surface 101s and includes a doped region 101R extending downward from the upper surface 101s. The peripheral circuit portion 100a is disposed below the substrate 101. In some embodiments, the array portion 100b including the first stack S1 and the second stack S2 overlaps with the peripheral circuit portion 100a in the normal direction of the upper surface 101s.

[0050] The array portion 100b of the present invention exemplarily describes an embodiment of a gate-all-around (GAA) memory structure, but the present invention is not limited thereto. The array portion 100b of the present invention can be a non-volatile memory structure of any nitride-based memory material.

[0051] The first stack S1 is disposed on the upper surface 101s, wherein the first stack S1 includes a plurality of first insulating layers 121-124... and a plurality of first conductive layers 111-113... alternately stacked along the Z-axis direction. Figure 1 Only three first conductive layers 111-113 and four first insulating layers 121-124 in the first stack S1 are shown as examples, but the present invention is not limited thereto, and the first stack S1 may include more conductive layers and insulating layers. In this embodiment, the first insulating layers 121 and 124 are located at the bottom and top of the first stack S1, respectively, and the first insulating layer 121 is in direct contact with the substrate 101. The first conductive layers 111-113 are configured to receive a first voltage V 1 (Pictured on Figure 2). The first insulating pillar 103, the first channel layer 104 and the first storage layer 102 vertically pass through the first stack S1 (for example, along the Z-axis direction). The first channel layer 104 and the first storage layer 102 surround the first insulating pillar 103. The first storage layer 102 surrounds the first channel layer 104. The first storage layer 102 is located between the first channel layer 104, the first insulating layers 121-124 and the first conductive layers 111-113. The first conductive connection 152 is disposed on the first storage layer 102, the first insulating pillar 103 and the first channel layer 104, and is electrically in contact with the first channel layer 104. The first dielectric layer 116 is located between the first storage layer 102, the first insulating layers 121-124 and the first conductive layers 111-113, and may surround the first conductive layers 111-113.

[0052] The second stack S2 is disposed on the first stack S1 , wherein the second stack S2 includes a plurality of second insulating layers 141 - 144 . . . and a plurality of second conductive layers 131 - 133 . . . alternately stacked along the Z-axis direction. Figure 1 Only three second conductive layers 131 - 133 and four second insulating layers 141 - 144 in the second stack S2 are illustrated as examples, but the present invention is not limited thereto, and the second stack S2 may include more conductive layers and insulating layers.

[0053] In this embodiment, the second insulating layers 141 and 144 are located at the bottom and top of the second stack S2, respectively. The second conductive layers 131-133 are configured to receive a voltage different from the first voltage V 1 A second voltage V 2 (Pictured on Figure 2 In some embodiments, the second voltage V 2 Greater than the first voltage V 1 . The second insulating pillar 105, the second channel layer 108 and the second storage layer 106 vertically pass through the second stack S2 (for example, along the Z-axis direction). The second channel layer 108 and the second storage layer 106 surround the second insulating pillar 105. The second storage layer 106 surrounds the second channel layer 108. The second storage layer 106 is located between the second channel layer 108, the second insulating layers 141-144 and the second conductive layers 131-133. The second conductive connection 154 is disposed on the second insulating pillar 105, the second storage layer 106 and the second channel layer 108, and is electrically contacted with the second channel layer 108. The second conductive connection 154 is configured to receive an erase voltage V er (Pictured on Figure 2). The first conductive connection 152 is located between the first channel layer 104 and the second channel layer 108, and is electrically connected to the first channel layer 104 and the second channel layer 108. The second dielectric layer 136 is located between the second storage layer 106, the second insulating layers 141-144 and the second conductive layers 131-133, and can surround the second conductive layers 131-133. The interconnect 156 is electrically in contact with the second conductive connection 154. The cover layer 158 is located on the second stack S2.

[0054] In some embodiments, the substrate 101 is, for example, a silicon substrate or other suitable substrate, for example, an N-type doped polysilicon substrate. The first conductive connector 152 and the second conductive connector 154 are, for example, N-type doped polysilicon layers. The doped region 101R of the substrate 101, the first conductive connector 152, and the second conductive connector 154 may be doped with N-type dopants, respectively, and have a first doping concentration, a second doping concentration, and a third doping concentration, respectively. The first doping concentration may be different from the second doping concentration and the third doping concentration. For example, the first doping concentration may be less than 5×10 18 cm -3 The second doping concentration and the third doping concentration may be greater than 1×10 19 cm -3 In some embodiments, the first doping concentration is less than the second doping concentration and the third doping concentration, and the second doping concentration may be the same as the third doping concentration. In some embodiments, the second doping concentration may be less than the third doping concentration. Compared to the substrate, the substrate has a high concentration of N-type dopants (e.g., greater than 1×10 19 cm -3 ), since the first doping concentration of the doping region 101R of the substrate 101 in the present case is relatively low, the degree of N-type dopants dissipating into the first channel layer 104 can be reduced, thereby alleviating the situation in which the ground selection line device adjacent to the substrate 101 (for example, the transistor formed at the intersection between the first conductive layers 111, 112 and the first storage layer 102) is affected by the N-type dopants and is continuously turned on, thereby failing to function.

[0055] For example, the first conductive layer 111 closest to the substrate 101 among the first conductive layers 111-113 can be used as a ground select line (GSL), and the intersection of the first conductive layer 111 closest to the substrate 101, the first storage layer 102 and the first channel layer 104 can form a ground select line transistor T GThe second conductive layer 133 closest to the second conductive connection 154 among the second conductive layers 131-133 can be used as a string select line (SSL), and the intersection of the second conductive layer 133 closest to the second conductive connection 154, the second storage layer 106 and the second channel layer 108 can form a string select line transistor T S . The first conductive layer 112, 113 ... and the second conductive layer 131, 132 ... located between the ground selection line and the serial selection line can serve as a word line (WL). Each intersection between the first conductive layer 112, 113 ..., the second conductive layer 131, 132 ..., the first storage layer 102 and the second storage layer 106 can form a memory cell M for storing data. The memory cell M defined by the first conductive layer 112, 113 ..., the second conductive layer 131, 132 ..., the first storage layer 102, the second storage layer 106, the first channel layer 104 and the second channel layer 108 can be electrically coupled to a decoder (not shown) through a bit line (not shown), and the decoder is, for example, a row decoder or a column decoder.

[0056] Assuming that the first channel layer 104 adjacent to the first conductive layer 111 is disturbed by N-type dopants, the first conductive layer 112 above the first conductive layer 111 is used as the ground selection line, and the intersection between the first conductive layer 112, the first storage layer 102 and the first channel layer 104 is used as the ground selection line transistor; assuming that the first channel layer 104 adjacent to the first conductive layer 112 is disturbed by N-type dopants, the first conductive layer above the first conductive layer 112 is used as the ground selection line, and the intersection between the first conductive layer above the first conductive layer 112, the first storage layer 102 and the first channel layer 104 is used as the ground selection line transistor, and so on.

[0057] In some embodiments, the materials of the first insulating layers 121-124, the first conductive layers 111-113, the first channel layer 104, the first storage layer 104, and the first insulating pillar 103 may be the same or similar to the second insulating layers 141-144, the second conductive layers 131-133, the second channel layer 108, the second storage layer 106, and the second insulating pillar 105. The first insulating layers 121-124, the first insulating pillar 103, the second insulating layers 141-144, the second insulating pillar 105, and the capping layer 158 may be formed of oxide, such as silicon dioxide (SiO 2). The first conductive layers 111-113 and the second conductive layers 131-133 may be formed of a conductive material, such as tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), or other suitable materials. The first storage layer 102 and the second storage layer 106 may be composed of a composite layer (i.e., ONO layer) including a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer. For example, the first storage layer 102 and the second storage layer 106 may include a tunneling layer, a capture layer, and a barrier layer, respectively. The tunneling layer may include silicon oxynitride (SiON) and silicon dioxide (SiO 2 ) or other suitable materials. The capture layer may include silicon nitride or other suitable materials. The barrier layer may include silicon dioxide (SiO 2 ) or other suitable materials. The first dielectric layer 116 and the second dielectric layer 136 may include a high dielectric constant material (high k material), such as aluminum oxide (Al 2 O 3 ) or other suitable materials. The first channel layer 104 and the second channel layer 108 can be single crystal or polycrystalline silicon layers (can also be epitaxial growth layers).

[0058] The first channel layer 104 and the second channel layer 108 in the embodiment of the present invention are formed in different process steps respectively, and are not formed by forming a channel opening and filling the channel material in the channel opening through a single etching process. With the increase in the number of word lines required, a memory stack structure with a high aspect ratio needs to be formed, and the formation of vertical channels is increasingly challenged. If a vertical channel opening is formed through a single etching process, it is easy to cause process errors and fail to form a channel layer with good electrical connection effect. Therefore, compared with the comparative example of forming a channel opening through a single etching process, the present case forms the second channel layer 108 in the second stack S2 after forming the first channel layer 104 in the first stack S1 through different processes, which can improve the above-mentioned process problems, so that the first channel layer 104 and the second channel layer 108 can have good electrical connection with the substrate 101 through the first conductive connector 152.

[0059] Figure 2 A cross-sectional view is shown of a method for performing an erase operation of a semiconductor device 10 according to an embodiment of the present invention.

[0060] Please also refer to Figure 1 and Figure 2 During an erase operation, an erase voltage V is applied through a bit line (not shown). erThe first conductive connection 154 is connected to the second conductive connection 154, and the potential of the second channel layer 108 is increased by the band-to-band tunneling (BTB tunneling) mechanism, and then the holes are injected into the second storage layer 106. During this erase operation, the potential of the first conductive connection 152 is increased by the high potential of the second channel layer 108, and the potential of the first channel layer 104 is further increased by another band-to-band tunneling mechanism, and then the holes are injected into the first storage layer 102, wherein the first channel layer 104 and the second channel layer 108 respectively have a first internal voltage and a second internal voltage different from the first internal voltage. In some embodiments, the second internal voltage is greater than the first internal voltage. Since there is a voltage difference between the first internal voltage and the second internal voltage, it is necessary to apply the first voltage V during this erase operation. 1 to the first conductive layer 111-113..., and apply a voltage different from the first voltage V 1 A second voltage V 2 To the second conductive layers 131-133, the erasing speed of all memory cells M in the first stack S1 and the second stack S2 can be consistent. In addition, during the erasing operation, the substrate 101 and the first conductive connection 152 are floating. That is, no voltage is applied to the substrate 101 and the first conductive connection 152.

[0061] In some embodiments, the second voltage V 2 Greater than the first voltage V 1 ; Erase voltage V er Greater than the first voltage V 1 and the second voltage V 2 ; The first voltage V 1 The voltage difference between the first internal voltage and the second voltage V 2 In some embodiments, the second voltage V 2 With the first voltage V 1 The voltage difference between them is greater than 0 and less than 5V.

[0062] Compared to the comparative example of applying an erase voltage to the substrate, since the erase voltage Ver of an embodiment of the present invention is applied to the second conductive connection 154, the substrate 101 is floating, and the degree of diffusion of N-type dopants from the substrate 101 to the first channel layer 104 can be relatively reduced, so excessive waste of the use of ground selection line devices can be avoided. For example, in the comparative example of applying an erase voltage to the substrate, at least three ground selection line devices adjacent to the substrate cannot perform normal functions, while in the present invention, the number of unusable ground selection line devices can be reduced to less than 2. In this way, the semiconductor device 10 of the present invention can be used more efficiently.

[0063] Figure 3 FIG. 1 is a waveform diagram showing an erase operation of the semiconductor device 10 according to an embodiment of the present invention.

[0064] Please refer to Figure 3 , which illustrates the waveform deduction of incremental step pulse erase (ISPE) for the semiconductor device 10. The bit line voltage V B The erase voltage V is applied through the bit line (not shown). er When the voltage of the bit line reaches the second conductive connection 154, the voltage of the bit line develops different waveforms over time. L Indicates that the first voltage V is applied 1 When the voltage of the first conductive layer 111-113 in the first stack S1 is applied, the voltage of the first conductive layer 111-113 develops different waveforms over time. U Indicates that the second voltage V is applied 2 When the second conductive layers 131-133 in the second stack S2 are connected, the voltages of the second conductive layers 131-133 develop different waveforms over time. Figure 3 As the result shows, with the increase of time, the erase voltage V er gradually increases (for example, by 1V every 2 milliseconds), the first voltage V 1 Maintain 0V, the second voltage V 2 Then maintain 2V.

[0065] According to the above embodiments, the present invention provides a semiconductor device and an operation method thereof. The semiconductor device includes a substrate, a first stack and a second stack. The substrate has an upper surface, wherein the substrate includes a doped region extending downward from the upper surface, and the doped region has a first doping concentration. The first stack is disposed on the upper surface, wherein the first stack includes a plurality of first insulating layers and a plurality of first conductive layers stacked alternately, a first channel layer, a first storage layer and a first conductive connection. The first conductive layer is configured to receive a first voltage. The first channel layer passes through the first stack. The first storage layer surrounds the first channel layer. The first conductive connection is disposed on the first channel layer and has a second doping concentration. The second stack is disposed on the first conductive connection and is located above the first stack, wherein the second stack includes a plurality of second insulating layers and a plurality of second conductive layers stacked alternately, a second channel layer, a second storage layer and a second conductive connection, wherein the second conductive layer is configured to receive a second voltage different from the first voltage. The second channel layer passes through the second stack, and the second storage layer surrounds the second channel layer. The second conductive connection is disposed on the second channel layer. The second conductive connection has a third doping concentration and is configured to receive an erase voltage, wherein the first conductive connection is electrically connected to the first channel layer and the second channel layer. The first doping concentration is less than the second doping concentration and the third doping concentration.

[0066] Compared to the comparative example in which the substrate has heavily doped N-type dopants, since the N-type doping region of the substrate of the semiconductor device of the present invention has a lower doping concentration, the degree of N-type dopants dissipating from the substrate to the channel layer can be reduced, so the situation where the ground selection line device is affected can be improved. In addition, since the erase voltage is applied to the second conductive connection during the erase operation instead of being applied to the substrate, the ground selection line device adjacent to the substrate can be alleviated from being affected by the N-type dopants and continuously turned on, thereby failing to function, thereby improving the utilization rate of the ground selection line device in the semiconductor device. Furthermore, by applying different first voltages and second voltages to the first conductive layer and the second conductive layer respectively, the situation where the internal voltages of the first channel layer and the second channel layer are different can be overcome, so that the erase speeds of all storage cells in the same series in the first stack and the second stack can be consistent.

[0067] In summary, although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. A person skilled in the art with common knowledge in the technical field to which the present invention belongs may make various modifications and improvements without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

[0068] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A substrate having an upper surface, wherein the substrate includes a doped region extending downward from the upper surface, the doped region having a first doping concentration; A first stack is disposed on the upper surface, wherein the first stack comprises: A plurality of first insulating layers and a plurality of first conductive layers are alternately stacked, wherein the first conductive layers are configured to receive a first voltage; a first channel layer passing through the first stack; a first storage layer surrounding the first channel layer; and a first conductive connection element, disposed on the first channel layer and having a second doping concentration; a second stack disposed on the first stack, wherein the second stack comprises: A plurality of second insulating layers and a plurality of second conductive layers are alternately stacked, wherein the second conductive layers are configured to receive a second voltage different from the first voltage; a second channel layer passing through the second stack; a second storage layer surrounding the second channel layer; and a second conductive connection disposed on the second channel layer, the second conductive connection having a third doping concentration and configured to receive an erase voltage, wherein the first conductive connection electrically connects the first channel layer and the second channel layer; The first doping concentration is smaller than the second doping concentration and the third doping concentration.

2. The semiconductor device according to claim 1, wherein the first doping concentration is less than 5×10 18 cm -3 . The semiconductor device according to claim 1 , wherein the second voltage is greater than the first voltage. 4 . The semiconductor device according to claim 1 , further comprising a peripheral circuit portion disposed under the substrate.

5. A method for operating a semiconductor device, characterized in that: include: A semiconductor device is provided, comprising: A substrate having an upper surface, wherein the substrate includes a doped region extending downward from the upper surface, the doped region having a first doping concentration; A first stack is disposed on the upper surface, wherein the first stack comprises: A plurality of first insulating layers and a plurality of first conductive layers stacked alternately; a first channel layer passing through the first stack; a first storage layer surrounding the first channel layer; and a first conductive connection element, disposed on the first channel layer and having a second doping concentration; a second stack disposed on the first stack, wherein the second stack comprises: A plurality of second insulating layers and a plurality of second conductive layers stacked alternately; a second channel layer passing through the second stack; a second storage layer surrounding the second channel layer; and a second conductive connection member disposed on the second channel layer, the second conductive connection member having a third doping concentration, wherein the first conductive connection member electrically connects the first channel layer and the second channel layer; wherein the first doping concentration is less than the second doping concentration and the third doping concentration; applying an erase voltage to the second conductive connection during an erase operation; applying a first voltage to the first conductive layers during the erase operation; and applying a second voltage to the second conductive layers during the erase operation; The second voltage is greater than the first voltage.

6. The method for operating a semiconductor device according to claim 5, wherein the first doping concentration is less than 5×10 18 cm -3 . 7 . The operating method of the semiconductor device according to claim 5 , wherein a voltage difference between the second voltage and the first voltage is less than 5V.

8. The method for operating a semiconductor device according to claim 5, wherein during the erase operation, the substrate is floating. 9 . The method for operating a semiconductor device according to claim 5 , wherein during the erase operation, the first conductive connection is floating. 10 . The operating method of the semiconductor device according to claim 5 , wherein during the erase operation, the erase voltage is greater than the first voltage and the second voltage.

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