Image sensor and method for manufacturing the same

Abstract

A method for manufacturing an image sensor includes at least the following steps: forming a material layer on an image capture chip; forming a patterned mask layer on the material layer, wherein a pattern density of the patterned mask layer changes from a central area of ​​the patterned mask layer to a peripheral area of ​​the patterned mask layer; and grinding the material layer using the patterned mask layer as a mask to form a lens layer including a single lens portion on the image capture chip.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to an image sensor and a method for manufacturing the same. Background Art

[0002] Integrated circuits (ICs) with image sensors are used in a variety of modern electronic devices, such as cameras and cell phones. In recent years, complementary metal oxide semiconductor (CMOS) image sensors have become widely used, largely replacing charge-coupled device (CCD) image sensors. Compared with CCD sensors, CMOS image sensors have many advantages, such as low operating voltage, low power consumption, compatibility with logic circuit systems, random access, and low cost. Some types of CMOS image sensors include front-side illuminated (FSI) image sensors and back-side illuminated (BSI) image sensors. Summary of the invention

[0003] According to an embodiment of the present disclosure, a method for manufacturing an image sensor includes: forming a material layer above an image capture chip; forming a patterned mask layer on the material layer, wherein a pattern density of the patterned mask layer changes from a central area of ​​the patterned mask layer to a peripheral area of ​​the patterned mask layer; and grinding the material layer using the patterned mask layer as a mask to form a lens layer on the image capture chip, the lens layer including a single lens portion.

[0004] According to an embodiment of the present disclosure, a method for manufacturing an image sensor includes: forming a material layer on an image capture chip; forming a patterned mask layer on the material layer; and grinding the patterned mask layer and the material layer to form a lens layer on the image capture chip, the lens layer including a single lens portion, wherein a central area of ​​the patterned mask layer and a peripheral area of ​​the patterned mask layer are ground at different grinding rates.

[0005] According to an embodiment of the present disclosure, an image sensor includes an image capture chip and a lens layer. The image capture chip includes an optical sensing area. The lens layer includes a single lens portion, the single lens portion covers the optical sensing area of ​​the image capture chip, an orthogonal projection of the single lens portion projected onto the image capture chip overlaps with the optical sensing area, and an optical axis of the single lens portion is substantially aligned with a center of the optical sensing area. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present invention can be best understood by reading the following detailed description in conjunction with the accompanying drawings. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figures 1 to 4 as well as Figures 6 to 8 are schematic cross-sectional views illustrating various stages of a method of manufacturing an image sensor according to some embodiments of the present invention.

[0008] FIG. 5A to FIG. 5D Describe some various embodiments according to the present invention Figure 4 Various top views of a patterned mask layer are shown.

[0009] Figures 9 to 12 are schematic cross-sectional views illustrating various stages of a method of manufacturing an image sensor according to some embodiments of the present invention.

[0010] Figure 13 to Figure 15 are schematic cross-sectional views illustrating various stages of a method of manufacturing an image sensor according to some embodiments of the present invention.

[0011] Figure 16 to Figure 18 are schematic cross-sectional views illustrating various stages of a method of manufacturing an image sensor according to some embodiments of the present invention. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples to implement the different features of the provided subject matter. Specific examples of components and arrangements are described below to make the present invention concise. Of course, these are only examples and are not intended to be limiting. For example, in the following description, a first feature formed on or formed on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature cannot be in direct contact. In addition, the present invention may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not essentially specify the relationship between the various embodiments and / or configurations discussed.

[0013] Additionally, for ease of description, spatially relative terms, such as "beneath," "below," "lower," "above," "upper," etc., may be used herein to describe the relationship of one element or feature to another element or feature, as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0014] Figures 1 to 4 as well as Figures 6 to 8 2 is a schematic cross-sectional view illustrating various stages of a method of manufacturing an image sensor according to some embodiments of the present invention. The image sensor may be, for example, a CMOS image sensor and / or an integrated circuit (IC) die or chip.

[0015] refer to Figure 1 , a semiconductor substrate 110 is provided, and a plurality of isolation structures 120 are formed in the semiconductor substrate 110 to define a plurality of active regions in the semiconductor substrate 110. Specifically, the semiconductor substrate 110 has a first surface 110a and a second surface 110b opposite to the first surface 110a. The plurality of isolation structures 120 extend from the first surface 110a of the semiconductor substrate 110 toward the inside of the semiconductor substrate 110. In other words, the isolation structure 120 is formed to be embedded in the semiconductor substrate 110. In some embodiments, the isolation structure 120 does not penetrate the semiconductor substrate 110. In a certain embodiment, the isolation structure 120 may be, for example, a shallow trench isolation (STI) structure. The formation process of the isolation structure 120 may be obtained by the following steps. First, a plurality of shallow trenches having a predetermined depth are formed in the semiconductor substrate 110 by, for example, a photolithography / etching process or other suitable patterning process. Then, a dielectric material is deposited in the trench. Subsequently, a portion of the dielectric material is removed (for example, by grinding, etching, or a combination thereof) to form the isolation structure 120 (i.e., the STI structure).

[0016] In some embodiments, the material of the semiconductor substrate 110 includes silicon, and the material of the isolation structure 120 (i.e., the STI structure) includes silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or combinations thereof. In some alternative embodiments, the semiconductor substrate 110 may be made of: some other suitable elemental semiconductors, such as diamond or germanium; suitable compound semiconductors, such as gallium arsenide, silicon carbide, indium arsenide, or indium phosphide; or suitable alloy semiconductors, such as silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide.

[0017] like Figure 1 As shown in , a plurality of photosensitive devices 130 are formed in a plurality of active regions defined in a semiconductor substrate 110. The photosensitive device 130 is configured to absorb radiation incident on the photosensitive device 130 to generate an electrical signal. In some embodiments, the photosensitive device 130 is formed by ion implantation on a first surface 110a of the semiconductor substrate 110. For example, the photosensitive device 130 is a photodiode. Each of the plurality of photodiodes may include at least one p-type doping region, at least one n-type doping region, and a pn junction formed between the p-type doping region and the n-type doping region. In detail, when the semiconductor substrate 110 is a p-type substrate, an n-type dopant (e.g., phosphorus or arsenic) may be doped into the active region of the semiconductor substrate 110 to form an n-type well, and the resulting pn junction in the active region is capable of performing an image sensing function. Similarly, when the semiconductor substrate 110 is an n-type substrate, a p-type dopant (e.g., boron or BF2) may be doped into the active region of the semiconductor substrate 110 to form a p-type well, and the resulting pn junction in the active region is capable of performing an image sensing function. A detailed description of the ion implantation process for forming an n-type doped region (well) or a p-type doped region (well) is omitted herein. When a reverse bias is applied to the pn junction of the photosensitive device 130, the pn junction is sensitive to incident light. The light received or detected by the photosensitive device 130 is converted into a photocurrent to generate an analog signal representing the intensity of the photocurrent. In some alternative embodiments, the photosensitive device 130 may be other optoelectronic elements capable of performing an image sensing function. For example, the photosensitive device 130 may include a pin junction, in which an intrinsic semiconductor region may be arranged between an n-type doped region and a p-type doped region and contact the n-type doped region and the p-type doped region.

[0018] In some embodiments, one or more transistors 140 may be formed on the first surface 110a of the semiconductor substrate 110. In some embodiments, the one or more transistors 140 may be, for example, transfer gate transistors configured to selectively transfer charges accumulated in the photosensitive device 130 from the photosensitive device 130 for readout. In some embodiments, other transistors (not shown) may also be formed on the first surface 110a of the semiconductor substrate 110, such as a source-follower transistor, a row select transistor, a reset transistor, or a combination thereof. In addition, a logic circuit may be formed on the semiconductor substrate 110. The logic circuit is designated to receive and process signals originating from the photosensitive device 130. For example, the logic circuit includes conductive traces and NAND / NOR gates. The material of the logic circuit may include, but is not limited to, metal and polysilicon. It should be noted that the location of the logic circuit is not limited to being located on the semiconductor substrate 110. In some alternative embodiments, the logic circuit may be fabricated on other elements (e.g., Figure 2 , and the explanation will be discussed later.

[0019] like Figure 1As shown in FIG. 1 , an interconnect layer 150 is formed on a first surface 110 a of a semiconductor substrate 110. The interconnect layer 150 is disposed on and electrically connected to the photosensitive device 130 so that a signal generated from the photosensitive device 130 can be transmitted to other components for processing. For example, the interconnect layer 150 transmits an analog signal generated from the photosensitive device 130 to other components (e.g., an analog-to-digital converter (ADC)) for processing. In a certain embodiment, the interconnect layer 150 includes alternating stacked conductive trace layers and interlayer dielectric layers, but this is not intended to be limiting in the present invention. In some alternative embodiments, some of the aforementioned layers within the interconnect layer 150 may be omitted as long as the analog signal generated from the photosensitive device 130 can be transmitted to other components for processing. Suitable materials for the conductive trace layer include conductors, such as metals. Note that the conductive trace layer may be made of the same material or different materials, and may include a single metal trace layer or multiple metal trace layers. In the case where there are multiple metal trace layers in the conductive trace layer, an interlayer dielectric layer (ILD) is inserted between each metal trace layer. The material of the ILD layer includes silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), spin-on glass (SOG), fluorinated silica glass (FSG), carbon-doped silicon oxide (e.g., SiCOH), polyimide and / or a combination thereof.

[0020] refer to Figure 1 and Figure 2, the semiconductor substrate 110 on which the interconnect layer 150 is formed may be flipped over and bonded to the support substrate 200. In some embodiments, the semiconductor substrate 110 and the support substrate 200 may be silicon substrates or substrates made of other suitable materials. The material of the semiconductor substrate 110 may be the same as that of the support substrate 200. For example, the semiconductor substrate 110 and the support substrate 200 are semiconductor wafers, and a wafer-level bonding process may be performed to flip the semiconductor substrate 110 and bond the interconnect layer 150 formed on the semiconductor substrate 110 to the support substrate 200. After the semiconductor substrate 110 is bonded to the support substrate 200, the interconnect layer 150 is located between the support substrate 200 and the photosensitive device 130. In some embodiments, the support substrate 200 may be a blank wafer for enhancing the mechanical strength of the device while serving as a protective layer. In some alternative embodiments, the support substrate 200 may include metal traces for signal transmission. For example, as described above, instead of forming the logic circuit on the semiconductor substrate 110 , the logic circuit may be formed in and / or on the supporting substrate 200 in some embodiments.

[0021] In some embodiments, a thinning process may be performed on the semiconductor substrate 110 so that the semiconductor substrate 110 is thinned until a thinned semiconductor substrate 110' is formed. In some embodiments, a backside grinding process is performed on the semiconductor substrate 110 to reduce the thickness of the semiconductor substrate 110. In other words, the back side (i.e., the second surface 110b) of the semiconductor substrate 110 opposite to the interconnect layer 150 is ground. For example, in some embodiments, the backside grinding is achieved by chemical mechanical polishing (CMP), and in some alternative embodiments, the backside grinding is achieved by chemical etching. The present invention is not limited to the grinding method, as long as the semiconductor substrate 110 is ground or removed to present a desired thickness.

[0022] The support substrate 200 provides sufficient structural support (eg, rigidity) to facilitate the thinning process of the semiconductor substrate 110. Due to the support of the support substrate 200, the photosensitive device 130 in the thinned semiconductor substrate 110' is not damaged during the thinning process of the semiconductor substrate 110.

[0023] refer to Figure 3In order to enhance the electrical isolation between the photosensitive devices 130 and minimize the leakage, a plurality of isolation structures 160 may be formed in the thinned semiconductor substrate 110'. For example, the isolation structure 160 is a deep trench isolation (DTI) structure. The aspect ratio of the isolation structure 160 may be greater than the aspect ratio of the isolation structure 120. The isolation structure 160 may be substantially aligned with the isolation structure 120. The process of forming the isolation structure 160 (i.e., DTI) is similar to the process of forming the isolation structure 120, and therefore a detailed description of the process of forming the isolation structure 160 is omitted here.

[0024] In some embodiments, after forming the isolation structure 160, a planarization layer 170 having a flat top surface may be formed to cover the surface 110b of the thinned semiconductor substrate 110' and the isolation structure 160. For example, the material of the planarization layer 170 includes silicon oxide or other suitable dielectric materials. In some alternative embodiments, the formation of the planarization layer 170 may be omitted. In addition, in some embodiments, a plurality of color filters (e.g., red filter, blue filter, green filter, etc., not shown) may be formed on the planarization layer 170. The color filters are respectively configured to transmit incident radiation of a specific wavelength and block incident radiation of other wavelengths. For example, the red filter filters incident radiation and allows red light to pass through, so that the photosensitive device 130 located below the red filter receives red light; the green filter filters incident radiation and allows green light to pass through, so that the photosensitive device 130 located below the green filter receives green light; and the blue filter filters incident radiation and allows blue light to pass through, so that the photosensitive device 130 located below the blue filter receives blue light. In some embodiments, the red filter, the green filter, and the blue filter may be formed of different photoresist materials, and the photoresist materials used to form the red filter, the green filter, and the blue filter may be patterned, for example, by a photolithography process.

[0025] like Figure 3 As shown in FIG. 1 , an image capture chip 100 including an optical sensing area SA is illustrated. The image capture chip 100 includes a plurality of sensing pixels P arranged in an array. The sensing pixels P are located within the optical sensing area SA of the image capture chip 100. Each of the plurality of sensing pixels P includes a photosensitive device 130. It should be noted that for illustration purposes, Figure 3 Only one image capture chip 100 is shown in FIG. However, before the semiconductor substrate (thinned semiconductor substrate 110 ′) is subjected to a singulation process, a plurality of image capture chips 100 in the semiconductor substrate (thinned semiconductor substrate 110 ′) may be connected to each other.

[0026] Then, a lens layer 300 ( Figure 8 ), the lens layer 300 is configured to direct incident radiation toward the photosensitive device 130. Figures 4 to 8 The manufacturing of the lens layer 300 is described in detail.

[0027] refer to Figure 4 , a material layer 210 is formed on the planarization layer 170, a liner layer 220 (or a buffer layer) is formed on the material layer 210, and a patterned mask layer 230 is formed on the liner layer 220. In some embodiments, the material layer 210 is made of a high refractive index material. In some embodiments, the refractive index of the material layer 210 may be greater than the refractive index of the dielectric layer of the interconnect layer 150. For example, the refractive index of the material layer 210 may be in the range of about 1.5 to about 2.5. In some embodiments, the material of the material layer 210 may be similar to or the same as the material of the patterned mask layer 230, and the material of the liner layer 220 may be different from the material of the material layer 210 and the material of the patterned mask layer 230. In some embodiments, the material of the material layer 210 and the material of the patterned mask layer 230 may be, for example, silicon nitride (SiN x ) or other suitable materials; and the material of the liner layer 220 may be, for example, silicon oxide or other suitable materials. However, in some alternative embodiments, the material of the material layer 210 may be different from the material of the patterned mask layer 230. In some embodiments, the patterned mask layer 230 is patterned by, for example, a photolithography / etching process or other suitable patterning process.

[0028] In some embodiments, the pattern density of the patterned mask layer 230 located directly above an image capture chip 100 varies from a central area of ​​the patterned mask layer 230 to a peripheral area of ​​the patterned mask layer 230 , wherein FIG. 5A to FIG. 5D Describe some various embodiments according to the present invention Figure 4 1 and 2. Various top views of the patterned mask layer 230 are shown. The pattern density of the patterned mask layer 230 is defined as the ratio of the area of ​​the mask pattern (e.g., light shielding pattern) of the patterned mask layer 230 in a specific region to the area of ​​the specific region. In some embodiments, the pattern density of the patterned mask layer 230 located directly above one image capture chip 100 changes linearly from the central region of the patterned mask layer 230 to the peripheral region of the patterned mask layer 230. In some embodiments, the pattern density of the patterned mask layer 230 located directly above one image capture chip 100 changes nonlinearly from the central region of the patterned mask layer 230 to the peripheral region of the patterned mask layer 230.

[0029] like Figure 4 and FIG. 5A to FIG. 5DAs shown in , the pattern density of the patterned mask layer 230 decreases from the central region of the patterned mask layer 230 to the peripheral region of the patterned mask layer 230. In other words, the patterned mask layer 230 is denser in the central region than in the peripheral region. Figure 5A In the embodiment, the patterned mask layer 230 may include a first mask pattern 232 and a second mask pattern 234 surrounding the first mask pattern 232. The shape of the first mask pattern 232 may be a rectangular pattern from a top view, and the shape of the second mask pattern 234 may be a rectangular frame pattern from a top view. In some embodiments, the width of the first mask pattern 232 may be greater than the width of the second mask pattern 234. In some embodiments, the patterned mask layer 230 may also include another mask pattern (not shown) surrounding the first mask pattern 232 and the second mask pattern 234, wherein the width of the other mask pattern may be smaller than the width of the second mask pattern 234, and / or the gap between the other mask pattern and the second mask pattern 234 may be wider than the gap between the second mask pattern 234 and the first mask pattern 232. The present invention does not limit the number of mask patterns. Figure 5B In the embodiment, the patterned mask layer 230 may be similar to Figure 5A The patterned mask layer 230 in FIG. 2 is a patterned mask layer 230, but the shape of the first mask pattern 232 may be a circular pattern from a top view angle, and the shape of the second mask pattern 234 may be a circular ring pattern from a top view angle. The present invention does not limit the shape of the mask pattern. Figure 5C In the embodiment, the patterned mask layer 230 may be similar to Figure 5A The patterned mask layer 230 in FIG. 2 is not limited to the patterned mask layer 230, but each of the first mask pattern 232 and the second mask pattern 234 may be formed by a plurality of separated dot patterns. Figure 5D In the embodiment, the patterned mask layer 230 may be similar to Figure 5B The patterned mask layer 230 in the embodiment of the present invention is a first mask pattern 232, but each of the first mask pattern 232 and the second mask pattern 234 is formed by a plurality of separated dot patterns. The present invention does not limit the pattern of the patterned mask layer 230, as long as the patterned mask layer 230 is polished to present a desired top profile, and the detailed explanation will be discussed later.

[0030] refer to Figures 6 to 8 , the patterned mask layer 230, the pad layer 220, and the material layer 210 are ground. In some embodiments, the patterned mask layer 230 is used as a grinding mask to grind the material layer 210 to form a lens layer 300 including a single lens portion 310 on the image capture chip 100. In some embodiments, the patterned mask layer 230, the pad layer 220, and the material layer 210 are ground using the same slurry. For illustration purposes, the Figure 6 and Figure 720 is a middle view of the polishing. In some embodiments, since the pattern density of the patterned mask layer 230 changes from the central area of ​​the patterned mask layer 230 to the peripheral area of ​​the patterned mask layer 230, the central area of ​​the patterned mask layer 230 and the peripheral area of ​​the patterned mask layer 230 may be polished at different polishing rates due to a loading effect. For example, the central area of ​​the patterned mask layer 230 is polished slower than the peripheral area of ​​the patterned mask layer 230.

[0031] like Figure 6 As shown in , since the pattern density of the patterned mask layer 230 decreases from the central area of ​​the patterned mask layer 230 to the peripheral area of ​​the patterned mask layer 230, the central area of ​​the patterned mask layer 230 is ground at a first grinding rate, and the peripheral area of ​​the patterned mask layer 230 is ground at a second grinding rate that is greater than the first grinding rate. In other words, during the grinding process, the grinding rate (removal rate) of the peripheral area of ​​the patterned mask layer 230 is higher than the grinding rate (removal rate) of the central area of ​​the patterned mask layer 230, so that the peripheral area of ​​the patterned mask layer 230 is more recessed than the central area of ​​the patterned mask layer 230, and the top surface of the patterned mask layer 230 can become rounded convex. In addition, in some embodiments, the peripheral area of ​​the pad layer 220 can be ground earlier than the central area of ​​the pad layer 220. In some embodiments, the peripheral area of ​​the pad layer 220 and the central area of ​​the pad layer 220 can be ground at the same grinding rate. Therefore, as Figure 7 As shown in , when the patterned mask layer 230 is ground away, the peripheral area of ​​the liner layer 220 is also recessed more than the central area of ​​the liner layer 220. Figure 8 As shown in FIG. 1 , the pad layer 220 is ground away, and a lens layer 300 including a single lens portion 310 is formed on the image capture chip 100 , wherein the single lens portion 310 of the lens layer 300 has a curved and convex light incident surface 310 a .

[0032] In some embodiments, the curvature of the curved and convex light incident surface 310a of the single lens portion 310 may be determined according to the pattern design of the patterned mask layer 230 and the grinding rates of the material layer 210, the pad layer 220, and the patterned mask layer 230. That is, the predetermined curvature of the curved and convex light incident surface 310a of the single lens portion 310 may be obtained by the pattern design of the patterned mask layer 230 and by appropriately selecting the materials of the plurality of layers (the material layer 210, the pad layer 220, and the patterned mask layer 230). In some embodiments, during the grinding process, the pad layer 220 may be ground at a grinding rate greater than the grinding rate of the peripheral region of the patterned mask layer 230 and / or the grinding rate of the central region of the patterned mask layer 230. In some embodiments, during the grinding process, the pad layer 220 may be ground at a grinding rate substantially equal to the grinding rate of the peripheral region of the patterned mask layer 230 or the grinding rate of the central region of the patterned mask layer 230. In some embodiments, during the polishing process, the liner layer 220 may be polished at a polishing rate that is lower than a polishing rate of a peripheral region of the patterned mask layer 230 and / or a polishing rate of a central region of the patterned mask layer 230 . For example, in some embodiments, the pad layer 220 may be ground at a grinding rate greater than both the grinding rate of the peripheral region of the patterned mask layer 230 and the grinding rate of the central region of the patterned mask layer 230; in some embodiments, the pad layer 220 may be ground at a grinding rate greater than the grinding rate of the central region of the patterned mask layer 230 and substantially equal to the grinding rate of the peripheral region of the patterned mask layer 230; in some embodiments, the pad layer 220 may be ground at a grinding rate between the grinding rate of the peripheral region of the patterned mask layer 230 and the grinding rate of the central region of the patterned mask layer 230; in some embodiments, the pad layer 220 may be ground at a grinding rate less than the grinding rate of the peripheral region of the patterned mask layer 230 and substantially equal to the grinding rate of the central region of the patterned mask layer 230; and in some embodiments, the pad layer 220 may be ground at a grinding rate less than both the grinding rate of the peripheral region of the patterned mask layer 230 and the grinding rate of the central region of the patterned mask layer 230.

[0033] In some embodiments, during the grinding process, the material layer 210 may be ground at a grinding rate greater than the grinding rate of the pad layer 220. In some embodiments, during the grinding process, the material layer 210 may be ground at a grinding rate substantially equal to the grinding rate of the pad layer 220. In some embodiments, during the grinding process, the material layer 210 may be ground at a grinding rate less than the grinding rate of the pad layer 220.

[0034] refer to Figure 8In some embodiments, after the lens layer 300 is formed by a series of wafer-level processes (e.g., film deposition, film patterning, grinding, etc.), a singulation process may be performed to obtain at least one image sensor 10. In some embodiments, the singulation process may be a wafer sawing process including mechanical sawing or laser cutting. In some embodiments, after the singulation process, the manufacturing process of the image sensor 10 is completed.

[0035] like Figure 8 As shown in , the image sensor 10 includes an image capture chip 100 and a lens layer 300 formed on the image capture chip 100. The lens layer 300 includes a single lens portion 310 covering an optical sensing area SA of the image capture chip 100, wherein an orthogonal projection of the single lens portion 310 onto the image capture chip 100 overlaps with the optical sensing area SA. In other words, the single lens portion 310 is disposed above the image capture chip 100 and completely covers the optical sensing area SA of the image capture chip 100. In some embodiments, the optical axis OA of the single lens portion 310 may be substantially aligned with the center of the optical sensing area SA. In other words, the optical axis OA of the single lens portion 310 may be substantially aligned with the center of the plurality of pixels P. In some embodiments, the sidewall 100s of the image capture chip 100 is substantially aligned with the sidewall 300s of the lens layer 300. In other words, the lens layer 300 is a chip-level lens formed on the image capture chip 100. In some embodiments, the bottom surface 300 b of the lens layer 300 may be in contact with a surface (eg, the backside surface 100 b ) of the image capture chip 100 .

[0036] In some embodiments, the lens layer 300 may further include a base portion 320. The single lens portion 310 is located on the base portion 320 and protrudes upward from the base portion 320. The single lens portion 310 partially covers the base portion 320, and the base portion 320 completely covers the image capture chip 100. In some embodiments, the base portion 320 includes: a flat bottom surface 300b in contact with a surface (e.g., backside surface 100b) of the image capture chip 100; and a sidewall 300s substantially aligned with the sidewall 100s of the image capture chip 100. However, in some alternative embodiments, the lens layer 300 may not include the base portion 320, and the single lens portion 310 may completely cover the image capture chip 100 and include: a flat bottom surface 300b in contact with a surface (e.g., backside surface 100b) of the image capture chip 100; and a sidewall 300s substantially aligned with the sidewall 100s of the image capture chip 100. In this case, since the lens layer 300 includes only the single lens portion 310 and does not include the base portion 320, the maximum thickness T1 of the lens layer 300 is substantially equal to the maximum thickness T2 of the single lens portion 310. In some embodiments, the maximum thickness T1 of the lens layer 300 may be in the range of about 1 micrometer to about 100 micrometers. In some embodiments, the maximum thickness T2 of the single lens portion 310 may be in the range of about 1 micrometer to about 100 micrometers.

[0037] like Figure 8 As shown in FIG. 1 , the lens layer 300 is formed on the back surface 100 b of the image capture chip 100 and is in contact with the back surface 100 b of the image capture chip 100 . In other words, Figure 8 The image sensor 10 in the embodiment is a backside illuminated (BSI) image sensor capable of capturing incident light from a backside surface. However, in some alternative embodiments, the image sensor 10 may be a frontside illuminated (FSI) image sensor capable of capturing incident light from a frontside surface, and the lens layer 300 may be formed on and in contact with the frontside surface of the image capture chip 100.

[0038] Since the lens layer 300 is directly formed on the image capture chip 100 and contacts the image capture chip 100, in some embodiments, it is not necessary to assemble an external lens module thicker than the image capture chip 100 on the image capture chip 100. In some embodiments, the single lens portion 310 of the lens layer 300 can partially or completely replace the external lens module, and the manufacturing process of the image sensor 10 can be simplified. The manufacturing cost can be reduced. In addition, the image sensor 10 can be more compact.

[0039] Figures 9 to 12 are schematic cross-sectional views illustrating various stages of a method of manufacturing an image sensor according to some embodiments of the present invention. Figures 9 to 12The manufacturing method of the image sensor 20 described in Figures 1 to 8 Therefore, the manufacturing method of the image sensor 10 described in the above is omitted here. Figures 9 to 12 The difference between the two manufacturing methods is that Fig. 9 , the pattern density of the patterned mask layer 240 increases from the central area of ​​the patterned mask layer 240 to the peripheral area of ​​the patterned mask layer 240. In other words, the patterned mask layer 240 is denser in the peripheral area than in the central area. Therefore, the single lens portion 410 of the lens layer 400 has a curved and concave light incident surface 410a, such as Fig.12 as shown in .

[0040] refer to Figure 10 to Figure 12 , the patterned mask layer 240, the liner layer 220, and the material layer 210 are ground. In some embodiments, the material layer 210 is ground using the patterned mask layer 240 as a grinding mask to form a lens layer 400 including a single lens portion 410 on the image capture chip 100. In some embodiments, the patterned mask layer 240, the liner layer 220, and the material layer 210 are ground using the same slurry. For illustration purposes, Fig.10 and Fig.11 For example, the central region of the patterned mask layer 240 is ground faster than the peripheral region of the patterned mask layer 240 .

[0041] like Fig.10 As shown in , since the pattern density of the patterned mask layer 240 increases from the central area of ​​the patterned mask layer 240 to the peripheral area of ​​the patterned mask layer 240, the central area of ​​the patterned mask layer 240 is ground at a first grinding rate, and the peripheral area of ​​the patterned mask layer 240 is ground at a second grinding rate that is smaller than the first grinding rate. In other words, during the grinding process, the grinding rate (removal rate) of the peripheral area of ​​the patterned mask layer 240 is lower than the grinding rate (removal rate) of the central area of ​​the patterned mask layer 240, so that the central area of ​​the patterned mask layer 240 is more recessed than the peripheral area of ​​the patterned mask layer 240, and the top surface of the patterned mask layer 240 can become concave. In addition, in some embodiments, the central area of ​​the pad layer 220 can be ground earlier than the peripheral area of ​​the pad layer 220. In some embodiments, the peripheral area of ​​the pad layer 220 and the central area of ​​the pad layer 220 can be ground at the same grinding rate. Therefore, as Fig.11 As shown in , when the patterned mask layer 240 is ground away, the central area of ​​the liner layer 220 is also more recessed than the peripheral area of ​​the liner layer 220. Fig.12As shown in FIG. 1 , the pad layer 220 is ground away, and a lens layer 400 including a single lens portion 410 is formed on the image capture chip 100 , wherein the single lens portion 410 of the lens layer 400 has a curved and concave light incident surface 410 a .

[0042] In some embodiments, the pad layer 220 may be ground at a grinding rate greater than both the grinding rate of the peripheral region of the patterned mask layer 240 and the grinding rate of the central region of the patterned mask layer 240; in some embodiments, the pad layer 220 may be ground at a grinding rate greater than the grinding rate of the peripheral region of the patterned mask layer 240 and substantially equal to the grinding rate of the central region of the patterned mask layer 240; in some embodiments, the pad layer 220 may be ground at a grinding rate between the grinding rate of the peripheral region of the patterned mask layer 240 and the grinding rate of the central region of the patterned mask layer 240; in some embodiments, the pad layer 220 may be ground at a grinding rate less than the grinding rate of the central region of the patterned mask layer 240 and substantially equal to the grinding rate of the peripheral region of the patterned mask layer 240; and in some embodiments, the pad layer 220 may be ground at a grinding rate less than both the grinding rate of the peripheral region of the patterned mask layer 240 and the grinding rate of the central region of the patterned mask layer 240.

[0043] like Fig.12 As shown in , the image sensor 20 includes an image capture chip 100 and a lens layer 400 formed on the image capture chip 100. The lens layer 400 includes a single lens portion 410 covering an optical sensing area SA of the image capture chip 100, wherein an orthogonal projection of the single lens portion 410 onto the image capture chip 100 overlaps with the optical sensing area SA. In other words, the single lens portion 410 is disposed above the image capture chip 100 and completely covers the optical sensing area SA of the image capture chip 100. In some embodiments, the optical axis OA of the single lens portion 410 may be substantially aligned with the center of the optical sensing area SA. In other words, the optical axis OA of the single lens portion 410 may be substantially aligned with the centers of the plurality of pixels P. In some embodiments, the sidewall 100s of the image capture chip 100 is substantially aligned with the sidewall 400s of the lens layer 400. In other words, the lens layer 400 is a chip-level lens formed on the image capture chip 100. In some embodiments, the bottom surface 400 b of the lens layer 400 may be in contact with a surface (eg, the backside surface 100 b ) of the image capture chip 100 .

[0044] In some embodiments, the single lens portion 410 may completely cover the image capture chip 100 and include: a flat bottom surface 400b in contact with a surface (e.g., backside surface 100b) of the image capture chip 100; and a sidewall 400s substantially aligned with the sidewall 100s of the image capture chip 100. In some embodiments, the maximum thickness T3 of the lens layer 400 may be in a range of about 1 micrometer to about 100 micrometers. In some embodiments, the maximum distance D1 between the topmost surface of the lens layer 400 and the curved and concave light incident surface 410a may be in a range of about 0.5 micrometers to about 95 micrometers. In some embodiments, the maximum thickness T3 of the lens layer 400 is greater than the maximum distance D1 between the topmost surface of the lens layer 400 and the curved and concave light incident surface 410a.

[0045] Since the lens layer 400 is directly formed on the image capture chip 100 and contacts the image capture chip 100, in some embodiments, it is not necessary to assemble an external lens module thicker than the image capture chip 100 on the image capture chip 100. In some embodiments, the single lens portion 410 of the lens layer 400 can partially or completely replace the above-mentioned external lens module, and the manufacturing process of the image sensor 10 can be simplified. The manufacturing cost can be reduced. In addition, the image sensor 10 can be more compact.

[0046] Figure 13 to Figure 15 are schematic cross-sectional views illustrating various stages of a method of manufacturing an image sensor according to some embodiments of the present invention. Figure 13 to Figure 15 The method for manufacturing the image sensor 10 described in Figures 1 to 8 Therefore, the manufacturing method of the image sensor 10 described in the above is omitted here. Figure 13 to Figure 15 The difference between the two manufacturing methods is that the material of the patterned mask layer 230 is different from the material layer 210, and therefore Fig.13 The liner layer 220 is omitted.

[0047] refer to Figure 14 to Figure 15 , the patterned mask layer 230 and the material layer 210 are ground. In some embodiments, the material layer 210 is ground using the patterned mask layer 230 as a grinding mask to form a lens layer 300 including a single lens portion 310 on the image capture chip 100. In some embodiments, the patterned mask layer 230 and the material layer 210 are ground using the same slurry. Fig.14 For example, a central region of the patterned mask layer 230 is ground slower than a peripheral region of the patterned mask layer 230 .

[0048] like Fig.14As shown in , since the pattern density of the patterned mask layer 230 decreases from the central area of ​​the patterned mask layer 230 to the peripheral area of ​​the patterned mask layer 230, the central area of ​​the patterned mask layer 230 is ground at a first grinding rate, and the peripheral area of ​​the patterned mask layer 230 is ground at a second grinding rate that is greater than the first grinding rate. In other words, during the grinding process, the grinding rate (removal rate) of the peripheral area of ​​the patterned mask layer 230 is higher than the grinding rate (removal rate) of the central area of ​​the patterned mask layer 230, so that the peripheral area of ​​the patterned mask layer 230 is more recessed than the central area of ​​the patterned mask layer 230, and the top surface of the patterned mask layer 230 can become rounded convex. In addition, in some embodiments, the peripheral area of ​​the material layer 210 can be ground earlier than the central area of ​​the material layer 210. In some embodiments, the peripheral area of ​​the material layer 210 and the central area of ​​the material layer 210 can be ground at the same grinding rate. Therefore, as Fig.15 As shown in , when the patterned mask layer 230 is ground away, the peripheral area of ​​the material layer 210 is also recessed more than the central area of ​​the pad layer 220, and a lens layer 300 including a single lens portion 310 is formed on the image capture chip 100, wherein the single lens portion 310 of the lens layer 300 has a curved and concave light incident surface 310a.

[0049] In some embodiments, during the grinding process, the material layer 210 may be ground at a grinding rate greater than the grinding rate of the peripheral region of the patterned mask layer 230 and / or the grinding rate of the central region of the patterned mask layer 230. In some embodiments, during the grinding process, the material layer 210 may be ground at a grinding rate substantially equal to the grinding rate of the peripheral region of the patterned mask layer 230 or the grinding rate of the central region of the patterned mask layer 230. In some embodiments, during the grinding process, the material layer 210 may be ground at a grinding rate less than the grinding rate of the peripheral region of the patterned mask layer 230 and / or the grinding rate of the central region of the patterned mask layer 230. For example, in some embodiments, the material layer 210 may be ground at a grinding rate greater than both the grinding rate of the peripheral region of the patterned mask layer 230 and the grinding rate of the central region of the patterned mask layer 230; in some embodiments, the material layer 210 may be ground at a grinding rate greater than the grinding rate of the central region of the patterned mask layer 230 and substantially equal to the grinding rate of the peripheral region of the patterned mask layer 230; in some embodiments, the material layer 210 may be ground at a grinding rate between the grinding rate of the peripheral region of the patterned mask layer 230 and the grinding rate of the central region of the patterned mask layer 230; in some embodiments, the material layer 210 may be ground at a grinding rate less than the grinding rate of the peripheral region of the patterned mask layer 230 and substantially equal to the grinding rate of the central region of the patterned mask layer 230; and in some embodiments, the material layer 210 may be ground at a grinding rate less than both the grinding rate of the peripheral region of the patterned mask layer 230 and the grinding rate of the central region of the patterned mask layer 230.

[0050] Figure 16 to Figure 18 are schematic cross-sectional views illustrating various stages of a method of manufacturing an image sensor according to some embodiments of the present invention. Figure 16 to Figure 18 The manufacturing method of the image sensor 20 described in Figures 9 to 12 Therefore, the manufacturing method of the image sensor 20 described in the above is omitted here. Figure 16 to Figure 18 The difference between the two manufacturing methods is that the material of the patterned mask layer 240 is different from that of the material layer 210, and therefore Fig.16 The liner layer 220 is omitted.

[0051] refer to Figure 17 to Figure 18, the patterned mask layer 240 and the material layer 210 are ground. In some embodiments, the material layer 210 is ground using the patterned mask layer 240 as a grinding mask to form a lens layer 400 including a single lens portion 410 on the image capture chip 100. In some embodiments, the patterned mask layer 240 and the material layer 210 are ground using the same slurry. For illustration purposes, Fig.17 For example, the central region of the patterned mask layer 240 is ground faster than the peripheral region of the patterned mask layer 240 .

[0052] like Fig.17 As shown in , since the pattern density of the patterned mask layer 240 increases from the central area of ​​the patterned mask layer 240 to the peripheral area of ​​the patterned mask layer 240, the central area of ​​the patterned mask layer 240 is ground at a first grinding rate, and the peripheral area of ​​the patterned mask layer 240 is ground at a second grinding rate that is smaller than the first grinding rate. In other words, during the grinding process, the grinding rate (removal rate) of the peripheral area of ​​the patterned mask layer 240 is lower than the grinding rate (removal rate) of the central area of ​​the patterned mask layer 240, so that the central area of ​​the patterned mask layer 240 is more recessed than the peripheral area of ​​the patterned mask layer 240, and the top surface of the patterned mask layer 240 can become concave. In addition, in some embodiments, the central area of ​​the material layer 210 can be ground earlier than the peripheral area of ​​the material layer 210. In some embodiments, the peripheral area of ​​the material layer 210 and the central area of ​​the material layer 210 can be ground at the same grinding rate. Therefore, as Fig.17 As shown in , when the patterned mask layer 240 is ground away, the central area of ​​the material layer 210 is also recessed more than the peripheral area of ​​the material layer 210, and a lens layer 400 including a single lens portion 410 is formed on the image capture chip 100, wherein the single lens portion 410 of the lens layer 400 has a curved and concave light incident surface 410a.

[0053] In some embodiments, during the grinding process, the material layer 210 may be ground at a grinding rate greater than the grinding rate of the peripheral region of the patterned mask layer 240 and / or the grinding rate of the central region of the patterned mask layer 240. In some embodiments, during the grinding process, the material layer 210 may be ground at a grinding rate substantially equal to the grinding rate of the peripheral region of the patterned mask layer 240 or the grinding rate of the central region of the patterned mask layer 240. In some embodiments, during the grinding process, the material layer 210 may be ground at a grinding rate greater than both the grinding rate of the peripheral region of the patterned mask layer 240 and / or the grinding rate of the central region of the patterned mask layer 240. For example, in some embodiments, the material layer 210 can be ground at a grinding rate greater than the grinding rate of the peripheral area of ​​the patterned mask layer 240 and the grinding rate of the central area of ​​the patterned mask layer 240; in some embodiments, the material layer 210 can be ground at a grinding rate greater than the grinding rate of the peripheral area of ​​the patterned mask layer 240 and substantially equal to the grinding rate of the central area of ​​the patterned mask layer 240; in some embodiments, the material layer 210 can be ground at a grinding rate between the grinding rate of the peripheral area of ​​the patterned mask layer 240 and the grinding rate of the central area of ​​the patterned mask layer 240; in some embodiments, the material layer 210 can be ground at a grinding rate less than the grinding rate of the central area of ​​the patterned mask layer 240 and substantially equal to the grinding rate of the peripheral area of ​​the patterned mask layer 240; and in some embodiments, the material layer 210 can be ground at a grinding rate less than both the grinding rate of the peripheral area of ​​the patterned mask layer 240 and the grinding rate of the central area of ​​the patterned mask layer 240.

[0054] In the above-mentioned embodiment, since the lens layer 300 (or the lens layer 400) is directly formed on the image capture chip 100 and contacts the image capture chip 100, in some embodiments, it is not necessary to assemble an external lens module thicker than the image capture chip 100 on the image capture chip 100. In some embodiments, the single lens portion 310 of the lens layer 300 (or the single lens portion 410 of the lens layer 400) can partially or completely replace the above-mentioned external lens module, and the manufacturing process of the image sensor 10 (or the image sensor 20) can be simplified. The manufacturing cost can be reduced. In addition, the image sensor 10 (or the image sensor 20) can be more compact.

[0055] According to some embodiments of the present invention, a method includes at least the following steps. A material layer is formed above an image capture chip. A patterned mask layer is formed on the material layer, wherein a pattern density of the patterned mask layer varies from a central area of ​​the patterned mask layer to a peripheral area of ​​the patterned mask layer. The material layer is ground using the patterned mask layer as a mask to form a lens layer including a single lens portion on the image capture chip. In an embodiment, the pattern density of the patterned mask layer decreases from the central area of ​​the patterned mask layer to the peripheral area of ​​the patterned mask layer. In an embodiment, the pattern density of the patterned mask layer increases from the central area of ​​the patterned mask layer to the peripheral area of ​​the patterned mask layer. In an embodiment, during the grinding of the material layer, the central area of ​​the patterned mask layer is ground at a first grinding rate, and the peripheral area of ​​the patterned mask layer is ground at a second grinding rate different from the first grinding rate. In an embodiment, the method further comprises: before forming the patterned mask layer on the material layer, forming a liner layer on the material layer, wherein the liner layer is removed during the grinding of the material layer. In an embodiment, during the grinding of the material layer, the central area of ​​the patterned mask layer is ground at a first grinding rate, the peripheral area of ​​the patterned mask layer is ground at a second grinding rate, and the liner layer is ground at a third grinding rate, the third grinding rate being greater than the first grinding rate or the second grinding rate. In an embodiment, during the grinding of the material layer, the central area of ​​the patterned mask layer is ground at a first grinding rate, the peripheral area of ​​the patterned mask layer is ground at a second grinding rate, and the liner layer is ground at a third grinding rate, the third grinding rate being less than the first grinding rate or the second grinding rate. In an embodiment, during the grinding of the material layer, the central area of ​​the patterned mask layer is ground at a first grinding rate, the peripheral area of ​​the patterned mask layer is ground at a second grinding rate, and the pad layer is ground at a third grinding rate, and the third grinding rate is substantially equal to the first grinding rate or the second grinding rate.

[0056] According to some embodiments of the present invention, a method includes at least the following steps. A material layer is formed on an image capture chip. A patterned mask layer is formed on the material layer. The patterned mask layer and the material layer are ground to form a lens layer including a single lens portion on the image capture chip, wherein a central area of ​​the patterned mask layer and a peripheral area of ​​the patterned mask layer are ground at different grinding rates. In an embodiment, the central area of ​​the patterned mask layer is ground at a first grinding rate, and the peripheral area of ​​the patterned mask layer is ground at a second grinding rate greater than the first grinding rate. In an embodiment, the central area of ​​the patterned mask layer is ground at a first grinding rate, and the peripheral area of ​​the patterned mask layer is ground at a second grinding rate less than the first grinding rate. In an embodiment, the method further includes: before forming the patterned mask layer on the material layer, forming a liner layer on the material layer, wherein the liner layer is ground away during the grinding of the patterned mask layer and the material layer. In an embodiment, during the polishing of the patterned mask layer and the material layer, the liner layer is polished at a third polishing rate, and the material layer is polished at a fourth polishing rate greater than the third polishing rate. In an embodiment, during the polishing of the patterned mask layer and the material layer, the liner layer is polished at a third polishing rate, and the material layer is polished at a fourth polishing rate less than or substantially equal to the third polishing rate.

[0057] According to some alternative embodiments of the present invention, an image sensor includes an image capture chip and a lens layer. The image capture chip includes an optical sensing area. The lens layer includes a single lens portion. The single lens portion covers the optical sensing area of ​​the image capture chip, an orthogonal projection of the single lens portion onto the image capture chip overlaps the optical sensing area, and an optical axis of the single lens portion is substantially aligned with a center of the optical sensing area. In an embodiment, a sidewall of the image capture chip is substantially aligned with a sidewall of the lens layer. In an embodiment, a maximum thickness of the lens layer is in a range of about 1 micron to about 100 microns. In an embodiment, the lens layer further includes a base portion, the single lens portion is located on the base portion, and the base portion includes a flat bottom surface in contact with a surface of the image capture chip. In an embodiment, the base portion completely covers the image capture chip, and the sidewall of the base portion is substantially aligned with the sidewall of the image capture chip. In an embodiment, the single lens portion includes a flat bottom surface in contact with a surface of the image capture chip.

[0058] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present invention. Those skilled in the art will appreciate that they can easily use the present invention as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also appreciate that these equivalent constructions do not depart from the spirit and scope of the present invention, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A method for manufacturing an image sensor, comprising: forming a material layer on the image acquisition chip; forming a patterned mask layer on the material layer, wherein a pattern density of the patterned mask layer changes from a central region of the patterned mask layer to a peripheral region of the patterned mask layer; as well as The material layer is ground using the patterned mask layer as a mask to form a lens layer on the image capture chip, the lens layer including a single lens portion, wherein a sidewall of the image capture chip is substantially aligned with a sidewall of the lens layer. 2 . The method of claim 1 , wherein the pattern density of the patterned mask layer decreases from the central region of the patterned mask layer to the peripheral region of the patterned mask layer. 3 . The method of claim 1 , wherein the pattern density of the patterned mask layer increases from the central region of the patterned mask layer to the peripheral region of the patterned mask layer.

4. The method according to claim 1, wherein during the grinding of the material layer, the central area of ​​the patterned mask layer is ground at a first grinding rate, and the peripheral area of ​​the patterned mask layer is ground at a second grinding rate different from the first grinding rate.

5. The method according to claim 1, further comprising: Before forming the patterned mask layer on the material layer, a liner layer is formed on the material layer, wherein the liner layer is removed during the grinding of the material layer.

6. The method according to claim 5, wherein during the grinding of the material layer, the central area of ​​the patterned mask layer is ground at a first grinding rate, the peripheral area of ​​the patterned mask layer is ground at a second grinding rate, and the pad layer is ground at a third grinding rate, wherein the third grinding rate is greater than the first grinding rate or the second grinding rate.

7. The method according to claim 5, wherein during the grinding of the material layer, the central area of ​​the patterned mask layer is ground at a first grinding rate, the peripheral area of ​​the patterned mask layer is ground at a second grinding rate, and the pad layer is ground at a third grinding rate, and the third grinding rate is less than the first grinding rate or the second grinding rate.

8. The method according to claim 5, wherein during the grinding of the material layer, the central area of ​​the patterned mask layer is ground at a first grinding rate, the peripheral area of ​​the patterned mask layer is ground at a second grinding rate, and the pad layer is ground at a third grinding rate, and the third grinding rate is substantially equal to the first grinding rate or the second grinding rate.

9. A method for manufacturing an image sensor, comprising: forming a material layer on the image acquisition chip; forming a patterned mask layer on the material layer; as well as The patterned mask layer and the material layer are ground to form a lens layer on the image capture chip, the lens layer including a single lens portion, wherein a central area of ​​the patterned mask layer and a peripheral area of ​​the patterned mask layer are ground at different grinding rates, wherein a sidewall of the image capture chip and a sidewall of the lens layer are substantially aligned. 10 . The method of claim 9 , wherein the central region of the patterned mask layer is polished at a first polishing rate, and the peripheral region of the patterned mask layer is polished at a second polishing rate greater than the first polishing rate. 11 . The method of claim 9 , wherein the central region of the patterned mask layer is polished at a first polishing rate, and the peripheral region of the patterned mask layer is polished at a second polishing rate that is less than the first polishing rate.

12. The method according to claim 9, further comprising: Before forming the patterned mask layer on the material layer, a liner layer is formed on the material layer, wherein the liner layer is ground away during the grinding of the patterned mask layer and the material layer. 13 . The method according to claim 12 , wherein during the polishing of the patterned mask layer and the material layer, the liner layer is polished at a third polishing rate, and the material layer is polished at a fourth polishing rate greater than the third polishing rate.

14. The method according to claim 12, wherein during the polishing of the patterned mask layer and the material layer, the liner layer is polished at a third polishing rate, and the material layer is polished at a fourth polishing rate that is less than or substantially equal to the third polishing rate.

15. An image sensor, comprising: An image acquisition chip including an optical sensing area; as well as A lens layer comprises a single lens portion, wherein the single lens portion covers the optical sensing area of ​​the image capture chip, an orthogonal projection of the single lens portion onto the image capture chip overlaps with the optical sensing area, and an optical axis of the single lens portion is substantially aligned with a center of the optical sensing area, wherein a side wall of the image capture chip is substantially aligned with a side wall of the lens layer. 16 . The image sensor according to claim 15 , wherein a maximum thickness of the lens layer is in a range from 1 μm to 100 μm. 17 . The image sensor according to claim 15 , wherein the lens layer further comprises a base portion, the single lens portion is located on the base portion, and the base portion comprises a flat bottom surface in contact with a surface of the image capture chip. 18 . The image sensor according to claim 17 , wherein the base portion completely covers the image capture chip, and a sidewall of the base portion is substantially aligned with a sidewall of the image capture chip.

19. The image sensor of claim 15, wherein the single lens portion includes a flat bottom surface that contacts a surface of the image capture chip. 20 . The image sensor of claim 19 , wherein the lens layer further comprises a non-planar top surface opposite to the planar bottom surface in a stacking direction of the lens layer and the image capture chip.

Images