Memory device with flat bottom electrode and method of forming the same

Abstract

A memory device and a method of forming the same include an array of memory cells overlaid on a substrate and located in a memory array region. Each memory cell includes a vertical stack comprising a bottom electrode, a memory element, a top electrode, and dielectric sidewall spacers located on the sidewalls of each vertical stack. The bottom electrode includes a flat-top portion extending horizontally beyond the outer periphery of the dielectric sidewall spacers. The device also includes a discrete etch-stop dielectric layer and a metal cell contact structure. This invention can maintain the thickness of the top electrode during the formation of the bottom electrode.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to semiconductor devices, and particularly to a semiconductor memory device employing an etch stop hard mask layer for a contact via structure and a method of forming the same. BACKGROUND

[0002] Semiconductor memory devices are widely used in modern electronic devices. Some semiconductor memory devices employ memory cells that each include a vertical stack formed of a bottom electrode, a memory element, and a top electrode. For example, a magnetic tunnel junction memory device can employ such a vertical stack, where the memory element includes a magnetic tunnel junction. A contact via structure can be employed to provide electrical contact to the top electrode. SUMMARY

[0003] A memory device of an embodiment of the present disclosure includes an array of memory cells formed over a substrate and located in a memory array region, each of the memory cells including a vertical stack including a bottom electrode, a memory element, a top electrode, and a dielectric sidewall spacer located on sidewalls of each of the vertical stacks, wherein the bottom electrode includes a flat top portion that extends horizontally beyond an outer periphery of the dielectric sidewall spacer, an etch stop dielectric layer over each of the memory cells including a horizontally extending portion extending over the flat top portion of the bottom electrode, and a metal cell contact structure contacting a respective subset of the top electrodes and a respective subset of vertically protruding portions of the etch stop dielectric layer.

[0004] A memory device of an embodiment of the present disclosure includes an array of memory cells formed over a substrate and located in a memory array region, each of the memory cells including a vertical stack including a bottom electrode, a memory element, a top electrode, and a dielectric sidewall spacer located on sidewalls of each of the vertical stacks, the memory element including a magnetic tunnel junction, wherein the bottom electrode includes a flat top portion that extends beyond an outer periphery of the dielectric sidewall spacer, an etch stop dielectric layer over each of the memory cells including a horizontally extending portion extending over the flat top portion of the bottom electrode, and a metal cell contact structure contacting a respective subset of the top electrodes and a respective subset of vertically protruding portions of the etch stop dielectric layer.

[0005] A method of forming a memory device, in accordance with an embodiment of the present disclosure, includes forming memory elements and top electrodes in an array of memory cells in a memory array region over a substrate; depositing a continuous dielectric sidewall spacer material layer over the memory array region; forming dielectric sidewall spacers on sidewalls of the memory cells by selectively removing the dielectric sidewall spacer material between the memory cells in the array of memory cells, wherein forming the dielectric sidewall spacers exposes a top surface of a continuous second bottom electrode material layer; forming an etch stop dielectric layer over the array of memory cells, the top electrodes, and the top surface of the continuous second bottom electrode material layer; forming a mask layer over the etch stop dielectric layer; patterning the mask layer; and forming bottom electrodes by etching the continuous second bottom electrode material layer and a continuous first bottom electrode material layer, wherein the bottom electrodes include flat top portions that extend horizontally beyond an outer periphery of the dielectric sidewall spacers. BRIEF DESCRIPTION OF DRAWINGS

[0006] Aspects of the application are best understood from the following detailed description when read in conjunction with the accompanying drawings. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 is a vertical cross-sectional view of an exemplary structure after forming a complementary metal-oxide-semiconductor (CMOS) transistor and a metal interconnect structure formed in a dielectric material layer, in accordance with an embodiment of the present disclosure.

[0008] Figure 2 is a vertical cross-sectional view of an exemplary structure after forming a dielectric cap layer and a via level dielectric layer, in accordance with an embodiment of the present disclosure.

[0009] Figure 3 is a vertical cross-sectional view of an exemplary structure after forming a lower electrode contact via cavity, in accordance with an embodiment of the present disclosure.

[0010] Figure 4 is a vertical cross-sectional view of an exemplary structure after forming a continuous metal barrier layer and a metal via fill material portion, in accordance with an embodiment of the present disclosure.

[0011] Figure 5 is a vertical cross-sectional view of an exemplary structure after forming a continuous first bottom electrode material layer, a continuous second bottom electrode material layer, a continuous selector material layer, a continuous synthetic antiferromagnet layer, a continuous non-magnetic tunnel barrier layer, a continuous free magnetization layer, at least one continuous cap layer, and a continuous top electrode material layer, in accordance with an embodiment of the present disclosure.

[0012] Figure 6 is a vertical cross-sectional view of an exemplary structure after forming an array of discrete vertical stacks each including a selector element, a synthetic antiferromagnetic structure, a non-magnetic tunnel barrier layer, a free magnetization layer, at least one cap layer, and a top electrode according to embodiments of the application.

[0013] Figure 7 is a vertical cross-sectional view of an exemplary structure after forming an array of dielectric spacers around the discrete vertical stacks according to embodiments of the application.

[0014] Figure 8 is a vertical cross-sectional view of an exemplary structure after etching the array of dielectric spacers.

[0015] Figure 9 is a vertical cross-sectional view of an exemplary structure after forming an etch stop dielectric layer according to embodiments of the application.

[0016] Figure 10 is a vertical cross-sectional view of an exemplary structure after forming a mask layer according to embodiments of the application.

[0017] Figure 11 is a vertical cross-sectional view of an exemplary structure after patterning the mask layer to expose portions of the etch stop dielectric according to embodiments of the application.

[0018] Figure 12 is a vertical cross-sectional view of an exemplary structure after forming a second bottom electrode, a first bottom electrode, and a bottom electrode connection via structure according to embodiments of the application.

[0019] Figure 13 is a vertical cross-sectional view of an exemplary structure after forming a silicon oxide liner layer according to embodiments of the application.

[0020] Figure 14 is a vertical cross-sectional view of an exemplary structure after forming a first dielectric matrix layer according to embodiments of the application.

[0021] Figure 15 is a vertical cross-sectional view of an exemplary structure after a chemical mechanical planarization process using portions of the etch stop dielectric layer in the memory array region as a stop structure according to embodiments of the application.

[0022] Figure 16is a vertical cross-sectional view of an exemplary structure after a touch-up planarization process that removes portions of the etch stop dielectric layer in the memory array region, in accordance with an embodiment of the present invention.

[0023] Figure 17 is a vertical cross-sectional view of an exemplary structure after formation of a second dielectric matrix layer, in accordance with an embodiment of the present invention.

[0024] Figure 18 is a vertical cross-sectional view of an exemplary structure after formation of a via cavity in the logic region, in accordance with an embodiment of the present invention.

[0025] Figure 19 is a vertical cross-sectional view of an exemplary structure after formation of an integrated line and via cavity in the logic region and formation of a cell contact cavity in the memory array region, in accordance with an embodiment of the present invention.

[0026] Figure 20 is a vertical cross-sectional view of an exemplary structure after formation of an integrated line and via structure in the logic region and formation of a metal cell contact structure in the memory array region, in accordance with an embodiment of the present invention.

[0027] Figure 21 is a vertical cross-sectional view of an exemplary structure after formation of additional metal interconnect structures formed in an additional dielectric material layer, in accordance with an embodiment of the present invention.

[0028] Figure 22 is a flow diagram showing the general processing steps of the method of the present invention.

[0029] [Explanation of Symbols]

[0030] 9: Substrate

[0031] 100: Memory array region

[0032] 101: Memory cell

[0033] 108: Dielectric cap layer

[0034] 110: Via level dielectric layer

[0035] 121: Lower electrode contact via cavity

[0036] 122: Metal barrier layer

[0037] 122L: Continuous metal barrier layer

[0038] 124: Metal via fill material portion

[0039] 126: first portion of bottom electrode / first bottom electrode

[0040] 126L: continuous first bottom electrode material layer / first bottom electrode material layer

[0041] 128: second portion of bottom electrode / second bottom electrode

[0042] 128L: continuous second bottom electrode material layer / second bottom electrode material layer

[0043] 130: selector element

[0044] 130L: continuous selector material layer

[0045] 140: synthetic antiferromagnet (SAF) structure

[0046] 140L: continuous synthetic antiferromagnet (SAF) layer

[0047] 141: ferromagnetic hard layer

[0048] 142: antiferromagnetic coupling layer

[0049] 143: reference magnetization layer

[0050] 146: non-magnetic tunnel barrier layer

[0051] 146L: continuous non-magnetic tunnel barrier layer

[0052] 148: free magnetization layer

[0053] 148L: continuous free magnetization layer

[0054] 158: cap layer

[0055] 158L: continuous cap layer

[0056] 160: top electrode

[0057] 160L: continuous top electrode material layer

[0058] 162: first dielectric spacer material / first dielectric sidewall spacer

[0059] 162L: first dielectric spacer material layer / dielectric sidewall spacer material

[0060] 164: second dielectric spacer material / second dielectric sidewall spacer

[0061] 164L: second dielectric spacer material layer / dielectric sidewall spacer material /

[0062] 170: etch stop dielectric layer / etch stop dielectric

[0063] 170L: continuous etch stop layer / etch stop dielectric layer

[0064] 172: second etch stop dielectric layer

[0065] 172L: continuous etch stop dielectric layer / etch stop dielectric layer

[0066] 175: mask layer

[0067] 176: first dielectric base layer

[0068] 177: portion of etch stop dielectric layer

[0069] 178: second dielectric base layer

[0070] 179: flat top portion

[0071] 181: via cavity

[0072] 183: integrated line and via cavity / line and via cavity

[0073] 184: integrated line and via structure

[0074] 187: cell contact cavity

[0075] 188: metallic cell contact structure

[0076] 200: logic region

[0077] 601: contact level dielectric material layer

[0078] 610: first metal line level dielectric material layer

[0079] 612: device contact via structure

[0080] 618: first metal line structure

[0081] 620: second line and via level dielectric material layer

[0082] 622: first metal via structure

[0083] 628: second metal line structure

[0084] 630: third line and via level dielectric material layer

[0085] 632: second metal via structure

[0086] 638: third metal line structure

[0087] 640: fourth line and via level dielectric material layer

[0088] 642: third metal via structure

[0089] 648: fourth metal line structure

[0090] 660: sixth line and via level dielectric material layer

[0091] 662: fifth metal via structure

[0092] 668: sixth metal line structure

[0093] 700: field effect transistor / complementary metal oxide semiconductor (CMOS) circuitry

[0094] 720: shallow trench isolation structure

[0095] 732: source region

[0096] 735: semiconductor channel

[0097] 738: drain region

[0098] 742: source side metal-semiconductor alloy region

[0099] 748: drain side metal-semiconductor alloy region

[0100] 750: gate structure

[0101] 752: gate dielectric

[0102] 754: gate electrode

[0103] 756: dielectric gate spacer

[0104] 758: gate capping dielectric

[0105] 2210, 2220, 2230, 2240, 2250, 2260, 2270: steps DETAILED DESCRIPTION

[0106] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the making of a first feature on top of or on a second feature in the following description can include embodiments where the first feature is formed directly contacting the second feature, and can also include embodiments where additional features can be formed between the first feature and the second feature such that the first feature can not directly contact the second feature. Additionally, the present application can make use of the same reference numbers throughout the description for the purpose of convenience and clarity and these reference numbers do not in any way limit the scope of the application. Accordingly, other embodiments are within the scope of the following claims.

[0107] Furthermore, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0108] Generally, the structures and methods of the present disclosure can be used in memory devices that include an array of memory cells formed over a substrate and in a memory array region, and a logic region that is outside the memory array region and free of memory cells. Each of the memory cells can include a vertical stack that includes a bottom electrode, a memory element, and a top electrode. The vertical stacks can be arranged in a one-dimensional array or a two-dimensional array at a high density sufficient to provide a topographic average height difference for a subsequently formed dielectric matrix layer. However, increasing the density of the memory cells introduces additional fabrication problems. As the lateral dimensions of the memory cells shrink, the process window for forming contact via structures shrinks. Cutting the bottom electrode layer and the electrode connection via structure layer to form the bottom electrode and the bottom electrode connection via structure can cause the thickness of the top electrode of the memory cell to undesirably decrease. For example, the thickness of the top electrode can decrease to

[0109] Prior to cutting the bottom electrode layer and the electrode connection via structure layer, an etch stop dielectric layer can be formed over the memory cells in the memory array region. A photoresist can then be formed over the etch stop dielectric layer. The photoresist can be patterned so that the bottom electrode layer and the electrode connection via structure layer can be cut while the photoresist and the etch stop layer protect the top electrode of the memory cells. In this way, the thickness of the top electrode can be maintained when the bottom electrode is formed. While the present disclosure is set forth in terms of embodiments in which each memory element includes a magnetic tunnel junction that provides magnetoresistance, embodiments in which the magnetic tunnel junction is replaced with any layer or any stack of layers that can provide at least two different resistance states between the bottom electrode and the top electrode are expressly contemplated herein. Accordingly, claims of the present disclosure should be interpreted to encompass all such variations unless otherwise limited to magnetoresistive memory devices that include a corresponding magnetic tunnel junction.

[0110] Furthermore, it should be understood that the memory device according to embodiments of the present invention may include a single discrete memory cell, a one-dimensional array of memory cells, or a two-dimensional array of memory cells. It should also be understood that the one-dimensional array of memory cells of the present invention may be implemented as a periodic one-dimensional array of memory cells, and the two-dimensional array of memory cells of the present invention may be implemented as a periodic two-dimensional array of memory cells. Additionally, although the present invention is illustrated using an embodiment in which a two-dimensional array of memory cells is formed within a fifth metal interconnect level, which is generally referred to as the fifth line and via (M5+V4) level, embodiments in which two-dimensional arrays of memory cells are formed within different metal interconnect levels are explicitly contemplated herein.

[0111] Reference Figure 1 This diagram illustrates an exemplary structure according to an embodiment of the present invention. The exemplary structure includes a substrate 9, which may be a semiconductor substrate, such as a commercially available silicon substrate. A shallow trench isolation structure 720 comprising a dielectric material such as silicon oxide may be formed in the upper portion of the substrate 9. Suitable doped semiconductor wells, such as p-type wells and n-type wells, may be formed in each region laterally enclosed by a continuous portion of the shallow trench isolation structure 720. A field-effect transistor 700 may be formed on the top surface of the substrate 9. For example, each field-effect transistor may include a source region 732, a drain region 738, a semiconductor channel 735, and a gate structure 750, the semiconductor channel 735 including a surface portion of the substrate 9 extending between the source region 732 and the drain region 738. Each gate structure 750 may include a gate dielectric 752, a gate electrode 754, a gate cap dielectric 758, and a dielectric gate spacer 756. A source-side metal-semiconductor alloy region 742 may be formed on each source region 732, and a drain-side metal-semiconductor alloy region 748 may be formed on each drain region 738.

[0112] The exemplary structure may include a memory array region 100 and a logic region 200. An array of memory elements may subsequently be formed in the memory array region 100, and logic means supporting the operation of the memory element array may be formed in the logic region 200. In one embodiment, the means in the memory array region 100 (e.g., field-effect transistors) may include bottom electrode access transistors that provide access to the bottom electrode of the subsequently formed memory cells. Top electrode access transistors may be formed in the logic region 200 that provide access to the top electrode of the subsequently formed memory cells. The means in the logic region 200 (e.g., field-effect transistors) may provide the functionality required to operate the subsequently formed array of memory cells. Specifically, the means in the logic region 200 may be configured to control programming operations, erasing operations, and sensing (reading) operations of the memory cell array. For example, the means in the logic region 200 may include a sensing circuitry and / or a top electrode biasing circuitry. The devices formed on the top surface of the substrate 9 may include complementary metal-oxide-semiconductor (CMOS) transistors and, if necessary, additional semiconductor devices (such as resistors, diodes, capacitors, etc.), and are collectively referred to as CMOS circuit system 700.

[0113] Various metal interconnect structures formed in the dielectric material layer can then be formed on the substrate 9 and the device (e.g., a field-effect transistor). The dielectric material layer may include, for example, a contact-level dielectric material layer 601, a first metal line-level dielectric material layer 610, a second line and via-level dielectric material layer 620, a third line and via-level dielectric material layer 630, and a fourth line and via-level dielectric material layer 640. The metal interconnect structure may include a device contact via structure 612 formed in a contact-level dielectric material layer 601 and in contact with a corresponding component of the CMOS circuit system 700, a first metal line structure 618 formed in a first metal line-level dielectric material layer 610, a first metal via structure 622 formed in the lower portion of a second line-via-level dielectric material layer 620, a second metal line structure 628 formed in the upper portion of a second line-via-level dielectric material layer 620, a second metal via structure 632 formed in the lower portion of a third line-via-level dielectric material layer 630, a third metal line structure 638 formed in the upper portion of a third line-via-level dielectric material layer 630, a third metal via structure 642 formed in the lower portion of a fourth line-via-level dielectric material layer 640, and a fourth metal line structure 648 formed in the upper portion of a fourth line-via-level dielectric material layer 640. In one embodiment, the second metal wire structure 628 may include a source line connected to the source-side power supply of the memory element array. The voltage provided by the source line can be applied to the bottom electrode via an access transistor disposed in the memory array region 100.

[0114] Each of the dielectric material layers (601, 610, 620, 630, 640) may comprise a dielectric material, such as undoped silicate glass, doped silicate glass, organosilicon glass, amorphous fluorinated carbon, porous variants thereof, or combinations thereof. Other suitable materials within the scope of the invention may also be used. Each of the metal interconnect structures (612, 618, 622, 628, 632, 638, 642, 648) may comprise at least one conductive material, which may be a combination of a metal liner layer (e.g., a metal nitride or metal carbide) and a metal filler material. Each metal liner layer may comprise TiN, TaN, WN, TiC, TaC, and WC, and each metal filler material portion may comprise W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and / or combinations thereof. Other suitable materials within the scope of the invention may also be used. In one embodiment, the first metal via structure 622 and the second metal wire structure 628 can be formed into an integrated wire and via structure using a dual damascene process; the second metal via structure 632 and the third metal wire structure 638 can be formed into an integrated wire and via structure using a dual damascene process; and / or the third metal via structure 642 and the fourth metal wire structure 648 can be formed into an integrated wire and via structure using a dual damascene process. Although the invention has been illustrated using an embodiment in which the memory cell array is formed on the fourth wire and via level dielectric material layer 640, embodiments in which the memory cell array can be formed at different metal interconnect levels are clearly contemplated herein.

[0115] Reference Figure 2 A dielectric capping layer 108 and a via-level dielectric layer 110 can be sequentially formed over the metal interconnect structure and the dielectric material layer. For example, the dielectric capping layer 108 can be formed on the top surface of the fourth metal wire structure 648 and the top surface of the fourth wire and via-level dielectric material layer 640. The dielectric capping layer 108 includes a dielectric capping material that can protect the underlying metal interconnect structure (e.g., the fourth metal wire structure 648). In one embodiment, the dielectric capping layer 108 may include a material that provides high etch resistance (i.e., a dielectric material) and may also be used as an etch stop material during subsequent anisotropic etching processes of the via-level dielectric layer 110. For example, the dielectric capping layer 108 may include silicon carbide or silicon nitride and may have a thickness in the range of 5 nm to 30 nm, but smaller and larger thicknesses are also possible.

[0116] The via-level dielectric layer 110 may contain any material that can be used as a dielectric material layer (601, 610, 620, 630, 640). For example, the via-level dielectric layer 110 may contain undoped or doped silicate glass deposited by the decomposition of tetraethyl orthosilicate (TEOS). The thickness of the via-level dielectric layer 110 may range from 50 nm to 200 nm, but smaller and larger thicknesses may also be used. The dielectric capping layer 108 and the via-level dielectric layer 110 may be formed as planar blanket (unpatterned) layers having corresponding flat top surfaces and corresponding flat bottom surfaces extending throughout the memory array region 100 and the logic region 200.

[0117] Reference Figure 3 Via cavities can be formed through the via-level dielectric layer 110 and the dielectric capping layer 108. For example, a photoresist layer (not shown) can be applied over the via-level dielectric layer 110, and the photoresist layer can be patterned to form openings in regions of the memory array region 100 overlying one of the fourth metal line structures 648. Anisotropic etching can be performed to transfer the pattern in the photoresist layer through the via-level dielectric layer 110 and the dielectric capping layer 108. The via cavity formed by the anisotropic etching process is referred to herein as a lower electrode contact via cavity 121 because a bottom electrode connection via structure will subsequently be formed in the lower electrode contact via cavity 121. The lower electrode contact via cavity 121 may have tapered sidewalls with a taper angle (relative to the vertical direction) ranging from 1 degree to 10 degrees. The top surface of the fourth metal line structure 648 may be substantially exposed at the bottom of each lower electrode contact via cavity 121. The photoresist layer can then be removed, for example, by ashing.

[0118] Reference Figure 4 A continuous metal barrier layer 122L can be formed as a continuous material layer. The continuous metal barrier layer 122L can cover the solidly exposed top surface of the fourth metal wire structure 648, the tapered sidewalls of the lower electrode contact via cavity 121, and the top surface of the via-level dielectric layer 110, without any holes penetrating therethrough. The continuous metal barrier layer 122L may contain conductive metal nitrides, such as TiN, TaN, and / or WN. Other suitable materials within the scope of this invention may also be used. The thickness of the continuous metal barrier layer 122L can range from 3 nm to 20 nm, but smaller and larger thicknesses are also possible.

[0119] A metallic filler material, such as tungsten or copper, can be deposited in the remaining volume of the lower electrode contact via cavity 121. Other suitable materials within the scope of the invention may also be used. The portion of the metallic filler material covering the horizontal plane including the top surface of the continuous metal barrier layer 122L can be removed by a planarization process (e.g., chemical mechanical planarization) to form a metallic via filler material portion 124. Each metallic via filler material portion 124 may have a top surface coplanar with the top surface of the continuous metal barrier layer 122L.

[0120] Reference Figure 5 A layer stack comprising a continuous first bottom electrode material layer 126L, a continuous second bottom electrode layer 128L, an optional continuous selector material layer 130L, a continuous synthetic antiferromagnet (SAF) layer 140L, a continuous nonmagnetic tunnel barrier layer 146L, a continuous free magnetization layer 148L, at least one continuous top cap layer 158L, and a continuous top electrode material layer 160L can be formed on the continuous metal barrier layer 122L and the metal via filling material portion 124. The layers within the layer stack can be deposited using appropriate chemical vapor deposition (CVD) or physical vapor deposition (PVD) processes. Each layer within the layer stack can be deposited as a flat blanket material layer having a uniform thickness throughout. In an embodiment, the optional continuous selector material layer 130L may be omitted.

[0121] The continuous first bottom electrode material layer 126L comprises at least one metallic material, such as TiN, TaN, WN, W, Cu, Al, Ti, Ta, Ru, Co, Mo, Pt, alloys thereof, and / or combinations thereof. Other suitable materials within the scope of the invention may also be used. For example, the continuous first bottom electrode material layer 126L may comprise tungsten (W), and / or may be substantially composed of tungsten (W). The thickness of the continuous first bottom electrode material layer 126L may range from 10 nm to 100 nm, but smaller and larger thicknesses may also be used.

[0122] The continuous second bottom electrode material layer 128L may contain the same material as the continuous first bottom electrode material layer 126L, or it may be a different material. In an embodiment, the continuous second bottom electrode material layer 128L contains a nonmagnetic material that can be used as a seed layer. Specifically, the continuous second bottom electrode layer 128L may provide a template crystal structure that aligns the polycrystalline particles of the material of the continuously synthesized antiferromagnetic layer 140L along a direction that maximizes the magnetization of the reference layer within the continuously synthesized antiferromagnetic layer 140L. The thickness of the continuous second bottom electrode layer 128L may be in the range of 3 nm to 20 nm, but smaller and larger thicknesses may also be used. The total thickness of the first bottom electrode material layer 126L and the second bottom electrode material layer 128L may be [missing information]. to Within the range.

[0123] The continuous selector material layer 130L comprises a selector material, i.e., a material exhibiting voltage-dependent switching characteristics. The continuous selector material layer 130L may comprise an oxygen-vacancy-modulated selector material (e.g., hafnium oxide or zirconium oxide, a bidirectional threshold switching material (e.g., zinc telluride)), or a vertical diode layer stack comprising a p-doped semiconductor layer and an n-doped semiconductor layer with a horizontal pn junction therebetween. Other suitable materials within the scope of this invention may also be used. Alternatively, other materials that conduct under high voltage bias and turn off under low voltage bias may be used in the continuous selector material layer 130L.

[0124] The continuously synthesized antiferromagnetic (SAF) layer 140L may comprise a stack of layers formed of a ferromagnetic hard layer 141, an antiferromagnetic coupling layer 142, and a reference magnetization layer 143. Each of the ferromagnetic hard layer 141 and the reference magnetization layer 143 may have a fixed magnetization direction. The antiferromagnetic coupling layer 142 provides antiferromagnetic coupling between the magnetization of the ferromagnetic hard layer 141 and the magnetization of the reference magnetization layer 143, such that the magnetization directions of the ferromagnetic hard layer 141 and the reference magnetization layer 143 remain fixed during the operation of the subsequently formed memory cell. The ferromagnetic hard layer 141 may comprise a hard ferromagnetic material, such as PtMn, IrMn, RhMn, FeMn, OsMn, etc. The reference magnetization layer 143 may comprise a hard ferromagnetic material, such as Co, CoFe, CoFeB, CoFeTa, NiFe, CoPt, CoFeNi, etc. Other suitable materials within the scope of the present invention may also be used. The antiferromagnetic coupling layer 142 may contain ruthenium or iridium. The thickness of the antiferromagnetic coupling layer 142 may be selected such that the exchange interaction induced by the antiferromagnetic coupling layer 142 stabilizes the relative magnetization directions of the ferromagnetic hard layer 141 and the reference magnetization layer 143 in opposite directions, i.e., antiparallel alignment. In one embodiment, the net magnetization of the continuous SAF layer 140L is achieved by matching the magnetization value of the ferromagnetic hard layer 141L with the magnetization value of the reference magnetization layer 143. The thickness of the continuous SAF layer 140L may range from 5 nm to 30 nm, but smaller and larger thicknesses may also be used.

[0125] The continuous nonmagnetic tunneling barrier layer 146L may comprise a tunneling-blocking material, which may be an electrically insulating material with a thickness allowing electron tunneling. For example, the continuous nonmagnetic tunneling barrier layer 146L may comprise magnesium oxide (MgO), aluminum oxide (Al2O3), aluminum nitride (AlN), aluminum oxynitride (AlON), hafnium oxide (HfO2), or zirconium oxide (ZrO2). Other suitable materials within the scope of this invention may also be used. The thickness of the continuous nonmagnetic tunneling barrier layer 146L may be from 0.7 nm to 1.3 nm, but smaller and larger thicknesses are also possible.

[0126] The continuous free magnetization layer 148L comprises a ferromagnetic material having two stable magnetization directions, parallel or antiparallel to the magnetization direction of the reference magnetization layer 143. The continuous free magnetization layer 148L comprises a hard ferromagnetic material, such as Co, CoFe, CoFeB, CoFeTa, NiFe, CoPt, CoFeNi, etc. Other suitable materials within the scope of this invention may also be used. The thickness of the continuous free magnetization layer 148L can range from 1 nm to 6 nm, but smaller and larger thicknesses are also possible.

[0127] The at least one continuous capping layer 158L comprises at least one capping material. Exemplary capping materials that can be used for the at least one continuous capping layer 158L include, but are not limited to, metallic materials such as Be, Mg, Al, Ti, Ta, W, Ge, Pt, Ru, Cu, their alloys, and their layer stacks. Other suitable materials within the scope of the invention may also be used. Alternatively, the at least one continuous capping layer 158L may comprise a conductive metal nitride. The total thickness of the at least one continuous capping layer 158L may range from 0.5 nm to 5 nm, but smaller and larger thicknesses may also be used.

[0128] The continuous top electrode material layer 160L comprises at least one metallic material, such as TiN, TaN, WN, W, Cu, Al, Ti, Ta, Ru, Co, Mo, Pt, alloys thereof, and / or combinations thereof. Other suitable materials within the scope of the invention may also be used. For example, the continuous top electrode material layer 160L may comprise tungsten (W), and / or may be substantially composed of tungsten (W). The thickness of the continuous top electrode material layer 160L may range from 10 nm to 100 nm, but smaller and larger thicknesses may also be used.

[0129] Reference Figure 6A photoresist layer (not shown) can be applied over a continuous top electrode material layer 160L, and the photoresist layer can be photolithographically patterned to form an array of discrete photoresist material portions. Each discrete photoresist material portion in the array can overlay a corresponding portion of the metal via filling material 124. In one embodiment, the metal via filling material portions 124 can be arranged as a two-dimensional periodic array having a first spacing along a first horizontal direction and a second spacing along a second horizontal direction. The discrete photoresist material portions can be arranged as a two-dimensional periodic array with the same periodicity as the two-dimensional periodic array of the metal via filling material portions 124.

[0130] An anisotropic etching process can be performed to etch unmasked areas of a continuous top electrode material layer 160L, the at least one continuous capping layer 158L, a continuous free magnetization layer 148L, a continuous nonmagnetic tunnel barrier layer 146L, a continuous SAF layer 140L, and a continuous selector material layer 130L. The chemical composition of the anisotropic etching process can be selected such that patterned portions of the continuous top electrode material layer 160L, the at least one continuous capping layer 158L, the continuous free magnetization layer 148L, the continuous nonmagnetic tunnel barrier layer 146L, the continuous SAF layer 140L, and the continuous selector material layer 130L have tapered sidewalls with a taper angle ranging from 1 degree to 20 degrees (e.g., 3 degrees to 10 degrees) relative to the vertical direction. In one embodiment, a continuous second bottom electrode layer 128L can be used as an etching stop layer for the anisotropic etching process.

[0131] Patterned portions of a continuous top electrode material layer 160L, at least one continuous top cap layer 158L, a continuous free magnetization layer 148L, a continuous nonmagnetic tunnel barrier layer 146L, a continuous SAF layer 140L, and a continuous selector material layer 130L can constitute an array formed by discrete vertical stacks. Each discrete vertical stack may include, from bottom to top, a selector element 130, a synthetic antiferromagnetic (SAF) structure 140, a nonmagnetic tunnel barrier layer 146, a free magnetization layer 148, at least one top cap layer 158, and a top electrode 160. Each selector element 130 is a patterned portion of a continuous selector material layer 130L. Each SAF structure 140 is a patterned portion of a continuous SAF layer 140L. Each nonmagnetic tunnel barrier layer 146 may be a patterned portion of a continuous nonmagnetic tunnel barrier layer 146L. Each free magnetization layer 148 may be a patterned portion of a continuous free magnetization layer 148L. Each capping layer 158 may be a patterned portion of the at least one continuous capping layer 158L. Each top electrode 160 may be a patterned portion of a continuous top electrode material layer 160L.

[0132] An array formed by discrete vertical stacks (130, 140, 146, 148, 158, 160) can be formed on substrate 9 in memory array region 100. Each SAF structure 140 may include a stack of layers formed by a ferromagnetic hard layer 141, an antiferromagnetic coupling layer 142, and a reference magnetization layer 143. A set of reference magnetization layers 143, nonmagnetic tunnel blocking layers 146, and free magnetization layers 148 within the discrete vertical stacks (130, 140, 146, 148, 158, 160) can constitute a magnetic tunnel junction (MTJ) used as a magnetoresistive memory element. The magnetization of the free magnetization layer 148 and the magnetization of the reference magnetization layer 143 within each discrete vertical stack (130, 140, 146, 148, 158, 160) can have two stable alignments, including parallel alignment and antiparallel alignment. The bistable magnetic coupling between the ferromagnetic material of the free magnetization layer 148 and the ferromagnetic material of the reference magnetization layer 143 within each magnetic tunnel junction provides magnetoresistance, i.e., the resistance variation between the free magnetization layer 148 and the reference magnetization layer 143 depends on the alignment of the magnetization directions of the free magnetization layer 148 and the reference magnetization layer 143. After anisotropic etching, the sidewalls of each element within each discrete vertical stack (130, 140, 146, 148, 158, 160) can be solidly exposed. The photoresist layer can then be removed, for example, by ashing.

[0133] Although the invention has been described using an embodiment in which the continuous metal barrier layer 122L, the continuous first bottom electrode material layer 126L, and the continuous second bottom electrode layer 128L are not patterned at this processing step, embodiments in which the continuous metal barrier layer 122L, the continuous first bottom electrode material layer 126L, and the continuous second bottom electrode layer 128L are patterned at this processing step are clearly contemplated herein.

[0134] Reference Figure 7At least one continuous dielectric spacer material layer can be conformally deposited on an array formed by discrete vertical stacks (130, 140, 146, 148, 158, 160) and on a portion of the solidly exposed top surface of the continuous second bottom electrode layer 128L. For example, a first dielectric spacer material layer 162L containing a first dielectric spacer material and a second dielectric spacer material layer 164L containing a second dielectric spacer material can be sequentially deposited using a suitable conformal deposition process (e.g., chemical vapor deposition). For example, the first dielectric spacer material 162 may include silicon nitride or a dielectric metal oxide (e.g., aluminum oxide), and the second dielectric spacer material 164 may include silicon oxide (e.g., TEOS oxide). The thickness of the first dielectric spacer material layer 162L can be in the range of 3nm to 10nm, and the thickness of the second dielectric spacer material layer 164L can be in the range of 30nm to 100nm, but smaller and larger thicknesses can be used for each of the first dielectric spacer material layer 162L and the second dielectric spacer material layer 164L.

[0135] Reference Figure 8An anisotropic etching process can be performed to remove the horizontal portions of the at least one dielectric spacer material layer (162L, 164L). The anisotropic etching process for etching the first dielectric spacer material 162 and the second dielectric spacer material 164 can be selective for the materials of the continuous second bottom electrode layer 128L and the top electrode 160. Therefore, the first dielectric sidewall spacer material 162 and the second dielectric sidewall spacer material 164 can be used as etching stops, such that an array of dielectric sidewall spacers (162, 164) can typically be formed around and on the corresponding discrete vertical stacks (130, 140, 146, 148, 158, 160) in an array formed of discrete vertical stacks (130, 140, 146, 148, 158, 160). Each remaining portion of the first dielectric spacer material layer constitutes a first dielectric sidewall spacer 162, and each remaining portion of the second dielectric spacer material layer constitutes a second dielectric sidewall spacer 164. In one embodiment, each discrete vertical stack (130, 140, 146, 148, 158, 160) may be laterally surrounded by the first dielectric sidewall spacer 162 and the second dielectric sidewall spacer 164 to form a sidewall spacer. In another embodiment, the first dielectric spacer 162 may be omitted. In such embodiments, each discrete vertical stack (130, 140, 146, 148, 158, 160) may be laterally surrounded by a single dielectric spacer (i.e., the second dielectric sidewall spacer 164). In this way, the thickness of the top electrode 160 can be maintained because the etching process can be stopped when the first dielectric sidewall spacer material 162 and the second dielectric sidewall spacer material 164, which serve as an etch stop layer, are reached. In other words, the thickness of the top electrode 160 in the finished device is substantially the same as the thickness of the top electrode 160 layer deposited during the manufacture of the memory device, for example, within 1% to 15% of the thickness of the top electrode 160 layer.

[0136] Reference Figure 9 A continuous etch stop layer 170L can be formed on the memory array region 100 and logic region 200 of the memory device through a deposition process. The etch stop dielectric layer 170L contains a dielectric material that can be used as an etch stop material during anisotropic etching processes. The etch stop dielectric layer 170L contains a non-reactive dielectric hard mask material. For example, the continuous etch stop dielectric layer 170L may contain AlO₂. x AlN, HfO x and / or ZrO x And / or can be essentially composed of AlO x AlN, HfO x and / or ZrO xComposition. Other suitable materials with high tolerance to fluorine (F) based etching within the preset scope of the invention may also be used. The etch stop dielectric layer 170L can be deposited by plasma-enhanced chemical vapor deposition (PECVD), high-density plasma chemical vapor deposition (HDP-CVD), or atmospheric pressure chemical vapor deposition (APCVD). The etch stop dielectric layer 170L can be deposited conformally or non-conformally.

[0137] Reference Figure 10 A mask layer 175 can be deposited on top of the etch-stop dielectric layer 170L. In this embodiment, the mask layer 175 is a photoresist. (See reference...) Figure 11 The mask layer 175 can be patterned to expose the portion 177 of the etch stop dielectric layer 170L between memory cells in the memory array region 100, and to expose the etch stop dielectric layer 170L in the logic region 200. The mask layer 175 can be patterned using anisotropic etching methods (e.g., reactive ion etching).

[0138] Reference Figure 12 An etching process can be performed to pattern the continuous second bottom electrode layer 128L, the continuous first bottom electrode material layer 126L, and the continuous metal barrier layer 122L by performing anisotropic etching. In such embodiments, unmasked portions of the continuous metal barrier layer 122L, the continuous first bottom electrode material layer 126L, and the continuous second bottom electrode layer 128L can be removed by the etching process. The etching process can be selective for the material of the via-level dielectric layer 110. The etching process may include anisotropic etching processes (e.g., reactive ion etching) and / or isotropic etching processes (e.g., wet etching). In this way, the bottom electrodes 126 and 128 can be formed without etching the top electrode 160. The mask layer 175 and the etch stop dielectric layer 170 protect the top electrode 160 from thinning during the etching process. Figure 12As shown, the resulting memory cell 101 has a first portion 126 of bottom electrode, a metal barrier layer 122, a second portion 128 of bottom electrode, and an etch stop dielectric layer 170, and includes a flat-top portion 179 extending horizontally beyond the outer periphery of the dielectric sidewall spacers 162 and 164. Therefore, the flat-top portion 179 of the bottom electrode can be formed from the first portion 126 of bottom electrode, the metal barrier layer 122, and the second portion 128 of bottom electrode. In an embodiment, the flat-top portion 179 may extend beyond the outer periphery of the dielectric sidewall spacers 162 and 164. to

[0139] Each patterned portion of the continuous second bottom electrode layer 128L constitutes a second portion 128 of the bottom electrode. Each patterned portion of the continuous first bottom electrode material layer 126L constitutes a first portion 126 of the bottom electrode. Each patterned portion of the continuous metal barrier layer 122L constitutes a metal barrier layer 122. Each vertical stack formed by the second portion 128 of the bottom electrode, the first portion 126 of the bottom electrode, and the metal barrier layer 122 may have vertically overlapping sidewalls located in the same vertical plane. Each consecutive combination of discrete vertical stacks (130, 140, 146, 148, 158, 160), the second bottom electrode layer 128 (which is an optional component), and the first bottom electrode 126 constitutes a memory cell 101, which is a magnetoresistive memory cell. Each combination of the metal barrier layer 122 and the metal via filling material portion 124 constitutes a bottom electrode connection via structure (122, 124), which provides an electrical connection between the corresponding first portion 126 of the bottom electrode and the corresponding fourth metal wire structure 648.

[0140] Typically, an array formed by bottom electrode connection via structures (122, 124) can be formed on one of the corresponding structures under the metal interconnection structure. An array of memory cells 101 can be formed on the array formed by the bottom electrode connection via structures (122, 124). The array formed by memory cells 101 can be formed on the substrate 9 in the memory array region 100. Each of the memory cells 101 may include a vertical stack comprising a first portion 126 of a bottom electrode, memory elements (e.g., magnetic tunnel junctions (143, 146, 148)), and a top electrode 160. Each magnetic tunnel junction (143, 146, 148) may include a vertical stack formed by a reference magnetization layer 143, a non-magnetic tunnel blocking layer 146, and a free magnetization layer 148. In one embodiment, each of the memory cells 101 may include a selector element 130 disposed on the respective magnetic tunnel junction (143, 146, 148). The selector element 130 may be overlaid on or under the respective magnetic tunnel junction (143, 146, 148).

[0141] In an alternative embodiment, patterning of the continuous second bottom electrode layer 128L, the continuous first bottom electrode material layer 126L, and the continuous metal barrier layer 122L may be performed after forming an array of discrete vertical stacks (130, 140, 146, 148, 158, 160) and before forming an array of dielectric sidewall spacers (162, 164). In this case, dielectric sidewall spacers (162, 164) may be formed on the sidewalls of the second portion 128 of the bottom electrode, the first portion 126 of the bottom electrode, and the metal barrier layer 122.

[0142] Reference Figure 13 Another continuous etch-stop dielectric layer 172L can be formed by a deposition process. The continuous etch-stop dielectric layer 172L comprises a dielectric material that can be used as a planarization stop material during a chemical mechanical planarization process and subsequently as an etch-stop material during anisotropic etching processes. The continuous etch-stop dielectric layer 172L comprises a non-reactive dielectric hard mask material. For example, the etch-stop dielectric layer 172L may comprise SiC, SiON, and / or SiN and / or may be substantially composed of SiC, SiON, and / or SiN. Materials of C within the scope of the present invention may also be used. x F y Other suitable materials with high selectivity. The second etch stop dielectric layer 172L can be deposited by plasma-enhanced chemical vapor deposition (PECVD), high-density plasma-enhanced chemical vapor deposition (HDP-CVD), or atmospheric pressure chemical vapor deposition (APCVD). The second etch stop dielectric layer 172L can be deposited conformally or non-conformally.

[0143] The second etch stop dielectric layer 172L can be formed over the first etch stop dielectric layer 170, the array formed by dielectric sidewall spacers (162, 164), and the array formed by memory cells 101. The second etch stop dielectric layer 172L includes a horizontally extending portion and an array of vertically protruding portions. The horizontally extending portion extends continuously throughout the memory array region 100 and into the logic region 200. The vertically protruding portions laterally surround each memory cell 101 in the array formed by the memory cells 101. The thickness of the horizontally extending portion of the second etch stop dielectric layer 172L in the logic region 200 or above the top surface of the top electrode 160 can range from 5 nm to 50 nm, but smaller and larger thicknesses are also possible.

[0144] Reference Figure 14 A first dielectric matrix layer 176 can be formed over the second etch-stop dielectric layer 172L. The first dielectric matrix layer 176 can be formed by a chemical vapor deposition process. In one embodiment, the first dielectric matrix layer 176 comprises a low-k dielectric material with a dielectric constant smaller than that of thermally heated silicon oxide (i.e., 3.9). In one embodiment, the first dielectric matrix layer 176 comprises an extremely low-k (ELK) dielectric material with a dielectric constant less than 2.5. In one embodiment, the first dielectric matrix layer 176 comprises a porous silicon oxide-based dielectric material with a dielectric constant less than 2.5. In this case, the porous silicon oxide-based dielectric material may comprise a SiCO-based material doped with a pore-forming agent and having a porous structure. The porous structure can be formed by incorporating a pore-generating material (pore-forming agent) into a carbon-doped oxide using a chemical vapor deposition process. Chemical vapor deposition processes may include plasma-enhanced chemical vapor deposition (PECVD) or thermochemical vapor deposition. At a wavelength of 632.8 nm (the wavelength of commercially available HeNe laser measuring instruments), the refractive index of the ELK dielectric material in the first dielectric matrix layer 176 can be in the range of 1.0 to 1.4.

[0145] The first portion of the top surface of the first dielectric matrix layer 176 located in the memory array region 100 may have a larger vertical separation distance from the substrate 9 compared to the second portion of the top surface of the first dielectric matrix layer 176 formed in the logic region 200. In other words, the top surface of the first dielectric matrix layer 176 may be higher in the memory array region 100 than in the logic region 200. The first portion of the top surface of the first dielectric matrix layer 176 may include the topmost portion of the top surface of the first dielectric matrix layer 176. The height difference between the first portion of the top surface of the first dielectric matrix layer 176 located in the memory array region 100 and the second portion of the top surface of the first dielectric matrix layer 176 formed in the logic region 200 is attributed to the presence of an array formed by memory cells 101 and an array formed by dielectric sidewall spacers (162, 164) in the memory array region 100.

[0146] During the deposition of the first dielectric matrix layer 176, in the memory array region 100, the profile of the top surface of the first dielectric matrix layer 176 initially follows the profile of the solidly exposed surfaces of the array formed by the memory cells 101 and the array formed by the dielectric sidewall spacers (162, 164). As material portions of the first dielectric matrix layer 176 merge between each pair of adjacent dielectric sidewall spacers (162, 164), the profile of the top surface of the first dielectric matrix layer 176 gradually flattens and bulges as dielectric material is continuously accumulated until the deposition process of the first dielectric matrix layer 176 terminates. In one embodiment, the duration of the deposition process for the first dielectric matrix layer 176 can be selected such that the top surface of the portion of the first dielectric matrix layer 176 in the logic region 200 is in the same horizontal plane as the top surface of the top electrode 160. In other words, the duration of the deposition process for depositing the first dielectric matrix layer 176 can be selected such that the thickness of the first dielectric matrix layer 176 in the logic region 200 is the same as the distance obtained by adding the height of the memory cell 101 and the thickness of the metal barrier layer 122 and then subtracting the thickness of the second etch stop dielectric layer 172 in the logic region 200.

[0147] The height difference between a first portion of the top surface of the first dielectric matrix layer 176 located in the memory array region 100 and a second portion of the top surface of the first dielectric matrix layer 176 formed in the logic region 200 can be in the range of 40% to 100%, for example 70% to 90%, of the vertical distance between a horizontal plane including the top surface of the via-level dielectric layer 110 and a horizontal plane including the top surface of the top electrode 160. In one embodiment, the first dielectric matrix layer 176 may have a vertical variation in height within the memory array region 100. In one embodiment, the height difference between the first portion of the top surface of the first dielectric matrix layer 176 located in the memory array region 100 and the second portion of the top surface of the first dielectric matrix layer 176 formed in the logic region 200 can be in the range of 40 nm to 400 nm, for example 80 nm to 200 nm, but smaller and larger height differences may also be used.

[0148] Reference Figure 15 The first dielectric matrix layer 176 can be planarized by performing a chemical mechanical planarization process. The portion of the first dielectric matrix layer 176 covering the horizontal plane can be removed from the memory array region 100 by the chemical mechanical planarization process. The top surface of the portion of the first dielectric matrix layer 176 in the logic region 200 may be coplanar with the top surface of the top electrode 160 in the logic region 200.

[0149] Reference Figure 16 A trimming planarization process can be performed to remove the portion of the etch stop dielectric layer 172 overlying the top electrode 160 in the memory array region 100. The trimming planarization process can use a dry etching process, which may include anisotropic dry etching (e.g., reactive ion etching) or isotropic dry etching (e.g., chemical dry etching). In this case, the etching chemical of the dry etching process can be selected to selectively remove the material of the etch stop dielectric layer 172 at the same etching rate as the material of the first dielectric matrix layer 176. Alternatively, a trimming chemical mechanical planarization process can be used. In this case, the chemical mechanical planarization process for removing the portion of the first dielectric matrix layer 176 in the memory array region 100 can continue until the portion of the etch stop dielectric layer 172 overlying the top electrode 160 in the memory array region 100 is removed.

[0150] If necessary, a portion of the first dielectric matrix layer 176 located above the horizontal plane including the top surface of the top electrode 160 can be removed in parallel during the trimming planarization process. Typically, the top surface of the top electrode 160 can be substantially exposed during or after the chemical mechanical planarization process that planarizes the first dielectric matrix layer 176.

[0151] Reference Figure 17 A second dielectric matrix layer 178 may be deposited on and directly on the horizontal surface substantially exposed over the remaining portion of the first dielectric matrix layer 176. The second dielectric matrix layer 178 may have the same material composition as the first dielectric matrix layer 176, or it may have a different material composition. In one embodiment, the second dielectric matrix layer 178 may comprise a low dielectric constant (low k) dielectric material, such as an ELK dielectric material with a dielectric constant less than 2.5. In another embodiment, the second dielectric matrix layer 178 comprises a porous silicon oxide-based dielectric material with a dielectric constant less than 2.5. The thickness of the second dielectric matrix layer 178 may be the same as the target height of the metal unit contact structure to be formed on the top surface of the top electrode 160. For example, the second dielectric matrix layer 178 may have a thickness in the range of 20 nm to 160 nm, such as 40 nm to 80 nm, but smaller and larger thicknesses are also possible. In one embodiment, the entire top surface of the second dielectric matrix layer 178 may lie within a first horizontal plane, and the entire bottom surface of the second dielectric matrix layer 178 may lie within a second horizontal plane. Therefore, the entire second dielectric matrix layer 178 may have a uniform thickness throughout.

[0152] Reference Figure 18 A first photoresist layer (not shown) can be applied over a second dielectric substrate layer 178, and the first photoresist layer can be photolithographically patterned to form an array of openings in the logic region 200. The opening pattern in the photoresist layer can be transferred through the second dielectric substrate layer 178, the first dielectric substrate layer 176, and the second etch stop dielectric layer 172. In one embodiment, the second etch stop dielectric layer 172 can serve as an etch stop layer for a first etching step that etches the materials of the second dielectric substrate layer 178 and the first dielectric substrate layer 176, and an etching chemical substance for etching the material of the second etch stop dielectric layer 172 can be used during a second etching step of an anisotropic etching process. A via cavity 181 is formed below each opening in the photoresist layer. The top surface of the via-level dielectric layer 110 can be solidly exposed at the bottom of each via cavity 181. The first photoresist layer can then be removed, for example, by ashing.

[0153] Reference Figure 19A second photoresist layer can be applied over the second dielectric substrate layer 178, and the second photoresist layer can be photolithographically patterned to form a line pattern. The area of ​​the line pattern in the photoresist layer can include all areas of the via cavity 181. Therefore, after developing the second photoresist layer, the second photoresist layer can be removed from inside the via cavity 181. An anisotropic etching process can be performed to transfer the line pattern in the second photoresist layer into the underlying material portion. Each via cavity 181 extends vertically through the via-level dielectric layer 110 and through the dielectric capping layer 108, such that the top surface of the corresponding fourth metal line structure 648 can be solidly exposed below each via cavity 181. Furthermore, portions of the second dielectric substrate layer 178 not masked by the patterned second photoresist layer can be etched through to form a line cavity. Integrated lines and via cavities 183 are formed in the logic region 200. Each integrated line and via cavity 183 may include a corresponding line cavity and at least one via cavity adjacent to the bottom surface of the corresponding line cavity. A cell contact cavity 187 is formed in the memory array region 100 overlying a corresponding one of the top electrodes 160.

[0154] According to aspects of the invention, the anisotropic etching process forming the unit contact cavities 187 and the integrated line and via cavities 183 can selectively etch the material of the etch stop dielectric layer 172. The unit contact cavities 187 can be formed by performing anisotropic etching through a second dielectric matrix layer 178, the anisotropic etching process selectively etching the material of the second dielectric matrix layer 178 to the material of the etch stop dielectric layer 172. In one embodiment, the lateral extent of the unit contact cavities 187 selected from the array formed by the unit contact cavities 187 (hereinafter referred to as first unit contact cavities) can be greater than the lateral extent of the corresponding underlying top electrode 160, i.e., greater than the lateral extent of the top electrode underlying the first unit contact cavity. In one embodiment, a plurality of unit contact cavities 187 can have their own lateral extent, which is greater than the lateral extent of the corresponding top electrode 160. In one embodiment, each of the unit contact cavities 187 can have its own lateral extent, which is greater than the lateral extent of the corresponding underlying top electrode 160. In this case, each unit contact cavity 187 (e.g., the first unit contact cavity) with a lateral extension greater than that of the corresponding underlying top electrode 160 may extend into the upper portion of the first dielectric matrix layer 176, and thus may include a downwardly projecting portion that extends below a horizontal plane including the top surface of the top electrode 160 and overlies a tapered portion of the second etch stop dielectric layer 172.

[0155] In one embodiment, the bottom surface of the wire trench within the integrated wire and via cavity 183 may be formed below the horizontal interface between the first dielectric matrix layer 176 and the second dielectric matrix layer 178. When the bottom surface of the wire trench is vertically recessed below the horizontal interface between the first dielectric matrix layer 176 and the second dielectric matrix layer 178, the vertically protruding portion of the etch stop dielectric layer 172 that laterally surrounds the memory cell 101 serves as an etch stop material portion. Therefore, the cell contact cavity 187 does not extend through the etch stop dielectric layer 172 and does not contact either of the underlying dielectric sidewall spacers (162, 164). Thus, the sidewalls of each layer within each memory cell 101 remain covered by the corresponding one of the dielectric sidewall spacers (162, 164).

[0156] Reference Figure 20 At least one conductive material may be deposited in the wire and via cavity 183 and the unit contact cavity 187. The at least one conductive material may include, for example, a metal liner material (e.g., TiN, TaN, or WN) and a metal filler material (e.g., W, Cu, Co, Ru, Mo, Al, their alloys, and / or their layer stacks). Other suitable materials within the scope of the invention may also be used. Excess portions of the at least one conductive material covering the horizontal plane including the top surface of the second dielectric matrix layer 178 may be removed by a planarization process (e.g., chemical mechanical polishing). Each remaining portion of the integrated wire and via cavity 183 filled with the at least one conductive material constitutes an integrated wire and via structure 184. Each remaining portion of the unit contact cavity 187 filled with the at least one conductive material constitutes a metal unit contact structure 188. The integrated wire and via structure 184, the metal cell contact structure 188, and the bottom electrode connection via structure (122, 124) together constitute the memory cell-level metal interconnect structure (122, 124, 184, 188), which is the metal interconnect structure in the memory cell level located in the volume between the horizontal plane including the top surface of the fourth metal wire structure 648 and the horizontal plane including the top surface of the integrated wire and via structure 184 and the top surface of the metal cell contact structure 188.

[0157] Reference Figure 21Subsequently, additional dielectric material layers and additional metal interconnect structures can be formed as needed. The combination of the dielectric capping layer 108, the via-level dielectric layer 110, the etch stop dielectric layer 172, the first dielectric matrix layer 176, and the second dielectric matrix layer 178 serves as the fifth line and via-level dielectric material layer. A sixth line and via-level dielectric material layer 660 can be formed on the second dielectric matrix layer 178. The fifth metal via structure 662 can be formed in the lower portion of the sixth line and via-level dielectric material layer 660, and the sixth metal line structure 668 can be formed in the upper portion of the sixth line and via-level dielectric material layer 660. A bonding pad (not shown) can be formed on the additional metal interconnect structure.

[0158] Reference Figure 22According to embodiments of the present invention, a general method for forming a memory device is provided. Referring to step 2210, an array of memory elements and a top electrode 160 may be formed in a memory array region 100 on a substrate 9. The memory elements may be magnetic tunnel junctions (143, 146, 148). Referring to step 2220, at least one continuous dielectric sidewall spacer material layer 162L, 164L may be conformally deposited on the memory array region 100. Referring to step 2230, dielectric sidewall spacers 162, 164 may be formed around the periphery of the memory elements by removing portions of the continuous dielectric sidewall spacer material layers 162L, 164L located between the memory elements in an etching process. The continuous dielectric sidewall spacer material layers 162L, 164L may be removed without etching the continuous first bottom electrode material layer 126L, the continuous second bottom electrode layer 128L, and the top electrode 160. Referring to step 2240, an etch stop dielectric layer 170L may be formed over the array formed by the memory elements and the top electrode 160, and over the portion of the continuous bottom electrode layer 128L exposed after the removal of portions of the continuous dielectric spacer material layers 162L and 164L. Referring to step 2250, a mask layer 175 may be formed over the etch stop dielectric layer 170L. The mask layer 175 may be, for example, a photoresist layer. Referring to step 2260, the mask layer 175 may be patterned to expose portions of the etch stop layer 170L located between the memory elements in the array formed by the memory elements. The mask layer 175 may be etched anisotropically. Referring to step 2270, the exposed portion of the etch stop layer 170L and the underlying continuous second bottom electrode layer 128L, continuous first bottom electrode material layer 126L, and continuous metal barrier layer 122L may be etched to form a discrete bottom electrode 126 for each corresponding memory cell 101. The resulting discrete bottom electrode 126 may have a flat-top portion 179. In an embodiment, the exposed portion of the etch stop layer 170L, as well as the underlying continuous second bottom electrode layer 128L, continuous first bottom electrode material layer 126L, and continuous metal barrier layer 122L, can be etched in the same step. In an alternative embodiment, the exposed portion of the etch stop layer 170L can be anisotropically etched in a first etching step, and the underlying continuous second bottom electrode layer 128L, continuous first bottom electrode material layer 126L, and continuous metal barrier layer 122L can be anisotropically etched in a second etching step.

[0159] The embodiment includes a memory device comprising: an array of memory cells 101 overlaid on a substrate 9 and located in a memory array region 100. Each of the memory cells 101 includes a vertical stack comprising bottom electrodes 126, 128, memory elements, a top electrode 160, and dielectric sidewall spacers 162, 164 located on the sidewalls of each vertical stack. The bottom electrode 126 includes a flat-top portion 179 extending horizontally beyond the outer periphery of the dielectric sidewall spacers 162, 164. The memory device further includes: an etch stop dielectric layer 170 over each of the memory cells 101, including a horizontal extension over the flat-top portion 179 of the bottom electrode 126; and metal cell contact structures 188 contacting a corresponding subset of the top electrode 160 and a corresponding subset of the vertical protrusions of the etch stop dielectric layer 170.

[0160] In some embodiments, the thickness of the top electrode in the finished device is the same as the thickness of the top electrode layer deposited during the fabrication of the memory device. In some embodiments, the etch-stop dielectric layer includes a vertical protrusion laterally surrounding each memory cell in the array of memory cells, wherein the vertical protrusion includes an opening at a topmost region and an annular topmost surface located in a horizontal plane including the top surface of the top electrode. In some embodiments, a dielectric layer is further included above the etch-stop dielectric layer, the dielectric layer extending continuously throughout the memory array region and logic region. In some embodiments, memory cell-level interconnect structures are further included located within the logic region. In some embodiments, the etch-stop dielectric layer is substantially composed of aluminum oxide (Al₂O₃). x It is composed of silicon nitride (Si3N4), silicon oxynitride (SiON), silicon carbide (SiC), silicon carbide nitride (SiCN), silicon oxycarbonate (SiOC), or nitrogen-free antireflective layer (NFARL).

[0161] Another embodiment includes a memory device comprising: an array of memory cells 101 overlaid on a substrate 9 and located in a memory array region 100. Each of the memory cells includes a vertical stack comprising bottom electrodes 126, 128, memory elements, a top electrode 160, and dielectric sidewall spacers 162, 164 located on the sidewalls of each vertical stack. The memory elements include magnetic tunnel junctions (143, 146, 148). The bottom electrode 126 includes a flat-top portion 179 extending beyond the outer periphery of the dielectric sidewall spacers 162, 164. The memory device further includes: an etch-stop dielectric 170 over each of the memory cells, including a horizontal extension over the flat-top portion 179 of the bottom electrode 126; and a metal cell contact structure 188 contacting a corresponding subset of the top electrode 160 and a corresponding subset of the vertical protrusions of the etch-stop dielectric layer 170.

[0162] In some embodiments, the magnetic tunnel junction includes a reference magnetization layer, a nonmagnetic tunnel blocking layer, and a free magnetization layer. In some embodiments, the memory element further includes a selector material, a ferromagnetic hard layer, and an antiferromagnetic capping layer. In some embodiments, it further includes a metal interconnect structure formed in a dielectric material layer and located between the substrate and a bottom electrode connector electrically connected to the bottom electrode. In some embodiments, the bottom electrode includes a first portion comprising a first material and a second portion comprising a second material.

[0163] Another embodiment includes a method of fabricating a memory device, comprising: forming an array of stacked memory elements (140, 146, 148) and a top electrode 160 in a memory array region 100 above a substrate; depositing continuous dielectric sidewall spacer material layers 162L, 164L above the memory array region 100; and forming dielectric sidewall spacers 162, 164 on the sidewalls of the memory elements (143, 146, 148) by selectively removing the dielectric sidewall spacer material 162L, 164L between the memory elements (143, 146, 148) in the array of memory elements (143, 146, 148), wherein forming the dielectric sidewall spacers 162, 164 exposes the top surface of a continuous second bottom electrode layer 128L. The method further includes forming an etch stop dielectric layer 170L on the top surface of the array formed by the memory elements (143, 146, 148), the top electrode 160, and the continuous second bottom electrode layer 128L; forming a mask layer 175 on the etch stop dielectric layer 170L; patterning the mask layer 175; and forming bottom electrodes 126 and 128 by etching the continuous second bottom electrode layer 128L, the continuous first bottom electrode material layer 126L, and the continuous metal barrier layer 122L. The bottom electrode 126 includes a flat top portion 179 that extends horizontally beyond the outer periphery of the dielectric sidewall spacers 162 and 164.

[0164] In some embodiments, forming the bottom electrode by etching the continuous first bottom electrode material layer further includes etching a continuous metal barrier layer located beneath the continuous first bottom electrode material layer. In some embodiments, forming the bottom electrode forms a flat-topped second bottom electrode portion and a flat-topped metal barrier portion, the flat-topped second bottom electrode portion and the flat-topped metal barrier portion extending horizontally beyond the outer periphery of the dielectric sidewall spacer. In some embodiments, forming an array of memory cells includes: depositing a continuous second bottom electrode material layer; depositing a continuous selector material layer; depositing a continuous synthetic antiferromagnetic coupling layer; depositing a continuous nonmagnetic tunnel barrier layer; depositing a continuous free magnetization layer; depositing a continuous capping layer; and anisotropically etching the continuous selector material layer, the continuous synthetic antiferromagnetic coupling layer, the continuous nonmagnetic tunnel barrier layer, the continuous free magnetization layer, and the continuous capping layer. In some embodiments, depositing the continuous synthetic antiferromagnetic coupling layer includes: depositing a ferromagnetic hard layer; depositing an antiferromagnetic coupling layer; and depositing a reference magnetization layer. In some embodiments, forming the mask layer includes depositing photoresist. In some embodiments, the method further includes forming a first dielectric substrate layer over the array of memory cells and planarizing the first dielectric substrate layer. In some embodiments, planarizing the first dielectric substrate layer exposes the top surface of the top electrode. In some embodiments, the method further includes: forming a second dielectric substrate layer over the first dielectric substrate layer; patterning the second dielectric substrate layer to form cell contact cavities in the second dielectric substrate layer; and filling the cell contact cavities with a conductive material.

[0165] Referring to all the drawings and various embodiments of the invention, a memory device and a method of manufacturing the memory device are provided, wherein the thickness of the top electrode 160 is substantially maintained (i.e., not thinned) during further fabrication of the memory device. Specifically, dielectric sidewall spacers 162, 164 can be formed on the sidewalls of the memory elements (143, 146, 148) by selectively etching continuous dielectric spacer material layers 162L, 164L. Selective etching exposes the top surface of the top electrode 160, but causes little or no thinning of the top electrode 160. To further protect the thickness of the top electrode 160, an etch stop dielectric layer 170L and a mask layer 175 can be formed over the array formed by the memory elements (143, 146, 148) and the top electrode 160 before etching the bottom electrode material layer 126L to form the bottom electrode 126. In this way, the bottom electrode 126 can be formed while the top electrode 160 is protected by the etch stop dielectric layer 170L and the mask layer 175. As a result of the processing operation, a flat-top portion 179 is formed of the bottom electrode 126, which extends horizontally beyond the outer periphery of the dielectric sidewall spacers 162, 164.

[0166] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the invention. Those skilled in the art will understand that they can easily use this invention as a basis to design or modify other processes and structures to achieve the same objectives and / or advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made to this document without departing from the spirit and scope of the invention.

Claims

1. A memory device, comprising: The bottom electrode is connected to a via structure that penetrates the via-level dielectric layer on the substrate. An array of memory cells is vertically formed on an array formed by the bottom electrode connection via structure. The array of memory cells is located in a memory array region. Each of the memory cells includes a bottom electrode covering the top surface of the bottom electrode connection via structure, a memory element, a vertical stack of top electrodes, and dielectric sidewall spacers on the sidewalls of each memory element and the top electrode. The top electrode and the memory element are vertically and overlappingly disposed on the bottom electrode connection via structure. The bottom electrode includes a flat-top portion that extends horizontally beyond the outer periphery of the dielectric sidewall spacer, which extends over the flat-top portion of the bottom electrode. An etch stop dielectric layer is formed on each of the memory cells, including a horizontal extension extending over the flat top portion of the bottom electrode and a vertical protrusion laterally surrounding the outer periphery of the memory cell and the dielectric sidewall spacer. as well as The metal unit contact structure contacts the vertical protrusion of the top electrode and the etch stop dielectric layer. The metal unit contact structure includes a downwardly protruding portion that extends downward from a horizontal plane on the top surface of the top electrode, surrounds the outer periphery of the etch stop dielectric layer and does not contact the dielectric sidewall spacer, and is spaced apart from the dielectric sidewall spacer by the etch stop dielectric layer.

2. The memory device of claim 1, wherein the thickness of the top electrode in the finished device is the same as the thickness of the top electrode layer deposited during the manufacture of the memory device, and the lateral extension of the metal cell contact structure is greater than the lateral extension of the top electrode and less than the lateral extension of the flat-top portion of the bottom electrode.

3. The memory device of claim 1, wherein the vertical protrusion includes an opening at the topmost region and an annular topmost surface located in a horizontal plane including the top surface of the top electrode.

4. The memory device of claim 1, further comprising a dielectric layer above the etch stop dielectric layer, the dielectric layer extending continuously throughout the memory array region and the logic region.

5. The memory device according to claim 4, further comprising a memory cell-level interconnection structure located in the logic region.

6. The memory device of claim 1, wherein the etch stop dielectric layer is composed of aluminum oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxynitride, silicon carbide, or a nitrogen-free antireflective layer.

7. A memory device, comprising: The bottom electrode is connected to a via structure that penetrates the via-level dielectric layer on the substrate. An array of memory cells is vertically formed on an array formed by the bottom electrode connection via structure, the array of memory cells being located in a memory array region. Each of the memory cells includes a bottom electrode covering the top surface of the bottom electrode connection via structure, a memory element, a vertical stack of top electrodes, and dielectric sidewall spacers located on the sidewalls of each memory element and the top electrode. The memory element includes a magnetic tunnel junction. The top electrode and the memory element are vertically and overlappingly disposed on the bottom electrode connection via structure, and the bottom electrode includes a flat-top portion extending beyond the outer periphery of the dielectric sidewall spacer, the dielectric sidewall spacer extending over the flat-top portion of the bottom electrode. An etch stop dielectric layer is formed on each of the memory cells, including a horizontal extension extending over the flat top portion of the bottom electrode and a vertical protrusion laterally surrounding the outer periphery of the memory cell and the dielectric sidewall spacer. as well as The metal unit contact structure contacts the vertical protrusion of the top electrode and the etch stop dielectric layer. The dielectric sidewall spacer includes a first dielectric sidewall spacer and a second dielectric sidewall spacer. The first dielectric sidewall spacer contacts each of the bottom electrode, the memory element, and the top electrode. The second dielectric sidewall spacer is located on the outer sidewall of the first dielectric sidewall spacer and does not contact the bottom electrode. The metal unit contact structure includes a downwardly protruding portion that extends downward from a horizontal plane on the top surface of the top electrode. The downwardly protruding portion surrounds the outer periphery of the etch stop dielectric layer and does not contact the first dielectric sidewall spacer and the second dielectric sidewall spacer. The downwardly protruding portion is spaced apart from the first dielectric sidewall spacer and the second dielectric sidewall spacer by the etch stop dielectric layer.

8. The memory device of claim 7, wherein the magnetic tunnel junction comprises a reference magnetization layer, a non-magnetic tunnel blocking layer, and a free magnetization layer.

9. The memory device of claim 8, wherein the memory element further comprises a selector material, a ferromagnetic hard layer, and an antiferromagnetic capping layer.

10. The memory device of claim 7, further comprising a metal interconnect structure formed in a dielectric material layer and located between the substrate and a via structure electrically connected to the bottom electrode.

11. The memory device of claim 7, wherein the bottom electrode comprises a first portion comprising a first material and a second portion comprising a second material.

12. A method of forming a memory device, comprising: Form a via-level dielectric layer on the substrate; A bottom electrode connection via structure is formed that penetrates the via-level dielectric layer; Memory elements and top electrodes are vertically formed on the array formed by the bottom electrode connecting through-hole structure, which is located in the memory array region. A continuous dielectric sidewall spacer material layer is deposited above the memory array region; Dielectric sidewall spacers are formed on the sidewalls of the memory cells by selectively removing dielectric sidewall spacer material between the memory cells in the array of memory cells, wherein forming the dielectric sidewall spacers exposes the top surface of a continuous second bottom electrode material layer. A first etch stop dielectric layer is formed above the top surface of the array of memory cells, the top electrode, and the continuous second bottom electrode material layer; A mask layer is formed above the first etch stop dielectric layer; The mask layer is patterned; A bottom electrode is formed by etching a first etch stop dielectric layer, a continuous second bottom electrode material layer, and a continuous first bottom electrode material layer, wherein the bottom electrode covers the top surface of the bottom electrode connection via structure, the top electrode and the memory element are vertically and overlappingly disposed on the bottom electrode connection via structure, and the bottom electrode includes a flat top portion that extends horizontally beyond the outer periphery of the dielectric sidewall spacer, and wherein the first etch stop dielectric layer includes a horizontally extending portion extending above the flat top portion of the bottom electrode and a vertically protruding portion that laterally surrounds the outer periphery of the memory cell and the dielectric sidewall spacer, and the dielectric sidewall spacer extends on the flat top portion of the bottom electrode; A second etch stop dielectric layer is formed on top of the first etch stop dielectric layer; A first dielectric matrix layer is formed above the second etch stop dielectric layer, exposing the top surface of the top electrode; A second dielectric matrix layer is formed above the top electrode and the first dielectric matrix layer; A unit contact cavity is formed by etching the second dielectric matrix layer, the unit contact cavity exposing the top electrode and extending downward from a horizontal plane of the top surface; as well as The unit contact cavity is filled to form a metal unit contact structure, wherein the metal unit contact structure contacts the top electrode and the vertical protrusion of the first etch stop dielectric layer, and the metal unit contact structure includes a downward protrusion extending downward from the horizontal plane of the top surface of the top electrode, the downward protrusion surrounding the outer periphery of the first etch stop dielectric layer and not contacting the dielectric sidewall spacer, and the downward protrusion is spaced apart from the dielectric sidewall spacer by the first etch stop dielectric layer.

13. The method of claim 12, wherein forming the bottom electrode by etching the first etch stop dielectric layer, the continuous second bottom electrode material layer and the continuous first bottom electrode material layer further comprises etching a continuous metal barrier layer located beneath the continuous first bottom electrode material layer.

14. The method of claim 13, wherein the flat-top portion forming the bottom electrode includes a second bottom electrode portion forming the flat top and a metal blocking portion forming the flat top, the second bottom electrode portion forming the flat top and the metal blocking portion forming the flat top extending horizontally beyond the outer periphery of the dielectric sidewall spacer.

15. The method of claim 12, wherein forming the array of memory cells comprises: Deposit the continuous second bottom electrode material layer; Deposit a continuous selector material layer; Depositing a continuous synthesis of antiferromagnetic coupling layers; Deposit a continuous nonmagnetic tunnel barrier layer; Deposit a continuous free magnetization layer; Deposition of a continuous caprock; as well as The continuous selector material layer, the continuous synthetic antiferromagnetic coupling layer, the continuous nonmagnetic tunneling barrier layer, the continuous free magnetization layer, and the continuous top cap layer are anisotropically etched.

16. The method of claim 15, wherein depositing the continuously synthesized antiferromagnetic coupling layer comprises: Depositing a ferromagnetic hard layer; Deposit an antiferromagnetic coupling layer; Deposit a reference magnetization layer.

17. The method of claim 12, wherein forming the mask layer comprises depositing photoresist.

18. The method of claim 12, further comprising planarizing the first dielectric matrix layer.

19. The method of claim 18, wherein planarizing the first dielectric matrix layer exposes the top surface of the top electrode.

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