Display device

Abstract

A display device of the present application includes a first substrate having a display region and a non-display region on one side of the display region; a second substrate disposed opposite the first substrate; a display element disposed on the display region and including a pixel electrode, an intermediate layer disposed on the pixel electrode, and a counter electrode disposed on the intermediate layer; a power supply line disposed on the non-display region; and a conductive layer disposed on the power supply line and including the same substance as the pixel electrode.

Description

Technical Field

[0001] This invention relates to display devices, and more specifically to display devices that improve the reliability of products. Background Technology

[0002] Recently, display devices have been diversifying their applications, with a trend towards thinner and lighter devices, and a wider range of uses.

[0003] Typically, a display device forms thin-film transistors and display elements (e.g., organic light-emitting diodes) on a first substrate, with the display elements emitting light to operate. Such display devices can be used as display units for small products such as mobile phones, as well as for large products such as televisions.

[0004] The display device is sealed by irradiating a laser after a first substrate and a second substrate, which are configured with thin-film transistors and display elements, are joined together, thereby preventing display elements such as organic light-emitting diodes (OLEDs) from being exposed to external air and moisture.

[0005] However, in existing display devices, when lasers are used to seal display elements such as organic light-emitting diodes (OLEDs), heat can damage the underlying metal wiring, potentially causing short circuits. Summary of the Invention

[0006] This invention addresses various problems, including those described above, and aims to provide a display device that improves reliability by preventing short circuits between adjacent wirings. However, these issues are illustrative and are not intended to limit the scope of the invention.

[0007] According to one aspect of the present invention, a display device is provided, comprising: a first substrate having a display area and a non-display area on one side of the display area; a second substrate disposed opposite to the first substrate; a display element disposed on the display area and including a pixel electrode, an intermediate layer disposed on the pixel electrode and a counter electrode disposed on the intermediate layer; a power supply line disposed on the non-display area; and a conductive layer disposed on the power supply line and comprising the same material as the pixel electrode.

[0008] According to this embodiment, the power supply line may include a first power supply line and a second power supply line configured to be away from the first power supply line, and the conductive layer is disposed on the second power supply line.

[0009] According to this embodiment, the conductive layer may be directly disposed on the second power supply line.

[0010] According to this embodiment, the conductive layer may cover the upper surface and both sides of the second power supply line.

[0011] According to this embodiment, it may further include: a sealing portion configured in the non-display area to surround the outline of the display area, thereby joining the first substrate and the second substrate.

[0012] According to this embodiment, at least a portion of the sealing portion may overlap with the second power supply line.

[0013] According to this embodiment, the sealing part may be in direct contact with the conductive layer.

[0014] According to this embodiment, the power supply line may include at least one of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti).

[0015] According to this embodiment, the conductive layer may include at least one substance selected from silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), and chromium (Cr).

[0016] According to this embodiment, the conductive layer may include at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO).

[0017] According to this embodiment, the conductive layer may have a stacked structure of indium tin oxide (ITO) / silver (Ag) / indium tin oxide (ITO).

[0018] According to this embodiment, the conductive layer may cover at least a portion of the upper surface and both sides of the second power supply line.

[0019] According to this embodiment, the conductive layer may include an opening that exposes at least a portion of the upper surface of the second power supply line.

[0020] According to this embodiment, the conductive layer may cover at least a portion of the upper surface of the second power supply line and the side of the second power supply line adjacent to the first power supply line.

[0021] According to another aspect of the present invention, a display device is provided, comprising: a first substrate having a display area and a non-display area on one side of the display area; a second substrate disposed opposite to the first substrate; a display element disposed on the display area and including a pixel electrode, an intermediate layer disposed on the pixel electrode, and a counter electrode disposed on the intermediate layer; a power supply line disposed on the non-display area and including a first power supply line and a second power supply line disposed away from the first power supply line; a conductive layer disposed on the second power supply line and comprising the same material as the pixel electrode; and a sealing portion disposed in the non-display area to surround the outline of the display area, thereby joining the first substrate and the second substrate.

[0022] According to this embodiment, the conductive layer may cover the upper surface and both sides of the second power supply line.

[0023] According to this embodiment, at least a portion of the sealing portion may overlap with the second power supply line.

[0024] According to this embodiment, the sealing part may be in direct contact with the conductive layer.

[0025] According to this embodiment, the power supply line may include at least one of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti).

[0026] According to this embodiment, the conductive layer may have a stacked structure of indium tin oxide (ITO) / silver (Ag) / indium tin oxide (ITO).

[0027] Other aspects, features, and advantages beyond those described above will become clearer from the following detailed description, claims, and drawings.

[0028] (Invention Effects)

[0029] According to one embodiment of the present invention configured as described above, by using a conductive layer to cover (cladding) the power supply lines, short circuits can be prevented between adjacent wires, thereby enabling a display device with improved reliability. Of course, this effect is not intended to limit the scope of the invention. Attached Figure Description

[0030] Figure 1 This is a perspective view schematically illustrating a display device according to an embodiment of the present invention.

[0031] Figure 2 This is a schematic plan view of a display panel according to an embodiment of the present invention.

[0032] Figure 3 and Figure 4 This is an equivalent circuit diagram of pixels that may be included in a display device according to an embodiment of the present invention.

[0033] Figure 5 This is a schematic cross-sectional view illustrating a display device according to an embodiment of the present invention.

[0034] Figure 6 This is a schematic enlarged plan view showing a portion of a display device according to an embodiment of the present invention.

[0035] Figure 7 This is a schematic cross-sectional view illustrating a display device according to an embodiment of the present invention.

[0036] Figure 8 This is a schematic cross-sectional view illustrating a display device according to an embodiment of the present invention.

[0037] Figure 9 This is a schematic enlarged plan view showing a portion of a display device according to an embodiment of the present invention.

[0038] Figure 10 This is a schematically enlarged cross-sectional view showing a portion of a display device according to an embodiment of the present invention.

[0039] Figure 11 This is a schematic enlarged plan view showing a portion of a display device according to an embodiment of the present invention.

[0040] Figure 12 This is a schematically enlarged cross-sectional view showing a portion of a display device according to an embodiment of the present invention.

[0041] (Symbol Explanation)

[0042] 1: Display device; 100: First substrate; 101: Buffer layer; 103: First insulating layer; 105: Second insulating layer; 107: Third insulating layer; 113: Planarization layer; 160: First power supply line; 170: Second power supply line; 210: Pixel electrode; 215: Conductive layer; 300: Second substrate; 400: Sealing portion. Detailed Implementation

[0043] This invention can have various modifications and embodiments. Specific embodiments are illustrated in the accompanying drawings, which are described in detail below. References and Appendix Figure 1 The effects, features, and methods of achieving these effects and features of the invention will become clear from the detailed embodiments described below. However, the invention is not limited to the embodiments disclosed below and can be implemented in various ways.

[0044] Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings. When describing with reference to the drawings, the same or corresponding constituent elements will be given the same reference numerals, and repeated descriptions thereof will be omitted.

[0045] In the following embodiments, terms such as "first," "second," etc., are not limiting terms but are used to distinguish one constituent element from others. Furthermore, singular expressions include multiple expressions unless explicitly stated otherwise in the text.

[0046] On the other hand, terms such as "including" or "having" should be understood as referring to the presence of features or constituent elements described in the specification, and not as excluding the possibility of additional features or constituent elements. Furthermore, when a membrane, region, constituent element, etc., is located on or above other parts, this includes not only cases where it is directly located on other parts, but also cases where other membranes, regions, constituent elements, etc., exist between them.

[0047] In the accompanying drawings, the sizes of the constituent elements may be enlarged or reduced for ease of illustration. For example, the sizes and thicknesses of the constituent elements shown are for illustrative purposes only, and the invention is not necessarily limited to the illustrated cases.

[0048] The x-axis, y-axis, and z-axis are not limited to the three axes of a Cartesian coordinate system; they can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be orthogonal to each other, or they can refer to different directions that are not orthogonal to each other.

[0049] In cases where a particular embodiment can be implemented in different ways, the order of operations can also be performed differently than described. For example, two operations described consecutively can be performed substantially simultaneously, or they can be performed in the reverse order described.

[0050] Figure 1 This is a perspective view schematically illustrating a display device according to an embodiment of the present invention.

[0051] Reference Figure 1 The display device 1 includes a display area DA for displaying an image and a non-display area NDA for not displaying an image. The non-display area NDA may be disposed on one side of the display area DA. The display device 1 can provide an image to the outside using light emitted from the display area DA.

[0052] exist Figure 1 The diagram shows a display device 1 with a quadrilateral display area DA, but the invention is not limited thereto. The shape of the display area DA can be a circle, ellipse, triangle, pentagon, or other polygonal shape. Furthermore, the diagram shows... Figure 1The display device 1 is a flat panel display device, but the display device 1 can of course also be a flexible, foldable, rollable or other forms of display device.

[0053] Although not shown, the display device 1 may include a display panel 10 ( Figure 2 A component (not shown) on one side of the device. The component can be an electronic element that utilizes light or sound. For example, the electronic element can be a sensor that receives and utilizes light, such as an infrared sensor; a camera that receives light to capture an image; a sensor that outputs light or sound and senses it to measure distance or identify fingerprints; a small lamp that outputs light; or a speaker that outputs sound.

[0054] Hereinafter, as an embodiment of the present invention, the display device 1 will be described using an organic light-emitting display device as an example; however, the display device of the present invention is not limited thereto. In other embodiments, the display device 1 of the present invention may be an inorganic light-emitting display device (or inorganic EL display device) or a quantum dot light-emitting display device. For example, the light-emitting layer of the display elements provided by the display device 1 may include organic matter, or inorganic matter, or quantum dots, or a combination of organic matter and quantum dots, or a combination of inorganic matter and quantum dots.

[0055] Figure 2 This is a schematic plan view of a display panel 10 according to an embodiment of the present invention.

[0056] Reference Figure 2 The display device 1 includes a display panel 10. A plurality of pixels P are disposed in the display area DA of the first substrate 100. The plurality of pixels P may each include, for example, an organic light-emitting diode (OLED) (see reference). Figure 3 These are display elements. Each pixel P can emit light, such as red, green, blue, or white, through an organic light-emitting diode (OLED).

[0057] A second substrate 300 may be provided on the upper part of the first substrate 100. The second substrate 300 is configured to face the first substrate 100 and sandwich the constituent elements formed on the first substrate 100 therebetween.

[0058] The second substrate 300 can be joined to the first substrate 100 via a sealing portion 400 located in the non-display area NDA to surround the outer contour of the display area DA, thereby sealing the display area DA from the outside and preventing display elements such as organic light-emitting diodes (OLEDs) from being exposed to external air and moisture. The sealing portion 400 can be implemented, for example, using glass material.

[0059] As an alternative embodiment, the display area DA may be covered by a thin-film encapsulation layer (not shown) instead of the second substrate 300, thereby protecting the display area DA from external air or moisture. The thin-film encapsulation layer may be integrally disposed corresponding to the entire surface of the display area DA, or a portion thereof may be disposed on the non-display area NDA. The thin-film encapsulation layer may be disposed to cover a portion or all of the first scan driving circuit 110, the first light-emitting driving circuit 115, the second scan driving circuit 120, the first power supply line 160, and the second power supply line 170, as described later.

[0060] Organic light-emitting diodes (OLEDs) are less susceptible to external factors such as moisture and oxygen, and the reliability of the display panel 10 can be improved by sealing the OLEDs. By replacing the second substrate 300 with a thin-film encapsulation layer, the thickness of the display panel 10 can be reduced while improving flexibility.

[0061] Each pixel P can be electrically connected to the outline circuitry configured in the non-display area NDA. The non-display area NDA can be configured with a first scan driving circuit 110, a first light-emitting driving circuit 115, a second scan driving circuit 120, a data driving circuit 150, a first power supply line 160, and a second power supply line 170.

[0062] The first scan driving circuit 110 can provide scan signals to each pixel P via scan line SL. The first light-emitting driving circuit 115 can provide light-emitting control signals to each pixel P via light-emitting control line EL. The second scan driving circuit 120 can be arranged side by side with the first scan driving circuit 110, sandwiching the display area DA. A portion of the pixels P disposed in the display area DA can be electrically connected to the first scan driving circuit 110, and the remaining pixels P can be electrically connected to the second scan driving circuit 120. As an embodiment, the second light-emitting driving circuit (not shown) can be arranged side by side with the first light-emitting driving circuit 115, sandwiching the display area DA.

[0063] The first light-emitting driving circuit 115 can be disposed on the non-display area NDA, away from the first scanning driving circuit 110 in the x-direction. As an embodiment, the first light-emitting driving circuit 115 can be disposed alternately with the first scanning driving circuit 110 in the y-direction.

[0064] Terminal 140 may be disposed on one side of the first substrate 100. Terminal 140 is not covered by an insulating layer but is exposed, thereby allowing electrical connection to a printed circuit board (PCB). Terminal PCB-P of the printed circuit board (PCB) may be electrically connected to terminal 140 of the display panel 10. The printed circuit board (PCB) transmits signals or power from the control unit (not shown) to the display panel 10.

[0065] The control signals generated by the control unit can be transmitted to the first scan driving circuit 110, the second scan driving circuit 120, and the first light-emitting driving circuit 115 via the printed circuit board (PCB). The control unit can supply the first power supply voltage ELVDD (see figure) to the first power supply line 160 and the second power supply line 170 via connecting wiring (not shown). Figure 3 ) and the second power supply voltage ELVSS (refer to Figure 3 The first power supply voltage ELVDD can be provided to each pixel P through the drive voltage line PL connected to the first power supply line 160, and the second power supply voltage ELVSS can be provided to the counter electrode of each pixel P connected to the second power supply line 170.

[0066] The first power supply line 160 may include sub-wires (not shown) extending side-by-side along the x-direction and sandwiching the display area DA in between. The second power supply line 170 may partially surround the display area DA in a ring shape with one side open.

[0067] The data driving circuit 150 is electrically connected to the data line DL. The data signal of the data driving circuit 150 can be provided to each pixel P through the connection wiring 151 connected to the terminal 140 and the data line DL connected to the connection wiring 151. Figure 2 The illustration shows the data driving circuit 150 disposed on a printed circuit board (PCB), but as an embodiment, the data driving circuit 150 may be disposed on the first substrate 100. For example, the data driving circuit 150 may be disposed between terminal 140 and the first power supply line 160.

[0068] Figure 3 and Figure 4 This is an equivalent circuit diagram of pixels that may be included in a display device according to an embodiment of the present invention.

[0069] Reference Figure 3 Each pixel P includes a pixel circuit PC connected to the scan line SL and the data line DL, and an organic light-emitting diode (OLED) connected to the pixel circuit PC.

[0070] The pixel circuit PC includes a driving thin-film transistor T1, a switching thin-film transistor T2, and an energy storage capacitor Cst. The switching thin-film transistor T2 is connected to the scan line SL and the data line DL, and transmits the data signal Dm input through the data line DL to the driving thin-film transistor T1 according to the scan signal Sn input through the scan line SL.

[0071] The energy storage capacitor Cst is connected to the switching thin-film transistor T2 and the drive voltage line PL, and stores a voltage equivalent to the difference between the voltage transmitted from the switching thin-film transistor T2 and the first power supply voltage (or drive voltage) ELVDD supplied to the drive voltage line PL.

[0072] The driving thin-film transistor T1 is connected to the driving voltage line PL and the energy storage capacitor Cst. The driving current flowing from the driving voltage line PL to the organic light-emitting diode (OLED) can be controlled according to the voltage value stored in the energy storage capacitor Cst. The OLED can then emit light with a predetermined brightness based on the driving current.

[0073] exist Figure 3 The diagram illustrates a pixel circuit PC comprising two thin-film transistors and one energy storage capacitor, but the invention is not limited thereto. For example... Figure 4 As shown, the pixel circuit PC may include seven thin-film transistors and one energy storage capacitor.

[0074] Reference Figure 4 Each pixel P includes a pixel circuit PC and an organic light-emitting diode (OLED) connected to the pixel circuit PC. The pixel circuit PC may include multiple thin-film transistors and storage capacitors. The thin-film transistors and storage capacitors may be connected to signal lines (SL, SL-1, EL, DL), initialization voltage line VL, and drive voltage line PL.

[0075] exist Figure 4 The diagram illustrates the connection of each pixel P to signal lines (SL, SL-1, EL, DL), initialization voltage line VL, and drive voltage line PL, but the invention is not limited thereto. As an embodiment, adjacent pixels may share at least one of the signal lines (SL, SL-1, EL, DL), the initialization voltage line VL, and the drive voltage line PL.

[0076] The multiple thin-film transistors may include a driving thin-film transistor (TFT) T1, a switching thin-film transistor (TFT) T2, a compensation thin-film transistor T3, a first initialization thin-film transistor T4, an operation control thin-film transistor T5, a light emission control thin-film transistor T6, and a second initialization thin-film transistor T7.

[0077] The signal lines include a scan line SL that transmits the scan signal Sn, a previous scan line SL-1 that transmits the previous scan signal Sn-1 to the first initialization thin-film transistor T4 and the second initialization thin-film transistor T7, an emission control line EL that transmits the emission control signal En to the operation control thin-film transistor T5 and the emission control thin-film transistor T6, and a data line DL that intersects the scan line SL and transmits the data signal Dm. The drive voltage line PL transmits the drive voltage ELVDD to the drive thin-film transistor T1, and the initialization voltage line VL transmits the initialization voltage Vint that initializes the drive thin-film transistor T1 and the pixel electrode.

[0078] The driving gate electrode G1 of the driving thin-film transistor T1 is connected to the first energy storage plate Cst1 of the energy storage capacitor Cst. The driving source electrode S1 of the driving thin-film transistor T1 is connected to the lower driving voltage line PL via the operation control thin-film transistor T5. The driving drain electrode D1 of the driving thin-film transistor T1 is electrically connected to the pixel electrode of the organic light-emitting diode (OLED) via the light-emitting control thin-film transistor T6. The driving thin-film transistor T1 receives the data signal Dm according to the switching operation of the switching thin-film transistor T2, thereby supplying a driving current I to the OLED. OLED .

[0079] The switching gate electrode G2 of the switching thin-film transistor T2 is connected to the scan line SL, the switching source electrode S2 of the switching thin-film transistor T2 is connected to the data line DL, and the switching drain electrode D2 of the switching thin-film transistor T2 is connected to the driving source electrode S1 of the driving thin-film transistor T1, while simultaneously being connected to the lower driving voltage line PL via the operation control thin-film transistor T5. The switching thin-film transistor T2 performs the following switching operation: when the scan signal Sn transmitted through the scan line SL is turned on, the data signal Dm transmitted to the data line DL is transmitted to the driving source electrode S1 of the driving thin-film transistor T1.

[0080] The compensation gate electrode G3 of the compensation thin-film transistor T3 is connected to the scan line SL. The compensation source electrode S3 of the compensation thin-film transistor T3 is connected to the driving drain electrode D1 of the driving thin-film transistor T1, and simultaneously connected to the pixel electrode of the organic light-emitting diode (OLED) via the light-emitting control thin-film transistor T6. The compensation drain electrode D3 of the compensation thin-film transistor T3 is connected to the first energy storage plate Cst1 of the energy storage capacitor Cst, the first initialization drain electrode D4 of the first initialization thin-film transistor T4, and the driving gate electrode G1 of the driving thin-film transistor T1. The compensation thin-film transistor T3 is turned on according to the scan signal Sn transmitted through the scan line SL, electrically connecting the driving gate electrode G1 and the driving drain electrode D1 of the driving thin-film transistor T1, thereby providing a diode connection to the driving thin-film transistor T1.

[0081] The first initialization gate electrode G4 of the first initialization thin-film transistor T4 is connected to the previous scan line SL-1. The first initialization source electrode S4 of the first initialization thin-film transistor T4 is connected to the second initialization drain electrode D7 and the initialization voltage line VL of the second initialization thin-film transistor T7. The first initialization drain electrode D4 of the first initialization thin-film transistor T4 is connected to the first energy storage plate Cst1 of the energy storage capacitor Cst, the compensation drain electrode D3 of the compensation thin-film transistor T3, and the driving gate electrode G1 of the driving thin-film transistor T1. The first initialization thin-film transistor T4 performs an initialization operation, that is, according to the previous scan signal Sn-1 transmitted through the previous scan line SL-1 being turned on, the initialization voltage Vint is transmitted to the driving gate electrode G1 of the driving thin-film transistor T1 to initialize the voltage of the driving gate electrode G1 of the driving thin-film transistor T1.

[0082] The operation control gate electrode G5 of the operation control thin film transistor T5 is connected to the light emission control line EL, the operation control source electrode S5 of the operation control thin film transistor T5 is connected to the lower driving voltage line PL, and the operation control drain electrode D5 of the operation control thin film transistor T5 is connected to the driving source electrode S1 of the driving thin film transistor T1 and the switching drain electrode D2 of the switching thin film transistor T2.

[0083] The light-emitting control gate electrode G6 of the light-emitting control thin-film transistor T6 is connected to the light-emitting control line EL. The light-emitting control source electrode S6 of the light-emitting control thin-film transistor T6 is connected to the driving drain electrode D1 of the driving thin-film transistor T1 and the compensation source electrode S3 of the compensation thin-film transistor T3. The light-emitting control drain electrode D6 of the light-emitting control thin-film transistor T6 is electrically connected to the second initialization source electrode S7 of the second initialization thin-film transistor T7 and the pixel electrode of the organic light-emitting diode OLED.

[0084] The operation control thin-film transistor T5 and the light-emitting control thin-film transistor T6 are simultaneously turned on according to the light-emitting control signal En transmitted through the light-emitting control line EL, transmitting the driving voltage ELVDD to the organic light-emitting diode OLED to drive the driving current I. OLED It flows through an organic light-emitting diode (OLED).

[0085] The second initialization gate electrode G7 of the second initialization thin film transistor T7 is connected to the previous scan line SL-1. The second initialization source electrode S7 of the second initialization thin film transistor T7 is connected to the light emission control drain electrode D6 of the light emission control thin film transistor T6 and the pixel electrode of the organic light emitting diode OLED. The second initialization drain electrode D7 of the second initialization thin film transistor T7 is connected to the first initialization source electrode S4 of the first initialization thin film transistor T4 and the initialization voltage line VL. The second initialization thin film transistor T7 is turned on according to the previous scan signal Sn-1 transmitted through the previous scan line SL-1, thereby initializing the pixel electrode of the organic light emitting diode OLED.

[0086] In Figure 4 the connection of the first initialization thin film transistor T4 and the second initialization thin film transistor T7 to the previous scan line SL-1 is shown, but the present invention is not limited thereto. As an embodiment, the first initialization thin film transistor T4 may be connected to the previous scan line SL-1 and driven according to the previous scan signal Sn-1, and the second initialization thin film transistor T7 may be connected to other signal lines (for example, the next scan line) and driven according to the signal transmitted to the other signal lines.

[0087] The second energy storage plate Cst2 of the energy storage capacitor Cst is connected to the driving voltage line PL, and the counter electrode of the organic light emitting diode OLED is connected to the common voltage ELVSS. Thus, the organic light emitting diode OLED can receive the driving current I OLED transmitted from the driving thin film transistor T1 and emit light, thereby displaying an image.

[0088] In Figure 4 the case where the compensation thin film transistor T3 and the first initialization thin film transistor T4 have double gate electrodes is illustrated, but the compensation thin film transistor T3 and the first initialization thin film transistor T4 may have one gate electrode.

[0089] Figure 5 is a cross-sectional view schematically showing a display device according to an embodiment of the present invention. Figure 5 Corresponding to Figure 1 I-I′ of

[0090] Referring to Figure 5 , the display device 1 includes a display area DA and a non-display area NDA on one side of the display area DA. The first substrate 100 and the second substrate 300 surround the display area DA and are joined by a sealing portion 400 located in the non-display area NDA.

[0091] The first substrate 100 can be formed of various materials, such as glass, metal, or plastic materials like polyethylene terephthalate, polyethylene naphthalate, and polyimide. The second substrate 300 can include a transparent material. For example, the second substrate 300 can be formed of various materials, such as glass, or plastic materials like polyethylene terephthalate, polyethylene naphthalate, and polyimide. The first substrate 100 and the second substrate 300 can include the same material, or they can include different materials.

[0092] Reference Figure 5 The display area DA can have a buffer layer 101 formed on the first substrate 100. The buffer layer 101 can block foreign matter or moisture from penetrating through the first substrate 100. For example, the buffer layer 101 may include silicon oxide (SiO2). x ), silicon nitride (SiN) x Inorganic materials such as silicon oxynitride (SiON) and / or silicon oxynitride (SiON) can be formed from a single layer or multiple layers.

[0093] On the first substrate 100, thin-film transistors (TFTs) and energy storage capacitors (Cst) located at positions corresponding to the display area DA, as well as display elements 200 electrically connected to them, such as organic light-emitting diodes (OLEDs), may be provided. Figure 4 ). Figure 5 Thin-film transistors (TFTs) can, for example, be equivalent to a reference. Figure 4 The pixel circuit PC described herein includes one of the thin-film transistors, for example, the driving thin-film transistor T1. Figure 5 The energy storage capacitor Cst can be equivalent to a reference. Figure 4 The energy storage capacitor Cst is described.

[0094] A thin-film transistor (TFT) may include a semiconductor layer 134, a gate electrode 136, a source electrode 137, and a drain electrode 138. The semiconductor layer 134 may, for example, include polysilicon. The semiconductor layer 134 may include a channel region 131 overlapping the gate electrode 136, and a source region 132 and a drain region 133 disposed on both sides of the channel region 131 and including impurities with a higher concentration than those in the channel region 131. Here, the impurities may include N-type impurities or P-type impurities. The source region 132 may be electrically connected to the source electrode 137 of the TFT, and the drain region 133 may be electrically connected to the drain electrode 138 of the TFT.

[0095] Semiconductor layer 134 may comprise oxide semiconductors and / or silicon semiconductors. When semiconductor layer 134 is formed of an oxide semiconductor, it may, for example, comprise an oxide of at least one substance selected from the group consisting of indium (In), gallium (Ga), selenium (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). For example, semiconductor layer 134 may be ITZO (InSnZnO), IGZO (InGaZnO), etc. When semiconductor layer 134 is formed of a silicon semiconductor, it may, for example, comprise amorphous silicon (a-Si) or low-temperature polycrystalline silicon (LTPS) formed by crystallizing amorphous silicon (a-Si).

[0096] The gate electrode 136 can be formed as a single layer or multiple layers from one or more metals selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). The gate electrode 136 can be connected to a gate line to which an electrical signal is applied.

[0097] A first insulating layer 103 may be disposed between the semiconductor layer 134 and the gate electrode 136. The first insulating layer 103 may comprise materials containing silicon dioxide (SiO2) or silicon nitride (SiN). x The first insulating layer 103 may be a single layer or multiple layers comprising the aforementioned inorganic insulating materials, including silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO).

[0098] The energy storage capacitor Cst includes a lower electrode 144 and an upper electrode 146 that overlap each other. A second insulating layer 105 may be disposed between the lower electrode 144 and the upper electrode 146.

[0099] The second insulating layer 105 is a layer with a predetermined dielectric constant, and can be, for example, silicon oxynitride (SiON) or silicon oxide (SiO2). x ) and / or silicon nitride (SiN) x Such inorganic insulating layers can be single-layered or multi-layered. Figure 5The illustration shows a case where the energy storage capacitor Cst overlaps with the thin-film transistor TFT and the lower electrode 144 is the gate electrode 136 of the thin-film transistor TFT, but the present invention is not limited thereto. As another embodiment, the energy storage capacitor Cst may not overlap with the thin-film transistor TFT, and the lower electrode 144 may be an independent component separate from the gate electrode 136 of the thin-film transistor TFT.

[0100] The energy storage capacitor Cst can be covered by a third insulating layer 107. The third insulating layer 107 can be, for example, silicon oxynitride (SiON) or silicon oxide (SiO). x ) and / or silicon nitride (SiN) x The inorganic insulating layer can be a single layer or multiple layers.

[0101] A source electrode 137 and a drain electrode 138 may be disposed on the third insulating layer 107. The source electrode 137 and the drain electrode 138 may comprise conductive materials including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or a single layer comprising the aforementioned materials. As an embodiment, the source electrode 137 and the drain electrode 138 may be formed of aluminum (Al). For example, the source electrode 137 and the drain electrode 138 may be formed of a Ti / Al / Ti multilayer structure.

[0102] A planarization layer 113 may be disposed on the source electrode 137 and the drain electrode 138. The planarization layer 113 may have contact holes through which the pixel electrode 210 (described later) and the pixel circuit PC are electrically connected.

[0103] The planarization layer 113 includes an organic insulator. The organic insulator may include general-purpose polymers such as imide-based polymers, polymethyl methacrylate (PMMA) or polystyrene (PS), phenolic polymer derivatives, acrylic polymers, aromatic ether-based polymers, amide-based polymers, fluorinated polymers, p-xylene-based polymers, vinyl alcohol-based polymers, and mixtures thereof. As one embodiment, the planarization layer 113 may include polyimide.

[0104] Display elements 200, including pixel electrodes 210, intermediate layers 220, and counter electrodes 230, can be disposed on planarization layer 113. Pixel electrodes 210 can be disposed on planarization layer 113. Pixel electrodes 210 can be (semi-)transparent electrodes or reflective electrodes. Pixel electrodes 210 may have a reflective film formed of at least one of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), and chromium (Cr), and a transparent or semi-transparent electrode layer formed on the reflective film. The transparent or semi-transparent electrode layer may include at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). More preferably, the pixel electrode 210 may have a stacked structure of indium tin oxide (ITO) / silver (Ag) / indium tin oxide (ITO).

[0105] A pixel defining film 180 can be disposed on the pixel electrode 210. The pixel defining film 180 can have openings corresponding to each pixel, that is, openings that expose at least a portion of the pixel electrode 210, thereby defining the light-emitting area of ​​the pixel. Furthermore, the pixel defining film 180 can increase the distance between the edge position of the pixel electrode 210 and the counter electrode 230, thereby preventing the generation of electric arcs or the like between them. The pixel defining film 180 can be formed of an organic material such as polyimide or hexamethyldisiloxane (HMDSO).

[0106] An intermediate layer 220 may be disposed on the pixel electrode 210, which is at least partially exposed through the pixel definition film 180. The intermediate layer 220 may include a light-emitting layer, and optionally, functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and an electron injection layer (EIL) may be included above or below the light-emitting layer.

[0107] The luminescent layer may include an organic material containing a fluorescent or phosphorescent substance that emits red, green, blue, or white light. The luminescent layer may be a low-molecular-weight organic material or a high-molecular-weight organic material. When the luminescent layer includes a low-molecular-weight substance, the intermediate layer 220 may have a single or composite structure of a hole injection layer (HIL), a hole transport layer (HTL), a luminescent layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). As a low-molecular-weight organic material, it may be represented by various organic substances such as copper phthalocyanine (CuPc), N,N'-di(naphthalene-1-yl)-N,N'-diphenyl-benzidine (NPB), and tris-8-hydroxyquinoline aluminum (Alq3). This layer can be formed using a vacuum deposition method.

[0108] When the light-emitting layer comprises a polymer material, the intermediate layer 220 may have a structure including a hole transport layer (HTL) and a light-emitting layer (EML). In this case, the hole transport layer may include PEDOT, and the light-emitting layer may include polymer materials such as PPV (poly-phenylene vinylene) or polyfluorene. This light-emitting layer can be formed by screen printing or inkjet printing methods, laser-induced thermal imaging (LITI), etc. The structure of the intermediate layer 220 is not limited to the above and can have various structures. For example, at least one of the layers forming the intermediate layer 220 may be integrally formed across multiple pixel electrodes 210. Alternatively, the intermediate layer 220 may include layers patterned in a manner corresponding to each of the multiple pixel electrodes 210.

[0109] The counter electrode 230 can be disposed above the display area DA and configured to cover the display area DA. That is, the counter electrode 230 is integrally formed to cover multiple pixels. The counter electrode 230 may include a conductive material with a low work function. For example, the counter electrode 230 may include a (semi-)transparent layer containing silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or alloys thereof. Alternatively, the counter electrode 230 may also include a layer such as ITO, IZO, ZnO, or In2O3 on the (semi-)transparent layer containing the above-mentioned materials.

[0110] A filler material (not shown) may be disposed between the counter electrode 230 and the second substrate 300. The filler material (not shown) may include, for example, one or more of photocurable epoxy materials and acrylate materials, but the present invention is not limited thereto.

[0111] Reference Figure 5 The non-display area NDA can be driven by a driving circuit 20 disposed on the first substrate 100. For example, the driving circuit 20 may be... Figure 2 The first scanning driving circuit 110 or the first light-emitting driving circuit 115.

[0112] The driving circuit 20 may include a thin-film transistor (TFT) and wiring (not shown) connected to the TFT. The TFT may be formed in the same process as the TFT of the pixel circuit PC.

[0113] The driving circuit 20 includes an insulating layer between elements forming the thin-film transistor TFT (e.g., semiconductor layer, gate electrode, etc.). For example, at least one of the buffer layer 101, the first insulating layer 103, the second insulating layer 105, and the third insulating layer 107 may extend to the non-display area NDA.

[0114] The driving circuit 20 can be configured to be relatively closer to the display area DA than the first scan driving circuit 110. Therefore, as Figure 5 As shown, a portion of the planarization layer 113 can extend to the non-display area NDA side and cover the driving circuit 20 at the top of the driving circuit 20. Alternatively, the planarization layer 113 may not cover the driving circuit 20, and only an inorganic insulating layer (not shown) may be provided on the driving circuit 20.

[0115] As an alternative embodiment, the driving circuit 20 may be covered by an inorganic insulating layer. The inorganic insulating layer can prevent conductive layers containing metals such as aluminum, which can be damaged by etchants, from being exposed to the etching environment during the manufacturing process of the display device. The inorganic insulating layer may also be disposed on the display area DA, depending on the situation. The inorganic insulating layer may include, for example, silicon oxide (SiO2). x ), silicon nitride (SiN) x Inorganic materials such as silicon oxynitride (SiON) and / or silicon oxynitride (SiON) can be formed from a single layer or multiple layers. The inorganic insulating layer can have approximately... The thickness is as described above. In other embodiments, the inorganic insulating layer can be... The above, or The above, or The above, or The above, or The above, or The above, or The above, or The above, or The above, or The above, or The above, or The above. Alternatively, the inorganic insulating layer can have... to The thickness.

[0116] Although Figure 5 Not shown in the diagram, but a second power supply line 170 can also be configured in the non-display area NDA. Figure 2 As one embodiment, the second power supply line 170 can be as follows: Figure 2 The second power supply line 170 can be configured to overlap with the sealing portion 400, or it can be configured to be located away from the sealing portion 400. Furthermore, as an embodiment, the second power supply line 170 can be configured to overlap with a portion of the drive circuit 20. The second power supply line 170 may include the same material as the source electrode 137 and the drain electrode 138.

[0117] A sealing portion 400 is disposed in the non-display area NDA and bonded to the first substrate 100 and the second substrate 300. The sealing portion 400 may be located on a buffer layer 101, a first insulating layer 103, a second insulating layer 105, and a third insulating layer 107 disposed on the first substrate 100. In this case, to ensure adhesion between the sealing portion 400 and the first substrate 100, the buffer layer 101, the first insulating layer 103, the second insulating layer 105, and the third insulating layer 107 between the sealing portion 400 and the first substrate 100 may all be formed of inorganic insulating layers. Figure 5The diagram shows the sealing portion 400 located on the buffer layer 101, the first insulating layer 103, the second insulating layer 105, and the third insulating layer 107 disposed on the first substrate 100. However, a portion of the buffer layer 101, the first insulating layer 103, the second insulating layer 105, and the third insulating layer 107 between the sealing portion 400 and the first substrate 100 may be removed, or other layers may be added.

[0118] As one embodiment, in the display device 1, the outer wall 400OE of the sealing portion 400 and the edge 300E of the second substrate 300 can be aligned with each other. In other words, the outer wall 400OE of the sealing portion 400 and the edge 300E of the second substrate 300 can be located on the same plane. This is because, as one embodiment, when manufacturing the display device 1, if the panel is cut in a manner that includes the sealing portion 400, the first substrate 100, the sealing portion 400, and the second substrate 300 are cut together along the cutting line CL during the manufacturing process. However, the present invention is not limited to the manufacturing method described above, and the outer wall 400OE of the sealing portion 400 and the edge 300E of the second substrate 300 may not be aligned with each other.

[0119] On the side of the inner wall 400IE of the sealing portion 400 facing outwards, a vacuum environment can be formed between the second substrate 300 and the first substrate 100. As an alternative embodiment, in... Figure 5 Organic / inorganic functional layers can be further configured on the counter electrode 230.

[0120] Figure 6 This is a schematically enlarged plan view illustrating a portion of a display device according to an embodiment of the present invention. Figure 7 This is a schematic cross-sectional view illustrating a display device according to an embodiment of the present invention. Figure 8 This is a schematic cross-sectional view illustrating a display device according to an embodiment of the present invention. More specifically, Figure 6 yes Figure 2 An enlarged view of part A. Figure 7 Corresponding to along Figure 6 The cross section taken from line II-II′, Figure 8 This figure is shown to illustrate the stacked structure of the conductive layer 215 according to one embodiment.

[0121] Reference Figure 6 An embodiment of the present invention relates to a display device having an overlapping area in a portion of the non-display area NDA where a second power supply line 170 overlaps with a sealing portion 400. Figure 6 The diagram shows the second power supply line 170 overlapping with the sealing portion 400, but in other embodiments, the first power supply line 160 may also overlap with the sealing portion 400.

[0122] A conductive layer 215 may be disposed on the second power supply line 170. The conductive layer 215 may be disposed directly on the second power supply line 170 or may be in direct contact with the sealing part 400.

[0123] In conventional display devices, during laser sealing, the second power supply line can be damaged by heat, resulting in problems such as hilling on the surface of the second power supply line or short circuits between the second and first power supply lines.

[0124] In this embodiment, to prevent the problems described above, a conductive layer 215 is disposed on the second power supply line 170, thereby preventing the second power supply line 170 from being damaged by heat during laser sealing, resulting in a hillock phenomenon on the surface of the second power supply line 170 or a short circuit between the second power supply line 170 and the first power supply line 160.

[0125] Reference Figure 7 A buffer layer 101, a first insulating layer 103, a second insulating layer 105, and a third insulating layer 107 may be disposed on the first substrate 100. A power supply line including a first power supply line 160 and a second power supply line 170 may be disposed on the third insulating layer 107. The first power supply line 160 and the second power supply line 170 may be disposed on the same layer, but separately disposed on the third insulating layer 107.

[0126] The first power supply line 160 and the second power supply line 170 may include conductive materials such as molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), and may be formed from multiple layers or a single layer of the aforementioned materials. Preferably, the first power supply line 160 and the second power supply line 170 may be formed of aluminum (Al). As an embodiment, the first power supply line 160 and the second power supply line 170 may be formed from a Ti / Al / Ti multilayer structure. For example, the first power supply line 160 and the second power supply line 170 may include the same material as the source electrode 137 and the drain electrode 138.

[0127] A conductive layer 215 can be disposed on the power supply line. The conductive layer 215 can be directly disposed on the second power supply line 170, and can cover the upper surface 170a and the two sides 170b and 170c of the second power supply line 170. The conductive layer 215 may include at least one substance selected from silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), and chromium (Cr). In addition, the conductive layer 215 may include at least one substance selected from indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO).

[0128] Reference Figure 8 The conductive layer 215 may include: a first layer 215a comprising indium tin oxide (ITO); a second layer 215b disposed on the first layer 215a and comprising silver (Ag); and a third layer 215c disposed on the second layer 215b and comprising indium tin oxide (ITO). Therefore, the conductive layer 215 may have a stacked structure of indium tin oxide (ITO) / silver (Ag) / indium tin oxide (ITO).

[0129] As one embodiment, the conductive layer 215 may include the same material as the pixel electrode 210 disposed in the display area DA, and the conductive layer 215 may be formed on the second power supply line 170 simultaneously with the process of forming the pixel electrode 210 on the pixel definition film 180. For example, the conductive layer 215 may be formed by patterning on the second power supply line 170 simultaneously with the process of patterning the pixel electrode 210 on the pixel definition film 180 without additional processes or additional masks.

[0130] By configuring a conductive layer 215 on the second power supply line 170 and having the conductive layer 215 covering the upper surface 170a and the two sides 170b and 170c of the second power supply line 170, it is possible to prevent the second power supply line 170 from being damaged by heat during laser sealing, thus preventing the formation of a hill on the surface of the second power supply line 170 or a short circuit between the second power supply line 170 and the first power supply line 160.

[0131] A sealing portion 400 and a second substrate 300 may be disposed on the conductive layer 215. In one embodiment, the sealing portion 400 may be directly disposed on the conductive layer 215 for bonding force, etc. The sealing portion 400 may be disposed on the conductive layer 215 and may have an overlap area that at least partially overlaps with the second power supply line 170. The first substrate 100 and the second substrate 300 can be bonded through the sealing portion 400. During this process, the sealing portion 400 overlapping with the second power supply line 170 is pressed against the display area DA side, and the first power supply line 160 and the sealing portion 400 will at least partially overlap.

[0132] Figure 9 This is a schematically enlarged plan view illustrating a portion of a display device according to an embodiment of the present invention. Figure 10 This is a schematically enlarged cross-sectional view showing a portion of a display device according to an embodiment of the present invention. Figure 9 and Figure 10 The difference between this embodiment and the embodiment described above lies in the structure of the conductive layer 215 disposed on the second power supply line 170. Hereinafter, the description will focus on the difference in the conductive layer 215 disposed on the second power supply line 170, omitting repetitive details.

[0133] Reference Figure 9 and Figure 10 One embodiment of the power supply line of the display device may include a first power supply line 160 and a second power supply line 170. The first power supply line 160 and the second power supply line 170 may be separate from each other and may be arranged on the same layer.

[0134] A conductive layer 215 may be disposed on the second power supply line 170. The conductive layer 215 may be disposed on the second power supply line 170 and may cover at least a portion of the upper surface 170a and both sides 170b, 170c of the second power supply line 170. For example, the conductive layer 215 may include an opening OP that exposes at least a portion of the upper surface 170a of the second power supply line 170.

[0135] By disposing of the conductive layer 215 on the second power supply line 170 and covering at least a portion of the upper surface 170a and both sides 170b and 170c of the second power supply line 170, it is possible to prevent the second power supply line 170 from being damaged by heat during laser sealing, thus preventing the formation of a hill on the surface of the second power supply line 170 or a short circuit between the second power supply line 170 and the first power supply line 160.

[0136] A sealing portion 400 and a second substrate 300 may be disposed on the conductive layer 215. As one embodiment, the sealing portion 400 may be directly disposed on the conductive layer 215 for bonding force, etc. The sealing portion 400 may be disposed on the conductive layer 215 and may have an overlap area that at least partially overlaps with the second power supply line 170. For example, the sealing portion 400 may directly contact the second power supply line 170 through an opening OP defined in the conductive layer 215. The first substrate 100 and the second substrate 300 can be bonded through the sealing portion 400. During this process, the sealing portion 400 overlapping with the second power supply line 170 is pressed against the display area DA side, and the first power supply line 160 may at least partially overlap with the sealing portion 400.

[0137] Figure 11 This is a schematically enlarged plan view illustrating a portion of a display device according to an embodiment of the present invention. Figure 12 This is a schematically enlarged cross-sectional view showing a portion of a display device according to an embodiment of the present invention. Figure 11 and Figure 12 The difference between this embodiment and the embodiment described above lies in the structure of the conductive layer 215 disposed on the second power supply line 170. Hereinafter, the description will focus on the difference in the conductive layer 215 disposed on the second power supply line 170, omitting repetitive details.

[0138] Reference Figure 11 and Figure 12 One embodiment of the power supply line of the display device may include a first power supply line 160 and a second power supply line 170. The first power supply line 160 and the second power supply line 170 may be separate from each other and may be arranged on the same layer.

[0139] A conductive layer 215 may be disposed on the second power supply line 170. The conductive layer 215 is disposed on the second power supply line 170 and may cover at least a portion of the upper surface 170a of the second power supply line 170 and the side surface 170b of the second power supply line 170 adjacent to the first power supply line 160.

[0140] By disposing a conductive layer 215 on the second power supply line 170 and covering at least a portion of the upper surface 170a of the second power supply line 170 and the side surface 170b of the second power supply line 170 adjacent to the first power supply line 160, it is possible to prevent the second power supply line 170 from being damaged by heat during laser sealing, resulting in a hillock on the surface of the second power supply line 170 or a short circuit between the second power supply line 170 and the first power supply line 160.

[0141] A sealing portion 400 and a second substrate 300 may be disposed on the conductive layer 215. In one embodiment, the sealing portion 400 may be directly disposed on the conductive layer 215 for bonding force. The sealing portion 400 may be disposed on the conductive layer 215 and have an overlap region that at least partially overlaps with the second power supply line 170. For example, the sealing portion 400 may directly contact at least a portion of the exposed second power supply line 170. The first substrate 100 and the second substrate 300 can be bonded through the sealing portion 400. During this process, the sealing portion 400 overlapping with the second power supply line 170 is pressed against the display area DA side, and the first power supply line 160 and the sealing portion 400 will at least partially overlap.

[0142] According to an embodiment of the present invention, in conventional display devices, when laser sealing is performed after bonding the first substrate 100 and the second substrate 300, there is a problem that at least one of the power supply lines may be damaged by heat, resulting in a hilling phenomenon or a short circuit between adjacent wirings. In order to solve such problems, a conductive layer is formed on the power supply line to cover the power supply line by using the same material and the same process as forming the pixel electrode 210. This provides a display device that prevents hilling or short circuits between adjacent wirings while improving product reliability.

[0143] So far, the display device has been mainly described, but the present invention is not limited thereto. For example, the manufacturing method of the display device for manufacturing such a display device is certainly also within the scope of the present invention.

[0144] The present invention has been described with reference to the embodiments shown in the accompanying drawings; however, these are merely illustrative, and those skilled in the art should understand that various modifications and equivalent embodiments can be implemented. Therefore, the true scope of protection of the invention should be determined by the technical concept of the claims.

Claims

1. A display device comprising: A first substrate has a display area and a non-display area on one side of the display area; The second substrate is disposed opposite to the first substrate; Display elements are disposed on the display area and include a pixel electrode, an intermediate layer disposed on the pixel electrode, and a counter electrode disposed on the intermediate layer; A power supply line is located on the non-display area; as well as A conductive layer is disposed on the power supply line and comprises the same material as the pixel electrode. The power supply line includes a first power supply line and a second power supply line. The first power supply line provides a first power supply voltage to each pixel, and the second power supply line is disposed away from the first power supply line and provides a second power supply voltage to the opposing electrode. The conductive layer covers at least a portion of the upper surface of the second power supply line and the first side surface of the second power supply line adjacent to the first power supply line, and exposes the second side surface of the second power supply line opposite to the first side surface.

2. The display device according to claim 1, wherein, The conductive layer is directly disposed on the second power supply line.

3. The display device according to claim 1, further comprising: A sealing portion is configured in the non-display area to surround the outline of the display area, thereby joining the first substrate and the second substrate.

4. The display device according to claim 3, wherein, At least a portion of the sealing portion overlaps with the second power supply line.

5. The display device according to claim 3, wherein, The sealing part is in direct contact with the conductive layer.

6. The display device according to claim 1, wherein, The power supply line includes at least one of molybdenum, aluminum, copper, and titanium.

7. The display device according to claim 1, wherein, The conductive layer comprises at least one substance selected from silver, magnesium, aluminum, platinum, palladium, gold, nickel, neodymium, iridium, and chromium (Cr).

8. The display device according to claim 7, wherein, The conductive layer comprises at least one of indium tin oxide, indium zinc oxide, zinc oxide, indium oxide, indium gallium oxide, and aluminum zinc oxide.

9. The display device according to claim 8, wherein, The conductive layer has a stacked structure of indium tin oxide / silver / indium tin oxide.

10. A display device comprising: A first substrate has a display area and a non-display area on one side of the display area; The second substrate is disposed opposite to the first substrate; Display elements are disposed on the display area and include a pixel electrode, an intermediate layer disposed on the pixel electrode, and a counter electrode disposed on the intermediate layer; A power supply line is disposed on the non-display area and includes a first power supply line that provides a first power supply voltage to each pixel and a second power supply line that is configured to be away from the first power supply line and provides a second power supply voltage to the counter electrode. A conductive layer is disposed on the second power supply line and comprises the same material as the pixel electrode; as well as A sealing portion is configured in the non-display area to surround the outline of the display area, thereby joining the first substrate and the second substrate. The second power supply line has an upper surface, a first side surface, and a second side surface. The first side surface is adjacent to the first power supply line, and the second side surface is located opposite the first side surface. The conductive layer at least covers the first side of the second power supply line, and the sealing portion at least contacts the upper surface of the second power supply line.

11. The display device according to claim 10, wherein, The conductive layer also covers at least a portion of the upper surface of the second power supply line and / or the second side surface.

12. The display device according to claim 10, wherein, The sealing part is in direct contact with the conductive layer.

13. The display device according to claim 10, wherein, The power supply line includes at least one of molybdenum, aluminum, copper, and titanium (Ti).

14. The display device according to claim 10, wherein, The conductive layer has a stacked structure of indium tin oxide / silver / indium tin oxide.

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