Power gating circuit

Abstract

The present invention discloses a power gating circuit, which includes two inverters and a voltage dividing subcircuit, a latch comparator, and a gate switch subcircuit respectively connected to an external 5V power supply circuit, wherein the voltage dividing subcircuit divides the 5V voltage, and the voltage dividing subcircuit outputs a first voltage and a second voltage to the latch comparator and the gate switch subcircuit, wherein the voltage values ​​of the first voltage and the second voltage are both less than the withstand voltage value of the field effect tube, and the voltage value of the first voltage is greater than the voltage value of the second voltage; the first voltage provides a working voltage for the two inverters and the two inverters are connected in series; the latch comparator compares the signals output by the two inverters and latches the comparison result; the gate switch subcircuit turns off / closes the entire power gating circuit according to the voltage value of the external control signal. The power gating circuit of the present invention can well ensure that when the high-voltage circuit is turned off, conventional devices with an internal withstand voltage of 3.3V will not have the problem of poor withstand voltage, thereby improving the stability of the circuit and extending the service life of the entire circuit.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and more particularly to a power gating circuit. Background Art

[0002] With the development of large-scale integrated circuits, systems on chip have been widely used in various fields, the scale of ICs has become larger and larger, and its low-power and low-cost design has become an indispensable part of circuit design.

[0003] When designing a circuit, considering the cost control in terms of process, the design generally uses conventional devices, such as CMOS devices using 3.3V IO devices, etc., but the system power supply voltage may be a more common 5V power supply circuit. When designing a circuit powered by a 5V power supply using a 3.3V IO device, special attention should be paid to the problem of poor withstand voltage, that is, all 3.3V CMOS devices in the circuit must ensure that the gate-source voltage value |VGS|, gate-drain voltage value |VGD|, and source-drain voltage value |VSD| of the COMS device are within the voltage range required by the process, whether the circuit is working normally or in the circuit off state. For example, for 3.3V IO devices, the general process requires that the above-mentioned gate-source voltage value |VGS|, gate-drain voltage value |VGD|, and source-drain voltage value |VSD| are all within the range of 3.3V±10%, otherwise it will cause reduced life, leakage or abnormal operation.

[0004] When the circuit is working normally, the problem of poor voltage resistance can be solved well by adding diodes to the circuit branches. However, when the circuit is in low power consumption, for example, to ensure low power consumption, the circuit needs to be shut down when not in use. At this time, since all switching devices are conventional 3.3V IO devices and 5V voltage is used as the high level of the control switch, the conventional switching circuit design cannot ensure that the gate-source voltage value |VGS|, gate-drain voltage value |VGD|, and source-drain voltage value |VSD| of the control switch are all within the voltage range required by the process (i.e. 3.3V±10%), poor voltage resistance will occur, which will affect the robustness of the entire circuit.

[0005] Therefore, it is necessary to provide a power gate circuit that can overcome the poor withstand voltage of various devices to overcome the above defects. Summary of the invention

[0006] The purpose of the present invention is to provide a power gating circuit. The power gating circuit of the present invention can well ensure that when the high-voltage circuit is turned off, conventional devices with an internal withstand voltage of 3.3V will not have the problem of poor withstand voltage, thereby improving the stability of the circuit and extending the service life of the entire circuit.

[0007] To achieve the above object, the present invention discloses a power gating circuit, which includes two inverters, a voltage dividing sub-circuit, a latch comparator, and a gating switch sub-circuit respectively connected to an external 5V power supply circuit. The voltage dividing sub-circuit divides the 5V voltage output by the external 5V power supply circuit, and the voltage dividing sub-circuit outputs a first voltage and a second voltage to the latch comparator and the gating switch sub-circuit. The voltage values of the first voltage and the second voltage are both less than the breakdown voltage of the field effect transistor, and the voltage value of the first voltage is greater than the voltage value of the second voltage. The first voltage provides operating voltage for the two inverters, and the two inverters are connected in series. An external control signal is sequentially input into the two inverters. The latch comparator compares the signals output by the two inverters and latches the comparison result. The gating switch sub-circuit is also connected to the latch comparator, and turns off / turns on the entire power gating circuit according to the voltage value of the external control signal to control the output voltage.

[0008] Preferably, the voltage dividing sub-circuit is composed of N voltage dividing field effect transistors, and the N voltage dividing field effect transistors are connected in series in sequence. Each voltage dividing field effect transistor is connected in a diode structure. The source of the first voltage dividing field effect transistor is connected to the external 5V power supply circuit, and the drain of the Nth voltage dividing field effect transistor is grounded, where N is a natural number greater than 3.

[0009] Preferably, the gates of each voltage dividing field effect transistor are respectively connected to their drains, and their substrates are respectively connected to their sources, and the aspect ratios of each voltage dividing field effect transistor are the same.

[0010] Preferably, each voltage dividing field effect transistor is a P-type field effect transistor. The first voltage is led out from the source of the ith voltage dividing field effect transistor, and correspondingly, the second voltage is led out from the source of the (i + 1)th voltage dividing field effect transistor, and 3 < i < N, where i is a natural number.

[0011] Preferably, the latch comparator includes a first field effect transistor, a second field effect transistor, a third field effect transistor, a fourth field effect transistor, a fifth field effect transistor, a sixth field effect transistor, a seventh field effect transistor and an eighth field effect transistor; the source electrodes of the first field effect transistor and the second field effect transistor are both connected to an external 5V power supply circuit, and the first field effect transistor and the second field effect transistor are connected in a positive feedback manner; the second voltage is input to the gate electrode of the third field effect transistor, the source electrode of the third field effect transistor is connected to the drain electrode of the first field effect transistor, and the drain electrode of the third field effect transistor is connected to the drain electrode of the fifth field effect transistor; the first voltage is input to the gate electrode of the fifth field effect transistor, The source of the fifth field effect tube is connected to the drain of the seventh field effect tube; the output end of the second inverter is connected to the gate of the seventh field effect tube, and the source of the seventh field effect tube is grounded; the second voltage is input to the gate of the fourth field effect tube, the source of the fourth field effect tube is connected to the drain of the second field effect tube, and the drain is connected to the drain of the sixth field effect tube; the first voltage is input to the gate of the sixth field effect tube, the source of the sixth field effect tube is connected to the drain of the eighth field effect tube; the output end of the first inverter is connected to the gate of the eighth field effect tube, and the source of the eighth field effect tube is grounded.

[0012] Preferably, the gate-controlled switch subcircuit includes a ninth field effect transistor, a tenth field effect transistor, an eleventh field effect transistor and a twelfth field effect transistor; the drain of the ninth field effect transistor is connected to an external 5V power supply circuit, the gate thereof is connected to the drain of the third field effect transistor, the drain is connected to the source of the tenth field effect transistor, the second voltage is input to the gates of the tenth field effect transistor and the eleventh field effect transistor, the drain of the tenth field effect transistor and the drain of the eleventh field effect transistor jointly form an output end, the source of the eleventh field effect transistor is connected to the drain of the twelfth field effect transistor, the gate of the twelfth field effect transistor is connected to the drain of the seventh field effect transistor, and the source thereof is grounded.

[0013] Preferably, the first field effect transistor, the second field effect transistor, the third field effect transistor, the fourth field effect transistor, the ninth field effect transistor and the tenth field effect transistor are all P-type field effect transistors, and their substrates are all connected to an external 5V power supply circuit.

[0014] Preferably, the fifth field effect transistor, the sixth field effect transistor, the seventh field effect transistor, the eighth field effect transistor, the eleventh field effect transistor and the twelfth field effect transistor are all N-type field effect transistors, and their substrates are all connected to a low level.

[0015] Preferably, the first field effect transistor and the second field effect transistor are connected in a positive feedback manner, specifically, the gate of the first field effect transistor is connected to the drain of the second field effect transistor, and the gate of the second field effect transistor is connected to the drain of the first field effect transistor.

[0016] Preferably, the third field effect transistor, the fourth field effect transistor, the fifth field effect transistor, the sixth field effect transistor, the tenth field effect transistor and the eleventh field effect transistor are voltage-resistant switch transistors.

[0017] Compared with the prior art, the power gate circuit of the present invention has the first voltage and the second voltage output by the voltage divider subcircuit both being lower than the withstand voltage of the field effect tube, so that the voltage on other field effect tubes in the entire circuit that obtain voltages through the first voltage or the second voltage will all be lower than their withstand voltage, i.e., each field effect tube will not have withstand voltage problems during circuit operation; accordingly, by reasonably configuring the voltage division mode of the voltage divider subcircuit, there will be no withstand voltage problems inside the voltage divider subcircuit; therefore, the power gate circuit of the present invention overcomes the influence of the withstand voltage problem on the circuit, improves the stability of the circuit, and extends the service life of the entire circuit.

[0018] The present invention will become more apparent from the following description taken in conjunction with the accompanying drawings, which are used to illustrate embodiments of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 4 is a circuit structure diagram of the power gating circuit of the present invention.

[0020] Figure 2 FIG. 1 is a circuit diagram of an embodiment of a power gating circuit of the present invention. DETAILED DESCRIPTION

[0021] The embodiments of the present invention are now described with reference to the accompanying drawings, in which like element numbers represent like elements. As described above, the present invention provides a power gating circuit, which can well ensure that when the high-voltage circuit is turned off, conventional devices with an internal withstand voltage of 3.3V will not have a problem of poor withstand voltage, thereby improving the stability of the circuit and extending the service life of the entire circuit.

[0022] Please refer to Figure 1 , Figure 1The circuit structure diagram of the power gating circuit of the present invention. As shown in the figure, the power gating circuit of the present invention includes two inverters (INV1, INV2) and a voltage dividing subcircuit, a latch comparator, and a gate switch subcircuit respectively connected to an external 5V power supply circuit; the voltage dividing subcircuit divides the 5V voltage VBAT output by the external 5V power supply circuit, and the voltage dividing subcircuit outputs the divided first voltage Va and the second voltage Vb to the latch comparator and the gate switch subcircuit; the voltage values ​​of the first voltage Va and the second voltage Vb are both less than the withstand voltage value of the field effect tube. In the present invention, all field effect tubes are 3.3V CMOS devices, that is, the withstand voltage value of the field effect tube is 3.3V; wherein the voltage value of the first voltage Va is greater than the voltage value of the second voltage Vb; the first voltage Va is The two inverters provide working voltage, and the two inverters are connected in series, and the external control signal EN is sequentially input into the two inverters, that is, the external control signal EN is input into the first inverter INV1, the output signal ENN of the first inverter INV1 is input into the second inverter INV2 and the latch comparator, and the second inverter INV2 outputs the signal ENP to the latch comparator; the latch comparator compares the signals output by the two inverters, that is, compares the input signals ENN and ENP, and latches the comparison result; the gate switch sub-circuit is also connected to the latch comparator, and turns off / closes the entire power gate circuit according to the voltage value of the external control signal EN to control the output voltage. In the present invention, the voltage values ​​of the first voltage Va and the second voltage Vb output by the voltage divider sub-circuit are both lower than the withstand voltage of the field effect tube, so that the voltage on other field effect tubes in the entire circuit that obtain voltages through the first voltage Va or the second voltage Vb will be lower than their withstand voltage, that is, each field effect tube will no longer have withstand voltage problems during circuit operation; accordingly, by reasonably configuring the voltage division mode of the voltage divider sub-circuit, there will be no withstand voltage problems inside the voltage divider sub-circuit; therefore, the power gating circuit of the present invention overcomes the influence of the withstand voltage problem on the circuit, improves the stability of the circuit, and extends the service life of the entire circuit.

[0023] Specifically, in the present invention, the voltage dividing sub-circuit is composed of N voltage dividing field effect transistors (FM1, FM2... FMi... FMN), and the N voltage dividing field effect transistors are connected in series in sequence. Each of the voltage dividing field effect transistors is connected in a diode structure. The source electrode of the first voltage dividing field effect transistor FM1 is connected to an external 5V power supply circuit, so that the external 5V voltage VBAT is input to the source electrode of the first voltage dividing field effect transistor FM1. The drain electrode of the Nth voltage dividing field effect transistor FMN is grounded, where N is a natural number greater than 3. Through the connection mode of the N voltage dividing field effect transistors (FM1, FM2... FMi... FMN), the external 5V voltage VBAT can be divided into N equal parts. Thus, by outputting the first voltage Va and the second voltage Vb from appropriate voltage dividing field effect transistors, it can be realized that both the first voltage Va and the second voltage Vb are less than the breakdown voltage value of the field effect transistor, so that the voltages on other field effect transistors in the entire circuit that obtain voltages through the first voltage Va or the second voltage Vb will all be less than their breakdown values, that is, ensuring that each field effect transistor will not have the problem of poor breakdown voltage. Among them, the value of N can be specifically selected according to the processes of various devices in the circuit.

[0024] Furthermore, the gate electrode of each of the voltage dividing field effect transistors is connected to the drain electrode, and the substrate of each is connected to its own source electrode, and the aspect ratio of each of the voltage dividing field effect transistors is the same; each of the voltage dividing field effect transistors is a P-type field effect transistor, so as to ensure that the source-drain voltages of the N voltage dividing field effect transistors (FM1, FM2... FMi... FMN) are exactly the same, and the voltage VBAT is divided into N equal parts; in addition, by adjusting the aspect ratio of the N voltage dividing field effect transistors (FM1, FM2... FMi... FMN), it can be ensured that each voltage dividing field effect transistor operates in the subthreshold region, and the current Ip of its series branch can be controlled in the order of nA (nanoampere). In addition, the first voltage Va is led out from the source electrode of the i-th voltage dividing field effect transistor FMi, and correspondingly, the second voltage Vb is led out from the source electrode of the (i + 1)-th voltage dividing field effect transistor FM(i + 1), and 3 < i < N, where i is a natural number; during the application process of the present invention, the value of i is preferably a number close to N / 2, which can better ensure the stable operation of the circuit; thus, the voltage values of the first voltage Va and the second voltage Vb are respectively as follows:

[0025] Va = i / N × VBAT;

[0026] Vb = (i + 1) / N × VBAT;

[0027] As can be seen from the above, to ensure that each field effect transistor does not have the problem of breakdown voltage, the first voltage Va at the voltage dividing point at this time needs to satisfy:

[0028] Va = i / N × VBAT < 3.3v

[0029] Therefore, in application, the values ​​of i and N can be reasonably selected so that the first voltage Va satisfies the above formula; of course, in practical applications, the first voltage Va can be slightly less than 3.3V, which not only ensures that there will be no voltage resistance problems in the field effect tubes in the circuit, but also ensures that each field effect tube can work normally. Correspondingly, the second voltage Vb is only slightly less than the first voltage Va, which can also be derived from the above formula.

[0030] Please refer to Figure 1 The latch comparator includes a first field effect transistor M1, a second field effect transistor M2, a third field effect transistor M3, a fourth field effect transistor M4, a fifth field effect transistor M5, a sixth field effect transistor M6, a seventh field effect transistor M7 and an eighth field effect transistor M8. The sources of the first field effect transistor M1 and the second field effect transistor M2 are connected to an external 5V power supply circuit, and the first field effect transistor M1 and the second field effect transistor M2 are connected in a positive feedback manner; wherein the positive feedback connection manner is specifically that the gate of the first field effect transistor M1 is connected to the drain of the second field effect transistor M2, and the gate of the second field effect transistor M2 is connected to the drain of the first field effect transistor M1. The second voltage Vb is input to the gate of the third field effect transistor M3, the source of the third field effect transistor M3 is connected to the drain of the first field effect transistor M1, and the drain is connected to the drain of the fifth field effect transistor M5; the first voltage Va is input to the gate of the fifth field effect transistor M5, the source of the fifth field effect transistor M5 is connected to the drain of the seventh field effect transistor M7; the output end of the second inverter INV2 is connected to the gate of the seventh field effect transistor M7, and the source of the seventh field effect transistor M7 is grounded; The second voltage Vb is input to the gate of the fourth field effect transistor M4, the source of the fourth field effect transistor M4 is connected to the drain of the second field effect transistor M2, and the drain is connected to the drain of the sixth field effect transistor M6; the first voltage Va is input to the gate of the sixth field effect transistor M6, the source of the sixth field effect transistor M6 is connected to the drain of the eighth field effect transistor M8; the output end of the first inverter INV1 is connected to the gate of the eighth field effect transistor M8, and the source of the eighth field effect transistor M8 is grounded. In the present invention, the first inverter INV1 outputs a signal ENN to the eighth field effect transistor M8, and the second inverter INV2 outputs a signal ENP to the seventh field effect transistor M7, so that the latch comparator compares the input signals ENN and ENP and latches the comparison result.

[0031] Furthermore, the gate-controlled switch subcircuit includes a ninth field effect transistor M9, a tenth field effect transistor M10, an eleventh field effect transistor M11 and a twelfth field effect transistor M12; the drain of the ninth field effect transistor M9 is connected to the external 5V power supply circuit, the gate thereof is connected to the drain of the third field effect transistor M3, the drain is connected to the source of the tenth field effect transistor M10, the second voltage Vb is input to the gates of the tenth field effect transistor M10 and the eleventh field effect transistor M11, the drain of the tenth field effect transistor M10 and the drain of the eleventh field effect transistor M11 jointly form an output end (not shown in the figure), and the output end outputs a voltage VBATO, the source of the eleventh field effect transistor M11 is connected to the drain of the twelfth field effect transistor M12, the gate of the twelfth field effect transistor M12 is connected to the drain of the seventh field effect transistor M7, and the source thereof is grounded. In the gate switch subcircuit diagram, when the control signal EN is at a high level of 3.3V, the power gate circuit is closed, and at this time, VBAT=VBATO; when the control signal EN is at a low level of 0V, the power gate circuit is turned off, and at this time VBATO is pulled down to ground.

[0032] In a preferred embodiment of the present invention, the first field effect transistor M1, the second field effect transistor M2, the third field effect transistor M3, the fourth field effect transistor M4, the ninth field effect transistor M9 and the tenth field effect transistor M10 are all P-type field effect transistors, and their substrates are all connected to an external 5V power supply circuit; the fifth field effect transistor M5, the sixth field effect transistor M6, the seventh field effect transistor M7, the eighth field effect transistor M8, the eleventh field effect transistor M11 and the twelfth field effect transistor M12 are all N-type field effect transistors, and their substrates are all connected to a low level; wherein, the connection method of the substrates of the above-mentioned field effect transistors is not shown in the figure.

[0033] Furthermore, in the present invention, the third field effect transistor M3, the fourth field effect transistor M4, the fifth field effect transistor M5, the sixth field effect transistor M6, the tenth field effect transistor M10 and the eleventh field effect transistor M11 are anti-voltage withstand switch tubes, which can clamp the voltage during the circuit operation to prevent the device itself from having poor voltage withstand problems, thereby ensuring the normal operation of the circuit.

[0034] From the above, it can be seen that the power gate circuit of the present invention, since the voltage values ​​of the first voltage and the second voltage output by the voltage divider sub-circuit are both lower than the withstand voltage value of the field effect tube, the voltage on other field effect tubes in the entire circuit that obtain voltage through the first voltage or the second voltage will be lower than its withstand voltage value, that is, each field effect tube will not have a withstand voltage problem during the operation of the circuit; correspondingly, since in the voltage divider sub-circuit, N>3, the voltage on each of the voltage divider field effect tubes will definitely be lower than 3.3V, so that there will be no withstand voltage problem inside the voltage divider sub-circuit; therefore, the power gate control circuit of the present invention overcomes the influence of the withstand voltage problem on the circuit, improves the stability of the circuit, and extends the service life of the entire circuit.

[0035] Please refer to Figure 2 , Figure 2 This is a circuit diagram of an embodiment of the power gating circuit of the present invention. As shown in the figure, in this embodiment, the value of N is 9, and the value of i is 5, that is:

[0036] Va = 5 / 9 × VBAT;

[0037] Vb = 4 / 9 × VBAT;

[0038] and:

[0039] Va=5 / 9×VBAT<3.3v.

[0040] Others Figure 1 The same is not repeated here.

[0041] Below Figure 2 Take the power gating circuit of the present invention as an example to describe the working principle of the power gating circuit of the present invention:

[0042] In the power gating circuit of the present invention, the supply voltage of the two inverters INV1 and INV2 is the first voltage Va after being divided by the voltage divider sub-circuit. As is well known, after the inverter is locked in the working state, the leakage current is at the pA (picoampere) level, which is much smaller than the current Ip. Because the current Ip is at the nA (nanoampere) level, the Va voltage will not be affected after the states of the inverters INV1 and INV2 are locked.

[0043] When the control signal EN is high level 3.3V:

[0044] Then the output signal ENN of the first inverter INV1 is low level, the output signal ENP of the second inverter INV2 is high level Va, and the latch comparator makes the voltage as follows through the turned-on anti-voltage switch tube third field effect tube M3, fourth field effect tube M4, fifth field effect tube M5, sixth field effect tube M6 and the first field effect tube M1 and second field effect tube M2 of the positive feedback circuit:

[0045] V d =0;

[0046] V c =V b +|V GSM3 |

[0047] Among them, V GSM3 is the gate-source voltage of the third field effect transistor M3.

[0048] After the latch comparator enters the stable state, the current flowing through the first field effect transistor M1, the third field effect transistor M3, the fifth field effect transistor M5, and the seventh field effect transistor M7 branch and the current flowing through the second field effect transistor M2, the fourth field effect transistor M4, the sixth field effect transistor M6, and the eighth field effect transistor M8 are in the pA level. Therefore, the V of the third field effect transistor M3 in the formula is GSM3 Very small, the gate-source voltage V GS for

[0049] |V GSM9 |=VBAT-V C =V a -|V GSM3 |<3.3V

[0050] Among them, V GSM9 is the gate-source voltage of the ninth field effect transistor M9.

[0051] Since the voltage Va is slightly less than 3.3V, the voltage V GSM9 It is very small, so the ninth field effect tube M9 can be smoothly turned on. As a switch tube, when it is turned on, its drain voltage is the same as the source. Therefore, the gate-drain voltage and drain-source voltage of the ninth field effect tube M9 will not have poor withstand voltage problems.

[0052] For the tenth field effect transistor M10:

[0053] |V GSM10 |=VBAT-V b =V a <3.3V

[0054] Among them, V GSM10 is the gate-source voltage of the tenth field effect transistor M10.

[0055] It can be known from the above formula that the gate-source voltage of the tenth field effect transistor M10 is also slightly less than 3.3V. At this time, the tenth field effect transistor M10 also serves as a switch tube, which can ensure that its gate-drain voltage and drain-source voltage will not have poor withstand voltage problems.

[0056] Since the voltage Vd = 0, the twelfth field effect transistor M12 as a switch is turned off, and its drain voltage is Vb-VGSM11 <3.3V, ensuring that the twelfth field effect transistor M12 has no voltage resistance problem.

[0057] For the eleventh field effect tube M11:

[0058] |V DSM11 |=VBAT-V b -V GSM11 =V a -V GSM11 <3.3V,

[0059] Among them, V GSM11 is the gate-source voltage of the eleventh field effect transistor M11, V DSM11 is the drain-source voltage of the eleventh field effect transistor M11.

[0060] Therefore, the eleventh field effect transistor M11 also has no voltage resistance problem.

[0061] Using the same analysis method as above, it can be calculated that the field effect transistors M1-M8 will not have voltage resistance problems, and all CMOS devices in the entire circuit will not have poor voltage resistance problems, while ensuring the smooth conduction of the ninth field effect transistor M9 and the tenth field effect transistor M10 as switch tubes.

[0062] When the control signal EN is low level 0:

[0063] Then the output signal ENN of the first inverter INV1 is a high level Va, the output signal ENP of the second inverter INV2 is a low level 0, and the latch comparator makes the voltage as follows through the turned-on withstand voltage switch tube third field effect tube M3, fourth field effect tube M4, fifth field effect tube M5, sixth field effect tube M6 and the first field effect tube M1 and the second field effect tube M2 of the positive feedback circuit:

[0064] V c =VBAT

[0065] V d =V a -|V GSM5 |

[0066] Among them, V GSM5 is the gate-source voltage of the fifth field effect transistor M5

[0067] Similarly, after the latch comparator enters the stable state, the current flowing through the first field effect transistor M1, the third field effect transistor M3, the fifth field effect transistor M5, the seventh field effect transistor M7 branch and the current flowing through the second field effect transistor M2, the fourth field effect transistor M4, the sixth field effect transistor M6, and the eighth field effect transistor M8 branch are in the pA level, so V in the formula is GSM5is very small, so the voltage Vd is close to 3.3V, which can ensure that the twelfth field effect transistor M12 as the switch tube is smoothly turned on. At this time, the gate-source voltage of the eleventh field effect transistor M11 as the switch tube is Vb, which can also ensure its smooth conduction without voltage resistance problem. At this time, VBATO is pulled down to the ground, that is, the circuit connected to VBATO is pulled to the ground level, thereby reliably shutting off the related circuits powered by VBATO.

[0068] Because the voltage Vc is the highest voltage VBAT, the ninth field effect tube M9 can be reliably turned off, and the tenth field effect tube M10 is also turned off. At this time, the two turned-off switch tubes are connected in series on the path from the voltage VBAT to VBATO (ground level at this time), which is a high-resistance voltage divider with equivalent impedance, which can ensure that neither of them will have a voltage withstand problem.

[0069] Using the same analysis method as above, it can be calculated that the field effect transistors M1-M8 will not have a voltage resistance problem, and all CMOS devices in the entire circuit will not have a voltage resistance problem.

[0070] Through the above analysis, when the control signal EN is at a low level, the ninth field effect transistor M9 and the tenth field effect transistor M10 serving as switch tubes are reliably turned off, and the voltage VBATO is pulled down to the ground level through the ninth field effect transistor M9 and the tenth field effect transistor M10, so that VBATO outputs a 0 level, and the circuit connected to VBATO is reliably turned off, and all devices will not have poor withstand voltage problems.

[0071] The present invention has been described above in conjunction with the best embodiments, but the present invention is not limited to the embodiments disclosed above, but should cover various modifications and equivalent combinations based on the essence of the present invention.

Claims

1. A power gating circuit, characterized in that: It includes two inverters, a voltage-dividing sub-circuit, a latch comparator, and a gated switch sub-circuit that are respectively connected to an external 5V power supply circuit. The voltage-dividing sub-circuit divides the 5V voltage output by the external 5V power supply circuit, and the voltage-dividing sub-circuit outputs a first voltage and a second voltage to the latch comparator and the gated switch sub-circuit. The voltage values of the first voltage and the second voltage are both less than the breakdown voltage of the field effect transistor, and the voltage value of the first voltage is greater than the voltage value of the second voltage. The first voltage provides the operating voltage for the two inverters, and the two inverters are connected in series. The external control signal is sequentially input into the two inverters. The latch comparator compares the signals output by the two inverters and latches the comparison result. The gated switch sub-circuit is also connected to the latch comparator and turns off / turns on the entire power gating circuit according to the voltage value of the external control signal to control the output voltage.

2. The power gating circuit according to claim 1, characterized in that: The voltage-dividing sub-circuit is composed of N voltage-dividing field effect transistors, and the N voltage-dividing field effect transistors are sequentially connected in series. Each voltage-dividing field effect transistor is connected in a diode structure. The source of the first voltage-dividing field effect transistor is connected to the external 5V power supply circuit, and the drain of the Nth voltage-dividing field effect transistor is grounded, where N is a natural number greater than 3.

3. The power gating circuit according to claim 2, characterized in that: The gate of each voltage-dividing field effect transistor is connected to its drain, and its substrate is connected to its source, and the aspect ratio of each voltage-dividing field effect transistor is the same.

4. The power gating circuit according to claim 3, characterized in that: Each voltage-dividing field effect transistor is a P-type field effect transistor. The first voltage is led out from the source of the ith voltage-dividing field effect transistor. Correspondingly, the second voltage is led out from the source of the (i + 1)th voltage-dividing field effect transistor, and 3 < i < N, where i is a natural number.

5. The power gating circuit according to claim 2, wherein: The latch comparator includes a first field effect transistor, a second field effect transistor, a third field effect transistor, a fourth field effect transistor, a fifth field effect transistor, a sixth field effect transistor, a seventh field effect transistor, and an eighth field effect transistor. The sources of the first field effect transistor and the second field effect transistor are both connected to the external 5V power supply circuit, and the first field effect transistor and the second field effect transistor are connected in a positive feedback manner. The second voltage is input to the gate of the third field effect transistor. The source of the third field effect transistor is connected to the drain of the first field effect transistor, and its drain is connected to the drain of the fifth field effect transistor. The first voltage is input to the gate of the fifth field effect transistor. The source of the fifth field effect transistor is connected to the drain of the seventh field effect transistor. The output terminal of the second inverter is connected to the gate of the seventh field effect transistor, and the source of the seventh field effect transistor is grounded. The second voltage is input to the gate of the fourth field effect transistor. The source of the fourth field effect transistor is connected to the drain of the second field effect transistor, and its drain is connected to the drain of the sixth field effect transistor. The first voltage is input to the gate of the sixth field effect transistor. The source of the sixth field effect transistor is connected to the drain of the eighth field effect transistor. The output terminal of the first inverter is connected to the gate of the eighth field effect transistor, and the source of the eighth field effect transistor is grounded.

6. The power gating circuit according to claim 5, characterized in that: The gate-controlled switch subcircuit includes a ninth field effect transistor, a tenth field effect transistor, an eleventh field effect transistor and a twelfth field effect transistor; the drain of the ninth field effect transistor is connected to an external 5V power supply circuit, the gate thereof is connected to the drain of the third field effect transistor, the drain is connected to the source of the tenth field effect transistor, the second voltage is input to the gates of the tenth field effect transistor and the eleventh field effect transistor, the drain of the tenth field effect transistor and the drain of the eleventh field effect transistor jointly form an output end, the source of the eleventh field effect transistor is connected to the drain of the twelfth field effect transistor, the gate of the twelfth field effect transistor is connected to the drain of the seventh field effect transistor, and the source thereof is grounded.

7. The power gating circuit according to claim 6, characterized in that: The first field effect transistor, the second field effect transistor, the third field effect transistor, the fourth field effect transistor, the ninth field effect transistor and the tenth field effect transistor are all P-type field effect transistors, and their substrates are all connected to an external 5V power supply circuit.

8. The power gating circuit according to claim 6, characterized in that: The fifth field effect transistor, the sixth field effect transistor, the seventh field effect transistor, the eighth field effect transistor, the eleventh field effect transistor and the twelfth field effect transistor are all N-type field effect transistors, and their substrates are all connected to a low level.

9. The power gating circuit according to claim 5, characterized in that: The first field effect tube and the second field effect tube are connected in a positive feedback manner, specifically, the gate of the first field effect tube is connected to the drain of the second field effect tube, and the gate of the second field effect tube is connected to the drain of the first field effect tube.

10. The power gating circuit according to claim 6, characterized in that: The third field effect transistor, the fourth field effect transistor, the fifth field effect transistor, the sixth field effect transistor, the tenth field effect transistor and the eleventh field effect transistor are voltage-resistant switch transistors.

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