Memory die, memory device, and electronic device

Abstract

A memory die includes a first memory bank including first memory cells, a second memory bank including second memory cells, a first local processor connected with first memory bank local input / output lines, transmitting first local bank data of the first memory bank through the first memory bank local input / output lines, and configured to perform a first local computation on the first local bank data, a second local processor connected with second memory bank local input / output lines, transmitting second local bank data of the second memory bank through the second memory bank local input / output lines, and configured to perform a second local computation on the second local bank data, and a global processor configured to control the first memory bank, the second memory bank, the first local processor, and the second local processor, and perform a global computation on a first local computation result of the first local computation and a second local computation result of the second local computation.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0005896, filed on January 16, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The present invention relates to a memory die, memory device, and electronic device that includes a local processor and a global processor. Background Technology

[0004] Multiple semiconductor dies can be stacked. Three-dimensional memory devices can process large amounts of data at high speeds. To achieve this three-dimensional structure, through-silicon vias (TVS) can be used to stack multiple semiconductor dies. Currently, even with increased data processing speeds, the separation of the processor and memory still causes latency in data transfer between them. To address this issue, in-memory processing (PIM), which integrates both the processor and memory, can be used. Summary of the Invention

[0005] The embodiments provide a memory die, memory device, and electronic device that includes a local processor and a global processor.

[0006] According to an exemplary embodiment, a memory die includes: a first memory bank; a second memory bank; a first local processor connected to a local input / output line of the first memory bank, transmitting first local memory bank data of the first memory bank through the local input / output line, and configured to perform a first local calculation on the first local memory bank data; a second local processor connected to a local input / output line of the second memory bank, transmitting second local memory bank data of the second memory bank through the local input / output line, and configured to perform a second local calculation on the second local memory bank data; and a global processor configured to control the first memory bank, the second memory bank, the first local processor, and the second local processor, and to perform a global calculation on the first local calculation result of the first local calculation and the second local calculation result of the second local calculation.

[0007] This document provides a memory die, comprising: a first memory bank including a first memory cell; a second memory bank including a second memory cell; a first local processor connected to a local input / output line of the first memory bank, transmitting first local memory bank data of the first memory bank through the local input / output line, the first local processor being configured to perform a first local calculation on the first local memory bank data; a second local processor connected to a local input / output line of the second memory bank, transmitting second local memory bank data of the second memory bank through the local input / output line, the second local processor being configured to perform a second local calculation on the second local memory bank data; and a global processor configured to: control the first memory bank, the second memory bank, the first local processor, and the second local processor, and perform a global calculation on the first local calculation result of the first local calculation and the second local calculation result of the second local calculation.

[0008] This document also provides a memory device, including: a first memory die including a first memory bank accessible via a channel, wherein the first memory die is configured to: receive commands for the first memory bank from a host via the channel, and perform data input / output with the host based on the commands via the channel; and a second memory die including: a second memory bank accessible via a channel; a local processor configured to perform local calculations on data in the second memory bank respectively; and a global processor configured to: control the second memory bank and the local processor, and perform global calculations on the local calculation results of the local calculations.

[0009] This document also provides an electronic device, comprising: a memory device including a first memory die and a second memory die, wherein the first memory die includes a first memory bank, and wherein the second memory die includes: a second memory bank; a local processor configured to perform local computations on data in the second memory bank respectively; and a global processor configured to: control the second memory bank and the local processor, and perform global computations on the local computation results of the local computations; and a system-on-a-chip including a memory controller configured to access one of the first memory die and the second memory die via a channel.

[0010] This document also provides a memory die, comprising: a multi-die data bus configured to provide communication with a host, wherein the host is external to the memory die; a global processor directly coupled to the multi-die data bus, the global processor being configured to execute video processing tasks according to commands from the host and to delegate computationally intensive portions of the video processing tasks to local processors; a first local bus gating circuit coupled to the multi-die data bus and the local bus; a second local bus gating circuit coupled to the local bus and the memory bank; and the memory bank; the local processors being coupled via the first local bus gating circuit to the multi-die data bus and via the second local bus gating circuit to the memory bank, wherein the multi-die data bus, the global processor, the local bus, the first local bus gating circuit, the second local bus gating circuit, and the local processors are configured to efficiently utilize limited bus bandwidth for high-speed data processing, wherein the high-speed data processing includes video processing tasks. Attached Figure Description

[0011] The above and other objects and features of the present invention will become clear from the detailed description of exemplary embodiments of the present invention with reference to the accompanying drawings.

[0012] Figure 1 and Figure 2 An electronic device according to an embodiment of the present invention is shown.

[0013] Figure 3 and Figure 4 Detailed illustration Figure 1 and Figure 2 Memory devices.

[0014] Figure 5 It shows Figure 3 and Figure 4 A block diagram of a PIM core.

[0015] Figure 6 It shows Figure 5 A block diagram of the local processor.

[0016] Figure 7 and Figure 8 It shows Figure 3 and Figure 4 A block diagram of a PIM core.

[0017] Figure 9 It shows Figure 1 and Figure 2 Block diagram of the system-on-a-chip.

[0018] Figure 10 It shows Figure 9 An example of a processor accessing a memory controller and a memory controller accessing a memory device.

[0019] Figure 11 It shows Figure 1 and Figure 2 An example of an electronic device performing multiple processes simultaneously.

[0020] Figures 12 to 14 It shows Figure 1 and Figure 2 An example of an on-chip system performing system processing and requesting on-chip processing from the global processor of the memory die.

[0021] Figure 15 An electronic device according to an embodiment is shown. Detailed Implementation

[0022] Figure 1 An electronic device according to an embodiment is shown. The electronic device 100a may include a memory device 1000, a system-on-a-chip (SoC) 2000, and an inserter 3000. The electronic device 100a may also be referred to as a "computing system" or an "electronic system".

[0023] Memory device 1000 may include in-memory processing / in-memory processor (PIM) dies 1100 to 1800 and buffer dies 1900. Each of the PIM dies 1100 to 1800 may also be referred to as a "memory die," "core die," "FIM die," or "slave die," and buffer die 1900 may also be referred to as an "interface die," "logic die," or "supervisor die." A die may also be referred to as a "chip." PIM die 1100 may be stacked on buffer die 1900, and PIM die 1200 may be stacked on PIM die 1100.

[0024] Memory device 1000 may have a three-dimensional memory structure with multiple stacked dies 1100 to 1900. To stack the dies 1100 to 1900, memory device 1000 may include through-silicon vias (TSVs) penetrating the dies 1100 to 1900, and microbumps (BPs) electrically connecting the TSVs. The TSVs and BPs can provide electrical and physical paths between the dies 1100 to 1900 in memory device 1000. The number of TSVs and BPs is not limited to... Figure 1 The example shown.

[0025] Memory device 1000 may relate to PIM or FIM, and in addition to reading and writing data, memory device 1000 may also perform data processing operations. Memory device 1000 may correspond to a computing memory device including random access memory (RAM) and processing element (PE) integrated in the same die. Each PIM die 1100 to 1800 of memory device 1000 may include a memory cell array (MCA) for reading and writing data and including multiple memory cells, and a processing element (PE) for performing data processing operations. For example, PE may also be referred to as a "processor" or "processing circuitry". A stack identifier SID0 may be assigned to PIM dies 1100 to 1400, and a stack identifier SID1 may be assigned to PIM dies 1500 to 1800. Stack identifiers SID0 / SID1 may be used to identify or distinguish multiple PIM dies 1100 to 1800 stacked on buffer die 1900. For example, memory controller 2100 can access PIM dies 1100 to 1400 or PIM dies 1500 to 1800 using stack identifiers SID0 / SID1. The number of PIM dies 1100 to 1800 for each stack identifier SID0 / SID1 and the number of PIM dies 1100 to 1400 / 1500 to 1800 are not limited to... Figure 1 The example shown.

[0026] Buffer die 1900 can operate as an interface circuit between memory controller 2100 and PIM dies 1100 to 1800 (or related to or associated with memory controller 2100 and PIM dies 1100 to 1800). Buffer die 1900 can receive commands, data, signals, etc., sent from memory controller 2100 through inserter 3000, and can transmit the received commands, data, signals, etc., to PIM dies 1100 to 1800 through through-silicon vias (TSVs) and microbumps (BPs). Buffer die 1900 can receive data output from PIM dies 1100 to 1800 through through-silicon vias (TSVs) and microbumps (BPs), and can transmit the received data to memory controller 2100 through inserter 3000. Buffer die 1900 may include a physical layer (PHY) 1980, buffer circuitry, or interface circuitry for receiving and amplifying the above signals.

[0027] In embodiments, memory device 1000 may be a general-purpose dynamic random-access memory (DRAM) such as DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), a mobile DRAM device such as LPDDR (Low Power Double Data Rate) SDRAM, a graphics DRAM device such as GDDR (Graphics Double Data Rate) SGRAM (Synchronous Graphics Random Access Memory), or a high-capacity, high-bandwidth DRAM device such as Wide I / O, HBM (High Bandwidth Memory), HBM2, HBM3, or HMC (Hybrid Memory Cube). System-on-a-chip 2000 can use memory device 1000 to execute applications supported by electronic device 100a. System-on-a-chip 2000 may also be referred to as a "host" or "application processor (AP)". System-on-a-chip 2000 may include a memory controller 2100 that controls memory device 1000 and performs data input / output with memory device 1000. For example, memory controller 2100 may access memory device 1000 in a direct memory access (DMA) manner. The memory controller 2100 may include a PHY 2180, which is electrically connected to the PHY 1980 of the memory device 1000 via an inserter 3000.

[0028] The interposer 3000 can connect the system-on-chip 2000 and the memory device 1000. The interposer 3000 provides a physical path connecting the memory device 1000 and the PHY 2180 of the system-on-chip 2000, and is formed of a conductive material for electrical connection. A substrate or printed circuit board (PCB) can be used instead of the interposer 3000.

[0029] Figure 2 An electronic device according to another embodiment of the present invention is illustrated. Electronic device 100b may include a memory device 1000 and a system-on-chip 2000. The memory device 1000 and system-on-chip 2000 in electronic device 100a may be interconnected via an inserter 3000, while the memory device 1000 of electronic device 100b may be stacked on the system-on-chip 2000. The system-on-chip 2000 may also include a through-silicon via (TSV) for providing an electrical connection to the memory device 1000, and PHYs 1980 and 2180 may be electrically interconnected via microbumps (BP).

[0030] Figure 3 Detailed illustration Figure 1 and Figure 2The memory controller 2100 can access the memory device 1000 through channels CH1 to CHk (k being a natural number of 2 or greater). For example, PIM dies 1100 and 1500 can be assigned to channel CH1, and PIM dies 1400 and 1800 can be assigned to channel CHk. As described above, the remaining dies 1200, 1300, 1600, and 1700 can be assigned to channels. PIM dies 1100 and 1500 assigned to the same channel CH1 can be identified by the stack identifier SID0 / 1. The memory device 1000 can include paths Path_1 to Path_K, which correspond to channels CH1 to CHk respectively, and signals transmitted through channels CH1 to CHk are transmitted through paths Path_1 to Path_K. Paths Path_1 to Path_K can provide electrical connection paths between buffer die 1900 and PIM dies 1100 to 1800, and can include references Figure 1 and Figure 2 Described vias (TSV) and bumps (BP).

[0031] PIM die 1100 may include memory banks BG0 to BG3, data buses DB0 and DB1, memory bank controllers BCTRL0 and BCTRL1, a global processor GP, a command and address decoder CADEC, and data input / output circuitry DATAIO. Although only PIM die 1100 is described and shown in detail, the configuration and operation of the remaining PIM dies 1200 to 1800 are substantially the same as those of PIM die 1100. A memory bank group can be identified by memory bank address bits BA2 and BA3 of memory bank addresses BA0 to BA3 (or referred to as "memory bank address bits BA0 to BA3"). For example, memory bank group BG0 can be selected when BA2 = 0 and BA3 = 0. Memory bank group BG0 may include memory banks BK0 to BK3. A memory bank within a memory bank group can be identified by memory bank address bits BA0 and BA1 of memory bank addresses BA0 to BA3. For example, when BA0 = 0, BA1 = 0, BA2 = 0 and BA3 = 0, the storage bank BK0 can be selected.

[0032] Figure 1 and Figure 2The memory cell array MCA can be divided into memory banks BK0 to BK15. Each of the memory banks BK0, BK2, BK4, BK6, BK8, BK10, BK12, and BK14, which can be selected when the memory bank address bit BA0 corresponding to the LSB in memory bank address bits BA0 to BA3 is "0", can be referenced as the top (or even) memory bank. Each of the memory banks BK1, BK3, BK5, BK7, BK9, BK11, BK13, and BK15, which can be selected when the memory bank address bit BA0 corresponding to the LSB in memory bank address bits BA0 to BA3 is "1", can be referenced as the bottom (or odd) memory bank. For example, each of memory banks BK0 to BK15 may include an equal number of memory cells, and each of memory bank groups BG0 to BG3 may include an equal number of memory banks. For example, memory banks BG0 to BG3 can be implemented as identical, and memory banks BK0 and BK15 can be implemented as identical.

[0033] Memory bank group BG0 may include local processors LP0 to LP3 (LP0, LP1, LP2, LP3). For example, local processor LP0 can perform local calculations on the data (or local memory data) of memory bank BK0, local processor LP1 can perform local calculations on the data of memory bank BK1, local processor LP2 can perform local calculations on the data of memory bank BK2, and local processor LP3 can perform local calculations on the data of memory bank BK3. Local processors may also be referred to as "local processing circuits," "local PE," or "local PE circuits," etc.

[0034] Memory bank group BG1 may include local processors LP4 to LP7 (LP4, LP5, LP6, LP7) that perform local computations on the data of memory banks BK4 to BK7 (BK4, BK5, BK6, BK7), respectively. Similar to memory banks BG0 and BG1, memory banks BG2 and BG3 may include local processors LP8 to LP15 (LP8, LP9, LP10, LP11, LP12, LP13, LP14, LP15), and perform local computations on the data of memory banks BK8 to BK15 (BK8, BK9, BK10, BK11, BK12, BK13, BK14, BK15), respectively. For example, local processors LP0 to LP15 may correspond to... Figure 1 and Figure 2 Each PIM die has 1100 to 1800 PE, or can be constructed Figure 1 and Figure 2 Each PIM die 1100 to 1800 has a PE (polyethylene) layer. The number of memory cell groups included in a PIM die 1100 and the number of memory cells in each memory cell group are not limited to... Figure 3An example is shown where a channel CH1 is assigned to PIM die 1100, and memory groups BG0 to BG3 and memory groups BK0 to BK15 are assigned to channel CH1, but the embodiment is not limited thereto.

[0035] One or more different channels can be further assigned to the PIM die 1100, and the PIM 1100 may also include memory cells and memory cell groups assigned to different channels. For example, the PIM die 1100 may include memory cell groups BG0 to BG15 and memory cells BK0 to BK63 assigned to four channels CH1 to CH4; as in Figure 3 As illustrated in channel CH1, memory bank groups and memory banks for each channel can be implemented in the PIM die 1100. A memory bank group comprises four local processors, and one local processor is assigned to one memory bank; however, a memory bank group may include local processors, the number of which is less than the number of memory banks, and one local processor may be assigned to two or more memory banks. In any case, the embodiments are not limited to the above values.

[0036] Data bus DB0 may include data input / output paths associated with memory banks BG0 and BG1. For example, data to be written to memory banks BK0 through BK3 or memory banks BK4 through BK7, data to be read from memory banks BK0 through BK3 or memory banks BK4 through BK7, data to be processed by local processors LP0 through LP3 or local processors LP4 through LP7, and data processed by local processors LP0 through LP3 or local processors LP4 through LP7 can be sent via data bus DB0. Data bus DB1 may include data input / output paths associated with memory banks BG2 and BG3. Besides the assigned memory banks, data buses DB0 and DB1 can be implemented as identical or can be integrated.

[0037] Memory controller BCTRL0 can control memory banks BK0 to BK7 of memory banks BG0 and BG1 under the control of command and address decoder CADEC. Memory controller BCTRL1 can control memory banks BK8 to BK15 of memory banks BG2 and BG3 under the control of command and address decoder CADEC. For example, memory controllers BCTRL0 and BCTRL1 can activate or precharge memory banks BK0 to BK15. Besides the assigned memory banks, memory controllers BCTRL0 and BCTRL1 can be implemented as identical or can be integrated.

[0038] The global processor (GP) can control memory banks BK0 to BK15 within memory banks BG0 to BG3 and local processors LP0 to LP15 under the control of the command and address decoder CADEC. For example, the GP can select data to be processed by local processors LP0 to LP15, or control the timing of starting or terminating local computations by local processors LP0 to LP15. Figure 3 The examples shown are different. For example, the global processor GP can be divided into a first global processor and a second global processor. The first global processor controls the memory banks BK0 to BK7 in memory banks BG0 and BG1 and the local processors LP0 to LP7. The second global processor controls the memory banks BK8 to BK15 in memory banks BG2 and BG3 and the local processors LP8 to LP15.

[0039] The command and address decoder CADEC can be based on the clock signal CK sent via channel CH1 and path Path_1 (reference). Figure 9 To receive command and address signals CA (see reference) sent via channel CH1 and path Path_1. Figure 9 The Command and Address Decoder (CADEC) can decode the command and address signals (CA). Based on the decoding results, the CADEC can control the components of the PIM die 1100.

[0040] Under the control of the command and address decoder CADEC, the data input / output circuit DATAIO can receive the data input / output signal DQ (reference) sent through channel CH1 and path Path_1. Figure 9 The data input / output circuit DATAIO can receive read data from memory banks BK0 to BK15 in memory banks BG0 to BG3 and local processors LP0 to LP15, and can output the data input / output signal DQ including the read data. The data input / output signal DQ including the read data can be sent to the memory controller 2100 through path Path_1 and channel CH1.

[0041] Figure 4 Detailed illustration Figure 1 and Figure 2 Memory devices. Will be focused on Figure 3 Memory device 1000 and Figure 4The differences between memory devices 1000 are described. Memory device 1000 may include PIM dies 1100 to 1400 and memory dies 1500 to 1800. Each PIM die 1100 to 1400 may be associated with... Figure 3 The PIM die 1100 is basically the same. Each memory die 1500 to 1800 can be compared with... Figure 3 The PIM die 1100 differs from the PIM die 1500. The memory die 1500 may include memory banks BG0 to BG3, memory banks BK0 to BK15, data buses DB0 and DB1, memory bank controllers BCTRL0 and BCTRL1, command and address decoder CADEC, and data input / output circuitry DATAIO. The memory die 1500 may not include local processors LP0 to LP15 and a global processor GP, and may not be referred to as a "PIM die". The configuration and operation of each of the remaining memory dies 1600 to 1800 may be substantially the same as those of the memory die 1500.

[0042] Figure 5 It shows Figure 3 and Figure 4 A block diagram of a PIM core. In Figure 5 Only memory bank group BG0 is shown in detail; however, as mentioned above, the remaining memory bank groups BG1 to BG3 can be implemented identically to memory bank group BG0. (See reference...) Figure 7 and Figure 8 describe Figure 5 The components CADEC and DATAIO are omitted. Memory bank BG0 may include row decoder RD0 and column decoder CD0. Row decoder RD0 can decode the row address of the memory address and can select and activate the word line WL0 of memory bank BK0. Here, the memory address can be obtained from... Figure 1 and Figure 2 The memory controller 2100 outputs information and can be used to access components of the memory device 1000. For example, the memory bank BK0 can be in an active state (or pre-charge state) when word line WL0 is activated (or deactivated). The column decoder CD0 can decode the column address of the memory address and can select and activate the column select line CSL0 of the memory bank BK0. The memory bank BK0 may include memory cells MC0 accessed via word line WL0 and column select line CSL0. The memory bank BK0 may also include memory cells accessed via other word lines and other column select lines.

[0043] The memory bank group BG0 may further include an input / output sense amplifier IOSA0, a write driver WDRV0, a ​​memory bank local input / output gating circuit BLIOGT0, a memory bank global input / output gating circuit BGIOGT0, and a data bus input / output gating circuit DBIOGT0. The input / output sense amplifier IOSA0 can sense and amplify read data output from the memory cell MC0 through the cell input / output line CIO0, and can output the read data to the memory bank local input / output line BLIO0. The write driver WDRV0 can receive write data sent through the memory bank local input / output line BLIO0, and can write write data to the memory cell MC0 through the cell input / output line CIO0.

[0044] The memory local input / output gating circuit BLIOGT0 can electrically connect the write driver WDRV0 to the memory local input / output line BLIO0, or electrically disconnect the write driver WDRV0 from the memory local input / output line BLIO0. The memory local input / output gating circuit BLIOGT0 can also electrically connect the input / output sense amplifier IOSA0 to the memory local input / output line BLIO0, or electrically disconnect the input / output sense amplifier IOSA0 from the memory local input / output line BLIO0. The memory global input / output gating circuit BGIOGT0 can electrically connect the memory local input / output line BLIO0 to the memory global input / output line BGIO0, or electrically disconnect the memory local input / output line BLIO0 from the memory global input / output line BGIO0. The memory global input / output line BGIO0 can be shared by memory cells BK0 to BK3 in memory cell group BG0. The data bus input / output gating circuit DBIOGT0 can electrically connect the memory bank global input / output line BGIO0 to the data bus DB0, or electrically disconnect the memory bank global input / output line BGIO0 from the data bus DB0. The data bus DB0 can be shared by memory banks BG0 and BG1. For example, each of the memory bank local input / output gating circuit BLIOGT0, the memory bank global input / output gating circuit BGIOGT0, and the data bus input / output gating circuit DBIOGT0 can operate as an input / output multiplexer or switch. The aforementioned components RD0, CD0, IOSA0, WDRV0, BLIOGT0, and BGIOGT0 can be used for data input / output of memory bank BK0. As described above, for the data input / output of memory banks BK1 to BK3, memory bank group BG0 may further include row decoders RD1 to RD3 (RD1, RD2, RD3), column decoders CD1 to CD3 (CD1, CD2, CD3), input / output sense amplifiers IOSA1 to IOSA3 (IOSA1, IOSA2, IOSA3), write drivers WDRV1 to WDRV3 (WDRV1, WDRV2, WDRV3), memory bank local input / output gating circuits BLIOGT1 to BLIOGT3 (BLIOGT1, BLIOGT2, BLIOGT3), and memory bank global input / output gating circuits BGIOGT1 to BGIOGT3 (BGIOGT1, BGIOGT2, BGIOGT3).

[0045] The local processor LP0 can be connected to the memory local input / output line BLIO0 and the memory global input / output line BGIO0. The local processor LP0 can perform local computations on at least one of the following: data sent via the memory local input / output line BLIO0, data sent via the memory global input / output line BGIO0, or internally generated data. For example, data sent via the memory global input / output line BGIO0 can be substantially the same as data sent via the data bus DB0.

[0046] As mentioned above, memory groups BG0 through BG4 can be implemented as identical. Figure 5 The following example is shown: memory banks BG1 to BG3 each include data bus input / output gating circuits DBIOGT1 to DBIOGT3, but memory banks BG1 to BG3 may include the remaining components of memory bank BG0.

[0047] The global processor GP can be connected to data buses DB0 and DB1. The global processor GP can perform global calculations on at least one of the following: data sent via data bus DB0, data sent via data bus DB1, internally generated data, and data sent from outside the memory device 1000 (e.g., system-on-chip 2000). For example, the global processor GP can perform global calculations on at least a portion or all of the local calculation results of local processors LP0 to LP15 sent via memory global input / output lines BGIO0 to BGIO3, data bus input / output strobe circuits DBIOGT0 to DBIOGT3, and data buses DB0 and DB1. For example, the global calculation can be ReLU (rectified linear unit), Softmax, or calculations of minimum (min), maximum (max), or average (avg).

[0048] Figure 6 It shows Figure 5A block diagram of the local processor. The local processor LP0 may include an input multiplexer IMUX, a local processing unit (LPE) array LPA, a local register REG, and an output multiplexer OMUX. The input multiplexer IMUX can receive local memory data (or write data or read data) from memory bank BK0 via the memory bank local input / output line BLIO0, receive data from memory bank group BG0 via the memory bank global input / output line BGIO0, and receive local register data from the register output line RO0. Here, the data from memory bank group BG0 can be one of the following: data from other memory banks BK1 to BK3 in memory bank group BG0, data from other memory banks BK4 to BK15 in other memory bank groups BG1 to BG3 transmitted via data buses DB0 and DB1, broadcast data transmitted via data buses DB0 and DB1 and broadcast by the global processor GP, and external data received via the data input / output circuit DATAIO and transmitted via data buses DB0 and DB1. Broadcast data can indicate that the global processor GP sends data to all local processors LP0 to LP15 or all memory banks BK0 to BK15. The input multiplexer IMUX can provide at least one of the above data to the LPE array LPA based on the input control signal ICTRL0, and can also provide the above data to the LPE array LPA as operands OPA to OPC.

[0049] The LPE array LPA can perform local calculations on at least one of the above data based on the processing control signal PCTRL0. For example, the local calculations that can be performed by the LPE array LPA can be various arithmetic or logical operations, such as addition, subtraction, multiplication, division, shift, AND, NAND, OR, NOR, XNOR, and XOR. The local register REG can receive and store the local calculation results of the LPE array LPA through the register input line RI0 based on the register control signal RCTRL0. The local register REG can output the stored local calculation results as local register data to the register output line RO0 based on the register control signal RCTRL0. The output multiplexer OMUX can output the local register data of the local register REG to at least one of the memory local input / output line BLIO0, the register output line RO0, and the memory global input / output line BGIO0 based on the output control signal OCTRL0.

[0050] Figure 7 It shows Figure 3 and Figure 4 A block diagram of a PIM die. The PIM die 1100a can be... Figure 3 and Figure 4An example of the PIM die 1100. The command and address decoder CADEC can decode the command and address signals CA and control the memory controllers BCTRL0 and BCTRL1, the data input / output circuit DATAIO, and the global processor GPa. The memory controller BCTRL0 can control the read and write operations of the memory cells in memory groups BG0 and BG1. The memory controller BCTRL1 can control the read and write operations of the memory cells in memory groups BG2 and BG3. The data input / output circuit DATAIO can output the data of the data input / output signal DQ to the data buses DB0 and DB1, or it can output the data input / output signal DQ including the data of the data buses DB0 and DB1. The data buses DB0 and DB1 can... Figures 3 to 5 They are separated from each other as in the example, or they can be like... Figure 7 The examples are integrated into a single bus.

[0051] Global Processor GPa can be Figure 5 An example of a Global Processor (GP). A Global Processor (GP) may include a processor controller 1001a, a program buffer 1002, an instruction queue 1003, an instruction decoder 1004, a local processor and memory controller 1005, a Global Processing Element (GPE) array 1006, a global register 1007, and a data buffer 1008. The processor controller 1001a may receive commands (CMD) and memory addresses (ADD) from the command and address decoder (CADEC). The processor controller 1001a may control the remaining components 1002 to 1008 of the Global Processor (GP) based on the commands (CMD) and memory addresses (ADD). For example, the processor controller 1001a may include a control register storing control information. The control information stored in the control register can be changed using commands (CMD) and memory addresses (ADD). The processor controller 1001a may control the remaining components 1002 to 1008 of the Global Processor (GP) based on the control information.

[0052] The program buffer 1002 can store the host program. The host can be an on-chip system 2000 or a device external to the memory device 1000. In an embodiment, such as Figure 7 As shown, the data input / output circuit DATAIO can receive data input / output signals DQ, including the host program, and can output the host program to data buses DB0 and DB1. The program buffer 1002 can receive and store the host program via data buses DB0 and DB1. In another embodiment, with... Figure 7Unlike the example shown, the command and address decoder CADEC can receive command and address signals CA, including the host's program, and can output the host's program to program buffer 1002. In any case, the host's program stored in program buffer 1002 can be updated. Program buffer 1002 can write or provide program instructions to instruction queue 1003. Instruction queue 1003 can store program instructions in program buffer 1002. Instruction decoder 1004 can retrieve instructions stored in instruction queue 1003 and can decode the instructions. Instruction decoder 1004 can determine whether the decoded instruction is associated with a local computation (or processing) or a global computation. For example, a local computation may indicate that it can be accessed by a reference... Figures 3 to 6 The description refers to computations performed by local processors, and global computations can indicate computations that can be performed by the global processor (GP).

[0053] When the decoded instruction is associated with local computation, the instruction decoder 1004 can provide the local computation instruction information LP_INSTR to the local processor and memory controller 1005. The local processor and memory controller 1005 can control local processors LP0 to LP15 and memory banks BK0 to BK15 based on the local computation instruction information LP_INSTR. For example, the local processor and memory controller 1005 can generate a PE control signal PE_CTRL based on the local computation instruction information LP_INSTR. The PE control signal PE_CTRL may include control signals ICTRL0, PCTRL0, RCTRL0, and OCTRL0 to be provided to local processor LP0 (see reference). Figure 6The system provides additional control signals to the remaining local processors LP1 to LP15. Furthermore, the local processors and memory controller 1005 can generate memory bank control signals BK_CTRL based on the local computation instruction information LP_INSTR. The local processors and memory controller 1005 can provide or send memory bank control signals BK_CTRL as memory bank controllers BCTRL0 and BCTRL1. Memory bank controllers BCTRL0 and BCTRL1 can control read and write operations of memory cells in memory bank groups BG0 to BG3 in response to the memory bank control signals BK_CTRL. The global processor GPa can execute the host program; when the program is executed, the global processor GPa can control local processors LP0 to LP15 or memory banks BK0 to BK15. Under the control of the global processor GPa, local processors LP0 to LP15 can perform computations and can perform data input / output to memory banks BK0 to BK15. The global processor GPa can execute the host program by requesting computations that can be performed by local processors LP0 to LP15, or data input / output to memory banks BK0 to BK15. In an embodiment, based on local computation instruction information LP_INSTR, the local processor and memory controller 1005 can control one of the local processors LP0 to LP15, or can simultaneously control two or more of the local processors LP0 to LP15. Furthermore, based on the local computation instruction information LP_INSTR, the local processor and memory controller 1005 can control one of the memory banks BK0 to BK15, or can simultaneously control two or more of the memory banks BK0 to BK15. For example, the local processor and memory controller 1005 can process at least one bit of the memory bank address to identify memory banks BK0 to BK15 as irrelevant bits.

[0054] When the decoded instruction is associated with a global computation, the instruction decoder 1004 can provide the global computation instruction information GP_INSTR to the GPE array 1006. The GPE array 1006 can perform a global computation based on the global computation instruction information GP_INSTR. For example, the computation that can be performed by the GPE array 1006 can be various arithmetic or logical operations, such as addition, subtraction, multiplication, division, shift, AND, NAND, OR, NOR, XNOR, and XOR. The global register 1007 can store the global computation result performed by the GPE array 1006. The global register 1007 can provide the global computation result as global computation output data GP_DOUT to the data buffer 1008. Data buffer 1008 can receive local calculation results executed by local processors LP0 to LP15 via data buses DB0 and DB1, receive external data included in the data input / output signal DQ sent from data input / output circuit DATAIO via data buses DB0 and DB1, and can receive global calculation output data GP_DOUT. Data buffer 1008 can provide at least one of the following to GPE array 1006 as global calculation input data GP_DIN: local calculation results, external data, and global calculation output data GP_DOUT. Data buffer 1008 can output the global calculation output data GP_DOUT to data buses DB0 and DB1. Data input / output circuit DATAIO can output a data input / output signal DQ including the global calculation output data GP_DOUT.

[0055] The memory controller 2100 of the system-on-a-chip 2000 can request calculations that can be executed by local processors LP0 to LP15, or data input / output of memory banks BK0 to BK15, by sending command and address signals CA to the memory device 1000. As described above, the global processor GPa can execute the host program. As in the memory controller 2100, which is an embedded memory controller, the global processor GPa can request calculations that can be executed by local processors LP0 to LP15 or data input / output of memory banks BK0 to BK15. For example, when the global processor GPa executes the host program, the global processor GPa can perform on-chip processing by requesting data input / output (e.g., read and write operations) of memory banks BK0 to BK15, or calculations that can be executed by local processors LP0 to LP15, or by performing global calculations. In other words, the term "on-die processing" can refer to computation (or processing) performed on a single die (e.g., 1100a) by a global processor (e.g., GPa) belonging to that single die: either computation (or processing) of data stored in memory belonging to that single die (e.g., BK0 to BK15), or computation of the results of computations that can be performed by local processors belonging to that single die (e.g., LP0 to LP15). Therefore, as a result of on-die processing, the computed (or processed) data can be output from the single die to an external device (e.g., a host).

[0056] Figure 8 It shows Figure 3 and Figure 4 A block diagram of a PIM die. The PIM die 1100b can be... Figure 3 and Figure 4Another example of PIM die 1100. The differences between PIM die 1100b and PIM die 1100a will be described focusing on the differences. PIM die 1100b may further include interrupt input / output circuitry 1010. Interrupt input / output circuitry 1010 may receive an interrupt signal INTR (or start interrupt signal) sent from the memory controller 2100 of the system-on-chip 2000, and may provide the interrupt signal INTR to the processor controller 1001b of the global processor GPb. Interrupt input / output circuitry 1010 may receive an interrupt signal INTR (or end interrupt signal) sent from the processor controller 1001b of the global processor GPb, and may provide the interrupt signal INTR to the memory controller 2100 of the system-on-chip 2000. For example, the interrupt signal INTR may be a bidirectional signal similar to the data input / output signal DQ. In another example, the interrupt signal INTR can be a unidirectional signal, and the start interrupt signal INTR sent from the memory controller 2100 of the system-on-chip 2000 and the end interrupt signal INTR provided from the processor controller 1001b of the global processor GPb can be different.

[0057] In addition to commands (CMD) and addresses (ADD), the processor controller 1001b can also control the remaining components 1002 to 1008 of the global processor GPb based on the interrupt signal INTR. For example, the processor controller 1001b can control the remaining components 1002 to 1008 of the global processor GPb in response to the interrupt signal INTR, thereby initiating the execution of on-die processing. When the global computation is complete, the processor controller 1001b can generate an interrupt signal INTR indicating the completion of the global computation and can provide the interrupt signal INTR to the interrupt input / output circuit 1010.

[0058] Figure 9 It shows Figure 1 and Figure 2 The block diagram of the system-on-a-chip (SoC) 2000 is shown. The SoC 2000 may include a memory controller 2100, a processor 2200, an on-chip memory 2300, and a system bus 2400.

[0059] The memory controller 2100 may include a control register 2111, a memory status register 2112, a system bus interface circuit 2120, a memory request queue 2130, an address converter 2140, a memory command queue 2150, a command scheduler 2160, a command sequencer 2170, a PHY 2180, a read buffer 2191, and a write buffer 2192.

[0060] Control register 2111 can store and provide control information for components 2120, 2130, 2140, 2150, 2160, 2170, 2180, 2191, and 2192 in memory controller 2100. The control information stored in control register 2111 can be changed by processor 2200 or by user request. Components 2120, 2130, 2140, 2150, 2160, 2170, 2180, 2191, and 2192 can operate based on the control information stored in control register 2111.

[0061] The memory bank status register 2112 can store the status information of multiple memory banks in the memory device 1000 (see reference). Figure 3 and Figure 4 For example, status information can indicate whether the memory has been activated or precharged.

[0062] The system bus interface circuit 2120 can receive memory requests sent from multiple cores 2210 to 2240 in the processor 2200 via the system bus 2400 based on the communication protocol of the system bus 2400. The system bus interface circuit 2120 can provide, send, or write the received memory requests to the memory request queue 2130.

[0063] Memory request queue 2130 can receive and store memory requests generated in the system-on-chip 2000 and provided from the system bus interface circuit 2120. A memory request associated with memory device 1000 can request an operation on memory device 1000 (e.g., a read operation, write operation, refresh operation, or processing) and can include the physical address of memory device 1000. Unlike virtual addresses, physical addresses can be used to access memory device 1000 and can be limited according to the capacity of memory device 1000. Generating memory requests at the system-on-chip 2000 can be faster than the memory device 1000 can process memory requests. Memory request queue 2130 can store multiple memory requests.

[0064] Address translator 2140 can translate the physical address of a memory request stored in memory request queue 2130 into a memory address. For example, address translator 2140 can map some bits of the physical address to a memory address. Some bits of the physical address can correspond to the memory address. The memory address may include a stack identifier SID, a bank address, a row address, and a column address. The stack identifier SID can be used to identify references. Figures 1 to 2The PIM dies 1100 to 1800 are described. Memory bank addresses can be used to identify memory banks BK0 to BK15 that constitute the memory cell array MCA of each PIM die 1100 to 1800. Row and column addresses can be used to identify memory cells within the memory bank (e.g., MC0).

[0065] The memory command queue 2150 can store memory commands for memory requests stored in the memory command queue 2150, as well as memory addresses translated by the address translator 2140. The command scheduler 2160 can adjust the processing order of memory commands and memory addresses stored in the memory command queue 2150 based on memory bank status information stored in the memory bank status register 2112. The command scheduler 2160 can perform scheduling on the memory commands and memory addresses stored in the memory command queue 2150. The command sequencer 2170 can output or provide the memory commands and memory addresses stored in the memory command queue 2150 to the PHY 2180 based on the scheduling order by the command scheduler 2160.

[0066] PHY 2180 can access memory device 1000 based on memory commands and memory addresses provided from command sequencer 2170. PHY 2180 can also be referred to as a "memory interface circuit". For example, PHY 2180 can generate and output command and address signals CA based on memory requests from memory request queue 2130 and memory addresses from address converter 2140. PHY 2180 can send memory commands and memory addresses based on memory requests to memory device 1000. PHY 2180 may include clock generator 2181, command and address generator 2182, receiver 2183, and transmitter 2184. Clock generator 2181 can generate a clock signal CK to be output to memory device 1000. For example, memory device 1000 may be a synchronous memory device operating based on clock signal CK. Command and address generator 2182 can receive memory commands and memory addresses from command sequencer 2170 and can send command and address signals CA, including memory commands and memory addresses, to memory device 1000. Command and address generator 2182 can modify the logical value of command and address signal CA differently based on the memory request in memory request queue 2130 and the memory address in address converter 2140. Receiver 2183 can receive data input / output signal DQ, including read data sent from memory device 1000. Receiver 2183 can provide the received read data to read buffer 2191. Transmitter 2184 can receive write data from write buffer 2192. Transmitter 2184 can send data input / output signal DQ, including write data, to memory device 1000.

[0067] Figure 9 The channel CH can correspond to Figure 3 and Figure 4 One of the channels CH1 to CHK. Command and address signals CA and data input / output signals DQ can be provided relative to channel CH. The PHY 2180 can generate and output clock signals CK and command and address signals CA for each channel CH1 to CHK, and can exchange the data input / output signals DQ for each channel CH1 to CHK with the memory device 1000. Assuming... Figure 3 and Figure 4 The number of channels CH1 to CHK is "4" (i.e., K = 4). However, the embodiments are not limited to the above values. For example, the memory controller 2100 can access PIM dies 1100 and 1500 through channel CH1, PIM dies 1200 and 1600 through channel CH2, PIM dies 1300 and 1700 through channel CH3, and PIM dies 1400 and 1800 through channel CH4. PIM dies 1100 and 1500 can share channel CH1, PIM dies 1200 and 1600 can share channel CH2, PIM dies 1300 and 1700 can share channel CH3, and PIM dies 1400 and 1800 can share channel CH4.

[0068] The memory controller 2100 can select one of a plurality of PIM dies assigned to a channel by using a stack identifier SID of the memory address. The memory controller 2100 can access one of the plurality of PIM dies assigned to a channel by using a memory address. For example, when the stack identifier SID has a first logical value (i.e., SID0), command and address signals CA and data input / output signals DQ transmitted through channels CH1 to CH4 can be associated with PIM dies 1100 to 1400. For example, when the stack identifier SID has a second logical value (i.e., SID1), command and address signals CA and data input / output signals DQ transmitted through channels CH1 to CH4 can be associated with PIM dies 1500 to 1800. For example, the number of PIM dies assigned to each channel, the number of channels, the number of channels assigned to a PIM die, etc., are not limited to the examples above. For example, a portion of the physical address bits can indicate whether the memory address is associated with any of the channels CH1 to CH4, and can be used to distinguish between channels CH1 to CH4.

[0069] Read buffer 2191 can store read data provided from receiver 2183. For example, read buffer 2191 can provide as much read data as cache line CL to system bus interface circuit 2120, and system bus interface circuit 2120 can send the read data to processor 2200 or on-chip memory 2300 via system bus 2400. Write buffer 2192 can receive and store write data provided from system bus interface circuit 2120 for transmission to memory device 1000. Write buffer 2192 can provide as much write data as the data input / output unit of memory device 1000 to transmitter 2184.

[0070] Processor 2200 can execute various software (e.g., applications, operating systems, file systems, and device drivers) loaded onto on-chip memory 2300. Processor 2200 may include multiple homogeneous cores or multiple heterogeneous cores, and may include multiple cores 2210 to 2240. For example, each of cores 2210 to 2240 may include at least one of a central processing unit (CPU), an image signal processing unit (ISP), a digital signal processing unit (DSP), a graphics processing unit (GPU), a vision processing unit (VPU), a tensor processing unit (TPU), and a neural processing unit (NPU). Each of cores 2210 to 2240 can generate a memory request associated with memory device 1000. The memory request generated by each of cores 2210 to 2240 may include the aforementioned physical address. For example, processor 2200 can perform system processing using memory controller 2100, which accesses PIM die 1100 and PIM / memory die 1500 in memory device 1000 via channel CH, sharing channel CH. Figure 7 and Figure 8 The on-chip processing and system processing performed by the global processor GPa / GPb can be executed independently (or separately).

[0071] Applications, operating systems, file systems, device drivers, etc., used to drive electronic devices 100a / 100b can be loaded onto the on-chip memory 2300. For example, the on-chip memory 2300 can be static RAM (SRAM) with a higher data input / output speed than memory device 1000, or it can be a cache memory shared by cores 2210 to 2240, but the embodiments are not limited to these. System bus 2400 can provide a communication path between memory controller 2100, processor 2200, and on-chip memory 2300. For example, system bus 2400 can be AHB (Advanced High Performance Bus), ASB (Advanced System Bus), APB (Advanced Peripheral Bus), or AXI (Advanced Extensible Interface) based on AMBA (Advanced Microcontroller Bus Architecture).

[0072] Figure 10 It shows Figure 9 Examples of processors accessing memory controllers and memory controllers accessing memory devices. For example, processor 2200 may access memory controller 2100 in a memory-mapped I / O (MMIO) manner. The system address space (or region) may include space allocated to memory controller 2100. Although not shown in the figures, the system address space may also include space allocated to any other component in the system-on-chip 2000 (e.g., on-chip memory 2300, intellectual property (IP) blocks, and controllers). Processor 2200 can access and control memory controller 2100 and any other component in the system-on-chip 2000 using the same system address space. Processor 2200 may access the space allocated to memory controller 2100 from the system address space and may write values ​​to the space allocated to memory controller 2100 using write instructions. Memory controller 2100 may respond to the value and, for example, may receive a memory request from processor 2200. Memory controller 2100 may ignore values ​​written from the remaining space in the system address space other than the space allocated to memory controller 2100.

[0073] The space allocated from the system address space to the memory controller 2100 can be a physical address space, can correspond to a physical address space, or can be mapped onto a physical address space. The physical address space can correspond to a range of physical addresses associated with a memory request. The physical address space can include space allocated to the control register 2111 and space allocated to the memory device 1000. The space allocated from the system address space to the memory controller 2100 can include space corresponding to the space allocated from the physical address space to the control register 2111, and the processor 2200 can change the value (or information) of the control register 2111 by accessing the space corresponding to the space allocated to the control register 2111. As described above, the space allocated from the system address space to the memory controller 2100 can include space corresponding to the space allocated from the physical address space to the memory device 1000, and the processor 2200 can access the memory device 1000 by accessing the space corresponding to the space allocated to the memory device 1000.

[0074] The memory controller 2100 can also access the memory device 1000 in MMIO mode. The physical address space may include the space allocated to the memory device 1000. The memory controller 2100 can access the space allocated to the memory device 1000 from the physical address space, and can translate the physical address of the space allocated to the memory device 1000 from the physical address space into a memory address.

[0075] The space allocated to memory device 1000 from the physical address space can be a memory address space, can correspond to a memory address space, or can be mapped onto a memory address space. The memory address space can correspond to a range of memory addresses. The memory address space may include the space allocated to the program buffer 1002 of the global processor GP, the space allocated to the control registers of the processor controllers 1001a / 1001b of the global processor GP, and the space allocated to memory cells. The space allocated to memory device 1000 from the physical address space may include the space corresponding to the space allocated to the program buffer 1002 of the global processor GP from the memory address space, and the memory controller 2100 can change the value (or information) of the program buffer 1002 of the global processor GP by accessing the space corresponding to the space allocated to the program buffer 1002. The space allocated from the physical address space to the memory device 1000 may include space corresponding to the space allocated from the memory address space to the control registers of the processor controllers 1001a / 1001b of the global processor GP, and the memory controller 2100 can change the value (or information) of the control registers of the processor controllers 1001a / 1001b of the global processor GP by accessing the space corresponding to the space allocated to the control registers of the processor controllers 1001a / 1001b. The space allocated from the physical address space to the memory device 1000 may include space corresponding to the space allocated from the physical address space to memory cells, and the memory controller 2100 can access memory cells by accessing the space corresponding to the space allocated to the memory cells.

[0076] Each memory cell of each memory bank BK0 to BK15 of each PIM die 1100 to 1800 of the memory device 1000, the program buffer 1002 of the global processor GPa / GPb of each PIM die 1100 to 1800 of the memory device 1000, and the control registers of the processor controllers 1001a / 1001b can all be mapped to the memory address associated with each PIM die 1100 to 1800 of the memory device 1000. For example, the memory controller 2100 can access the memory cells, the program buffer 1002, and the control registers of the processor controllers 1001a / 1001b by generating or issuing various commands for the memory device 1000 as defined in the JEDEC (Joint Electron Device Engineering Committee) standard. For example, commands for the memory device 1000 may include activation commands, precharge commands, read commands, write commands, etc., associated with memory cells. Because the memory cells, program buffer 1002, and control registers of processor controllers 1001a / 1001b are all mapped to memory addresses, memory controller 2100 can access program buffer 1002 of global processor GPa / GPb and control registers of processor controllers 1001a / 1001b using the commands associated with the memory cells described above. In another example, the various commands for memory device 1000 may further include dedicated commands for accessing program buffer 1002 of global processor GPa / GPb and control registers of processor controllers 1001a / 1001b, as well as the commands associated with the memory cells described above.

[0077] Figure 11 It shows Figure 1 and Figure 2 An example of an electronic device performing multiple processes simultaneously. The System-on-Chip 2000 can access the PIM dies 1100 and 1500 of the memory device 1000 (reference) via channel CH1. Figure 3 and Figure 4 ).

[0078] For example, the processor 2200 of the system-on-chip 2000 (hereinafter referred to as the "system processor") can perform system processing by using the memory controller 2100, wherein the memory controller 2100 accesses the memory banks BK0 to BK15 of the PIM die (reference) through channel CH1. Figure 3 In another example, system processor 2200 can perform system processing using memory controller 2100, wherein memory controller 2100 accesses memory banks BK0 to BK15 of memory dies excluding the global processor GP via channel CH1 (see reference). Figure 4 ).

[0079] For example, while system processing can be image processing based on neural networks (e.g., convolutional neural networks (CNN)), it can also be, but is not limited to, deep neural networks (DNN), recurrent neural networks (RNN), and stuttering neural networks (SNN). Under the control of memory controller 2100, PIM / memory die 1500 can write data sent from memory controller 2100 to memory banks BK0 to BK15, or can send data from memory banks BK0 to BK15 to memory controller 2100. PIM / memory die 1500 can perform data input / output with memory controller 2100. In response to a memory request from system processor 2200, memory controller 2100 can access memory banks BK0 to BK15, local processors LP0 to LP15, or global processor GP of PIM / memory die 1500. The global processor GP of PIM die 1500 can perform global calculations based on a request from memory controller 2100. However, because the memory controller 2100 can access memory banks BK0 to BK15 or local processors LP0 to LP15, the global processor GP of the PIM die 1500 can control memory banks BK0 to BK15 or local processors LP0 to LP15 only in response to requests from the memory controller 2100, and may not control memory banks BK0 to BK15 or local processors LP0 to LP15 automatically.

[0080] System processor 2200 can simultaneously execute multiple processes using multiple PIM dies 1100 and 1500 sharing a single channel CH1 in memory device 1000. One of the multiple processes can be the system process described above. Memory controller 2100 can send a program for one of the multiple processes to the program buffer 1002 of the global processor GP in PIM die 1100 based on a memory request from system processor 2200. Memory controller 2100 can send data input / output signals DQ, including the program, to PIM die 1100 via channel CH1, and the data input / output circuit DATAIO of PIM die 1100 can send the program to program buffer 1002 via data buses DB0 and DB1. The global processor GP of PIM die 1100 can decode the program instructions and can control memory banks BK0 to BK15 and local processors LP0 to LP15 based on the decoding result. The global processor (GP) can perform on-die processing by requesting data input / output from memory banks BK0 to BK15 or by performing local computations or global computations from local processors LP0 to LP15. That is, the system processor 2200 can perform system processing by using the memory controller 2100, which performs data input / output with the PIM / memory die 1500, and can request on-die processing from the global processor (GP) of the PIM die 1100 by using the memory controller 2100. Depending on the memory request from the system processor 2200, the memory controller 2100 can control the PIM die 1100 such that the PIM dies 1100 in the shared channel CH1 and 1500 perform on-die processing, and can control the PIM die 1500 such that the remaining PIM dies 1100 and 1500 in the shared channel CH1 are used for system processing that can be executed by the system processor 2200. For example, on-chip processing can be, but is not limited to, speech recognition processing based on neural networks (e.g., LSTM (Long Short-Term Memory) networks).

[0081] Reference Figure 11During the intervals from T1 to T2 and from T3 to T4, the system processor 2200 can perform system processing by using the memory controller 2100, which accesses the PIM / memory die 1500 via channel CH1. Furthermore, the system processor 2200 can request on-die processing of the PIM die 1100 by using the memory controller 2100, and the global processor GP of the PIM die 1100 can perform on-die processing. During the interval from T2 to T3, the system processor 2200 can receive on-die processing results from the PIM die 1100 by using the memory controller 2100. The system processor 2200 can perform calculations on the system processing results and the on-die processing results to generate new data. Alternatively, the system processor 2200 can receive data from the PIM / memory die 1500 and the PIM die 1100, and can generate new data by performing calculations on the received data. The system processor 2200 can store new data and can send the new data to the PIM / memory die 1500 and PIM die 1100 by using the memory controller 2100.

[0082] As described above, PIM / memory die 1500 and PIM die 1100 can share channel CH1. Furthermore, command and address signals CA and data input / output signals DQ associated with dies 1100 and 1500 can be transmitted via path_1 of channel CH1. Path_1 of channel CH1 may include through-silicon vias (TSVs) and microbumps (BPs) that pass through PIM / memory die 1500, PIM die 1100, and buffer die 1900. System processor 2200 can perform system processing by using memory controller 2100, which accesses PIM / memory die 1500 via channel CH1; PIM / memory die 1500 can receive commands from memory controller 2100 and perform data input / output with memory controller 2100; and the path Path_1 of channel CH1 can be used for transmitting commands from memory controller 2100 and for data input / output between PIM / memory die 1500 and memory controller 2100, while the global processor GP of PIM die 1100 performs on-die processing. Path_1 of channel CH1 may not be used for on-die processing of the global processor GP.

[0083] In an embodiment, where the memory device 1000 includes PIM dies 1100 to 1800 that are implemented identically, the system processor 2200 can perform system processing by using a memory controller 2100 that accesses the PIM die 1100 via channel CH1, and can request on-die processing of the PIM die 1500 by using the memory controller 2100. That is, the location of the PIM die performing system processing and on-die processing is not limited to the examples described above.

[0084] Figure 12 It shows Figure 1 and Figure 2 An example of an on-chip system performing system processing and requesting on-chip processing from a global processor in the memory die. For example, Figure 12 The timing diagram can be a portion of the interval from T1 to T2 and the interval from T3 to T4. Depending on the memory request of the system processor 2200, the memory controller 2100 can send multiple read commands RD1 to RD7 to the memory device 1000 via channel CH1. Read commands RD1, RD3, RD5, and RD7 can be associated with the PIM die 1100 having the stack identifier SID0, and read commands RD2, RD4, and RD6 can be associated with the PIM / memory chip 1500 having the stack identifier SID1. The interval between read commands RD1 to RD7 can be, but is not limited to, the column address flicker (CAS) to CAS delay tCCD defined in the standards of the memory device 1000 (e.g., the JEDEC (Joint Electron Device Engineering Committee) standard). The number of read commands RD1 to RD7 is not limited to... Figure 12 The example shown.

[0085] The PIM die 1100's command and address decoder CADEC can examine the stack identifier SID0 and can efficiently decode only read commands RD1, RD3, RD5, and RD7 out of RD1 through RD7. The PIM die 1100's global processor GP can perform global calculations based on the decoding results of read commands RD1, RD3, RD5, and RD7.

[0086] The PIM die 1500's command and address decoder CADEC can examine the stack identifier SID1 and can effectively decode only read commands RD2, RD4, and RD6 out of read commands RD1 through RD7. The PIM die 1500's command and address decoder CADEC can control any other components (e.g., at least a portion of BG0, BG1, BG2, BG3, DB0, DB1, BCTRL0, BCTRL1, and DATAIO) based on the decoding results. The data input / output circuit DATAIO can receive read data requested by read commands RD2, RD4, and RD6 via data buses DB0 and DB1, and can output data input / output signals DQ, including the read data, to channels CH1 (DOUT2, DOUT4, and DOUT6). That is, the PIM die 1500 can perform read operations in response to read commands RD2, RD4, and RD6, and can output data input / output signals DQ to channel CH1. For example, the interval between the time when PIM die 1500 receives the read command RD2 and the time when PIM die 1500 outputs the data input / output signal DQ to channel CH1 can be the read delay RL.

[0087] exist Figure 12 The following example is illustrated: Memory controller 2100 can generate multiple read commands RD1 to RD7 based on a memory request from system processor 2200. In another example, memory controller 2100 may not generate read commands, but instead generate any other command associated with a memory cell (e.g., an activation command, write command, or precharge command). The command and address decoder CADEC of PIM die 1100 can decode this other command, and the global processor GP of PIM die 1100 can perform on-die processing based on the decoding result of this other command. The command and address decoder CADEC of PIM die 1500 can decode said other command. PIM die 1500 can perform any other operation in response to said other command.

[0088] Figure 13 It shows Figure 1 and Figure 2 This is another example of on-chip processing where the system-on-chip performs system processing and requests memory from the global processor on the memory die. The main description will focus on... Figure 13 The timing diagram and Figure 12The differences between the timing diagrams. Depending on the memory request of the system processor 2200, the memory controller 2100 can send execution commands to request the start and end of execution of on-chip processing of the global processor GP on the PIM die 1100. The commands for requesting the start and end of execution of on-chip processing can have a stack identifier SID0. For example, each command for requesting the start and end of execution of on-chip processing can be an activation command, read command, write command, precharge command, etc., associated with the aforementioned memory cell. For another example, each command for requesting the start and end of execution of on-chip processing can not be a command associated with a memory cell, but a dedicated command for accessing the program buffer 1002 of the global processor GP / GPb and the control registers of the processor controllers 1001a / 1001b. Depending on the memory request of the system processor 2200, the memory controller 2100 can send consecutive read commands RD1 to RD7 to the memory device 1000 via channel CH1. Each of the multiple read commands RD1 to RD7 can have a stack identifier SID1.

[0089] The command and address decoder CADEC of PIM die 1100 can examine the stack identifier SID1 and can efficiently decode commands used to request the start and end of execution for processing on the die. The global processor GP of PIM die 1100 can start and end global computation based on the decoded results of the commands used to request the start and end of execution for processing on the die. PIM die 1500 can perform read operations in response to read commands RD1 through RD7 and can output data input / output signals DQ to channels CH1 (DOUT1 through DOUT7).

[0090] Figure 12 An example is shown below: The memory controller 2100 alternately issues an execution start command for requesting on-chip processing of the global processor GP of the PIM die 1100, and a read command for requesting data from the PIM die 1500 at intervals tCCD. A data input / output signal DQ including read data is not output from the memory device 1000 via the execution start command for requesting on-chip processing of the global processor GP of the PIM die 1100; instead, a data input / output signal DQ including data is output via the read command for requesting the PIM die 1500. Thus, the memory controller 2100 receives the data input / output signal DQ including read data from the memory device 1000 in a non-seamless manner. In contrast, in Figure 13An example is shown below: Memory controller 2100 sends a command to memory device 1000 to initiate execution of on-die processing of the global processor GP for requesting PIM die 1100, and then sends consecutive read commands RD1 to RD7 to request data from PIM die 1500 at tCCD intervals. Therefore, memory controller 2100 can seamlessly receive data input / output signals DQ, including read data, from memory device 1000. Figure 12 In the present, the memory controller 2100 may not be able to fully utilize the bandwidth of channel CH1 (i.e., utilize half of the maximum bandwidth of channel CH1); however, in Figure 13 In this context, the memory controller 2100 can fully utilize the bandwidth of channel CH1.

[0091] Figure 14 It shows Figure 1 and Figure 2 This is another example of on-chip processing where the system-on-chip performs system processing and requests memory from the global processor on the memory die. The main description will focus on... Figure 14 The timing diagram and Figure 13 The differences between the timing diagrams. Figure 13 In the process, the memory controller 2100 sends a command to the memory device 1000 to initiate execution of on-die processing of the global processor GP of the PIM die 1100, and then sends continuous read commands RD1 to RD7 to request data from the PIM die 1500 at intervals of tCCD. The PIM die 1100 includes... Figure 8 In the case of the interrupt input / output circuit 1010 and the global processor GPb, the memory controller 2100 can generate an interrupt signal to request the start of execution of on-chip processing by the global processor GPb on the PIM die 1100. The global processor GPb can execute on-chip processing in response to the interrupt signal requesting the start of execution of on-chip processing. When on-chip processing is completed (or terminated), the global processor GPb can generate an interrupt signal indicating the end of execution of on-chip processing. The aforementioned interrupt signal can be transmitted between the memory controller 2100 and the memory device 1000.

[0092] Figure 15 An electronic device according to another embodiment is illustrated. The electronic device 100c may include memory devices 1000_1 to 1000_4 (1000_1, 1000_2, 1000_3, 1000_4), a system-on-a-chip 2000, an inserter 3000, and a package board 4000. Each of the memory devices 1000_1 to 1000_4 may correspond to the aforementioned memory device 1000, and the number of memory devices 1000_1 to 1000_4 is not limited to this. Figure 15The example shown illustrates this. The inserter 3000 may include paths to multiple channels that allow the system-on-chip 2000 to access memory devices 1000_1 to 1000_4. The inserter 3000 may be stacked on the package board 4000. However, embodiments are not limited thereto. For example, memory devices 1000_1 to 1000_4 and the system-on-chip 2000 may be mounted on the package board 4000 without the inserter 3000.

[0093] The memory die of the memory device according to the embodiment may include both a local processor and a global processor. Therefore, the memory controller can fully utilize the bandwidth of the channels associated with the memory device.

[0094] Although this disclosure has been described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of this disclosure as set forth in the appended claims.

Claims

1. A memory die, comprising: The first storage bank includes a first memory cell; The second storage bank includes a second memory cell; A first local processor is connected to a first memory local input / output line, and transmits first local memory data of the first memory through the first memory local input / output line. The first local processor is configured to perform a first local calculation on the first local memory data. A second local processor is connected to a second memory local input / output line, and transmits second local memory data of the second memory through the second memory local input / output line. The second local processor is configured to perform second local calculations on the second local memory data; and The global processor is configured as follows: Control the first memory, the second memory, the first local processor, and the second local processor, and Perform a global calculation on the first local calculation result of the first local calculation and the second local calculation result of the second local calculation. The first memory unit, the second memory unit, the control register of the global processor, and the program buffer of the global processor's memory host are respectively mapped to memory addresses associated with the memory die.

2. The memory die according to claim 1, wherein, The first local processor includes: The input multiplexer is configured as follows: Data from the first local memory is received via the local input / output lines of the first memory. Broadcast data broadcast by the global processor is received via the memory's global input / output lines, and Receive local register data; A Local Processing Element (LPE) array is configured to perform the first local computation on at least one of the first local memory data, the broadcast data, and the local register data. A local register is configured to store the result of the first local computation and output the result of the first local computation as data in the local register; and An output multiplexer is configured to output the local register data to at least one of the first memory local input / output lines, the memory global input / output lines, and the input multiplexer.

3. The memory die according to claim 2, further comprising: A memory global input / output gating circuit is configured to electrically connect the first memory local input / output line to the memory global input / output line under the control of the global processor.

4. The memory die according to claim 3, further comprising: An input / output sense amplifier is configured to receive first local memory data output from the first memory bank and output the first local memory data to the first memory bank local input / output line; A write driver is configured to write data from the first local memory bank to the first memory cell; as well as A memory local input / output gating circuit is configured to electrically connect the write driver to the first memory local input / output line.

5. The memory die according to claim 1, wherein, The global processor includes: A program buffer is configured to store programs on the host computer. An instruction queue is configured to store the instructions of the program; An instruction decoder is configured to decode instructions stored in the instruction queue; A first controller is configured to control the first memory and the second memory, as well as the first local processor and the second local processor, based on the result of decoding the instruction at the instruction decoder. A global processing element (GPE) array is configured to perform the global computation based on the result of decoding the instruction at the instruction decoder. A global register is configured to store the global computation results of the global computation; A data buffer is configured to: receive the first local calculation result and the second local calculation result via a data bus, provide the first local calculation result and the second local calculation result to the GPE array, and output the global calculation result to the data bus; and The second controller is configured to control the program buffer, the instruction queue, the instruction decoder, the first controller, the GPE array, the global register, and the data buffer.

6. The memory die according to claim 5, wherein, The global processor is also configured to: On-die processing is performed by: requesting data input / output to the first and second memory banks, or by performing the first and second local computations, or by performing the global computation in response to a start interrupt signal sent from the host; and When the processing on the die is fully executed, an end interrupt signal is sent to the host.

7. The memory die according to claim 5, wherein, The first controller is configured as follows: The bits used to identify the memory addresses of the first and second memory banks are treated as irrelevant bits, and the first and second memory banks are controlled simultaneously.

8. A memory device, comprising: A first memory die includes a first memory bank accessible via a channel, wherein the first memory die is configured as follows: Commands for the first storage are received from the host through the channel, and Based on the command, data input / output is performed with the host through the channel; and The second memory die includes: A second storage unit that can be accessed via a channel. Local processors are configured to perform local computations on the data in the second memory bank, and The global processor is configured as follows: Control the second memory and the local processor, and Perform a global calculation on the local calculation results. The first memory bank, the second memory bank, the control register of the global processor, and the program buffer of the global processor that stores the program of the host are respectively mapped to memory addresses associated with the memory device.

9. The memory device according to claim 8, wherein, The global processor is also configured to: On-die processing is performed in the following manner: Requesting data input / output of the second storage unit, or the local computation, or The global computation is performed in response to a start interrupt signal sent from the host; and When the processing on the die is fully executed, an end interrupt signal is sent to the host.

10. The memory device of claim 9, further comprising: Buffer die, The first memory die and the second memory die are stacked on the buffer die, and The path of the channel includes multiple through-silicon vias (TSVs) passing through the buffer die, the first memory die, and the second memory die, respectively.

11. The memory device according to claim 10, wherein, When the first memory die receives the command and executes the data input / output, and the global processor of the second memory die executes the on-die processing, the path of the channel is used to transmit commands for the first memory bank and for data input / output with the host.

12. The memory device according to claim 8, wherein, The first memory die is implemented to be the same as the second memory die. The first memory die further includes: A first local processor is configured to perform a first local computation on the data in the first memory bank, and The first global processor is configured as follows: Control the first memory and the first local processor, and Perform a first global calculation on the local calculation results of the first local calculation, and Wherein, the local computation is a second local computation, the local processor is a second local processor, and the global computation is a second global computation.

13. The memory device according to claim 12, wherein, The first global processor is also configured to: On-die processing is performed in the following manner: Requesting data input / output from the first storage unit, or the local computation, or The local computation is performed in response to a start interrupt signal sent from the host; and When the processing on the die is fully executed, an end interrupt signal is sent to the host.

14. The memory device according to claim 8, wherein, The first memory die is implemented differently from the second memory die.

15. An electronic device comprising: The memory device includes a first memory die and a second memory die. Wherein, the first memory die includes a first memory cell, and The second memory die includes: Second storage; Local processors are configured to perform local calculations on the data in the second memory bank, respectively; and The global processor is configured as follows: Control the second memory and the local processor, and Perform global computation on the results of the local computation; and The system-on-a-chip includes a memory controller configured to access one of the first memory die and the second memory die via a channel. The first memory bank, the second memory bank, the control register of the global processor, and the program buffer of the program of the global processor's memory host are respectively mapped to memory addresses associated with the memory device.

16. The electronic device according to claim 15, wherein, The on-chip system also includes: The system processor is configured to perform system processing by using the memory controller, which accesses the first memory bank of the first memory die through the channel. The global processor of the second memory die is configured to perform on-die processing in the following manner: Requesting data input / output of the second storage unit, or the local computation, or The global computation is performed when the system processor executes the system processing.

17. The electronic device according to claim 16, wherein, The memory device includes: A buffer die, wherein the first memory die and the second memory die are stacked on the buffer die; and The path of the first channel is located between the buffer die and the first memory die and the second memory die, and The path of the first channel is configured to be used for the system processing when the system processor performs the system processing and the global processor of the second memory die performs the on-die processing.

18. The electronic device according to claim 16, wherein, The system processing is image processing, and the on-chip processing is speech recognition processing.

19. A memory die, comprising: A multi-die data bus is configured to provide communication with a host, wherein the host is external to the memory die; A global processor, directly coupled to the multi-die data bus, is configured as follows: To execute video processing tasks according to the commands of the host, and The computationally intensive parts of the video processing task are delegated to local processors; The first local bus gating circuit is coupled to the multi-die data bus and the local bus; The second local bus gating circuit is coupled to the local bus and the memory storage; The memory storage unit; The local processor is coupled in the following manner: Coupled to the multi-die data bus via the first local bus gating circuit, and It is coupled to the memory bank via the second local bus gating circuit. The multi-chip data bus, the global processor, the local bus, the first local bus gating circuit, the second local bus gating circuit, and the local processor are configured to: effectively utilize limited bus bandwidth for high-speed data processing, wherein the high-speed data processing includes the video processing task.

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