Semiconductor structure and method for forming semiconductor structure

Abstract

A semiconductor structure and a method for forming the same, comprising: providing a substrate; forming a drift region and a body region within the substrate, the drift region and the body region being adjacent, the drift region having first ions and the body region having second ions, the first and second ions having opposite conductivity types; forming a gate structure on the substrate, the gate structure being located on the surfaces of the drift region and the body region, and the gate structure extending from the surface of the drift region to the surface of the body region; forming a shielding doping layer on the surface of the drift region, the shielding doping layer being adjacent to the gate structure; and forming a drain region within the drift region, the drain region being adjacent to the shielding doping layer, the drain region and the drift region having the same first ion conductivity type. The semiconductor structure formed by this method has improved performance.

Description

Technical Field

[0001] The present invention relates to a semiconductor manufacturing process, and in particular to a semiconductor structure and a method for forming the semiconductor structure. Background Art

[0002] Lateral double-diffused metal oxide semiconductor (LDMOS) is a high-voltage power device characterized by high operating voltage, relatively simple manufacturing process, and high switching frequency. Furthermore, the mature processing technology based on bulk silicon materials makes LDMOS devices promising broad development prospects. The drain, source, and gate electrodes of LDMOS devices are all located on the surface, making them easy to integrate into chips. Therefore, they are particularly suitable for use as high-voltage power devices in high-voltage integrated circuits and power integrated circuits.

[0003] In order to increase the breakdown voltage of a lateral double diffused metal oxide semiconductor (LDMOS), a drift region is usually added between the source and drain regions. The lower the impurity concentration of the drift region, the longer the length, and the deeper the junction depth, the higher the withstand voltage of the lateral double diffused metal oxide semiconductor. However, the device's withstand voltage and on-resistance have conflicting requirements for the concentration, junction depth, and length of the drift region. The lower the impurity concentration of the drift region, the longer the length, and the deeper the junction depth, the greater the chip area and on-resistance.

[0004] Therefore, the performance of existing LDMOS needs to be improved. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the semiconductor structure, so as to improve the performance of a lateral double diffused metal oxide semiconductor.

[0006] To solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a drift region and a body region in the substrate, the drift region and the body region being adjacent, the drift region having a first ion, the body region having a second ion, and the first ion and the second ion having opposite conductivity types; forming a gate structure on the substrate, the gate structure being located on the surfaces of the drift region and the body region, and the gate structure extending from the surface of the drift region to the surface of the body region; forming a shielding doping layer on the surface of the drift region, the shielding doping layer being adjacent to the gate structure; forming a drain region in the drift region, the drain region being adjacent to the shielding doping layer, and the drain region having the same first ion conductivity type as the drift region.

[0007] Optionally, the method for forming the shielding doping layer on the surface of the drift region includes: forming a mask layer on the substrate and the surface of the gate structure, the mask layer exposing a portion of the drift region surface adjacent to the gate structure; performing ion implantation on the exposed drift region surface to form the shielding doping layer on the surface of the drift region, the top plane of the shielding doping layer being lower than or flush with the top plane of the drift region.

[0008] Optionally, the implanted ions in the ion implantation process are third ions; the third ions include fluorine ions, carbon ions or nitrogen ions; the concentration range of the fluorine ions and nitrogen ions is 4e14 atoms per cubic centimeter to 5e15 atoms per cubic centimeter, and the concentration range of the carbon ions is 1e14 atoms per cubic centimeter to 1e15 atoms per cubic centimeter.

[0009] Optionally, the thickness of the shielding doping layer ranges from 0 nanometers to 10 nanometers.

[0010] Optionally, the method for forming a shielding doping layer on the surface of the drift region includes: forming a shielding material layer on the substrate and the surface of the gate structure; performing ion implantation on the shielding material layer to form a shielding doping material layer; forming a patterned mask layer on the surface of the shielding doping material layer, wherein the patterned mask layer blocks a portion of the shielding doping material layer on the surface of the drift region adjacent to the gate structure; etching the shielding doping material layer using the patterned mask layer as a mask until the surface of the substrate is exposed, thereby forming a shielding doping layer on the surface of the drift region, wherein the top plane of the shielding doping layer is higher than the top plane of the drift region.

[0011] Optionally, the implanted ions for ion implantation into the shielding material layer are third ions; the third ions include fluorine ions, carbon ions or nitrogen ions; the dosage range of the fluorine ions and nitrogen ions is 4e14 atoms per square centimeter to 5e15 atoms per square centimeter, and the dosage range of the carbon ions is 1e14 atoms per square centimeter to 1e15 atoms per square centimeter.

[0012] Optionally, the shielding material layer is made of silicon oxide or silicon oxynitride.

[0013] Optionally, the thickness of the shielding doping layer ranges from 1 nanometer to 5 nanometers.

[0014] Optionally, it further includes: forming a source region in the body region, the source region is adjacent to the gate structure, and the source region has the same conductivity type as the first ion; and the source region and the drain region are formed simultaneously.

[0015] Optionally, the method for forming the source region and the drain region includes: forming a blocking material layer on the substrate, the surface of the shielding doping layer, and the top surface and side wall surface of the gate structure; forming a patterned layer on the blocking material layer, the patterned layer blocking a portion of the top surface of the blocking material layer on the surface of the shielding doping layer; etching the blocking material layer using the patterned layer as a mask until the substrate surface is exposed, forming a blocking layer on the surface of the shielding doping layer and a portion of the side wall surface and top surface of the gate structure; performing ion implantation on the exposed surfaces of the drift region and body region using the blocking layer and the gate structure as masks to form a drain region in the drift region and a source region in the body region.

[0016] Optionally, the implanted ions in the ion implantation process are fourth ions, the concentration of the fourth ions is greater than the concentration of the first ions, and the concentration of the fourth ions is greater than the concentration of the second ions.

[0017] Optionally, the method further includes: forming metal silicide on the surface of the source region, the surface of the drain region and the top surface of the gate structure; the material of the metal silicide includes cobalt silicon, nickel silicon or titanium silicon.

[0018] Optionally, the first ions include N-type ions, which include phosphorus ions or arsenic ions; the second ions include P-type ions, which include boron ions, boron fluoride ions or indium ions.

[0019] Correspondingly, the technical solution of the present invention also provides a semiconductor structure, including: a substrate; a drift region and a body region located in the substrate, the drift region and the body region are adjacent, the drift region has a first ion, the body region has a second ion, and the conductivity types of the first ion and the second ion are opposite; a gate structure located on the substrate, the gate structure is located on the surface of the drift region and the body region, and the gate structure extends from the surface of the drift region to the surface of the body region; a shielding doping layer located on the surface of the drift region, the shielding doping layer is adjacent to the gate structure; a drain region located in the drift region, the drain region is adjacent to the shielding doping layer, and the drain region has the same first ion conductivity type as the drift region.

[0020] Optionally, the shielding doping layer contains third ions, and the third ions include fluorine ions, carbon ions or nitrogen ions.

[0021] Optionally, a top plane of the shielding doping layer is lower than or flush with a top plane of the drift region.

[0022] Optionally, the thickness of the shielding doping layer ranges from 0 nanometers to 10 nanometers.

[0023] Optionally, a top plane of the shielding doping layer is higher than a top plane of the drift region.

[0024] Optionally, the thickness of the shielding doping layer ranges from 1 nanometer to 5 nanometers.

[0025] Optionally, the material of the shielding doping layer includes silicon oxide or silicon oxynitride.

[0026] Optionally, it further includes: a source region located in the body region, the source region is adjacent to the gate structure, and the source region has the same conductivity type as the first ion.

[0027] Optionally, there are fourth ions in the drain region and the source region, and the concentration of the fourth ions is greater than the concentration of the first ions, and the concentration of the fourth ions is greater than the concentration of the second ions.

[0028] Optionally, the method further includes: a barrier layer located on the surface of the shielding doping layer and a portion of the sidewall surface and the top surface of the gate structure.

[0029] Optionally, it further includes: a metal silicide located on the surface of the source region, the surface of the drain region and the top surface of the gate structure; the material of the metal silicide includes cobalt silicon, nickel silicon or titanium silicon.

[0030] Optionally, the first ions include N-type ions, and the N-type ions include phosphorus ions or arsenic ions. Optionally, the second ions include P-type ions, and the P-type ions include boron ions, boron fluoride ions, or indium ions.

[0031] Optionally, the gate structure includes a gate dielectric layer, a gate layer located on the gate dielectric layer, and sidewalls located on sidewalls of the gate dielectric layer and the gate layer.

[0032] Optionally, the thickness of the sidewall spacer ranges from 20 nanometers to 80 nanometers.

[0033] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0034] The formation method in the technical solution of the present invention forms a shielding doping layer on the surface of the drift region between the drain region and the gate structure. On the one hand, the shielding doping layer can eliminate the induced electric field formed on the surface of the drift region, avoiding the electrostatic influence of the induced electric field on the gate structure; it also avoids the induced charge from accumulating on the surface of the drift region, making the resistance of the drift region smaller, thereby reducing the breakdown voltage of the semiconductor structure; on the other hand, the shielding doping layer can block the doping ions in the drain region from diffusing into the channel, thereby avoiding the situation where the resistance of the channel becomes smaller after the doping ions in the drain region diffuse into the channel, making the semiconductor structure easy to break down. In summary, the performance of the semiconductor structure is improved.

[0035] Furthermore, the third ions include fluorine ions, carbon ions or nitrogen ions, and the fluorine ions, carbon ions or nitrogen ions can react with the dangling bonds on the surface of the substrate to form stable chemical bonds, thereby making it difficult to generate induced charges and form an induced electric field, making it difficult for the carriers to be attracted and gathered at the bottom of the isolation structure, thereby reducing the resistance of the drift region and reducing the breakdown voltage of the semiconductor structure.

[0036] Improved performance of semiconductor structures.

[0037] In the semiconductor structure of the technical solution of the present invention, the surface of the drift region has a shielding doping layer, and the shielding doping layer is adjacent to the gate structure. On the one hand, the shielding doping layer can eliminate the induced electric field formed on the surface of the drift region, avoiding the electrostatic influence of the induced electric field on the gate structure; it also avoids the induced charge from accumulating on the surface of the drift region, which reduces the resistance of the drift region and thus reduces the breakdown voltage of the semiconductor structure; on the other hand, the shielding doping layer can block the doping ions in the drain region from diffusing into the channel, thereby avoiding the situation where the resistance of the channel becomes smaller after the doping ions in the drain region diffuse into the channel, making the semiconductor structure easy to break down. In summary, the performance of the semiconductor structure is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 is a schematic diagram of a cross-sectional structure of a laterally double diffused metal oxide semiconductor in one embodiment;

[0039] Figures 2 to 9 is a schematic cross-sectional view of a semiconductor structure forming process according to an embodiment of the present invention;

[0040] Figures 10 to 12 It is a cross-sectional structural diagram of a semiconductor structure forming process in another embodiment of the present invention. DETAILED DESCRIPTION

[0041] As described in the background art, the performance of existing lateral double diffused metal oxide semiconductors needs to be improved. This will now be analyzed and explained in conjunction with specific embodiments.

[0042] Figure 1 FIG. 1 is a schematic diagram of a cross-sectional structure of a laterally double diffused metal oxide semiconductor in one embodiment.

[0043] Please refer to Figure 1, comprising: a substrate 100, the substrate 100 including a drift region 102 and a body region 101, the drift region 102 and the body region 101 being adjacent to each other; a gate structure 107 located on the drift region 102 and the body region 101, the top surface of the gate structure 107 having a gate silicide 109; a drain region 103 located in the drift region 102, the surface of the drain region 103 having a drain silicide 105; a source region 104 located in the body region 101, the surface of the source region 104 having a source silicide 106, the source region 104 being adjacent to the gate structure 107; a barrier layer 108 located on a portion of the surface of the drift region 102, a portion of the sidewall surface and a portion of the top surface of the gate structure 107, the drain region 103 being adjacent to the barrier layer 108.

[0044] After power is applied to the LDMOS, because the substrate 100 is made of silicon and the silicon surface has dangling bonds, the oxide of the barrier layer 108 in contact with the substrate generates static charges that accumulate on the substrate surface at the bottom of the barrier layer 108, thereby generating an induced electric field. This induced electric field attracts carriers to converge on the substrate surface at the bottom of the barrier layer 108, resulting in a larger tunneling current at the edge of the gate structure, thereby reducing the resistance of the drift region. This reduces the breakdown voltage of the semiconductor structure, making the LDMOS easily broken down, thereby causing the LDMOS to fail in performance.

[0045] In order to solve the above problems, the technical solution of the present invention provides a semiconductor structure and a method for forming a semiconductor structure. By forming a shielding doping layer on the surface of the drift region between the drain region and the gate structure, the shielding doping layer can eliminate the induced electric field formed on the surface of the drift region between the drain region and the gate structure, thereby avoiding the electrostatic influence of the induced electric field on the gate structure; it also avoids the induced charge from accumulating at the bottom of the isolation structure, thereby reducing the resistance of the drift region and thus reducing the breakdown voltage of the semiconductor structure, thereby improving the performance of the semiconductor structure.

[0046] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0047] Figures 2 to 9 It is a schematic cross-sectional structural diagram of the semiconductor structure forming process in an embodiment of the present invention.

[0048] Please refer to Figure 2 , providing a substrate 200.

[0049] In this embodiment, the material of the substrate 200 is single crystal silicon; in other embodiments, the substrate may also be made of semiconductor materials such as polycrystalline silicon, germanium, silicon germanium, gallium arsenide, or silicon on insulator.

[0050] In this embodiment, the substrate 200 has second ions in it, and the second ions are P-type ions. The P-type ions include boron ions, boron fluoride ions, or indium ions.

[0051] Please refer to Figure 3 , a drift region 202 is formed in the substrate 200 , and the drift region 202 has first ions.

[0052] The method for forming the drift region 202 includes: forming a first photoresist layer on the substrate 200, wherein the first photoresist layer exposes a portion of the surface of the substrate 200; using the first photoresist layer as a mask, performing first ion implantation on the exposed surface of the substrate 200 to form the drift region 202; after forming the drift region 202, removing the first photoresist layer.

[0053] In this embodiment, the first ions include N-type ions, and the N-type ions include phosphorus ions or arsenic ions.

[0054] Please continue to refer to Figure 3 After the drift region 202 is formed, a body region 201 is formed in the substrate 200 . The body region 201 is adjacent to the drift region 202 . The body region 201 has second ions. The first ions and the second ions have opposite conductivity types.

[0055] The method for forming the body region 201 includes: forming a second photoresist layer on the substrate 200, wherein the first photoresist layer covers the surface of the drift region 202, and the second photoresist layer exposes a portion of the surface of the substrate 200; using the second photoresist layer as a mask, performing second ion implantation on the exposed surface of the substrate 200 to form the body region 201; after the body region 201 is formed, removing the second photoresist layer.

[0056] In this embodiment, the second ions include P-type ions, and the P-type ions include boron ions, boron fluoride ions or indium ions.

[0057] Please refer to Figure 4 , a gate structure is formed on the substrate 200 , wherein the gate structure is located on the surfaces of the drift region 202 and the body region 201 , and the gate structure extends from the surface of the drift region 202 to the surface of the body region 201 .

[0058] The gate structure includes a gate dielectric layer (not shown), a gate layer 203 located on the gate dielectric layer, and sidewall spacers 204 located on sidewalls of the gate dielectric layer and the gate layer 203 .

[0059] The method for forming the gate structure includes: forming a gate dielectric material layer (not shown) on the substrate; forming a gate material layer (not shown) on the gate dielectric material layer; forming a patterned mask layer (not shown) on the gate material layer; etching the gate material layer and the gate dielectric material layer using the patterned mask layer as a mask until the surface of the substrate 200 is exposed, forming a gate dielectric layer (not shown) and a gate layer 203 located on the gate dielectric layer; forming a sidewall material layer (not shown) on the sidewall surface of the gate dielectric layer, the top surface of the gate layer 203 and the sidewall surface; etching back the sidewall material layer until the surface of the substrate 200 is exposed, forming a sidewall 204, and forming the gate structure.

[0060] In this embodiment, the thickness of the sidewall spacer 204 ranges from 20 nanometers to 80 nanometers.

[0061] The sidewall 204 can protect the gate structure. If the thickness of the sidewall 204 is less than 20 nanometers, on the one hand, when ion implantation is performed when a shielding doping layer is subsequently formed on the surface of the drift region 202, the implanted ions will diffuse into the channel region below the gate structure, thereby affecting the operating current of the semiconductor structure; on the other hand, the distance between the subsequently formed drain region and the gate layer is too close, and when a high voltage is applied to the drain region, the semiconductor structure is easily broken down; if the thickness of the sidewall 204 is greater than 80 nanometers, the distance between the subsequently formed source region and the drain region is too far, resulting in an excessively large on-resistance of the semiconductor structure, which slows down the reaction speed of the semiconductor structure.

[0062] The material of the gate dielectric layer includes silicon oxide, silicon nitride or silicon oxynitride; the material of the gate layer 203 includes polysilicon or metal; the material of the sidewall spacer 204 includes silicon oxide or silicon nitride.

[0063] In this embodiment, the material of the gate dielectric layer includes silicon oxide; the material of the gate layer 203 includes polysilicon; and the material of the sidewall spacer 204 includes silicon nitride.

[0064] The process for forming the gate dielectric material layer includes a chemical vapor deposition process or an atomic layer deposition process; the process for forming the gate material layer includes a physical vapor deposition process or an atomic layer deposition process; the process for etching the gate material layer and the gate dielectric material layer includes a dry etching process or a wet etching process; the process for forming the sidewall material layer includes a chemical vapor deposition process or an atomic layer deposition process.

[0065] In this embodiment, the process of forming the gate dielectric material layer includes an atomic layer deposition process, which can form a gate dielectric material layer with a thin thickness and a dense structure; the process of forming the gate material layer includes a physical vapor deposition process, which can form a gate material layer with a thick thickness and a dense structure; the process of etching the gate material layer and the gate dielectric material layer includes a dry etching process, which can form a gate structure with good sidewall morphology; the process of forming the sidewall material layer includes a chemical vapor deposition process.

[0066] After forming the gate structure, a shielding doping layer is formed on the surface of the drift region 202. For the detailed formation process of the shielding doping layer, please refer to Figure 5 and Figure 6 .

[0067] Please refer to Figure 5 A mask layer 205 is formed on the substrate 200 and the surface of the gate structure, and the mask layer 205 exposes a portion of the surface of the drift region 202 adjacent to the gate structure.

[0068] In this embodiment, the mask layer 205 also exposes a portion of the top surface of the gate structure adjacent to the drift region 202, so that when ion implantation is subsequently performed on the surface of the drift region 202, the mask layer 205 is avoided from being blocked, so that the implanted ions can be fully implanted into the surface of the drift region 202 adjacent to the gate structure to form a shielding doping layer adjacent to the gate structure.

[0069] In this embodiment, the material of the mask layer 205 includes photoresist; and the process of forming the mask layer 205 includes a spin coating process or a spray coating process.

[0070] Please refer to Figure 6 , ion implantation is performed on the exposed surface of the drift region 202 to form a shielding doping layer 206 on the surface of the drift region 202 , wherein the top plane of the shielding doping layer 206 is lower than or flush with the top plane of the drift region 202 .

[0071] The implanted ions used for ion implantation into the exposed surface of the drift region 202 are third ions; the third ions include fluorine ions, carbon ions, or nitrogen ions.

[0072] The third ions include fluorine ions, carbon ions, or nitrogen ions. These fluorine ions, carbon ions, or nitrogen ions can react with dangling bonds on the substrate surface to form stable chemical bonds, thereby reducing the generation of induced charges and the formation of an induced electric field. This makes it difficult for carriers to be attracted and accumulated at the bottom of the isolation structure, thereby reducing the resistance of the drift region and the breakdown voltage of the semiconductor structure. This improves the performance of the semiconductor structure.

[0073] In this embodiment, the third ions include fluorine ions, and the dosage of the fluorine ions ranges from 4e14 atoms per square centimeter to 5e15 atoms per square centimeter.

[0074] In other embodiments, the third ions include nitrogen ions, and a dosage of the nitrogen ions ranges from 4e14 atoms per square centimeter to 5e15 atoms per square centimeter.

[0075] In other embodiments, the third ions include carbon ions, and the dosage of the carbon ions is in a range of 1e14 atoms per square centimeter to 1e15 atoms per square centimeter.

[0076] If the concentration of the third ion is too high, it is easy to form a high sub-region of the third ion on the surface of the drift region 202. The high sub-region will affect the working current between the drain region and the gate structure, making the working current of the semiconductor structure smaller; if the concentration of the third ion is too low, the shielding doping layer 206 formed will not play a role in eliminating the induced electric field formed on the surface of the drift region 202.

[0077] The thickness of the shielding doping layer 206 ranges from 0 nanometers to 10 nanometers.

[0078] If the thickness of the shielding doping layer 206 is too large, the working current path of the semiconductor structure will become longer, resulting in an increase in the working resistance of the semiconductor structure and a decrease in the working current, which is not conducive to improving the performance of the semiconductor structure; on the other hand, if the thickness of the shielding doping layer 206 is too large and the depth of the ion implantation is deeper, the shielding doping layer 206 is prone to defects, thereby affecting the performance of the semiconductor structure.

[0079] A shielding doping layer 206 is formed on the surface of the drift region 202. The shielding doping layer 206 can eliminate the induced electric field formed on the surface of the drift region 202, thereby preventing the induced electric field from generating electrostatic effects on the gate structure. It also prevents the induced charges from accumulating on the surface of the drift region 202, thereby reducing the resistance of the drift region 202 and thus reducing the breakdown voltage of the semiconductor structure.

[0080] Next, a drain region is formed in the drift region 202, the drain region is adjacent to the shield doping layer 206, and the drain region has the same conductivity type as the first ion in the drift region; a source region is formed in the body region 201, the source region is adjacent to the gate structure, and the source region has the same conductivity type as the first ion. The formation process of the source and drain regions can be found in Figure 7 and Figure 8 .

[0081] The source region and the drain region are formed simultaneously.

[0082] After forming the shielding doping layer 206 , the mask layer 205 is removed.

[0083] In this embodiment, the process of removing the mask layer 205 includes an ashing process.

[0084] Please refer to Figure 7 A barrier layer 207 is formed on the surface of the shielding doping layer 206 and a portion of the sidewall surface and the top surface of the gate structure.

[0085] The method for forming the blocking layer 207 includes: forming a blocking material layer (not shown) on the substrate 200, on the shielding doping layer 206, and on the top surface and sidewall surface of the gate structure; forming a patterned layer (not shown) on the blocking material layer, wherein the patterned layer blocks a portion of the top surface of the blocking material layer on the surface of the shielding doping layer 206; etching the blocking material layer using the patterned layer as a mask until the surface of the substrate 200 is exposed, thereby forming a blocking layer 207 on the surface of the shielding doping layer 206 and a portion of the sidewall surface and top surface of the gate structure.

[0086] The barrier layer 207 serves as a mask layer when a drain region is subsequently formed within the drift region 202, preventing the drain region from being too close to the gate structure. This reduces the resistance between the drain region and the gate structure, thereby reducing the high voltage applied to the drain region and causing the gate structure to break down. Furthermore, the barrier layer 207 protects the surface of the drift region 202, preventing the metal silicide from being located on the surface of the drift region 202 between the drain region and the gate structure when metal silicide is subsequently formed on the top surfaces of the source region, drain region, and gate structure, thereby preventing the metal silicide from being located on the surface of the drift region 202 between the drain region and the gate structure, thereby causing a short circuit between the drain region and the gate structure.

[0087] In this embodiment, the barrier layer 207 is also located on part of the sidewall surface and the top surface of the gate structure, so that the barrier layer 207 can isolate the metal silicide subsequently formed on the top surface of the gate structure and the surface of the drain region, thereby preventing the metal silicide on the top surface of the gate structure and the surface of the drain region from being too close, resulting in the high voltage subsequently loaded on the drain being too close to the gate, making the semiconductor structure prone to breakdown.

[0088] In other embodiments, the blocking layer 207 may be located only on the surface of the shielding doping layer.

[0089] The material of the barrier layer 207 includes silicon oxide or silicon oxynitride; the process of forming the barrier material layer includes a chemical vapor deposition process or an atomic layer deposition process; and the process of etching the barrier material layer includes a dry etching process or a wet etching process.

[0090] In this embodiment, the material of the barrier layer 207 includes silicon oxide; the process of forming the barrier material layer includes a chemical vapor deposition process; and the process of etching the barrier material layer includes a dry etching process.

[0091] In this embodiment, the thickness of the barrier layer 207 is in the range of 50 nanometers to 300 nanometers.

[0092] If the thickness of the blocking layer 207 is less than 50 nanometers, the thickness of the blocking layer 207 is relatively thin. When ion implantation is subsequently performed using the blocking layer 207 as a mask to form source and drain regions, the ions will pass through the blocking layer 207 and reach the surface of the drift region, thereby failing to serve as a mask. If the thickness of the blocking layer 207 is greater than 300 nanometers, the thickness of the blocking layer 207 is relatively thick, requiring increased conditions for the process of forming the blocking layer 207, thereby causing waste of the process and making it difficult to remove the blocking material layer.

[0093] Please refer to Figure 8 Ion implantation is performed on the exposed surfaces of the drift region 202 and the body region 201 using the barrier layer 207 and the gate structure as masks to form a drain region 208 in the drift region 202 and a source region 209 in the body region 201 .

[0094] The implanted ions for ion implantation into the surfaces of the drift region 202 and the body region 201 are fourth ions, which have the same conductivity type as the first ions of the drift region 202 . The fourth ions include N-type ions, which include phosphorus ions or arsenic ions.

[0095] The concentration of the fourth ions is greater than the concentration of the first ions, and the concentration of the fourth ions is greater than the concentration of the second ions.

[0096] Since a shielding doping layer 206 is formed between the drain region 208 and the gate structure, the shielding doping layer 206 can prevent the doping ions in the drain region 208 from diffusing into the channel, thereby avoiding the situation where the resistance of the channel becomes smaller after the doping ions in the drain region 208 diffuse into the channel, making the semiconductor structure easy to break down, thereby improving the performance of the semiconductor structure.

[0097] Please refer to Figure 9 A metal silicide 210 is formed on the surface of the source region 209, the surface of the drain region 208 and the top surface of the gate structure.

[0098] The metal silicide 210 can reduce the resistance of the source region 209 , the drain region 208 and the gate structure, thereby making the on-resistance of the semiconductor structure smaller and easier to conduct, thereby improving the reaction speed of the semiconductor structure.

[0099] The material of the metal silicide 210 includes cobalt silicon, nickel silicon or titanium silicon.

[0100] The method for forming metal silicide on the surface of the source region 209, the surface of the drain region 208 and the top surface of the gate structure includes: forming a metal material layer (not shown) on the surface of the source region 209, the surface of the drain region 208, the top of the gate structure and the surface of the barrier layer 207; annealing the metal material layer so that the metal material reacts with the substrate silicon; and removing unreacted metal material to form the metal silicide.

[0101] At this point, the semiconductor structure formed forms a shielding doping layer on the surface of the drift region between the drain region and the gate structure. On the one hand, the shielding doping layer can eliminate the induced electric field formed on the surface of the drift region, preventing the induced electric field from having an electrostatic effect on the gate structure; it also prevents the induced charge from accumulating on the surface of the drift region, which reduces the resistance of the drift region and thus reduces the breakdown voltage of the semiconductor structure; on the other hand, the shielding doping layer can block the doping ions in the drain region from diffusing into the channel, thereby avoiding the situation where the resistance of the channel becomes smaller after the doping ions in the drain region diffuse into the channel, making the semiconductor structure prone to breakdown. In summary, the performance of the semiconductor structure is improved.

[0102] Accordingly, the embodiment of the present invention further provides a semiconductor structure, please continue to refer to Figure 9 ,include:

[0103] substrate 200;

[0104] A drift region 202 and a body region 201 are located in the substrate 200 , wherein the drift region 202 and the body region 201 are adjacent to each other, the drift region 202 has first ions, and the body region 201 has second ions, wherein the first ions and the second ions have opposite conductivity types;

[0105] A gate structure located on the substrate 200 , the gate structure being located on the surfaces of the drift region 202 and the body region 201 , and the gate structure extending from the surface of the drift region 202 to the surface of the body region 201 ;

[0106] a shielding doping layer 206 located on the surface of the drift region 202 , wherein the surface of the shielding doping layer 206 is exposed on the surface of the substrate 200 , and the shielding doping layer 206 is adjacent to the gate structure;

[0107] A drain region 208 is located in the drift region 202 . The drain region 208 is adjacent to the shielding doping layer 206 . The drain region 208 and the drift region 202 have the same first ion conductivity type.

[0108] In this embodiment, the shielding doping layer 206 contains third ions, and the third ions include fluorine ions, carbon ions, or nitrogen ions.

[0109] In this embodiment, a top plane of the shielding doping layer 206 is lower than or flush with a top plane of the drift region.

[0110] In this embodiment, the thickness of the shielding doping layer 206 ranges from 0 nanometers to 10 nanometers.

[0111] In this embodiment, the source region 209 is located in the body region 201 , and the source region 209 is adjacent to the gate structure. The source region 209 and the drift region 202 have the same first ion conductivity type.

[0112] In this embodiment, fourth ions are present in the drain region 208 and the source region 209 . The concentration of the fourth ions is greater than that of the first ions, and the concentration of the fourth ions is greater than that of the second ions.

[0113] In this embodiment, the present invention further includes: a barrier layer 207 located on the surface of the shielding doping layer 206 and a portion of the sidewall surface and the top surface of the gate structure.

[0114] In this embodiment, it further includes: a metal silicide 210 located on the surface of the source region 208, the surface of the drain region 209 and the top surface of the gate structure; the material of the metal silicide includes cobalt silicon, nickel silicon or titanium silicon.

[0115] The semiconductor structure has a shielding doping layer on the surface of the drift region, and the shielding doping layer is adjacent to the gate structure. On the one hand, the shielding doping layer can eliminate the induced electric field formed on the surface of the drift region, avoiding the electrostatic influence of the induced electric field on the gate structure; it also avoids the induced charge from accumulating on the surface of the drift region, which reduces the resistance of the drift region and thus reduces the breakdown voltage of the semiconductor structure; on the other hand, the shielding doping layer can block the doping ions in the drain region from diffusing into the channel, thereby avoiding the situation where the resistance of the channel becomes smaller after the doping ions in the drain region diffuse into the channel, making the semiconductor structure easy to break down. In summary, the performance of the semiconductor structure is improved.

[0116] Figures 10 to 12 It is a cross-sectional structural diagram of a semiconductor structure forming process in another embodiment of the present invention.

[0117] Please refer to Figure 10 , Figure 10 For Figure 4Based on the structural schematic diagram, a shielding material layer (not shown) is formed on the substrate 200 and the surface of the gate structure; ion implantation is performed on the shielding material layer to form a shielding doping material layer 301, and the top plane of the shielding doping layer 301 is higher than the top plane of the drift region 202.

[0118] The shielding doping material layer 301 is used to subsequently form a shielding doping layer on the surface of the drift region 202 .

[0119] The implanted ions used in the ion implantation into the shielding material layer are third ions; the third ions include fluorine ions, carbon ions or nitrogen ions.

[0120] The third ions include fluorine ions, carbon ions or nitrogen ions. The fluorine ions, carbon ions or nitrogen ions can react with the dangling bonds on the surface of the substrate to form stable chemical bonds, thereby making it difficult to generate induced charges and form an induced electric field, making it difficult for the carriers to be attracted and accumulated at the bottom of the isolation structure, thereby reducing the resistance of the drift region and the breakdown voltage of the semiconductor structure, thereby improving the performance of the semiconductor structure.

[0121] In this embodiment, the third ions include fluorine ions, and the dosage of the fluorine ions ranges from 4e14 atoms per square centimeter to 5e15 atoms per square centimeter.

[0122] In other embodiments, the third ions include nitrogen ions, and a dosage of the nitrogen ions ranges from 4e14 atoms per square centimeter to 5e15 atoms per square centimeter.

[0123] In other embodiments, the third ions include carbon ions, and the dosage of the carbon ions is in a range of 1e14 atoms per square centimeter to 1e15 atoms per square centimeter.

[0124] If the concentration of the third ion is too high, it is easy to form a high sub-region of the third ion on the surface of the drift region 202. The high sub-region will affect the working current between the drain region and the gate structure, making the working current of the semiconductor structure smaller; if the concentration of the third ion is too low, the shielding doping layer formed will not play a role in eliminating the induced electric field formed on the surface of the drift region 202.

[0125] The shielding material layer is made of silicon oxide, silicon nitride or silicon oxynitride. The shielding material layer is formed by a thermal oxidation process, an atomic layer deposition process or a chemical vapor deposition process.

[0126] In this embodiment, the material of the shielding material layer includes silicon oxide, which has a good shielding effect, is easy to be implanted by the third ion to form a shielding doping layer, and has stable chemical properties; the process of forming the shielding material layer includes an atomic layer deposition process, which can form a shielding material layer with a relatively thin thickness and a dense structure.

[0127] In this embodiment, the thickness of the shielding material layer ranges from 1 nanometer to 5 nanometers.

[0128] If the thickness of the shielding material layer is less than 1 nanometer, and the shielding material layer is too thin when ion implantation is performed on the shielding material layer, the implanted ions will pass through the shielding material layer and enter the drift region 202, thereby lengthening the working current path of the semiconductor structure, thereby increasing the on-resistance of the semiconductor structure, making it difficult to conduct, and affecting the performance of the semiconductor structure; if the thickness of the shielding material layer is less than or greater than 5 nanometers, higher energy is required when ion implantation is performed on the shielding material layer, thereby causing process waste.

[0129] Please refer to Figure 11 , forming a blocking material layer (not shown) on the surface of the shielding doping material layer 301; forming a patterned mask layer (not shown) on the surface of the blocking material layer, the patterned mask layer blocks a portion of the blocking material layer on the surface of the drift region 202 adjacent to the gate structure; etching the blocking material layer and the shielding doping material layer 301 using the patterned mask layer as a mask until the surface of the substrate 200 is exposed, forming a shielding doping layer 302 on the surface of the drift region 202 and the top surface and sidewall surface of part of the gate structure, and forming a blocking layer 303 on the surface of the shielding doping layer 302.

[0130] The process of etching the barrier material layer and the shielding doping material layer 301 includes a dry etching process or a wet etching process. In this embodiment, the process of etching the barrier material layer and the shielding doping material layer 301 includes a dry etching process, and the dry etching process can form the shielding doping layer 302 and the barrier layer 303 with better sidewall morphology.

[0131] A shielding doping layer 302 is formed on the surface of the drift region 202. The shielding doping layer 302 can eliminate the induced electric field formed on the surface of the drift region 202, thereby preventing the induced electric field from generating electrostatic effects on the gate structure. It also prevents the induced charges from accumulating on the surface of the drift region 202, thereby reducing the resistance of the drift region 202 and thus reducing the breakdown voltage of the semiconductor structure.

[0132] In this embodiment, the shielding doping layer 302 and the blocking layer 303 are also located on part of the sidewall surface and the top surface of the gate structure, so that the shielding doping layer 302 and the blocking layer 303 can isolate the metal silicide subsequently formed on the top surface of the gate structure and the surface of the drain region, thereby avoiding the metal silicide on the top surface of the gate structure and the surface of the drain region being too close to each other, resulting in the high voltage subsequently loaded on the drain being too close to the gate, and the semiconductor structure being prone to breakdown.

[0133] In other embodiments, the shielding doping layer and the barrier layer can be located only on the surface of the shielding doping layer.

[0134] The material of the barrier layer 303 includes silicon oxide or silicon oxynitride; the process of forming the barrier material layer includes a chemical vapor deposition process or an atomic layer deposition process; and the process of etching the barrier material layer includes a dry etching process or a wet etching process.

[0135] In this embodiment, the material of the barrier layer 303 includes silicon oxide; and the process of forming the barrier material layer includes a chemical vapor deposition process.

[0136] In this embodiment, the thickness of the barrier layer 303 ranges from 50 nanometers to 300 nanometers.

[0137] If the thickness of the blocking layer 303 is less than 50 nanometers, the thickness of the blocking layer 303 is relatively thin. When ion implantation is subsequently performed using the blocking layer 303 as a mask to form source and drain regions, the ions will pass through the blocking layer 303 and reach the surface of the drift region, thereby failing to serve as a mask. If the thickness of the blocking layer 303 is greater than 300 nanometers, the thickness of the blocking layer 303 is relatively thick, requiring increased conditions for the process of forming the blocking layer 303, thereby causing waste of the process and making it difficult to remove the blocking material layer.

[0138] In this embodiment, the material of the patterned mask layer includes photoresist.

[0139] After forming the shielding doping layer 302 , the patterned mask layer is removed. The process of removing the patterned mask layer includes an ashing process.

[0140] Please refer to Figure 12 , using the shielding doping layer 302, the blocking layer 303 and the gate structure as masks, ion implantation is performed on the exposed surfaces of the drift region 202 and the body region 201 to form a drain region 304 in the drift region 202 and a source region 305 in the body region 201; and metal silicide 306 is formed on the surface of the source region 305, the surface of the drain region 304 and the top surface of the gate structure.

[0141] For details on the process, materials and methods for forming the source region 305, the drain region 304 and the metal silicide 306, please refer to Figure 8 and Figure 9 , I will not go into details here.

[0142] The semiconductor structure thus formed, by forming a shielding doped layer on the surface of the drift region between the drain region and the gate structure, can eliminate the induced electric field formed on the surface of the drift region, preventing the induced electric field from having an electrostatic effect on the gate structure. It also prevents the induced charge from accumulating on the surface of the drift region, reducing the resistance of the drift region and thus reducing the breakdown voltage of the semiconductor structure. In summary, the performance of the semiconductor structure is improved.

[0143] Accordingly, the embodiment of the present invention further provides a semiconductor structure, please continue to refer to Figure 12 ,include:

[0144] substrate 200;

[0145] A drift region 202 and a body region 201 are located in the substrate 200 , wherein the drift region 202 and the body region 201 are adjacent to each other, the drift region 202 has first ions, and the body region 201 has second ions, wherein the first ions and the second ions have opposite conductivity types;

[0146] A gate structure located on the substrate 200 , the gate structure being located on the surfaces of the drift region 202 and the body region 201 , and the gate structure extending from the surface of the drift region 202 to the surface of the body region 201 ;

[0147] a shielding doped layer 302 located on the surface of the drift region 202 , wherein the shielding doped layer 302 is adjacent to the gate structure;

[0148] A drain region 304 is located in the drift region 202 . The drain region 304 is adjacent to the shielding doping layer 302 . The drain region 304 and the drift region 202 have the same first ion conductivity type.

[0149] In this embodiment, the shielding doping layer 302 contains third ions, and the third ions include fluorine ions, carbon ions, or nitrogen ions.

[0150] In this embodiment, a top plane of the shielding doping layer 302 is higher than a top plane of the drift region 202 .

[0151] In this embodiment, the thickness of the shielding doping layer 302 is in the range of 1 nm to 5 nm.

[0152] In this embodiment, the material of the shielding doping layer 302 includes silicon oxide or silicon oxynitride.

[0153] In this embodiment, the present invention further includes: a source region 305 located in the body region 201 , the source region 305 is adjacent to the gate structure, and the source region 305 has the same conductivity type as the first ion.

[0154] In this embodiment, fourth ions are present in the drain region 304 and the source region 305 . The concentration of the fourth ions is greater than that of the first ions, and the concentration of the fourth ions is greater than that of the second ions.

[0155] In this embodiment, the present invention further includes: a barrier layer 303 located on the surface of the shielding doping layer 302 and a portion of the sidewall surface and the top surface of the gate structure.

[0156] In this embodiment, the metal silicide 306 is located on the source region 209 , the drain region 208 and the top surface of the gate structure; the material of the metal silicide includes cobalt silicon, nickel silicon or titanium silicon.

[0157] In this embodiment, the first ions include N-type ions, and the N-type ions include phosphorus ions or arsenic ions.

[0158] In this embodiment, the second ions include P-type ions, and the P-type ions include boron ions, boron fluoride ions, or indium ions.

[0159] In this embodiment, the gate structure includes a gate dielectric layer, a gate layer located on the gate dielectric layer, and sidewall spacers located on sidewalls of the gate dielectric layer and the gate layer.

[0160] In this embodiment, the thickness of the sidewall spacer ranges from 20 nanometers to 80 nanometers.

[0161] The semiconductor structure has a shielding doping layer on the surface of the drift region, and the shielding doping layer is adjacent to the gate structure. On the one hand, the shielding doping layer can eliminate the induced electric field formed on the surface of the drift region, avoiding the electrostatic influence of the induced electric field on the gate structure; it also avoids the induced charge from accumulating on the surface of the drift region, which reduces the resistance of the drift region and thus reduces the breakdown voltage of the semiconductor structure; on the other hand, the shielding doping layer can block the doping ions in the drain region from diffusing into the channel, thereby avoiding the situation where the resistance of the channel becomes smaller after the doping ions in the drain region diffuse into the channel, making the semiconductor structure easy to break down. In summary, the performance of the semiconductor structure is improved.

[0162] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a drift region and a body region in the substrate, wherein the drift region and the body region are adjacent to each other, the drift region has first ions, the body region has second ions, and the first ions and the second ions have opposite conductivity types; forming a gate structure on the substrate, wherein the gate structure is located on the surfaces of the drift region and the body region, and the gate structure extends from the surface of the drift region to the surface of the body region; forming a shielding doping layer on the surface of the drift region, wherein the shielding doping layer contains third ions, and the third ions are used to eliminate induced charges on the surface of the drift region, the shielding doping layer is adjacent to the gate structure, and the top plane of the shielding doping layer is lower than or flush with the top plane of the drift region; forming a barrier layer on the substrate, the surface of the shielding doping layer, and a portion of the sidewall surface and the top surface of the gate structure; A drain region is formed in the drift region, the drain region is adjacent to the shielding doping layer, and the drain region and the drift region have the same first ion conductivity type.

2. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming a shielding doping layer on the surface of the drift region includes: forming a mask layer on the substrate and the surface of the gate structure, the mask layer exposing a portion of the drift region surface adjacent to the gate structure; performing ion implantation on the exposed drift region surface to form the shielding doping layer on the drift region surface, the top plane of the shielding doping layer being lower than or flush with the top plane of the drift region.

3. The method for forming a semiconductor structure according to claim 2, wherein: The implanted ions in the ion implantation process are third ions; the third ions include fluorine ions, carbon ions or nitrogen ions; the dosage range of the fluorine ions and nitrogen ions is 4e14 atoms per square centimeter to 5e15 atoms per square centimeter, and the dosage range of the carbon ions is 1e14 atoms per square centimeter to 1e15 atoms per square centimeter.

4. The method for forming a semiconductor structure according to claim 2, wherein: The thickness of the shielding doping layer ranges from 0 nanometers to 10 nanometers.

5. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: A source region is formed in the body region, the source region is adjacent to the gate structure, and the source region has the same conductivity type as the first ion; the source region and the drain region are formed simultaneously.

6. The method for forming a semiconductor structure according to claim 5, wherein: The method for forming the source region, the drain region and the barrier layer includes: forming a barrier material layer on the substrate, the surface of the shielding doping layer and the top surface and side wall surface of the gate structure; forming a patterned layer on the barrier material layer, wherein the patterned layer blocks a portion of the top surface of the barrier material layer on the surface of the shielding doping layer; etching the barrier material layer using the patterned layer as a mask until the substrate surface is exposed, and forming a barrier layer on the surface of the shielding doping layer and a portion of the side wall surface and top surface of the gate structure; and performing ion implantation on the exposed surfaces of the drift region and body region using the barrier layer and the gate structure as masks to form a drain region in the drift region and a source region in the body region.

7. The method for forming a semiconductor structure according to claim 6, wherein: The implanted ions in the ion implantation process are fourth ions, the concentration of the fourth ions is greater than the concentration of the first ions, and the concentration of the fourth ions is greater than the concentration of the second ions.

8. The method for forming a semiconductor structure according to claim 5, wherein: Also includes: forming metal silicide on the surface of the source region, the surface of the drain region and the top surface of the gate structure; The material of the metal silicide includes cobalt silicon, nickel silicon or titanium silicon.

9. The method for forming a semiconductor structure according to claim 1, wherein: The first ions include N-type ions, which include phosphorus ions or arsenic ions; the second ions include P-type ions, which include boron ions, boron fluoride ions or indium ions.

10. A semiconductor structure, characterized in that include: substrate; A drift region and a body region located in the substrate, the drift region and the body region being adjacent to each other, the drift region having first ions, the body region having second ions, and the first ions and the second ions having opposite conductivity types; A gate structure located on the substrate, the gate structure is located on the surfaces of the drift region and the body region, and the gate structure extends from the surface of the drift region to the surface of the body region; a shielding doping layer located on the surface of the drift region, wherein the shielding doping layer has third ions therein, wherein the third ions are used to eliminate induced charges on the surface of the drift region, the shielding doping layer is adjacent to the gate structure, and the top plane of the shielding doping layer is lower than or flush with the top plane of the drift region; a barrier layer located on the substrate, the surface of the shielding doping layer, and a portion of the sidewall surface and the top surface of the gate structure; A drain region is located in the drift region, the drain region is adjacent to the shielding doping layer, and the drain region and the drift region have the same first ion conductivity type.

11. The semiconductor structure according to claim 10, wherein: The shielding doping layer has third ions therein, and the third ions include fluorine ions, carbon ions or nitrogen ions.

12. The semiconductor structure according to claim 10, wherein: A top plane of the shielding doping layer is lower than or flush with a top plane of the drift region.

13. The semiconductor structure according to claim 12, wherein: The thickness of the shielding doping layer ranges from 0 nanometers to 10 nanometers.

14. The semiconductor structure according to claim 10, wherein: Also includes: A source region is located in the body region, the source region is adjacent to the gate structure, and the source region has the same conductivity type as the first ion.

15. The semiconductor structure according to claim 14, wherein: There are fourth ions in the drain region and the source region, and the concentration of the fourth ions is greater than the concentration of the first ions, and the concentration of the fourth ions is greater than the concentration of the second ions.

16. The semiconductor structure according to claim 14, wherein: Also includes: Metal silicide located on the surface of the source region, the surface of the drain region and the top surface of the gate structure; the material of the metal silicide includes cobalt silicon, nickel silicon or titanium silicon.

17. The semiconductor structure according to claim 10, wherein: The first ions include N-type ions, and the N-type ions include phosphorus ions or arsenic ions.

18. The semiconductor structure according to claim 10, wherein: The second ions include P-type ions, and the P-type ions include boron ions, boron fluoride ions, or indium ions.

19. The semiconductor structure according to claim 10, wherein: The gate structure includes a gate dielectric layer, a gate layer located on the gate dielectric layer, and sidewalls located on the sidewalls of the gate dielectric layer and the gate layer.

20. The semiconductor structure according to claim 19, wherein The thickness of the sidewalls ranges from 20 nanometers to 80 nanometers.

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