Package and semiconductor device and method for manufacturing the same

Abstract

A device includes: an interconnect device connected to a redistribution structure, wherein the interconnect device includes a conductive wiring connected to a conductive connector disposed on a first side of the interconnect device; a molding material at least laterally surrounding the interconnect device; a metallization pattern located above the molding material and the first side of the interconnect device, wherein the metallization pattern is electrically connected to the conductive connector; a first external connector connected to the metallization pattern; and a semiconductor device connected to the first external connector. Embodiments of the present application also relate to a package and a semiconductor device and a method for manufacturing the same.

Description

Technical Field

[0001] Embodiments of the present application also relate to a package and a semiconductor device and a method for manufacturing the same. Background Art

[0002] The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components, and thus more functions, to be integrated into a given area. Integrated circuits with high functionality require many input / output pads. However, for applications where miniaturization is important, a small package may be required.

[0003] Integrated fan-out (InFO) packaging technology is becoming increasingly popular, especially when used in conjunction with wafer-level packaging (WLP) technology, where an integrated circuit is packaged in a package that typically includes a redistribution layer (RDL) or post-passivation interconnect to fan out the wiring for the package contact pads so that electrical contacts can be made at a larger pitch than the contact pads of the integrated circuit. The resulting package structure provides high functional density with a relatively low cost and high performance package. Summary of the invention

[0004] According to one aspect of the present application, a method for forming a semiconductor device is provided, comprising: placing an interconnect device on a first carrier, wherein the interconnect device includes a first conductive connector and a second conductive connector; forming a first via and a second via on the first carrier; forming a redistribution structure above the interconnect device, the first via, and the second via, wherein a first side of the redistribution structure is connected to the first via and the second via; connecting the interconnect structure to a second side of the redistribution structure, wherein the interconnect structure includes an organic substrate and a plurality of wiring layers; connecting the interconnect structure to a second carrier; connecting a first semiconductor die to the first conductive connector and the first via of the interconnect device; and connecting a second semiconductor die to the second conductive connector and the second via of the interconnect device, wherein the second semiconductor die is electrically connected to the first semiconductor die through the interconnect device.

[0005] According to another aspect of the present application, a semiconductor device is provided, comprising: an interconnect device connected to a redistribution structure, wherein the interconnect device comprises conductive wiring connected to a plurality of conductive connectors arranged on a first side of the interconnect device; a molding material at least laterally surrounding the interconnect device; a metallization pattern located above the molding material and the first side of the interconnect device, wherein the metallization pattern is electrically connected to the plurality of conductive connectors; a plurality of first external connectors connected to the metallization pattern; and a plurality of semiconductor devices connected to the plurality of first external connectors.

[0006] According to another aspect of the present application, a package is provided, comprising: a redistribution structure comprising a plurality of insulating layers and a plurality of redistribution layers; a first molding compound layer located on the redistribution structure; a plurality of vias located in the first molding compound layer; a plurality of interconnect devices located in the first molding compound layer, wherein each interconnect device comprises a plurality of contacts; a dielectric layer covering the first molding compound layer, the vias, and the plurality of interconnect devices; and a plurality of semiconductor devices located above the dielectric layer, wherein the plurality of semiconductor devices are electrically connected to the vias through the dielectric layer, and are electrically connected to a plurality of contacts of the plurality of interconnect devices through the dielectric layer, wherein at least two of the plurality of semiconductor devices are electrically connected through at least one of the plurality of interconnect devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0008] Figures 1 to 6 illustrates a cross-sectional view of an intermediate step in forming a device structure including an interconnect device according to some embodiments;

[0009] Figure 7A-7B A cross-sectional view showing an intermediate step of connecting an interconnect structure to a device structure according to some embodiments;

[0010] Figures 8 to 13 shows a cross-sectional view of an intermediate step in forming a package according to some embodiments;

[0011] Fig.14 shows a plan view of a package according to some embodiments;

[0012] Figure 15A-15B shows a cross-sectional view of a portion of a package according to some embodiments;

[0013] Fig.16 shows a cross-sectional view of a package according to some embodiments;

[0014] Fig.17 shows a plan view of a package according to some embodiments;

[0015] Fig.18A and Fig.18B Intermediate steps in forming device structures on different types of carrier substrates are shown in accordance with some embodiments. DETAILED DESCRIPTION

[0016] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or structures discussed.

[0017] Furthermore, for ease of description, spatially relative terms such as "under," "beneath," "lower," "over," "upper," etc. may be used herein to easily describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0018] In the present invention, various aspects of packages and their formation are described. In some embodiments, an interconnect device incorporated in a package can electrically connect two or more semiconductor dies. The interconnect device can have a high wiring density and can be located close to the semiconductor die, which can improve the communication bandwidth between the semiconductor dies. The interconnect device can also allow for reduced warping and improve the connection reliability of the package. In addition, other types of electronic devices such as integrated passive devices (IPDs) or integrated voltage regulators (IVRs) can be incorporated into the package in a manner similar to the interconnect device to provide additional functions to the package.

[0019] Figures 1 to 6 A device structure 100 having an interconnect device 110 is shown in accordance with some embodiments (see FIG. Figure 6 ) is a cross-sectional view of an intermediate step. Fig. 7A and Figure 7B A cross-sectional view is shown of an intermediate step in connecting the interconnect structure 200 to the device structure 100 in accordance with some embodiments. Figures 8 to 13 FIG. 3 shows a package 300 (see FIG. 4 ) formed in conjunction with, for example, the device structure 100 according to some embodiments. Fig.13 ) is a cross-sectional view of an intermediate step. Fig.14 A plan view of a package 350 is shown in accordance with some embodiments. Fig.16 A cross-sectional view of a package 400 is shown in accordance with some embodiments. Fig.17 A plan view of a package 450 is shown in accordance with some embodiments.

[0020] Go to Figure 1 , which shows a first carrier substrate 102 according to some embodiments, on which a through molded via (TMV) 106 has been formed. The first carrier substrate 102 may include, for example, a silicon-based material, such as a silicon substrate (e.g., a silicon wafer), a glass material, silicon oxide, or other materials such as aluminum oxide, etc., or a combination thereof. In some embodiments, the first carrier substrate 102 may be a flat plate structure, which may be, for example, a supporting substrate formed of a suitable dielectric material such as a glass material, a plastic material, or an organic material. The flat plate structure may be, for example, a rectangular flat plate.

[0021] As an illustrative example, according to some embodiments, Fig.18A and Fig.18B A device structure 100 is shown formed using different types of carrier substrates 102 (see FIG. Figure 6 ). Fig.18A An embodiment is shown in which the carrier substrate 102 is a silicon wafer, and Fig.18B An embodiment is shown where the carrier substrate 102 is a flat plate structure. Figure 18A-18B A plurality of device structures 100 are shown formed on a carrier substrate 102. In this manner, different types of carrier substrates 102 may be used to form a plurality of device structures 100. Subsequently, the structures formed on the first carrier substrate 102 may be singulated.

[0022] In some embodiments, a release layer (not shown) may be formed on the top surface of the first carrier substrate 102 to facilitate subsequent release of the first carrier substrate 102. In some embodiments, the release layer may be formed of a polymer-based material that may be removed from an overlying structure to be formed in a subsequent step together with the first carrier substrate 102. In some embodiments, the release layer is an epoxy-based thermal release material that loses its adhesive properties when heated, such as a light-to-heat conversion (LTHC) release coating. In other embodiments, the release layer may be an ultraviolet (UV) glue that loses its adhesive properties when exposed to ultraviolet light. The release layer may be dispensed in the form of a liquid and cured, and may be a laminated film laminated on the first carrier substrate 102 or the like. The top surface of the release layer may be horizontal and may have a high degree of coplanarity. In some embodiments, a die attach film (DAF) (also not shown) may be used instead of the release layer, or a die attach film (DAF) may be used in addition to the release layer.

[0023] In one embodiment, TMV106 can be formed by first forming a seed layer 104. In some embodiments, the seed layer 104 is a metal layer, which can be a single layer, or a composite layer including multiple sublayers formed by different materials. In some embodiments, the seed layer 104 includes a copper layer above a titanium layer and a titanium layer, but in other embodiments, the seed layer 104 can include different materials or different layers. The seed layer 104 can be formed using a suitable process such as PVD, CVD, sputtering, etc. The seed layer 104 is formed above the first carrier substrate 102 (or above the stripping layer, if present). A photoresist (also not shown) can then be formed to cover the seed layer 104, and then patterned to expose those parts of the seed layer at the position where the TMV106 will be formed later. Once the photoresist is formed and patterned, a conductive material can be formed on the seed layer 104. The conductive material can be a material such as copper, titanium, tungsten, aluminum, another metal, etc., or a combination thereof. The conductive material can be formed by a deposition process such as electroplating, chemical plating, etc. However, although the materials and methods discussed are suitable for forming conductive materials, these are only examples. Any other suitable material or any other suitable formation process (e.g., CVD or PVD) can be used alternatively to form TMV106. Once the conductive material is formed, the photoresist can be removed by a suitable removal process (e.g., an ashing process) or a chemical stripping process (e.g., using oxygen plasma, etc.). In some embodiments, the seed layer 104 is not removed after forming TMV106. In some embodiments, TMV106 can have a height between about 3 μm and about 100 μm.

[0024] Go to Figure 2 In accordance with some embodiments, the interconnect device 110 is connected to the first carrier substrate 102 . Figure 2 Also shown is an enlarged view of an example of an interconnect device 110 and adjacent TMVs 106 on the first carrier substrate 102. In some embodiments, the interconnect device 110 includes a conductive connector 112 that can be used to make electrical connections to the interconnect device 110. Figure 2 The interconnect devices 110 shown have conductive connectors 112 formed on a single side of each interconnect device 110, but in some embodiments, the interconnect devices 110 can have conductive connectors 112 formed on both sides. In some embodiments, solder material 114 is formed on each conductive connector 112 before connection. Figure 2Two interconnect devices 110 are shown connected to the first carrier substrate 102, but in other embodiments, only one interconnect device 110 may be connected, or more than two interconnect devices 110 may be connected. The connected interconnect devices 110 may include a plurality of similar interconnect devices 110, and / or include more than one different type of interconnect devices 110. In some embodiments, in addition to the interconnect devices 110, other types of devices may also be connected to the first carrier substrate 102, such as the following. Figure 15A-Figure 16 Electronic device 410 described in.

[0025] In some embodiments, the conductive connector 112 includes a metal pad or a metal column (e.g., a copper column). The conductive material that the conductive connector 112 may include is, for example, solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or a combination thereof. In some embodiments, the metal column may be solderless and / or have a substantially vertical sidewall. In some embodiments, a metal capping layer is formed on the top of the metal column. The metal capping layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc., or a combination thereof, and may be formed by a plating process. In some embodiments, the pitch of the conductive connector 112 may be between about 20 μm and about 80 μm, and the height of the conductive connector 112 may be between about 2 μm and about 30 μm.

[0026] In some embodiments, the solder material 114 formed on the conductive connector 112 may be a ball grid array (BGA) connector, a solder ball, a controlled collapse chip connection (C4) bump, a micro bump (e.g., a μ bump), a bump formed by electroless nickel plating-electroless palladium-immersion gold technology (ENEPIG), etc. The solder material 114 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or a combination thereof. In some embodiments, the solder material 114 is formed by first forming a solder layer by evaporation, electroplating, printing, solder transfer, solder ball placement, etc. Once the solder layer is formed on the conductive connector 112, reflow may be performed to shape the material into a desired shape.

[0027] The interconnect device 110 may be placed on the first carrier substrate 102, for example, using a pick and place process. In some embodiments, once the solder material 114 of the interconnect device 110 is in physical contact with the seed layer 104, a reflow process may be performed to bond the solder material 114 to the seed layer 104, thereby connecting the interconnect device 110 to the first carrier substrate 102.

[0028] In some embodiments, the interconnect device 110 includes one or more layers of electrical wiring 115 (e.g., redistribution layer (RDL), metallization pattern, metal line, and via, etc.) formed in the substrate 113. In some embodiments, the interconnect device 110 including the electrical wiring 115 is used to form interconnections or additional wiring between other devices in the package, such as semiconductor devices (e.g., Fig.13 ), dies, chips, etc. In some embodiments, the interconnect device 110 includes one or more active devices (e.g., transistors, diodes, etc.) and / or one or more passive devices (e.g., capacitors, resistors, inductors, etc.). In some embodiments, the interconnect device 110 includes electrical wiring 115 and is substantially free of active devices or passive devices. In some embodiments, the interconnect device 110 may have a thickness between about 10 μm and about 100 μm (excluding the conductive connector 112 or the solder material 114). In some embodiments, the interconnect device 110 may have a lateral dimension between about 2 mm by 2 mm and about 80 mm by 80 mm, for example, about 2 mm by 3 mm or 50 mm by 80 mm.

[0029] The interconnect device 110 can be formed using an applicable manufacturing process. The substrate 113 can be, for example, a semiconductor substrate, such as silicon, which can be doped or undoped, and it can be an active layer of a silicon wafer or a semiconductor on insulator (SOI) substrate, etc. The semiconductor substrate can include other semiconductor materials, such as: germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates can also be used, such as multilayer substrates or gradient substrates. The electrical wiring 115 can be formed of alternating layers of dielectrics (e.g., low-k dielectric materials) and conductive materials (e.g., copper), with vias that interconnect the conductive material layers, and can be formed by any suitable process (e.g., deposition, damascene, dual damascene, etc.).

[0030] The electrical wiring 115 of the interconnect device 110 can be formed by any suitable conductive material using any suitable process. In some embodiments, a damascene process is used, in which the corresponding dielectric layer is patterned and etched using photolithography to form grooves corresponding to the desired pattern of the metallization layer and / or vias. An optional diffusion barrier layer and / or an optional adhesion layer can be deposited, and the grooves can be filled with conductive materials. Suitable materials for barrier layers include titanium, titanium nitride, tantalum, tantalum nitride, or other substitutes, and suitable materials for conductive materials include copper, silver, gold, tungsten, aluminum, combinations thereof, and the like. In one embodiment, a metallization layer can be formed by depositing a seed layer of copper or a copper alloy and filling the grooves by electroplating. Chemical mechanical planarization (CMP) can be used to remove excess conductive material from the surface of the corresponding dielectric layer and planarize the surface for subsequent processes.

[0031] In some embodiments, the electrical wiring 115 of the interconnect device 110 may include a fine pitch RDL having a pitch less than about 1 μm. The fine pitch RDL may be formed, for example, using a single damascene and / or dual damascene process as described above. By forming the electrical wiring 115 having a fine pitch, the density of the electrical wiring 115 in the interconnect device 110 may be increased, thereby improving the wiring capability of the interconnect device 110. In some cases, a higher density of the electrical wiring 115 in the interconnect device 110 may allow a smaller amount of wiring (e.g., Figure 5 The RDL of the redistribution structure 120, or Fig. 7A The wiring layers 212 / 213 of the interconnect structure 200 in the package (eg Fig.13 ) elsewhere in the package 300 shown in . By reducing the wiring spacing within the package, the size of the package can be reduced, the process cost of the package can be reduced, or the performance can be improved. In some cases, the use of a fine pitch formation process (e.g., a damascene or dual damascene process) can allow for improved conductivity and connection reliability within the interconnect device 110. In some cases, during high-speed operations (e.g., greater than about 2 Gbit / second), electrical signals can be conducted near the surface of the conductive component. Fine pitch wiring may have less surface roughness than other types of wiring, and therefore can reduce the resistance experienced by high-speed signals, and can also reduce signal losses (e.g., insertion losses) during high-speed operations. This can improve the performance of high-speed operations, such as serializer / deserializer ("SerDes") circuits or other circuits that can operate at higher speeds.

[0032] Go to Figure 3According to some embodiments, the interconnect device 110 and the TMV 106 are sealed using a sealant 108. Prior to sealing, an underfill 107 is deposited in the gap between each interconnect device 110 and the first carrier substrate 102. The material of the underfill 107 may be, for example, a molding compound, an epoxy resin, an underfill, a molded underfill (MUF), a resin, or the like. The underfill 307 may protect the conductive connector 112 and provide structural support for the interconnect device 110. In some embodiments, the underfill 107 may be cured after deposition. Sealing may be implemented in a molded device, or another technique may be used to deposit the sealant 108. The sealant 108 may be, for example, a molding compound, such as a resin, polyimide, PPS, PEEK, PES, an epoxy molding compound (EMC), another material, or the like, or a combination thereof. As Figure 3 As shown, the encapsulant 108 may surround and / or cover the interconnect device 110 and the TMV 106 .

[0033] exist Figure 4 In some embodiments, a planarization process is performed on the encapsulant 108. The planarization process may be performed, for example, using a mechanical grinding process, a chemical mechanical polishing (CMP) process, etc. The planarization process removes excess portions of the encapsulant 108 and exposes the TMVs 106. In some cases, the planarization process may also expose one or more interconnect devices 110. After the planarization process, the TMVs 106 and / or the interconnect devices 110 may have a surface flush with the surface of the encapsulant 108.

[0034] Go to Figure 5 According to some embodiments, a redistribution structure 120 is formed over the interconnect device 110, the TMV 106, and the encapsulant 108. The redistribution structure 120 is electrically connected to the TMV 106. In some embodiments where the interconnect device has conductive connectors 112 on a side opposite to the first carrier substrate 102, the redistribution structure 120 can be electrically connected to these conductive connectors. The illustrated redistribution structure 120 includes insulating layers 122A-122E and 123, and includes redistribution layers (RDL) 124A-124G. In other embodiments, a redistribution structure 120 can be formed with respect to the TMV 106. Figure 5 For example, in some embodiments, the redistribution structure 120 may include between about 1 and about 15 insulating layers or RDLs, or other numbers of insulating layers or RDLs. In some embodiments, the insulating layers may include different materials, for example, the insulating layers 122A-122E are different materials from the insulating layer 123, which will be described in more detail below. In some embodiments, the redistribution structure 120 may be, for example, a fan-out structure.

[0035] Still reference Figure 5 , a first insulating layer 122A is formed over the interconnect device 110, the TMV 106, and the sealant 108. The insulating layer 122A may be made of one or more suitable dielectric materials, which may be, for example, an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), a polymer material, a polyimide material, a low-k dielectric material, a molding material (e.g., EMC, etc.), another dielectric material, etc., or a combination thereof. The insulating layer 122A may be formed by processes such as spin coating, lamination, CVD, etc., or a combination thereof. The insulating layer 122A may have a thickness between about 1 μm and about 50 μm, for example, about 5 μm, but any suitable thickness may be used. In some embodiments, an opening into the insulating layer 122A may be formed using a suitable photolithographic mask and etching process. For example, a photoresist may be formed over the insulating layer 122A and may be patterned, and a portion of the insulating layer 122A may be removed using one or more etching processes (e.g., a wet etching process or a dry etching process). In some embodiments, insulating layer 122A is formed of a photosensitive polymer such as PBO, polyimide, BCB, etc., in which openings can be directly patterned using photolithographic masking and etching processes. The openings in insulating layer 122A can expose TMV 106 and conductive connector 112 of interconnect device 110 (if present).

[0036] Then, the first RDL 124A is formed over the insulating layer 122A. The RDL 124A may be a patterned conductive layer (e.g., a metallization pattern) including a line portion (also referred to as a wire) located on and extending along the main surface of the insulating layer 122A. The RDL 124A further includes a via portion (also referred to as a conductive via) extending through the insulating layer 122A to physically and electrically connect to the TMV 106 (and the conductive connector 112 of the interconnect device 110, if present). In one embodiment, the RDL 124A may be formed by first forming a seed layer (not shown). In some embodiments, the seed layer is a metal layer, which may be a single layer, or a composite layer including multiple sublayers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer above the titanium layer. The seed layer may be formed using a suitable formation process such as PVD, CVD, sputtering, or the like. The seed layer is formed above the insulating layer 122A and above the TMV 106 (and the conductive connector 112 of the interconnect device 110, if present) exposed by the opening in the insulating layer 122A. A photoresist (also not shown) can then be formed to cover the seed layer, and then patterned to expose those parts of the seed layer at the position where the RDL 124A will be formed later. Once the photoresist is formed and patterned, a conductive material can be formed on the seed layer 104. The conductive material can be a material such as copper, titanium, tungsten, aluminum, another metal, or a combination thereof. The conductive material can be formed by a deposition process such as electroplating, chemical plating, etc. However, although the materials and methods discussed are suitable for forming conductive materials, these are only examples. Any other suitable material or any other suitable formation process (such as CVD or PVD) can be used alternatively to form the RDL 124A. Once the conductive material is formed, the photoresist can be removed by a suitable removal process (such as an ashing process) or a chemical stripping process (such as using oxygen plasma, etc.). Additionally, after removing the photoresist, those portions of the seed layer covered by the photoresist may be removed, for example, by a suitable wet etching process or a dry etching process (which may use the conductive material as an etching mask). The remaining portions of the seed layer and the conductive material form the RDL 124A. In some embodiments, the portion of the RDL 124A extending over the insulating layer 122A may have a thickness between about 1 μm and about 25 μm, although any suitable thickness may be used.

[0037] Then, additional insulating layers 122B-122E / 123 and RDLs 124B-124G may be formed over RDL 124A and insulating layer 122A to provide additional routing and electrical connections within redistribution structure 220. Insulating layers 122B-122E / 123 and RDLs 124B-124G may be formed in alternating layers. In some embodiments, redistribution structure 120 may include different types of insulating layers, such as insulating layers formed by different materials and / or different processes. As an illustrative example, Figure 5 The insulating layers 122B-122E shown are different types of insulating layers than the insulating layer 123. In some embodiments, the insulating layers 122A-122E can be formed of a photopolymer and the insulating layer 123 can be formed of a molding compound, but in other embodiments, the insulating layers 122A-122E / 123 can be formed of materials different from these materials. In some embodiments, the insulating layer 123 can be formed of a material similar to the encapsulant 108. The redistribution structure 120 can have any number, combination, or arrangement of different types of insulating layers, including those having the same or different properties. Figure 5 For example, the redistribution structure 120 may include multiple insulating layers similar to the insulating layer 123, or all insulating layers of the redistribution structure 120 may be of the same type.

[0038] Insulating layers similar to insulating layer 122A, such as insulating layers 122B-122E, may be formed using processes and materials similar to those used for insulating layer 222A or redistribution layer 224A. For example, an insulating layer may be formed and then an opening may be formed through the insulating layer to expose a portion of the underlying RDL using a suitable photolithography mask and etching process. A seed layer may be formed over the insulating layer, and a conductive material may be formed on a portion of the seed layer to form the upper RDL. These steps may be repeated to form a redistribution structure 120 having a suitable number and configuration of insulating layers and RDLs.

[0039] Insulating layer 123 or an insulating layer similar to insulating layer 123 may be formed differently from insulating layers 122A-122E. For example, insulating layer 123 and similar insulating layers may be formed from a molding compound such as EMC. In some embodiments having an insulating layer formed from a molding compound, vias extending through the insulating layer (e.g., via portions of RDL 124C extending through insulating layer 123) may first be formed on an underlying RDL (e.g., RDL 124B) using a seed layer and a plating process similar to the process described above for forming TMV 106. The molding compound may then be deposited over the vias and planarized to expose the vias and form an insulating layer (e.g., insulating layer 123). The insulating layer (e.g., insulating layer 123) may have a thickness between about 1 μm and about 50 μm, for example about 10 μm, but any suitable thickness may be used. Portions of the RDL extending over insulating layers, such as metal line portions of RDL 124C extending over insulating layer 123, may be formed using techniques similar to those described above for forming RDL 124A. These steps may be repeated to form a redistribution structure 120 having a suitable number and configuration of insulating layers and RDLs.

[0040] In some cases, the impedance of interconnects within a redistribution structure such as redistribution structure 120 can be controlled by one or more insulating layers formed of different materials and / or having different thicknesses. For example, by forming an insulating layer (e.g., insulating layer 123) from a mold compound, the impedance of an associated RDL (e.g., RDL 124C) can be controlled according to a particular application or design. Controlling interconnect impedance in this manner can allow for greater flexibility in package design and can improve the operational performance of the package.

[0041] Go to Figure 6 , an external connector 126 is formed on the redistribution structure 120, thereby forming the device structure 100. In some embodiments, an under bump metallization structure (UBM, not shown) is first formed on the topmost redistribution layer (e.g. Figure 6The UBM may be formed on a portion of the redistribution layer 124G in the redistribution structure 120. The UBM may, for example, include three layers of conductive material, such as a titanium layer, a copper layer, and a nickel layer. However, other materials and layer arrangements may be used, such as an arrangement of chromium / chromium-copper alloy / copper / gold, an arrangement of titanium / titanium tungsten / copper, or an arrangement of copper / nickel / gold suitable for the formation of the UBM. Any suitable material or material layer that can be used for the UBM is fully intended to be included within the scope of the present application. The UBM may be created by forming each layer of the UBM above the redistribution structure 120. The formation of each layer may be implemented using a plating process such as electroplating or chemical plating, but other formation processes such as sputtering, evaporation, or PECVD processes may be used alternatively depending on the desired material. Once the desired layer is formed, a portion of the layer may be removed by a suitable photolithography mask and etching process to remove the unwanted material and keep the UBM in the desired shape, such as a circle, an octagon, a square, or a rectangle, but any desired shape may be formed alternatively. In some embodiments, as part of the formation of the redistribution structure 220, the UBM is formed over the topmost redistribution layer, which may include using the same lithography steps as used to form the topmost redistribution layer. For example, a layer of the UBM may be deposited over the topmost redistribution layer, and then excess material of the topmost redistribution layer and the UBM may be removed in the same process. In some embodiments, the UBM may be part of the topmost redistribution layer of the redistribution structure 120, and may, for example, extend through the topmost insulating layer (e.g., Figure 6 Insulating layer 122E in.

[0042] Still reference Figure 6, and then the external connector 126 is formed on the topmost redistribution layer of the redistribution structure 120 (e.g., on the redistribution layer 124G or on the UBM, if present). The external connector 126 can be a ball grid array (BGA) connector, a solder ball, a metal column, a controlled collapse chip connection (C4) bump, a microbump, a bump formed by chemical nickel plating-chemical palladium immersion gold technology (ENEPIG), etc. The external connector 126 may include a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or a combination thereof. In some embodiments, the external connector 126 is formed by first forming a solder layer by evaporation, electroplating, printing, solder transfer, solder ball placement, etc. Once the solder layer is formed on the structure, reflow can be implemented to shape the material into the desired bump shape. In another embodiment, the external connector 126 includes a metal column (e.g., a copper column) formed by sputtering, printing, electroplating, chemical plating, CVD, etc. The metal column can be solder-free and have a substantially vertical sidewall. In some embodiments, a metal capping layer is formed on top of the metal pillar. The metal capping layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc., or a combination thereof, and may be formed by a plating process. In some embodiments, the pitch of the external connector 126 may be between about 150 μm and about 1250 μm.

[0043] Figure 7A-7B 2 shows the connection of an interconnect structure 200 to a device structure 100 according to some embodiments. The interconnect structure 200 provides additional routing and stability to the device structure 100. For example, the interconnect structure 200 can reduce the warping of the device structure 100, especially for devices with large areas (e.g., greater than about 90 mm2). 2 ) device structure 100.

[0044] Go to Fig. 7A , showing an interconnect structure 200 according to some embodiments. In some embodiments, the interconnect structure 200 may be, for example, a plug-in or a "semi-finished substrate", and may not have active devices. In some embodiments, the interconnect structure may include a wiring layer formed on a central substrate 202. The central substrate 202 may include materials such as Ajinomoto built-up film (ABF), pre-impregnated composite fiber (prepreg) materials, epoxy resins, molding compounds, epoxy molding compounds, glass fiber reinforced resin materials, printed circuit board (PCB) materials, silica fillers, polymer materials, polyimide materials, paper, glass fiber, non-woven fabrics, glass, ceramics, other laminates, etc., or combinations thereof. In some embodiments, the central substrate may be a double-sided copper clad laminate (CCL) substrate, etc. The central substrate 202 may have a thickness between about 30 μm and about 2000 μm, for example, about 500 μm or about 1200 μm.

[0045] The interconnect structure 200 may have one or more wiring structures 212 / 213 formed on each side of the central substrate 202, and a via 210 extending through the central substrate 202. The wiring structures 212 / 213 and the through vias 210 provide additional electrical wiring and interconnection. The wiring structures 212 / 213 may include one or more wiring layers 208 / 209, and one or more dielectric layers 218 / 219. In some embodiments, the wiring layers 208 / 209 and / or the through vias 210 may include one or more layers of copper, nickel, aluminum, other conductive materials, etc., or a combination thereof. In some embodiments, the dielectric layer 218 / 219 may include materials such as build-up materials, ABF, prepreg materials, laminated materials, another material similar to the materials described above for the central substrate 202, etc., or a combination thereof. Fig. 7A The illustrated interconnect structure 200 shows two wiring structures having a total of six wiring layers, but in other embodiments, more or fewer wiring layers may be formed on either side of the central substrate 202 .

[0046] In some embodiments, the openings in the center substrate 202 for the through vias 210 may be filled with a filling material 211. The filling material 211 may provide structural support and protection for the conductive material of the through vias 210. In some embodiments, the filling material 211 may be, for example, a molding material, an epoxy, an epoxy molding compound, a resin, a material including a monomer or an oligomer, such as an acrylated urethane, a rubber-modified acrylated epoxy, or a multifunctional monomer, or the like, or a combination thereof. In some embodiments, the filling material 211 may include a pigment or dye (e.g., for color), or other fillers and additives that change rheology, improve adhesion, or affect other properties of the filling material 211. In some embodiments, the conductive material of the through vias 210 may completely fill the through vias 210, thereby omitting the filling material 211.

[0047] In some embodiments, the interconnect structure 200 may include a passivation layer 207 formed over one or more sides of the interconnect structure 200. The passivation layer 207 may be a material such as a nitride, an oxide, a polyimide, a low temperature polyimide, a solder resist, a combination thereof, etc. Once formed, the passivation layer 207 may be patterned (e.g., using suitable photolithography and etching processes) to expose portions of the wiring layers 208 / 209 of the wiring structures 212 / 213.

[0048] Figure 7BAn arrangement is shown in which an interconnect structure 200 is electrically connected to a device structure 100 in accordance with some embodiments. In one embodiment, the interconnect structure 200 is placed in physical contact with an external connector 126 on the device structure 100 using, for example, a pick and place process. The interconnect structure 200 can be placed so that an exposed area of ​​a topmost wiring layer of a wiring structure (e.g., wiring structure 213) is aligned with a corresponding external connector 126 of the device structure 100. Once in physical contact, a reflow process can be used to bond the external connector 126 of the device structure 100 to the interconnect structure 200. In some embodiments, an external connector formed on the interconnect structure 200 is substituted for the external connector 126 formed on the device structure 100, or an external connector is formed on the interconnect structure 200 in addition to the external connector 126 formed on the device structure 100. In some embodiments, the external connector 126 is not formed on the device structure 100, and the interconnect structure 200 is bonded to the device structure 100 using a direct bonding technique such as a thermocompression bonding technique.

[0049] exist Figure 8 In the embodiment of the present invention, bottom filler 304 is deposited along the sidewalls of interconnect structure 200 and in the gap between interconnect structure 200 and device structure 100. Bottom filler 304 can be, for example, the following materials: molding compound, epoxy resin, bottom filler, molded bottom filler (MUF), resin, etc. Bottom filler 304 can protect external connector 126 and provide structural support for device structure 100. In some embodiments, bottom filler 304 can be cured after deposition. In some embodiments, bottom filler 304 can be thinned after deposition. Thinning can be implemented, for example, using mechanical grinding or CMP process. In some embodiments, bottom filler 304 can be deposited above wiring structure 212, and thinning can expose the topmost wiring layer of wiring structure 212.

[0050] Go to Fig. 9 , peeling off the first carrier substrate 102 so that the first carrier substrate 102 is separated (or "peeled off"). Then, according to some embodiments, the structure is flipped over and bonded to the second carrier substrate 302. In some embodiments, peeling off includes: projecting light such as laser or UV light on the peeling layer on the first carrier substrate 102, so that the peeling layer decomposes under the heat of the light, and the first carrier substrate 102 can be removed. The second carrier substrate 302 can be similar to those described above for the first carrier substrate 102. For example, the second carrier substrate 302 can be similar to Fig.18A The wafer shown in, or similar to Fig.18B A plurality of packages 300 may also be formed using different types of second carrier substrates 302 (see Fig.13). The structure formed on the second carrier substrate 302 may then be singulated to form individual packages 300. A release layer (not shown) may be formed on the second carrier substrate 302 to facilitate connection of the structure to the second carrier substrate 302.

[0051] like Fig. 9 As shown, one side of the interconnect structure 200 is connected to the second carrier substrate 302. After the connection, a planarization process (e.g., a grinding process or a CMP process) can be performed on the device structure 100. The planarization process can remove a portion of the encapsulant 108 and can also remove the remaining portion of the seed layer 104 and / or the solder material 114. In this way, the planarization process can expose the TMV 106 and the conductive connector 112 (or solder material 114) of the interconnect device 110. The following Fig.15A FIG. 1 shows an embodiment in which the solder material 114 is completely removed by a planarization process. Fig. 15B An embodiment in which the solder material 114 is exposed by a planarization process is shown.

[0052] Go to Fig.10 According to some embodiments, RDL 306 and protection layer 308 are formed over the structure. RDL 306 may be, for example, a metallization pattern including wires that electrically connect interconnect device 110 and redistribution structure 120 to external devices, such as Fig.12 306. In some embodiments, RDL 306 may be formed using materials and processes similar to RDL 124A-124G of redistribution structure 120. For example, a seed layer may be formed, and a photoresist may be formed on top of the seed layer and patterned with the desired pattern for RDL 306. The photoresist may be patterned to expose TMV 106 and conductive connector 112 of interconnect device 110. Conductive material may then be formed in the patterned opening of the photoresist using, for example, a plating process. The photoresist may then be removed, and the seed layer may be removed by etching to form RDL 306. In this way, RDL 306 may be electrically connected between TMV 106 and conductive connector 112 of interconnect device 110.

[0053] After forming the RDL 306, a protective layer 308 may be formed over the structure, covering the RDL 306. The protective layer 308 may be formed of one or more suitable dielectric materials, which may be, for example, polybenzoxazole (PBO), polymer materials, polyimide materials, polyimide derivatives, oxides, nitrides, molding compounds, etc., or a combination thereof. The protective layer 308 may be formed by spin coating, lamination, CVD, etc., or a combination thereof. In some embodiments, the protective layer 308 may have a thickness between about 2 μm and about 50 μm.

[0054] Go to Fig.11 According to some embodiments, an under bump metallization (UBM) 310 and an external connector 312 are formed on the structure. The UBM 310 extends through the protective layer 308 and forms an electrical connection with the RDL 306. In some embodiments, the UBM 310 can be formed by, for example, forming an opening in the protective layer 308 and then forming a conductive material of the UBM 310 over the protective layer 308 and within the opening in the protective layer 308. In some embodiments, the opening in the protective layer 308 can be formed by forming a photoresist over the protective layer 308, patterning the photoresist, and etching the protective layer 308 through the patterned photoresist using a suitable etching process (e.g., a wet etching process and / or a dry etching process).

[0055] In some embodiments, UBM310 includes three layers of conductive material, such as a titanium layer, a copper layer, and a nickel layer. Other arrangements of materials and layers, such as an arrangement of chromium / chromium-copper alloy / copper / gold, an arrangement of titanium / titanium tungsten / copper, or an arrangement of copper / nickel / gold, can be used to form UBM310. Any suitable material or material layer that can be used for UBM310 is fully intended to be included within the scope of the present application. The conductive material (e.g., some layers) of UBM310 can be formed using one or more plating processes (e.g., electroplating or chemical plating processes), but other formation processes such as sputtering, evaporation, or PECVD processes can also be used alternatively. Once the conductive material of UBM310 is formed, a portion of the conductive material can be removed by a suitable photolithography mask and etching process to remove unwanted material. The remaining conductive material forms UBM310. In some embodiments, UBM310 can have a pitch between about 20 μm and about 80 μm.

[0056] Still reference Fig.11 According to some embodiments, the external connector 312 is formed above the UBM 310. In some embodiments, the external connector 312 may be a ball grid array (BGA) connector, a solder ball, a controlled collapse chip connection (C4) bump, a micro bump (e.g., a μ bump), a bump formed by chemical nickel-chemical palladium immersion gold technology (ENEPIG), etc. The external connector 312 may include a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or a combination thereof. In some embodiments, the external connector 312 is formed by first forming a solder layer by evaporation, electroplating, printing, solder transfer, solder ball placement, etc. Once the solder layer is formed on the external connector 312, reflow may be performed to form the material into a desired shape.

[0057] Fig.12Connection of semiconductor devices 320A-320C to external connector 312 is shown in accordance with some embodiments. Semiconductor devices 320A-320C are physically and electrically connected to external connector 312 to make electrical connections between semiconductor devices 320A-320C and RDL 306. In this manner, semiconductor devices 320A-320C also make electrical connections to interconnect device 110 and / or TMV 106. Semiconductor devices 320A-320C may be placed on external connector 312 using a suitable process such as a pick and place process.

[0058] In some cases, the semiconductor devices 320A-320C are at least partially connected to each other through the interconnect device 110. By making the interconnect device 110 formed in the layer of the device structure 100 close to the semiconductor devices 320A-320C as described herein, the wiring pitch of the connection between the semiconductor devices 320A-320C can be reduced, which can increase the bandwidth or speed of the electrical signals communicated between the semiconductor devices 320A-320C, thereby improving high-speed operations. In addition, the greater wiring density available in the interconnect device 110 can provide more efficient wiring between the semiconductor devices 320A-C, and in some cases can reduce the number of RDLs used in the redistribution structure 120, or the number of wiring layers used in the interconnect structure 200. In some cases, by connecting the semiconductor devices to the RDL 306 through a relatively thin protective layer 308 (e.g., compared to the insulating layer of the redistribution structure 120, for example), the integrity or stability of the power supplied to the semiconductor devices 320A-320C can be improved.

[0059] Additionally, in some cases, connecting the semiconductor devices 320A-320C to the device structure 100 rather than to an interconnect structure (e.g., interconnect structure 200, an organic core substrate, a substrate with additional wiring, etc.) can reduce warpage, for example, due to coefficient of thermal expansion (CTE) mismatch. Using the interconnect device 110 to interconnect the semiconductor devices 320A-320C rather than using a separate interconnect structure to interconnect the semiconductor devices 320A-320C can allow the semiconductor devices 320A-320C to be directly connected to the device structure 100, which can reduce the overall size of the structure, as well as reduce warpage. The use of the interconnect device 110 can also provide electrical wiring with reduced warpage due to improved CTE matching with the semiconductor devices 320A-320C. This can reduce the risk of contact fatigue issues for electrical connections to the semiconductor devices 320A-320C, particularly for semiconductor devices 320A-320C or packages with larger areas. Reducing warpage may also reduce alignment mismatch when connecting semiconductor devices 320A- 320C.

[0060] According to some embodiments, one or more semiconductor devices 320A-320C may include devices designed for intended purposes, such as memory dies (e.g., DRAM dies, stacked memory dies, high bandwidth memory (HBM) dies, etc.), logic dies, central processing unit (CPU) dies, I / O dies, system on chip (SoC), components on wafer (CoW), integrated fan-out structure (InFO), packages, etc., or combinations thereof. In some embodiments, one or more semiconductor devices 320A-320C include integrated circuit devices, such as transistors, capacitors, inductors, resistors, metallization layers, external connectors, etc., as required by specific functions. Fig.12 The connection of three semiconductor devices is shown, but in other embodiments, one, two, or more than three semiconductor devices may be connected to external connector 312. In some embodiments, the semiconductor devices connected to external connector 312 may include more than one semiconductor device of the same type, or may include two or more semiconductor devices of different types.

[0061] The semiconductor devices 320A-320C may be positioned such that the conductive areas (e.g., contact pads, conductive connectors, solder bumps, etc.) of the semiconductor devices 320A-320C are aligned with the corresponding external connectors 312. Once physically in contact, the external connectors 312 may be bonded to the semiconductor devices 320A-320C using a reflow process. Fig.12 As shown, an underfill 314 may be deposited between each semiconductor device 320A-320C and the protective layer 308. The underfill 314 may also at least partially surround the external connector 312 or the UBM 310. The material of the underfill 314 may be, for example, a molding compound, an epoxy, an underfill, a molded underfill (MUF), a resin, etc., and may be similar to the underfill 304 or the underfill 107 described previously.

[0062] Go to Fig.13 According to some embodiments, the second carrier substrate 302 is peeled off, and the external connector 322 is formed on the interconnect structure 200 to form the package 400. In some embodiments, the peeling includes projecting light such as laser or UV light on the peeling layer on the second carrier substrate 302, so that the peeling layer decomposes under the heat of the light, and the second carrier substrate 302 can be removed. In some embodiments, a plurality of packages 300 are formed on the second carrier substrate 302 and then singulated to form individual packages 300.

[0063] Still reference Fig.13, the external connector 322 can be formed on an exposed portion of the topmost wiring layer of the interconnect structure 200. In some embodiments, the UBM is formed on the interconnect structure 200, and the external connector 322 is formed above the UBM. The external connector 322 can be, for example, a contact bump or a solder ball, but any suitable type of connector can be used. In an embodiment where the external connector 322 is a contact bump, the external connector 322 can include a material such as tin or other suitable materials such as silver, lead-free tin, or copper. In an embodiment where the external connector 322 is a solder bump, the external connector 322 is formed by first forming a solder layer using techniques such as evaporation, electroplating, printing, solder transfer, solder ball placement, etc. Once the solder layer is formed on the structure, reflow can be performed to shape the material into the bump shape required for the external connector 322. In some embodiments, the external connector 322 can be similar to the above description of Figure 6 External connector 126 is depicted. In this manner, package 300 including interconnect device 110 may be formed.

[0064] Go to Fig.14 , an illustrative plan view of package 350 is shown, according to some embodiments. Fig.14 The package 350 shown is an illustrative example and may be similar to Fig.13 For example, the package 350 includes the interconnect device 110 and the semiconductor device 320, which may be similar to Fig.12 For clarity, the semiconductor devices 320A-320C are omitted. Fig.14 Some components of the package 350 shown in FIG. Fig.14 As shown, the interconnect device 110 may be located in a region between adjacent semiconductor devices 320. In this manner, the interconnect device 110 is configured to provide electrical connection between adjacent semiconductor devices 320. Fig.14 The package 350 shown is an illustrative example, and the semiconductor device 320 or the interconnect device 110 may have a different size, shape, arrangement, or configuration than shown, or may be present in a different number than shown.

[0065] Figure 15A-15B An enlarged cross-sectional view of a package 300 is shown, in accordance with some embodiments. Fig.15A and Fig. 15B The area shown in the cross-sectional view is approximately Fig.13 The corresponding marked areas are shown in . Fig.15A The package 300 shown is similar to Fig.13 The package 300 shown in FIG. Fig. 9 The described planarization process removes all solder material 114. Fig.15AAs shown, the RDL 306 is thus formed on the conductive connector 112 of the interconnect device 110 . Fig. 15B The package 300 shown is similar to Fig.13 The package 300 shown is different in that it does not have the Fig. 9 The planarization process described above does not remove the solder material 114, but only exposes the solder material 114 through the planarization process. Fig. 15B As shown, the RDL 306 is thus formed on the solder material 114 of the interconnect device 110 .

[0066] Fig.16 FIG. 4 shows a package 400 including an interconnect device 110 and an electronic device 410 according to some embodiments. The package 400 may be similar to Fig.13 The package 300 shown is different in that, in addition to the interconnect structure 110 , an electronic device 410 is also formed in the device structure 100 . Similar to the interconnect device 110 , the electronic device 410 may be electrically connected to the semiconductor devices 320A- 320C and / or the redistribution structure 120 of the device structure 100 . Fig.16 One electronic device 410 is shown, but in other embodiments, there may be multiple electronic devices 410. The multiple electronic devices may include similar electronic devices 410 and / or different electronic devices 410. Figure 2 The electronic device 410 is formed in the device structure 100 by placing it on the first carrier substrate 102 in a manner similar to the interconnect device 110 described in . The package 400 can then be formed in a manner similar to the package 300 .

[0067] The electronic device 410 can be, for example, a die (e.g., an integrated circuit die, a power integrated circuit die, a logic die, etc.), a chip, a semiconductor device, a memory device (e.g., an SRAM, etc.), a passive device (e.g., an integrated passive device (IPD), a multilayer ceramic capacitor (MLCC), an integrated voltage regulator (IVR), etc.), etc., or a combination thereof. The electronic device 410 can include one or more active devices such as transistors, diodes, etc., and / or one or more passive devices such as capacitors, resistors, inductors, etc. In this way, different electronic devices 410 can be implemented in a package, thereby providing additional functional and characteristic benefits. For example, by combining an IPD or IVR such as a power supply wiring connected to the package 400 with the electronic device 410, the stability of the power supplied to the semiconductor devices 320A-320C can be improved. In some embodiments, the electronic device 410 can also provide additional wiring between the semiconductor devices 320A-320C, similar to the wiring provided by the interconnect device 110.

[0068] Go to Fig.17, an illustrative plan view of package 450 is shown, according to some embodiments. Fig.17 The package Jan450 shown is an illustrative example and may be similar to Fig.16 For example, the package 450 includes the interconnect device 110, the electronic device 410, and the semiconductor device 320, which may be similar to Fig.12 In this manner, the interconnect device 110 may provide additional wiring, and the electronic device 410 may provide additional functionality (eg, as an additional active device and / or passive device). Fig.17 Some features of the package 450 are shown. Fig.17 As shown, the interconnect device 110 may be located in a region between adjacent semiconductor devices 320. The electronic device 410 may be located in a region between adjacent semiconductor devices 320 and / or in other regions, such as a region below the semiconductor device 320. In this way, the design of a package including the electronic device 410 is flexible, for example, the electronic device 410 may be located in a region suitable for its function. Fig.17 The package 450 shown is an illustrative example, and the semiconductor device 320 , the interconnect device 110 , or the electronic device 410 may have a different size, shape, arrangement, or configuration than shown, or may be present in a different number than shown.

[0069] Other features and processes may also be included. For example, a test structure may be included to assist in verification testing of 3D packages or 3DIC devices. The test structure may include, for example, a test pad formed in a redistribution layer or on a substrate, which allows the 3D package or 3DIC to be tested using a probe and / or a probe card, etc. Verification testing may be performed on intermediate structures and final structures. In addition, the structures and methods disclosed herein may be used in conjunction with a test method for intermediate verification of known good dies to increase yield and reduce costs.

[0070] By utilizing the embodiments described herein, the performance of device packaging can be improved, and the reliability of device packaging can be improved. The different features of the embodiments described herein can be combined to achieve these and other benefits. In some cases, the use of interconnect devices to connect semiconductor devices as described above can improve the conductivity and reliability of electrical connections between semiconductor devices, and allow for improved bandwidth during high-speed operations. In some cases, the technology described herein can be implemented in a process flow together with other typical manufacturing processes, so only a small cost or no additional cost is added relative to existing processes. In addition, the use of the described process technology can increase yield and improve connection reliability, particularly for packages with larger areas. For example, the process technology described herein can reduce warpage. In some cases, in addition to interconnect devices that can provide additional functions, electronic devices can also be incorporated in packages. For example, electronic devices including IPDs or IVRs can improve the power integrity of packages.

[0071] In some embodiments, a method includes: placing an interconnect device on a first carrier, wherein the interconnect device includes a first conductive connector and a second conductive connector; forming a first via and a second via on the first carrier; forming a redistribution structure over the interconnect device, the first via, and the second via, wherein a first side of the redistribution structure is connected to the first via and the second via; connecting the interconnect structure to a second side of the redistribution structure, wherein the interconnect structure includes an organic substrate and a wiring layer; connecting the interconnect structure to a second carrier; connecting a first semiconductor die to the first conductive connector and the first via of the interconnect device; and connecting a second semiconductor die to the second conductive connector and the second via of the interconnect device, wherein the second semiconductor die is electrically connected to the first semiconductor die through the interconnect device. In one embodiment, the method includes: forming a mold compound over the first carrier, the mold compound surrounding the interconnect device, the first via, and the second via. In one embodiment, the method includes: placing an integrated voltage regulator (IVR) die on the first carrier, and including connecting the first semiconductor die to the IVR. In one embodiment, the method includes: forming a seed layer on the first carrier, and performing a reflow process to bond the first conductive connector and the second conductive connector to the seed layer. In one embodiment, the first semiconductor die extends over the interconnect device and the second semiconductor die extends over the interconnect device. In one embodiment, the method includes: forming an underfill between the interconnect device and the first carrier. In one embodiment, forming a redistribution structure includes: forming a mold compound layer and a redistribution layer extending through the mold compound layer. In one embodiment, the method includes: forming a metallization pattern over the interconnect device, the first via, and the second via, wherein the metallization pattern is located between the first semiconductor die and the interconnect device. In one embodiment, the method includes: forming a protective layer over the metallization pattern. In one embodiment, the method includes: forming an external connector extending through the protective layer and contacting the metallization pattern, wherein the first semiconductor die is electrically connected to the external connector.

[0072] In one embodiment, a device includes: an interconnect device connected to a redistribution structure, wherein the interconnect device includes a conductive wiring connected to a conductive connector disposed on a first side of the interconnect device; a molding material at least laterally surrounding the interconnect device; a metallization pattern located above the molding material and the first side of the interconnect device, wherein the metallization pattern is electrically connected to the conductive connector; a first external connector connected to the metallization pattern; and a semiconductor device connected to the first external connector. In one embodiment, the conductive wiring of the interconnect device has a pitch of less than 1 μm. In one embodiment, the device includes: an integrated passive device (IPD) connected to the redistribution structure, and the molding material at least laterally surrounding the IPD. In one embodiment, the device includes: a second external connector located on the redistribution structure; and an interconnect structure connected to the second external connector. In one embodiment, the device includes: an underfill extending between the redistribution structure and the interconnect structure. In one embodiment, the device includes: an insulating layer located above the metallization pattern, wherein the first external connector extends through the insulating layer.

[0073] In one embodiment, a package includes: a redistribution structure, the redistribution structure including an insulating layer and a redistribution layer; a first mold compound layer located on the redistribution structure; a via located in the first mold compound layer; an interconnect device located in the first mold compound layer, wherein each interconnect device includes a contact; a dielectric layer covering the first mold compound layer, the via, and the interconnect device; and a semiconductor device located above the dielectric layer, wherein the semiconductor device is electrically connected to the via through the dielectric layer and is electrically connected to the contact of the interconnect device through the dielectric layer, wherein at least two semiconductor devices of the semiconductor devices are electrically connected through at least one of the interconnect devices. In one embodiment, the package includes: an interconnect structure electrically connected to the redistribution structure, the interconnect structure including: a wiring structure formed above a substrate; and an underfill material extending between the redistribution structure and the interconnect structure. In one embodiment, the package includes an integrated passive device (IPD) located in the first mold compound layer, wherein the IPD is electrically connected to at least one semiconductor device of the semiconductor devices. In one embodiment, the insulating layer in the insulating layer of the redistribution structure includes a second mold compound layer.

[0074] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as the present disclosure. Those skilled in the art should also be aware that such equivalent structures do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and modifications can be made without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a semiconductor device, comprising: placing an interconnect device on a first carrier, wherein the interconnect device comprises a first conductive connector and a second conductive connector; forming a first via hole and a second via hole on the first carrier; forming a redistribution structure over the interconnect device, the first via, and the second via, wherein a first side of the redistribution structure is connected to the first via and the second via; connecting an interconnect structure to a second side of the redistribution structure, wherein the interconnect structure comprises an organic substrate and a plurality of wiring layers; connecting the interconnect structure to a second carrier; connecting a first semiconductor die to the first conductive connector and the first via of the interconnect device; and A second semiconductor die is connected to the second conductive connector and the second via of the interconnect device, wherein the second semiconductor die is electrically connected to the first semiconductor die through the interconnect device.

2. The method according to claim 1, further comprising: A molding compound is formed over the first carrier, the molding compound surrounding the interconnect device, the first via, and the second via.

3. The method according to claim 1, further comprising: An integrated voltage regulator (IVR) die is placed on the first carrier and further comprising connecting the first semiconductor die to the integrated voltage regulator.

4. The method according to claim 1, further comprising: A seed layer is formed on the first carrier, and a reflow process is performed to bond the first conductive connector and the second conductive connector to the seed layer.

5. The method according to claim 1, wherein: The first semiconductor die extends over the interconnect device, and wherein the second semiconductor die extends over the interconnect device.

6. The method according to claim 1, further comprising: An underfill is formed between the interconnect device and the first carrier.

7. The method according to claim 1, wherein: Forming the redistribution structure includes forming a mold compound layer and a redistribution layer extending through the mold compound layer.

8. The method according to claim 1, further comprising: A metallization pattern is formed over the interconnect device, the first via, and the second via, wherein the metallization pattern is located between the first semiconductor die and the interconnect device.

9. The method according to claim 8, further comprising: A protection layer is formed over the metallization pattern.

10. The method according to claim 9, further comprising: An external connector is formed extending through the protection layer and contacting the metallization pattern, wherein the first semiconductor die is electrically connected to the external connector.

11. A semiconductor device comprising: an interconnect device connected to the redistribution structure, wherein the interconnect device includes conductive routing connected to a plurality of conductive connectors disposed on a first side of the interconnect device; a molding material at least laterally surrounding the interconnect device, wherein a surface of the molding material is flush with a second side of the interconnect device; a metallization pattern over the molding material and the first side of the interconnect device, wherein the metallization pattern is electrically connected to the plurality of conductive connectors; a plurality of first external connectors connected to the metallization pattern; and A plurality of semiconductor devices are connected to the plurality of first external connectors.

12. The device according to claim 11, wherein The conductive wiring of the interconnect device has a pitch less than 1 μm.

13. The device according to claim 11, further comprising: An integrated passive device is connected to the redistribution structure, and the molding material at least laterally surrounds the integrated passive device.

14. The device according to claim 11, further comprising: a second external connector located on the redistribution structure; and an interconnect structure connected to the second external connector.

15. The device according to claim 14, further comprising: An underfill extends between the redistribution structure and the interconnect structure.

16. The device according to claim 11, further comprising: An insulating layer is located above the metallization pattern, wherein the plurality of first external connectors extend through the insulating layer.

17. A package comprising: A redistribution structure comprising a plurality of insulating layers and a plurality of redistribution layers; a first molding compound layer on the redistribution structure, wherein the first molding compound layer is in physical contact with the redistribution structure; a plurality of vias located within the first molding compound layer; a plurality of interconnect devices disposed within the first molding compound layer, wherein each interconnect device comprises a plurality of contacts; a dielectric layer covering the first molding compound layer, the vias, and the plurality of interconnect devices; and A plurality of semiconductor devices are located above the dielectric layer, wherein the plurality of semiconductor devices are electrically connected to the vias through the dielectric layer and are electrically connected to the plurality of contacts of the plurality of interconnect devices through the dielectric layer, wherein at least two semiconductor devices of the plurality of semiconductor devices are electrically connected through at least one interconnect device of the plurality of interconnect devices.

18. The package of claim 17, further comprising: An interconnect structure is electrically connected to the redistribution structure, the interconnect structure comprising: a wiring structure formed over a substrate; and an underfill material extending between the redistribution structure and the interconnect structure.

19. The package of claim 17, further comprising: An integrated passive device is located within the first molding compound layer, wherein the integrated passive device is electrically connected to at least one semiconductor device of the plurality of semiconductor devices.

20. The package according to claim 17, wherein: An insulating layer of the plurality of insulating layers of the redistribution structure includes a second mold compound layer.

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