Method for manufacturing semiconductor device

Abstract

The present disclosure relates to a method for manufacturing a semiconductor device. A method for forming a gas spacer in a semiconductor device and a semiconductor device including the gas spacer are disclosed. According to one embodiment, the method includes forming a gate stack above a substrate; forming a first gate spacer on a sidewall of the gate stack; forming a second gate spacer on a sidewall of the first gate spacer; removing the second gate spacer using an etching process to form a first opening, the etching process being performed at a temperature less than 0°C and using an etching solution containing hydrogen fluoride; and depositing a dielectric layer over the first gate spacer and the gate stack, the dielectric layer sealing the gas spacer in the first opening.

Description

Technical Field

[0001] The present disclosure relates to semiconductor manufacturing technology, and more particularly to a method for manufacturing a semiconductor device. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconducting layers onto a semiconductor substrate. These layers are then patterned using lithography to form circuit components and elements on the semiconductor substrate.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that should be addressed. Summary of the Invention

[0004] According to some embodiments, a method for manufacturing a semiconductor device is provided. The method includes forming a gate stack over a substrate; forming a first gate spacer on a sidewall of the gate stack; forming a second gate spacer on a sidewall of the first gate spacer; removing the second gate spacer using an etching process to form a first opening, wherein the etching process is performed at a temperature less than 0° C. and wherein the etching process uses an etching solution containing hydrogen fluoride; and depositing a dielectric layer over the first gate spacer and the gate stack, the dielectric layer sealing a gas spacer in the first opening.

[0005] According to other embodiments, a method for manufacturing a semiconductor device is provided. The method includes forming a gate stack above a semiconductor substrate; forming a first gate spacer on a sidewall of the gate stack; forming a second gate spacer on the sidewall of the first gate spacer; epitaxially growing source / drain regions on both sides of the gate stack; removing the second gate spacer using an etching process, wherein the removal of the second gate spacer forms a first opening; during the etching process, forming a solid etching film on surfaces of the gate stack, the first gate spacer, and the source / drain regions, and forming a liquid etching film on a surface of the second gate spacer; and depositing a first dielectric layer to seal the first opening and define a gas spacer on the sidewall of the first gate spacer.

[0006] According to other embodiments, a method for manufacturing a semiconductor device is provided. The method includes forming a dummy gate above a semiconductor substrate; depositing a first spacer above the dummy gate; depositing a second spacer above the first spacer; depositing a third spacer above the second spacer; patterning the first spacer, the second spacer, and the third spacer to form a first gate spacer, a second gate spacer, and a third gate spacer, respectively; epitaxially growing a source / drain region on both sides of the dummy gate adjacent to the third gate spacer; replacing the dummy gate with a metal gate; and after replacing the dummy gate, removing the second gate spacer and the third gate spacer using an etching process at a temperature below 0°C, wherein the removal of the second gate spacer and the third gate spacer forms a void, and the void exposes the surface of the first gate spacer and the source / drain region. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The following detailed description, in conjunction with the accompanying drawings, will provide a better understanding of the embodiments of the present disclosure. It should be emphasized that, in accordance with standard industry practice, many components are not drawn to scale. In fact, the dimensions of various components may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 An example of a FinFET is illustrated in three-dimensional schematic form according to some embodiments.

[0009] Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 、 Figures 8A to 8D 、 Figures 9A to 9D 、 Figures 10A to 10D 、 Figures 11A to 11E 、 Figures 12A to 12D 、 Figures 13A to 13D 、 Figures 14A to 14D 、 Figures 15A to 15E 、 Figures 16A to 16D 、 Figures 17A to 17D 、 Figures 18A to 18E 、 Figures 19A to 19D 、 Figures 20A to 20D and Figures 21A to 21D is a schematic cross-sectional view of an intermediate stage during the fabrication of a FinFET according to some embodiments.

[0010] The description of the accompanying drawings is as follows:

[0011] 50: Base

[0012] 50N, 50P: Area

[0013] 51: Divider

[0014] 52: Fins

[0015] 54: Insulation material

[0016] 56: Shallow Trench Isolation

[0017] 58: Channel Area

[0018] 60: Virtual dielectric layer

[0019] 62: Dummy gate layer

[0020] 64: Mask layer

[0021] 72: Dummy gate

[0022] 74: Mask

[0023] 80: First gate spacer

[0024] 82: Second gate spacer

[0025] 84: Third gate spacer

[0026] 92: Epitaxial source / drain region

[0027] 93: Gap

[0028] 94: First contact etch stop layer

[0029] 96: First interlayer dielectric

[0030] 98: Hard Mask

[0031] 100: Groove

[0032] 101: Area

[0033] 102: Gate dielectric layer

[0034] 104: Gate electrode

[0035] 104A: Lining

[0036] 104B: Work function adjustment layer

[0037] 104C: Filling material

[0038] 106: Solid state etching film

[0039] 108: Liquid etching film

[0040] 110: Gas spacer

[0041] 112: First dielectric layer

[0042] 114: Gate mask

[0043] 116: Second interlayer dielectric

[0044] 118: Gate contact

[0045] 120: Source / drain contacts

[0046] A-A', B-B', C-C', D-D', E-E': Section

[0047] H1: Height

[0048] W1: width DETAILED DESCRIPTION

[0049] The following content provides many different embodiments or examples for implementing different components of the embodiments of the present disclosure. Specific examples of components and configurations are described below to simplify the embodiments of the present disclosure. Of course, these are merely examples and are not intended to limit the embodiments of the present disclosure. For example, if the description refers to a first component being formed on or above a second component, it may include an embodiment in which the first component and the second component are in direct contact, and it may also include an embodiment in which an additional component is formed between the first component and the second component so that the first component and the second component are not in direct contact. In addition, the embodiments of the present disclosure may reuse reference numbers and / or letters in different examples. This repetition is for the purpose of simplicity and clarity and does not represent a specific relationship between the different embodiments and / or configurations discussed.

[0050] In addition, spatially relative terms may be used herein, such as "under," "beneath," "below," "above," "upper," and similar terms. These spatially relative terms are intended to facilitate describing the relationship between one element or component and another element or component as shown in the figures. These spatially relative terms encompass different orientations of the device in use or operation, as well as the orientations depicted in the figures. When the device is rotated in a different orientation (rotated 90 degrees or other orientations), the spatially relative adjectives used herein will also be interpreted based on the rotated orientation.

[0051] Various embodiments provide improved processes for forming gas spacers in semiconductor devices. For example, an etching process at a temperature of less than 0°C can be used to remove various dummy gate spacers. The etching process can use an etchant such as hydrogen fluoride and a catalyst such as water, ethanol, or a similar material. Performing the etching process at a temperature of less than 0°C can improve the etch selectivity of the etching process relative to structures that are not desired to be etched by the etching process. This reduces device defects and improves the performance of the completed semiconductor device formed by the improved process.

[0052] Figure 1An example of a fin field-effect transistor is illustrated in a three-dimensional schematic diagram according to some embodiments. The fin field-effect transistor includes a fin 52 on a substrate 50 (e.g., a semiconductor substrate). Shallow trench isolation (STI) regions 56 are disposed in the substrate 50, and the fin 52 protrudes from between adjacent shallow trench isolation regions 56 and protrudes above the shallow trench isolation regions 56. Although the shallow trench isolation regions 56 are described / illustrated as being separated from the substrate 50, as used herein, the term "substrate" may refer only to a semiconductor substrate or a semiconductor substrate including an isolation region. In addition, although the fin 52 is illustrated as a single, continuous material of the substrate 50, the fin 52 and / or the substrate 50 may include a single material or multiple materials. In this document, the fin 52 refers to the portion extending between adjacent isolation regions 56.

[0053] A gate dielectric layer 102 is formed along the sidewalls of the fin 52 and over the top surface of the fin 52, and a gate electrode 104 is formed over the gate dielectric layer 102. Epitaxial source / drain regions 92 are disposed on either side of the fin 52 relative to the gate dielectric layer 102 and the gate electrode 104. Figure 1 Reference cross sections used in subsequent figures are further illustrated. Cross section AA' is along the longitudinal axis of one of the gate electrodes 104 and is oriented, for example, perpendicular to the direction of current flow between the epitaxial source / drain regions 92 of the FinFET. Cross section BB' is perpendicular to cross section AA' and along the longitudinal axis of one of the fins 52 and is oriented, for example, in the direction of current flow between the epitaxial source / drain regions 92 of the FinFET. Cross section CC' is parallel to cross section AA' and extends through the epitaxial source / drain regions 92 of the FinFET. Cross section DD' is parallel to cross section BB' and extends through the gate electrode 104 of the FinFET. Cross section EE' is perpendicular to cross sections AA', BB', CC', and DD', is parallel to the major surface of substrate 50, and extends through fin 52 and gate electrode 104. For clarity, subsequent figures refer to these reference cross sections.

[0054] Some embodiments discussed herein are discussed in the context of FinFETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Furthermore, some embodiments contemplate use in planar devices, such as planar FETs.

[0055] Figures 2 to 21D is a schematic cross-sectional view of an intermediate stage during the fabrication of a FinFET according to some embodiments. Figures 2 to 7 Draw Figure 1 Reference cross section AA' is shown, except for multiple fins / FinFETs. Figure 8A 、 Figure 9A、 Figure 10A 、 Figure 11A 、 Figure 12A 、 Figure 13A 、 Figure 14A 、 Figure 15A 、 Figure 16A 、 Figure 17A 、 Figure 18A 、 Figure 19A 、 Figure 20A and Figure 21A It is along Figure 1 The reference cross section AA' is shown. Figure 8B 、 Figure 9B 、 Figure 10B 、 Figure 11B 、 Figure 12B 、 Figure 13B 、 Figure 14B 、 Figure 15B 、 Figure 15E 、 Figure 16B 、 Figure 17B 、 Figure 18B 、 Figure 19B 、 Figure 20B and Figure 21B It is along Figure 1 The reference cross section BB' is shown. Figure 8C 、 Figure 9C 、 Figure 10C 、 Figure 11C 、 Figure 11E 、 Figure 12C 、 Figure 13C 、 Figure 14C 、 Figure 15C 、 Figure 16C 、 Figure 17C 、 Figure 18C 、 Figure 19C 、 Figure 20C and Figure 21C It is along Figure 1 The reference cross section CC' is shown. Figure 8D 、 Figure 9D 、 Figure 10D 、 Figure 11D 、 Figure 12D 、 Figure 13D 、 Figure 14D 、 Figure 15D 、 Figure 16D 、 Figure 17D 、 Figure 18D 、 Figure 19D 、 Figure 20D and Figure 21D It is along Figure 1 The reference cross section DD' is shown. Figure 18E It is along Figure 1 The reference cross section EE' is shown.

[0056] exist Figure 2In the embodiment of the present invention, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Generally speaking, a semiconductor-on-insulator substrate is a layer of semiconductor material formed on an insulating layer. For example, the insulating layer may be a buried oxide (BOX) layer, a silicon oxide layer, or a similar film layer. The insulating layer is provided on a substrate, which is typically a silicon or glass substrate. Other substrates, such as multilayer or graded substrates, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination of the foregoing.

[0057] Substrate 50 has a region 50N and a region 50P. Region 50N can be used to form an n-type device, such as an N-type metal oxide semiconductor (NMOS) transistor, such as an n-type FinFET. Region 50P can be used to form a p-type device, such as a P-type metal oxide semiconductor (PMOS) transistor, such as a p-type FinFET. Region 50N can be physically separated from region 50P (illustrated by separator 51), and any number of device components (such as other active devices, doped regions, isolation structures, etc.) can be disposed between region 50N and region 50P.

[0058] exist Figure 3 In the embodiment, fins 52 are formed in substrate 50. Fins 52 are semiconductor strips. In some embodiments, fins 52 can be formed in substrate 50 by etching trenches in substrate 50. The etching process can be any suitable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), similar etching processes, or a combination thereof. The etching process can be anisotropic. Figure 3 As shown, substrate 50 may include pairs of fins 52. The fins 52 in each pair of fins 52 may be separated by a distance of about 48 nm to about 56 nm, and a pair of fins 52 may be separated from an adjacent pair of fins 52 by a distance of about 48 nm to about 56 nm.

[0059] The fins 52 can be patterned by any suitable method. For example, the patterning of the fins 52 can use one or more photolithography processes, including double patterning or multiple patterning processes. In general, double patterning or multiple patterning processes combine photolithography and self-alignment processes to allow the production of patterns with, for example, pitches that are smaller than the pitch of patterns that can be obtained using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed above the substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins 52.

[0060] exist Figure 4 In the embodiment shown, insulating material 54 is formed over substrate 50 and between adjacent fins 52. Insulating material 54 can be an oxide, such as silicon oxide, nitride, a similar material, or a combination thereof, and can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition (FCVD) (e.g., chemical vapor deposition (CVD)-based material deposition in a remote plasma system followed by post-curing to convert it to another material, such as an oxide), a similar method, or a combination thereof. Other insulating materials formed by any suitable method can be used. In the illustrated embodiment, insulating material 54 is silicon oxide formed by a flowable chemical vapor deposition process. Once insulating material 54 is formed, an annealing process can be performed. In one embodiment, insulating material 54 is formed such that excess insulating material 54 covers fins 52. Although insulating material 54 is illustrated as a single layer, some embodiments may utilize a multilayer structure. For example, in some embodiments, a liner (not shown) may be formed along the surfaces of the substrate 50 and the fins 52. Thereafter, a filling material, such as those described above, may be formed over the liner.

[0061] exist Figure 5In the process, a removal process is applied to the insulating material 54 to remove excess insulating material 54 above the fin 52. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch back process, a combination thereof, or the like may be used. The planarization process exposes the fin 52 so that after the planarization process is completed, the top surface of the insulating material 54 and the fin 52 are flush.

[0062] exist Figure 6 In the embodiment of the present invention, the insulating material 54 is etched back to form shallow trench isolation regions 56. The insulating material 54 is etched back so that the upper portions of the fins 52 in regions 50N and 50P protrude from between adjacent shallow trench isolation regions 56. In addition, the top surface of the shallow trench isolation region 56 may have a flat surface, a convex surface, a concave surface (e.g., dishing) as shown in the figure, or a combination thereof. The top surface of the shallow trench isolation region 56 may be formed to be flat, convex, and / or concave by appropriate etching. The etching of the shallow trench isolation region 56 may use a suitable etching process, such as an etching process that is selective to the material of the insulating material 54 (e.g., etches the material of the insulating material 54 at a faster rate than the material of the fin 52). For example, the chemical oxide is removed by a suitable etching process, such as the etching process that may use dilute hydrofluoric acid (dHF).

[0063] The process described above is only one example of how the fin 52 may be formed. In some embodiments, the fin may be formed by an epitaxial growth process. For example, a dielectric layer may be formed over the top surface of the substrate 50, and a trench may be etched through the dielectric layer to expose the substrate 50 below. A homoepitaxial structure may be epitaxially grown in the trench, and the dielectric layer may be recessed so that the homoepitaxial structure protrudes from the dielectric layer to form the fin 52. Additionally, in some embodiments, a heteroepitaxial structure may be used for the fin 52. For example, a heteroepitaxial structure may be recessed. Figure 5fins 52 in the substrate 50, and a material different from the fins 52 can be epitaxially grown over the etched fins 52. In such an embodiment, the fins 52 include the etched material and the epitaxially grown material disposed over the etched material. In another embodiment, a dielectric layer can be formed over the top surface of the substrate 50, and trenches can be etched through the dielectric layer. A heteroepitaxial structure can then be epitaxially grown in the trench using a material different from the substrate 50, and the dielectric layer can be etched back such that the heteroepitaxial structure protrudes from the dielectric layer to form the fins 52. In some embodiments of epitaxially grown homoepitaxial or heteroepitaxial structures, the epitaxially grown material can be doped in situ during growth, which can obviate previous and subsequent implantations, although in situ and implantation doping can be used together.

[0064] Furthermore, it may be advantageous to epitaxially grow a different material in region 50N (eg, NMOS region) than in region 50P (eg, PMOS region). In various embodiments, the upper portion of fin 52 may be made of silicon germanium (SiGe). x Ge 1-x , where x can range from 0 to 1), silicon carbide, pure or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, or similar materials. For example, usable materials for forming III-V compound semiconductors include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and similar materials.

[0065] Further in Figure 6 In the embodiment of the present invention, appropriate wells (not separately shown) may be formed in the fin 52 and / or the substrate 50. In some embodiments, a P-well may be formed in the region 50N, and an N-well may be formed in the region 50P. In some embodiments, either a P-well or an N-well may be formed in both the region 50N and the region 50P.

[0066] In embodiments with different well types, photoresist or other masks (not separately shown) may be used to implement different implantation steps for regions 50N and 50P. For example, a photoresist may be formed over shallow trench isolation regions 56 and fins 52 in region 50N. The photoresist is patterned to expose regions 50P of substrate 50, such as the PMOS region. The photoresist may be formed using a spin-on technique, and the photoresist may be patterned using suitable optical lithography techniques. Once the photoresist is patterned, an n-type impurity implant is performed in region 50P, and the photoresist may act as a mask to substantially prevent the n-type impurity from being implanted into region 50N, such as the NMOS region. The n-type impurity may be phosphorus, arsenic, or a similar impurity, implanted into the region at a concentration equal to or less than 10 18cm -3 , for example about 10 17 cm -3 to about 10 18 cm -3 After implantation, the photoresist may be removed, for example by a suitable ashing process.

[0067] After the region 50P is implanted, a photoresist is formed over the shallow trench isolation region 56 and the fin 52 in the region 50P. The photoresist is patterned to expose a region 50N of the substrate 50, such as the NMOS region. The photoresist can be formed by using a spin coating technique, and can be patterned using a suitable optical lithography technique. Once the photoresist is patterned, a p-type impurity implant can be performed in the region 50N, and the photoresist can act as a mask to substantially prevent the p-type impurity from being implanted into the region 50P, such as the PMOS region. The p-type impurity can be boron, BF2, or a similar impurity, and the concentration implanted into the region is equal to or less than 10 18 cm -3 , for example about 10 17 cm -3 to about 10 18 cm -3 After implantation, the photoresist may be removed, for example by a suitable ashing process.

[0068] After implanting regions 50N and 50P, an anneal may be performed to activate the implanted p-type and / or n-type impurities. In some embodiments, the growing material of the epitaxial fins may be doped in situ during growth, which may eliminate implantation, although both in situ and implantation doping may be used together.

[0069] exist Figure 7In the embodiment of the present invention, a dummy dielectric layer 60 is formed on the fin 52. The dummy dielectric layer 60 can be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and can be deposited or thermally grown according to a suitable technique. A dummy gate layer 62 is formed above the dummy dielectric layer 60, and a mask layer 64 is formed above the dummy gate layer 62. The dummy gate layer 62 can be deposited above the dummy dielectric layer 60, and then planarized, for example, by chemical mechanical polishing. The mask layer 64 can be deposited above the dummy gate layer 62. The dummy gate layer 62 can be a conductive material and can be selected from the group consisting of amorphous silicon, polysilicon, polycrystalline silicon germanium (poly-SiGe), metal nitride, metal silicide, metal oxide, and metal. The dummy gate layer 62 can be deposited by physical vapor deposition (PVD), chemical vapor deposition, sputtering, or other techniques known in the art for depositing conductive materials. Dummy gate layer 62 can be formed from other materials that have high etch selectivity to the isolation regions. Mask layer 64 can include, for example, SiN, SiON, or similar materials. In this example, a single dummy gate layer 62 and a single mask layer 64 are formed across region 50N and region 50P. It should be noted that dummy dielectric layer 60 is shown covering only fin 52 for illustrative purposes only. In some embodiments, dummy dielectric layer 60 can be deposited so that it covers shallow trench isolation region 56 and extends between dummy gate layer 62 and shallow trench isolation region 56.

[0070] Figures 8A to 21D Various additional steps in the fabrication of example devices are depicted. Figures 8A to 21D Components in any one of the regions 50N and 50P are shown. For example, Figures 8A to 21D The illustrated structure may be applicable to both region 50N and region 50P. Differences in the structures of region 50N and region 50P, if any, are described in the text accompanying each figure.

[0071] exist Figures 8A to 8D In the embodiment, the mask layer 64 (see Figure 7) is patterned to form a mask 74. The pattern of the mask 74 can then be transferred to the dummy gate layer 62 to form a dummy gate 72. The pattern of the mask 74 can also be transferred to the dummy dielectric layer 60 by a suitable etching technique. The dummy gate 72 covers each channel region 58 of the fin 52. The pattern of the mask 74 can be used to physically separate each dummy gate 72 from an adjacent dummy gate. The length direction of the dummy gate 72 can also be substantially perpendicular to the length direction of the corresponding epitaxial fin 52. The combination of the dummy gate 72, the mask 74 and the dummy dielectric layer 60 can be referred to as a dummy gate stack 76. The dummy gate stack 76 can be separated from the adjacent dummy gate stack by a distance of about 80 nm to about 100 nm.

[0072] exist Figures 9A to 9D , a first gate spacer 80, a second gate spacer 82, and a third gate spacer 84 are formed on the exposed surface of the dummy gate stack 76 and / or the fin 52. The first gate spacer 80 may be formed by a conformal deposition process, such as atomic layer deposition (ALD), chemical vapor deposition, or a similar process. The first gate spacer 80 may include an insulating material, such as silicon carbide, silicon oxynitride, a multilayer or combination thereof, or a similar material. The thickness of the first gate spacer 80 may be from about 3 nm to about 7 nm, such as about 5 nm. Forming the first gate spacer 80 to a thickness outside the specified range may affect the semiconductor characteristics of the complete NSFET, such as capacitance, channel resistance, and epitaxial source / drain regions (e.g., as described below with reference to FIG. Figures 11A to 11E The dimensions of the epitaxial source / drain regions 92 are discussed.

[0073] The second gate spacer 82 may be formed over the first gate spacer 80 by a conformal deposition process, such as atomic layer deposition, chemical vapor deposition, or the like. The second gate spacer 82 may comprise an insulating material, such as silicon oxide, silicon nitride, silicon oxycarbon nitride, multiple layers or combinations thereof, or the like. The thickness of the second gate spacer 82 may be from about 2 nm to about 6 nm, such as about 4 nm. Forming the second gate spacer 82 to a thickness outside of the specified range may affect the semiconductor properties of the complete NSFET, such as capacitance, channel resistance, and epitaxial source / drain regions (e.g., as described below with reference to FIG. 1 ). Figures 11A to 11E The dimensions of the epitaxial source / drain regions 92 are discussed.

[0074] The third gate spacer 84 may be formed over the second gate spacer 82 by a conformal deposition process, such as atomic layer deposition, chemical vapor deposition, or the like. The third gate spacer 84 may comprise an insulating material, such as silicon nitride, silicon oxide, silicon oxycarbon nitride, multiple layers or combinations thereof, or the like. The thickness of the third gate spacer 84 may be from about 2 nm to about 5 nm, such as about 4 nm. Forming the third gate spacer 84 to a thickness outside of the specified range may affect the semiconductor characteristics of the complete NSFET, such as capacitance, channel resistance, and epitaxial source / drain regions (e.g., as described below with reference to FIG. 1 ). Figures 11A to 11E The dimensions of the epitaxial source / drain regions 92 are discussed.

[0075] The first gate spacer 80 may be formed of a material having an etch selectivity different from that of the second gate spacer 82 and the third gate spacer 84. In this way, the second gate spacer 82 and the third gate spacer 84 may be removed without removing the first gate spacer 80. The second gate spacer 82 and the third gate spacer 84 may be formed of the same or different materials and may have the same or different etch selectivities. Figures 10A to 10D During the discussion), the first gate spacer 80 and the second gate spacer 82 can be used to shield a portion of the substrate 50. The third gate spacer 84 can be used to control the epitaxial source / drain regions (e.g., as described below). Figures 11A to 11E The growth of epitaxial source / drain regions 92) is discussed.

[0076] exist Figures 10A to 10D In the process, the first gate spacer 80, the second gate spacer 82 and the third gate spacer 84 are etched. The etching of the first gate spacer 80, the second gate spacer 82 and the third gate spacer 84 can be carried out by an anisotropic etching process, an isotropic etching process or any combination of anisotropic and isotropic etching processes. Figures 10B to 10D As shown, remaining portions of the first gate spacer 80 , the second gate spacer 82 , and the third gate spacer 84 may remain adjacent to the fin 52 and adjacent to the dummy gate stack 76 .

[0077] Specifically, in Figure 10A In the embodiment, the first gate spacer 80, the second gate spacer 82 and the third gate spacer 84 are removed from the top surface of the mask 74. Figure 10B In the embodiment, the third gate spacer 84 is removed from the top surface of the fin 52 and the surface and sidewalls of the dummy gate stack 76. Figure 10B In , the second gate spacer 82 and the first gate spacer 80 are removed from the top surface of the dummy gate stack 76 and the fin 52 , and the second gate spacer 82 and the first gate spacer 80 remain on the sidewalls of the dummy gate stack 76 . Figure 10C In the embodiment, the third gate spacer 84 is removed from the top surface and outer sidewalls of the pair of fins 52 and the top surface of the shallow trench isolation region 56 outside the pair of fins 52. Figure 10C In FIG, the third gate spacer 84 remains on the inner sidewalls of the pair of fins 52 and extends continuously between adjacent fins 52 above the shallow trench isolation region 56. The second gate spacer 82 and the first gate spacer 80 are removed from the top surface and upper portion of the sidewalls of the fin 52 and the top surface of the shallow trench isolation region 56 outside the pair of fins 52. Figure 10C In FIG, the first gate spacer 80 and the second gate spacer 82 remain on the lower portion of the sidewalls of the fin 52 and extend continuously between adjacent fins 52 above the shallow trench isolation region 56. Figure 10D , the third gate spacer 84 is removed from the top surface and upper portions of the sidewalls of the dummy gate stack 76, and the third gate spacer 84 remains on the lower portions of the sidewalls of the dummy gate stack 76 and continuously extends between adjacent dummy gate stacks 76 above the shallow trench isolation region 56. Figure 10D , the first gate spacer 80 and the second gate spacer 82 are removed from the top surface of the dummy gate stack 76, and the first gate spacer 80 and the second gate spacer 82 remain on the sidewalls of the dummy gate stack and extend continuously between adjacent dummy gate stacks 76 above the shallow trench isolation region 56.

[0078] After etching the first gate spacer 80, the second gate spacer 82, and the third gate spacer 84, the remaining portion of the third gate spacer 84 can be used to control the epitaxial source / drain regions (e.g., as described below with reference to FIG. Figures 11A to 11E As discussed above, the epitaxial growth of the epitaxial source / drain region 92 can be patterned according to the desired shape of the epitaxial source / drain region 92. Figure 10C As shown, the portions of the first and second gate spacers 80, 82 disposed on the inner sidewalls of the fins 52 can be greater in height than the portions of the first and second gate spacers 80, 82 disposed on the outer sidewalls of the fins 52. This height difference is caused by the third gate spacer 84 protecting the second and first gate spacers 82, 80, and the fact that the fins 52 shield the areas between the fins 52. Etchant can flow more easily around the portions of the second and first gate spacers 82, 80 outside the fins 52 than around the portions disposed within the fins 52. The first, second, and third gate spacers 80, 82, 84 can be formed and etched in any desired order. For example, in one embodiment, the first gate spacer 80 can be formed and etched before the second and third gate spacers 82, 84 are formed.

[0079] The implantation for lightly doped source / drain (LDD) regions (not shown separately) can be performed at any time during the formation and etching of the first gate spacer 80, the second gate spacer 82, and the third gate spacer 84. For example, in some embodiments, the lightly doped source / drain regions can be implanted after the first gate spacer 80 is formed and before the second gate spacer 82 and the third gate spacer 84 are formed. In embodiments with different device types, similar to the above, the implantation of the lightly doped source / drain regions can be performed after the first gate spacer 80 is formed and before the second gate spacer 82 and the third gate spacer 84 are formed. Figure 6 In the implantation discussed above, a mask, such as a photoresist, may be formed over region 50N while exposing region 50P, and an appropriate type (e.g., p-type) impurity may be implanted into the exposed fin 52 in region 50P. The mask may then be removed. Subsequently, a mask, such as a photoresist, may be formed over region 50P while exposing region 50N, and an appropriate type (e.g., n-type) impurity may be implanted into the exposed fin 52 in region 50N. The mask may then be removed. The n-type impurity may be any of the n-type impurities previously discussed, and the p-type impurity may be any of the p-type impurities previously discussed. The lightly doped source / drain regions may have a density of approximately 10 15 cm -3 to about 10 16 cm -3 Annealing can be used to activate the implanted impurities.

[0080] exist Figures 11A to 11E In the embodiment of the present invention, epitaxial source / drain regions 92 are formed in the fins 52. The epitaxial source / drain regions 92 can apply stress in each channel region 58, thereby improving performance. The epitaxial source / drain regions 92 are formed in the fins 52 so that each dummy gate 72 is disposed between respective adjacent pairs of epitaxial source / drain regions 92. In some embodiments, the epitaxial source / drain regions 92 can extend to the fins 52 and can also pass through the fins 52. In some embodiments, the first gate spacer 80, the second gate spacer 82, and the third gate spacer 84 are used to separate the epitaxial source / drain regions 92 from the dummy gate 72 at an appropriate lateral distance so that the epitaxial source / drain regions 92 do not short-circuit with the gate of the subsequently formed FinFET.

[0081] The epitaxial source / drain regions 92 in the region 50N (e.g., NMOS region) can be formed by masking the region 50P (e.g., PMOS region) and etching the source / drain regions of the fin 52 in the region 50N to form a recess in the fin 52. The epitaxial source / drain regions 92 in the region 50N are then epitaxially grown in the recess. The epitaxial source / drain regions 92 can include any suitable material, such as suitable for an n-type fin field-effect transistor. For example, if the fin 52 is silicon, the epitaxial source / drain regions 92 in the region 50N can include a material that applies tensile strain in the channel region 58, such as silicon, SiC, SiCP, SiP, or the like. The epitaxial source / drain regions 92 in the region 50N can have a surface that protrudes from the corresponding surface of the fin 52 and can have facets.

[0082] The epitaxial source / drain regions 92 in the region 50P (e.g., a PMOS region) can be formed by masking the region 50N (e.g., an NMOS region) and etching the source / drain regions of the fin 52 in the region 50P to form a recess in the fin 52. The epitaxial source / drain regions 92 in the region 50P are then epitaxially grown in the recess. The epitaxial source / drain regions 92 can include any suitable material, such as a material suitable for a p-type fin field-effect transistor. For example, if the fin 52 is silicon, the epitaxial source / drain regions 92 in the region 50P can include a material that applies compressive strain in the channel region 58, such as SiGe, SiGeB, Ge, GeSn, or a similar material. The epitaxial source / drain regions 92 in the region 50P can also have a surface that protrudes from the corresponding surface of the fin 52 and can have facets.

[0083] The epitaxial source / drain regions 92 and / or fins 52 may be implanted with dopants to form source / drain regions, similar to the process previously discussed for forming lightly doped source / drain regions, followed by annealing. The epitaxial source / drain regions 92 may have a thickness of approximately 10 19 cm -3 to about 10 21 cm -3 The n-type and / or p-type impurities used in the source / drain regions can be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 92 can be doped in situ during growth.

[0084] As a result of the epitaxial process used to form epitaxial source / drain regions 92 in regions 50N and 50P, the upper surfaces of epitaxial source / drain regions 92 have facets that extend laterally outward beyond the sidewalls of fin 52. In some embodiments, these facets merge adjacent epitaxial source / drain regions 92 of the same FinFET. Figure 11C shown. Figure 11DA schematic cross-sectional view of the merged portion of the epitaxial source / drain regions 92 is shown. As shown in the figure, the merged portion of the epitaxial source / drain regions 92 may have a generally spherical shape, such as a circle or an ellipse. Figure 11C and Figure 11D As shown, a portion of the remaining portion of the first gate spacer 80, the second gate spacer 82, and the third gate spacer 84 can be disposed below the merged portion of the epitaxial source / drain region 92. In other embodiments, for example Figure 11E In the illustrated embodiment, adjacent epitaxial source / drain regions 92 remain separated after the epitaxial growth process is completed.

[0085] like Figure 11C and Figure 11D As further shown, a void 93 can be formed below the epitaxial source / drain region 92 between the epitaxial source / drain region 92 and the third gate spacer 84. The void 93 can be formed by using a selective epitaxial growth process to form the epitaxial source / drain region 92. As will be discussed in more detail below, the void 93 can be a gas spacer (e.g., referring to FIG. Figures 20A to 20D Part of the gas spacer 110 discussed.

[0086] exist Figures 12A to 12D in Figures 11A to 11D A first interlayer dielectric 96 is deposited over the structure shown. The first interlayer dielectric 96 can be formed of a dielectric material and can be deposited by any suitable method, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition (PECVD), or flowable chemical vapor deposition. The dielectric material can include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or similar materials. Other insulating materials formed by any suitable process can be used.

[0087] In some embodiments, a first contact etch stop layer (CESL) 94 is disposed between the first interlayer dielectric 96 and the epitaxial source / drain regions 92, the mask 74, the first gate spacer 80, the second gate spacer 82, and the third gate spacer 84. The first CESL 94 may comprise an insulating material, such as SiN, SiCN, SiON, a multilayer or combination thereof, or similar materials. The first CESL 94 may be deposited by a conformal deposition method, such as chemical vapor deposition, atomic layer deposition, or a similar process. The first CESL 94 may be formed of a material having a different etch selectivity than the material of the second gate spacer 82 and the third gate spacer 84. In this way, the second gate spacer 82 and the third gate spacer 84 may be removed without removing the first CESL 94. In some embodiments, the first CESL 94 may be formed of the same material as the first gate spacer 80.

[0088] exist Figures 13A to 13D In the process, a planarization process, such as chemical mechanical polishing, may be performed on the first interlayer dielectric 96. In some embodiments, the planarization process may be used to make the top surface of the first interlayer dielectric 96 flush with the top surface of the dummy gate 72. In other embodiments, the planarization process may be used to make the top surface of the first interlayer dielectric 96 flush with the top surface of the mask 74. The planarization process may also be used to remove a portion of the first contact etch stop layer 94, the first gate spacer 80, and the second gate spacer 82, so that after the planarization process, the top surface of the first interlayer dielectric 96 may also be flush with the top surfaces of the first contact etch stop layer 94, the first gate spacer 80, and the second gate spacer 82.

[0089] exist Figures 14A to 14DDuring the etching step, the dummy gate 72 and mask 74 (if present) are removed, thereby forming recesses 100. A portion of the dummy dielectric layer 60 beneath the dummy gate 72 may also be removed. In some embodiments, only the dummy gate 72 is removed, leaving the dummy dielectric layer 60 exposed by the recesses 100. In some embodiments, the dummy dielectric layer 60 is removed from the recesses 100 in a first region of the die (e.g., the core logic region) and remains in the recesses 100 in a second region of the die (e.g., the input / output region). In some embodiments, the dummy gate 72 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the dummy gate 72 without etching the first interlayer dielectric 96, the first contact etch stop layer 94, the first gate spacer 80, or the second gate spacer 82. Each recess 100 exposes a channel region 58 of a corresponding fin 52. Each channel region 58 is disposed between adjacent pairs of epitaxial source / drain regions 92. During removal, the dummy dielectric layer 60 may serve as an etch stop when etching the dummy gate 72. The dummy dielectric layer 60 may then be optionally removed after the dummy gate 72 is removed.

[0090] exist Figures 15A to 15E In the process, a gate dielectric layer 102 and a gate electrode 104 are formed to replace the gate. Figure 15E Draw Figure 15B A gate dielectric layer 102 is conformally deposited in the recess 100 (e.g., Figure 15B and Figure 15D ), for example, on the top surface and sidewalls of the fin 52 and on the sidewalls of the first gate spacer 80. The gate dielectric layer 102 may also be formed on the top surface of the hard mask 98, the first contact etch stop layer 94, and the shallow trench isolation region 56. According to some embodiments, the gate dielectric layer 102 comprises silicon oxide, silicon nitride, or a multilayer structure of the foregoing. In some embodiments, the gate dielectric layer 102 comprises a high-k dielectric material, and in these embodiments, the gate dielectric layer 102 may have a k value greater than about 7.0 and may comprise a silicide or metal oxide of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. The method of forming the gate dielectric layer 102 may include molecular-beam deposition (MBD), atomic layer deposition, plasma-assisted chemical vapor deposition, or a similar process. In embodiments where a portion of the dummy dielectric layer 60 remains in the recess 100, the gate dielectric layer 102 comprises the material of the dummy dielectric layer 60 (e.g., SiO2).

[0091] The gate electrodes 104 are deposited on the gate dielectric layer 102 and fill the remaining portion of the recess 100. The gate electrodes 104 may include a metal-containing material such as TiN, TiO, TaN, TaC, Co, Ru, Al, W, a combination thereof, or a multilayer structure thereof. For example, although Figure 15A 、 Figure 15B and Figure 15D A single-layer gate electrode 104 is shown in FIG. 1 , but the gate electrode 104 may include any number of liner layers 104A, any number of work function adjustment layers 104B, and filler materials 104C, such as Figure 15E As shown. After filling the gate electrode 104, a planarization process (e.g., chemical mechanical polishing) can be performed to remove excess portions of the gate dielectric layer 102 and the material of the gate electrode 104 that are above the top surface of the hard mask 98. The remaining portions of the gate dielectric layer 102 and the material of the gate electrode 104 thus form a replacement gate of the resulting FinFET. The gate electrode 104 and the gate dielectric layer 102 can be collectively referred to as a "gate stack." The gate and the gate stack can extend along the sidewalls of the channel region 58 of the fin 52. The gate height of the gate stack can be about 10 nm to about 60 nm, for example, about 40 nm.

[0092] The formation of gate dielectric layer 102 in region 50N and region 50P can occur simultaneously, such that gate dielectric layer 102 in each region is formed of the same material, and the formation of gate electrode 104 can occur simultaneously, such that gate electrode 104 in each region is formed of the same material. In some embodiments, gate dielectric layer 102 in each region can be formed using different processes, such that gate dielectric layer 102 can be made of different materials, and / or gate electrode 104 in each region can be formed using different processes, such that gate electrode 104 can be made of different materials. When different processes are used, various masking steps can be used to mask and expose appropriate regions.

[0093] exist Figures 16A to 16D In the embodiment of the present invention, the first interlayer dielectric 96 is etched back and a hard mask 98 is formed over the first interlayer dielectric 96. The etch back of the first interlayer dielectric 96 can use an anisotropic etching process (such as reactive ion etching, neutral beam etching or similar processes) or an isotropic etching process (such as a wet etching process). The first interlayer dielectric 96 can be etched back a distance relative to the height of the gate stack, such as about 1 / 10 to about 1 / 2 of the height of the gate stack. The hard mask 98 can then be deposited on the resulting structure using chemical vapor deposition, plasma-assisted chemical vapor deposition, atomic layer deposition, sputtering or similar methods, and planarized using a process such as chemical mechanical polishing. Figure 16B and Figure 16DAs shown, after planarization of the hard mask 98, the top surface of the hard mask 98 can be flush with the top surfaces of the first contact etch stop layer 94, the first gate spacer 80, the second gate spacer 82, the gate dielectric layer 102 and the gate electrode 104. The planarization process for planarizing the hard mask 98 can also planarize the gate dielectric layer 102 and the gate electrode 104 so that the height of the gate stack after planarization is about 10 nm to about 50 nm. The hard mask 98 can be formed of, for example, silicon nitride, silicon oxide, silicon oxycarbide, silicon carbide nitride, a combination or multilayer structure of the foregoing, or the like. The hard mask 98 can be formed over the first interlayer dielectric 96 to protect the first interlayer dielectric 96 from being affected by the etching process for removing the second gate spacer 82 and the third gate spacer 84 (see below). Figures 17A to 18D discuss).

[0094] Figures 17A to 17D The intermediate stage of removing the second gate spacer 82 and the third gate spacer 84 is shown, and the Figures 18A to 18E As shown. Although Figures 17A to 17D Although not separately depicted, the etching process may etch through the second gate spacer 82 to expose the third gate spacer 84, and then the third gate spacer 84 may be etched. The etching process may be an isotropic etching process. The etching process may use an etching solution comprising an etchant substance and a catalyst substance. The etchant substance may comprise hydrogen fluoride or a similar material. The catalyst substance may comprise water, ethanol, a combination thereof, or a similar material. The etchant substance may be provided at a flow rate of approximately 50 standard cubic centimeters per minute (SCCM) to approximately 700 SCCM. In embodiments where the catalyst substance comprises water, the catalyst substance may be provided at a flow rate of approximately 300 milligrams per minute (MGM) to approximately 1800 MGM. In embodiments where the catalyst substance comprises ethanol, the catalyst substance may be provided at a flow rate of approximately 100 SCCM to approximately 800 SCCM. The etchant substance and the catalyst substance may be provided in the form of a liquid, a gas, or the like. In certain embodiments, the etchant substance may be provided as a gas, and the catalyst substance may be provided as a liquid.

[0095] Figures 16A to 16D The entire structure shown can be exposed to an etching solution. The etching process can be performed in a low temperature processing chamber, such as a temperature below 0°C, a temperature of about -30°C to about 30°C, a temperature of about -30°C to about 0°C, a temperature of about -20°C, or the like. The processing chamber can be maintained at a pressure of about 1 Torr to about 20 Torr. Figure 17AAs shown, the etching solution can form a solid etching film 106 along the surfaces of the hard mask 98, the first contact etch stop layer 94, the first gate spacer 80, the gate dielectric layer 102, and the gate electrode 104. The etching solution can form a liquid etching film 108 along the surfaces of the second gate spacer 82 and the third gate spacer 84. The intermediate product and the etchant species formed by etching the second gate spacer 82 and the third gate spacer 84 can lower the freezing point of the etching solution, so that the etching solution forms a liquid etching film only along the surfaces of the second gate spacer 82 and the third gate spacer 84 where the intermediate product exists. The temperature during the etching process and the flow rate of the etchant species and the catalyst species can be controlled to control the phases present on the surface of the structure to be etched (for example, to control the expansion of the solid etching film 106 and the liquid etching film 108).

[0096] Performing the etching process at a low temperature so that the etching solution forms the solid etching film 106 and the liquid etching film 108 can reduce the etching rate of the structure to maintain the etching rate relative to the second gate spacer 82 and the third gate spacer 84. For example, performing the etching process at a low temperature can reduce the etching rate of the hard mask 98, the first gate spacer 80, the gate dielectric layer 102, the gate electrode 104, the first contact etch stop layer 94, and the epitaxial source / drain region 92 (e.g., the structure provided with the solid etching film 106) relative to the etching rate of the second gate spacer 82 and the third gate spacer 84 (e.g., the structure provided with the liquid etching film 108). Specifically, the presence of solid etch film 106 along the surfaces of hard mask 98, first gate spacer 80, gate dielectric layer 102, gate electrode 104, first contact etch stop layer 94, and epitaxial source / drain regions 92 can reduce the removal of any products etched from hard mask 98, first gate spacer 80, gate dielectric layer 102, gate electrode 104, first contact etch stop layer 94, or epitaxial source / drain regions 92. This increases the etch selectivity of the etch and reduces material loss from hard mask 98, first gate spacer 80, gate dielectric layer 102, gate electrode 104, first contact etch stop layer 94, and epitaxial source / drain regions 92 caused by the etch process. Using the etch process can also reduce damage to the gate stack, such as profile bowing. This reduces defects in the completed semiconductor device fabricated by the above method and improves performance.

[0097] For materials including silicon nitride, silicon oxide, silicon oxycarbon nitride, etc., the etching process can have a high etch rate. x , tungsten, WO x , silicon carbide, silicon, silicon germanium, silicon phosphide, etc., the etching process can have a low etching rate. Etching at low temperature can reduce the etching rate of silicon carbide, titanium nitride, TiNO x and WOx In certain embodiments where the gate dielectric layer 102 and / or the gate electrode 104 comprise a metal oxide, the material of the gate dielectric layer 102 and / or the gate electrode 104 may be removed according to the following reaction:

[0098] HF (aq) +H2O+MO2→MF x (OH) y

[0099] Where M represents the metal material of the gate dielectric layer 102 and / or the gate electrode 104. Forming the solid etching film 106 along the gate dielectric layer 102 and the gate electrode 104 can reduce MF x , thereby reducing the removal of material from the gate dielectric layer 102 and / or the gate electrode 104.

[0100] In embodiments where the second gate spacer 82 and the third gate spacer 84 comprise silicon oxide, the etchant species comprises hydrogen fluoride, and the catalyst species comprises water, the second gate spacer 82 and the third gate spacer 84 may be removed according to the following reaction:

[0101] 4HF+H2O+SiO2→SiF4+3H2O

[0102] In this way, etching the second and third gate spacers can produce water. If the water concentration in the etching solution becomes too high, the etching solution may freeze and the excess water may make it difficult to control the etching process. In this way, the etching process can be cyclic, wherein a purge is used to periodically remove the etching solution from the processing chamber after each etching cycle (for example, to remove excess water). To prevent the etching solution from freezing, the etching solution can be heated during the purge process. In some embodiments, one to three etching cycles can be used to etch the second and third gate spacers 82 and 84. The etching process can remove the second and third gate spacers 82 and 84 from one of the regions 50N or 50P faster than from the other of the regions 50N or 50P. The etching can be performed for a duration sufficient to completely remove the second and third gate spacers 82 and 84 from both the regions 50N and 50P, for example, from about 40 seconds to about 200 seconds, for example, about 120 seconds.

[0103] Although it has been described that the second gate spacer 82 and the third gate spacer 84 are removed after forming the replacement gate, in some embodiments, the second gate spacer 82 and the third gate spacer 84 may be removed before forming the replacement gate. Figures 13A to 13D After the process described and with reference to Figures 14A to 14DPrior to the described process, a hard mask 98 may be formed and the second gate spacer 82 and the third gate spacer 84 may be removed. The second gate spacer 82 and the third gate spacer 84 may be removed using the aforementioned selective etching process to minimize the removal of material from the dummy gate 72, the hard mask 98, the first gate spacer 80, the first contact etch stop layer 94, and the epitaxial source / drain regions 92.

[0104] exist Figures 18A to 18E in Figures 17A to 17D A first dielectric layer 112 is formed over the structure, which forms a gas spacer 110 by closing the opening formed by removing the second gate spacer 82 and the third gate spacer 84. The first dielectric layer 112 can be formed by a conformal deposition process, such as chemical vapor deposition, atomic layer deposition, or a similar process. In certain embodiments, the first dielectric layer 112 can be deposited by a process with low conformity, such as physical vapor deposition (PVD). The first dielectric layer 112 can include a dielectric material, such as silicon nitride, silicon oxide, silicon oxycarbide, silicon carbide nitride, or a similar material. Although the bottom surface of the first dielectric layer 112 is illustrated as flat, the bottom surface of the first dielectric layer 112 can be curved. For example, in some embodiments, the bottom surface of the first dielectric layer 112 can be convex or concave.

[0105] Because the first dielectric layer 112 may be deposited using a process with poor uniformity, the first dielectric layer 112 may only partially extend into the opening formed by removing the second gate spacer 82 and the third gate spacer 84. The depth to which the first dielectric layer 112 extends into the opening may be greater than the thickness of the hard mask 98, such that after the hard mask 98 is removed by a process such as planarization, a portion of the first dielectric layer 112 remains (as described below with reference to FIG. Figures 19A to 19DAs discussed above, for example, the bottom surface of the first dielectric layer 112 can be disposed below the bottom surface of the hard mask 98 by a distance of approximately 30 nm. Because a portion of the opening remains unfilled by the first dielectric layer 112, a gas spacer 110 is formed below the first dielectric layer 112 between the first gate spacer 80 and the first contact etch stop layer 94. The gas spacer 110 can include any gas present in the reaction chamber when the first dielectric layer 112 is deposited. According to one embodiment, the gas spacer 110 can include air. In some embodiments, the gas spacer 110 can include nitrogen (N2), argon (Ar), xenon (Xe), ammonia (NH3), chlorine (Cl2), combinations thereof, or the like. In some embodiments, the gas spacer 110 can further include a precursor gas for forming the first dielectric layer 112, including silane (SiH4), dichlorosilane (SiH2Cl2), silicon tetrachloride (SiCl4), ammonia, combinations thereof, or the like. In various embodiments, the first dielectric layer 112 can be deposited in a vacuum or partial vacuum deposition process at a pressure of about 10 Torr to about 15 Torr (e.g., about 12.5 Torr). Thus, the gas spacer 110 can have a low pressure of about 10 Torr to about 15 Torr, for example, about 12.5 Torr. The width W1 of the gas spacer 110 adjacent to the gate stack can be about 1.5 nm to about 3 nm, and the height H1 can be less than about 90 nm. The gas spacer 110 can have a dielectric constant (e.g., k value) of 1 or close to 1.

[0106] Gas spacers 110 have a low dielectric constant value of 1 or close to 1, which is lower than the dielectric constant value of second gate spacer 82 or third gate spacer 84. As described above, second gate spacer 82 or third gate spacer 84 can be formed of silicon oxide, silicon nitride, silicon oxycarbon nitride, or similar materials. Replacing third gate spacer 84 and second gate spacer 82 with gas spacers 110 reduces the overall effective dielectric constant value of the spacers (e.g., the combination of gas spacers 110 and first gate spacer 80) and reduces the parasitic capacitance of the device formed according to the above method. This can improve the circuit speed, reliability, and overall device performance of the device formed according to the above method.

[0107] Figure 18E A schematic cross-sectional view parallel to the main surface of the substrate 50 is shown. Figure 18E As shown, a portion of the gas spacer 110 may surround a portion of the first interlayer dielectric 96 and the first contact etch stop layer 94. The first gate spacer 80 may surround the gas spacer 110. The first contact etch stop layer 94 and the first interlayer dielectric 96 may not be present between adjacent epitaxial source / drain regions 92, for example, below a merged portion of the epitaxial source / drain regions 92.

[0108] Figure 18E It is further shown that some gate electrodes 104 may be cut. In one embodiment, when referring to Figures 10A to 10D After the above process, the dummy gate 72 and the mask 74 can be etched. Figures 10A to 10D A patterned mask, such as a patterned photoresist, is formed over the structure shown. This can be achieved by using a spin coating or similar process. Figures 10A to 10D A photoresist layer is deposited over the structure shown to form a patterned photoresist. The photoresist layer can then be patterned by exposing the photoresist layer to a patterned energy source (e.g., a patterned light source) and developing the photoresist layer to remove exposed or unexposed portions of the photoresist layer, thereby forming a patterned photoresist. The dummy gate 72, mask 74, first gate spacer 80, second gate spacer 82, and third gate spacer 84 are then etched using a suitable etching process, such as an anisotropic etching process (e.g., a dry etching process) or the like. Reference may be used. Figures 12A to 12D The process described deposits the first interlayer dielectric 96 in the recess left by etching the dummy gate 72, the mask 74, the first gate spacer 80, the second gate spacer 82, and the third gate spacer 84. The dummy gate 72 or gate electrode 104 may be cut at any suitable point or by any suitable method to form Figure 18E The gate electrode 104 is shown cut.

[0109] exist Figures 19A to 19D In the process, first dielectric layer 112 is planarized and hard mask 98 is removed. First dielectric layer 112 may be planarized by a process such as chemical mechanical polishing. A portion of first dielectric layer 112 disposed over first interlayer dielectric 96, first contact etch stop layer 94, first gate spacer 80, gate dielectric layer 102, and gate electrode 104 may be removed, and after planarization, the top surfaces of first dielectric layer 112 and gate stack may be flush with the top surface of first interlayer dielectric 96. The planarization process may further remove hard mask 98. As described above, first dielectric layer 112 may be deposited in the opening left by removing second gate spacer 82 and third gate spacer 84 to a depth greater than the thickness of hard mask 98, such that first dielectric layer 112 remains after hard mask 98 is removed by the planarization process. After planarization, the height of the gate stack may be approximately 10 nm to approximately 30 nm. Although the top surface of the first dielectric layer 112 is depicted as being flat, after the planarization process, the top surface of the first dielectric layer 112 may be curved. For example, in some embodiments, the top surface of the first dielectric layer 112 may be convex or concave.

[0110] exist Figures 20A to 20DIn the embodiment of the present invention, a second interlayer dielectric 116 is deposited over the first interlayer dielectric 96, the gate electrode 104, the gate dielectric layer 102, the first contact etch stop layer 94, the first dielectric layer 112 and the first gate spacer 80. In some embodiments, the second interlayer dielectric 116 is a flowable film formed by a flowable chemical vapor deposition method. The second interlayer dielectric 116 can be formed of a dielectric material, such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG) or the like, and can be deposited by any suitable method, such as chemical vapor deposition and plasma-assisted chemical vapor deposition. According to some embodiments, before forming the second interlayer dielectric 116, the gate stack (including the gate dielectric layer 102 and the gate electrode 104) is recessed, thereby forming a groove directly above the gate stack and between the opposing portions of the first gate spacer 80, such as Figure 20A and Figure 20B The recess is filled with a gate mask 114 comprising one or more layers of dielectric material (e.g., silicon nitride, silicon oxynitride, or similar materials), and then a planarization process is performed to remove the excess portion of the dielectric material extending above the first interlayer dielectric 96. The gate contact (e.g., as described below) is subsequently formed. Figures 21A to 21D The gate contact 118 passes through the gate mask 114 to contact the top surface of the recessed gate electrode 104 .

[0111] According to some embodiments, Figures 21A to 21DIn the embodiment of the present invention, a gate contact 118 and a source / drain contact 120 are formed through the second interlayer dielectric 116 and the first interlayer dielectric 96. An opening for the source / drain contact 120 is formed through the second interlayer dielectric 116, the first interlayer dielectric 96, and the first contact etch stop layer 94, and an opening for the gate contact 118 is formed through the second interlayer dielectric 116 and the gate mask 114. The openings can be formed using suitable photolithography and etching techniques. The openings can be formed in a controlled manner to avoid exposing the gas spacer 110. A liner layer, such as a diffusion barrier layer, an adhesion layer, and a conductive material are formed in the opening. The liner layer can include titanium, titanium nitride, tantalum, tantalum nitride, or a similar material. The conductive material can be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or a similar material. The gate contact and the source / drain contact can be deposited by, for example, physical vapor deposition (PVD), chemical vapor deposition, or a similar process. A planarization process, such as chemical mechanical polishing, may be performed to remove excess material from the surface of the second interlayer dielectric 116. The remaining liner and conductive material form source / drain contacts 120 and gate contacts 118 in the openings. An annealing process may be performed to form silicide at the interface between the epitaxial source / drain regions 92 and the source / drain contacts 120. The source / drain contacts 120 are physically and electrically coupled to the epitaxial source / drain regions 92, and the gate contact 118 is physically and electrically coupled to the gate electrode 104. The source / drain contacts 120 and the gate contact 118 may be formed using different processes or may be formed using the same process. Although illustrated as being formed with the same cross-section, it should be understood that each of the source / drain contacts 120 and the gate contact 118 may be formed with a different cross-section, which may avoid shorting of the contacts.

[0112] As described above, forming gas spacers 110 reduces the effective dielectric constant of the spacers used in the structures of the present application. This reduces parasitic capacitance, which increases circuit speed, reliability, and overall device performance of the device formed according to the above method. Furthermore, using a low-temperature etching process to form gas spacers 110 improves the etch selectivity of the etching process, allowing the removal of second gate spacers 82 and third gate spacers 84 without removing or damaging other structures. This reduces device defects and improves device performance of the device formed according to the above method.

[0113] According to one embodiment, a method includes forming a gate stack over a substrate; forming a first gate spacer on a sidewall of the gate stack; forming a second gate spacer on the sidewall of the first gate spacer; removing the second gate spacer using an etching process to form a first opening, the etching process being performed at a temperature less than 0°C and using an etching solution containing hydrogen fluoride; and depositing a dielectric layer over the first gate spacer and the gate stack, the dielectric layer sealing a gas spacer in the first opening. In one embodiment, the etching solution further includes a catalyst comprising water. In one embodiment, the flow rate of hydrogen fluoride in the etching solution is 50 SCCM to 700 SCCM, and the flow rate of water in the etching solution is 300 MGM to 1800 MGM. In one embodiment, the etching solution further includes a catalyst comprising ethanol. In one embodiment, the flow rate of hydrogen fluoride in the etching solution is 50 SCCM to 700 SCCM, and the flow rate of ethanol in the etching solution is 100 SCCM to 800 SCCM. In one embodiment, the etching process includes one to three etching cycles, with a purge performed after each etching cycle. In one embodiment, during the etching process, a solid etching film is formed on surfaces of the gate stack and the first gate spacer, and a liquid etching film is formed on surfaces of the second gate spacer.

[0114] According to another embodiment, a method includes forming a gate stack above a semiconductor substrate; forming a first gate spacer on the sidewalls of the gate stack; forming a second gate spacer on the sidewalls of the first gate spacer; epitaxially growing source / drain regions on both sides of the gate stack; removing the second gate spacer using an etching process, wherein the removal of the second gate spacer forms a first opening; during the etching process, a solid etching film is formed on the surfaces of the gate stack, the first gate spacer, and the source / drain regions, and a liquid etching film is formed on the surface of the second gate spacer; and depositing a first dielectric layer to seal the first opening and define a gas spacer on the sidewalls of the first gate spacer. In one embodiment, the second gate spacer comprises a silicon oxide layer and a silicon nitride layer, and the first gate spacer comprises silicon carbide nitride. In one embodiment, the gate stack comprises a second dielectric layer and a metal gate overlying the second dielectric layer, and the second gate spacer is removed after forming the gate stack. In one embodiment, the etching process uses an etching solution comprising hydrogen fluoride and ethanol. In another embodiment, the etching process uses an etching solution comprising hydrogen fluoride and water. In one embodiment, the etching process is performed at a temperature of -30°C to 0°C.

[0115] According to another embodiment, a method for fabricating a semiconductor device includes forming a dummy gate over a semiconductor substrate; depositing a first spacer over the dummy gate; depositing a second spacer over the first spacer; depositing a third spacer over the second spacer; patterning the first, second, and third spacers to form a first gate spacer, a second gate spacer, and a third gate spacer, respectively; epitaxially growing source / drain regions on both sides of the dummy gate adjacent to the third gate spacer; replacing the dummy gate with a metal gate; and after replacing the dummy gate, removing the second and third gate spacers using an etching process at a temperature below 0°C, wherein the removal of the second and third gate spacers forms a void that exposes the surfaces of the first gate spacer and the source / drain regions. In one embodiment, the method further includes forming an interlayer dielectric over the source / drain regions and the dummy gate; planarizing the interlayer dielectric and the dummy gate; etching back the interlayer dielectric to form a first opening; and filling the first opening with a hard mask. After filling the first opening, the second and third gate spacers are removed. In one embodiment, the method further includes forming a dielectric layer over the hard mask, the metal gate, and the void, the dielectric layer sealing the void to form an air spacer adjacent to the first gate spacer. In one embodiment, a portion of the air spacer extends below a portion of the source / drain region in a direction perpendicular to the main surface of the semiconductor substrate. In one embodiment, the method further includes performing a second planarization to planarize the dielectric layer, the interlayer dielectric, the first gate spacer, and the metal gate, and removing the hard mask, wherein before the second planarization, the gate height of the metal gate is 10 nm to 60 nm, and after the second planarization, the gate height of the metal gate is 10 nm to 30 nm. In one embodiment, the etching process uses an etching solution comprising hydrogen fluoride and water. In one embodiment, the etching process uses an etching solution comprising hydrogen fluoride and ethanol.

[0116] The above overview of the components of several embodiments enables those skilled in the art to better understand the aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments of the present disclosure to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art should also understand that such equivalent structures do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions, and adjustments without violating the spirit and scope of the embodiments of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, comprising: forming a gate stack over a substrate; forming a first gate spacer on a sidewall of the gate stack; forming a second gate spacer on a sidewall of the first gate spacer; forming a source / drain region adjacent to the gate stack; removing the second gate spacer using an etching process to form a first opening exposing a bottom surface of the source / drain region and a horizontal surface of the first gate spacer below a top surface of the first gate spacer, wherein the etching process is performed at a temperature less than 0° C., and wherein the etching process uses an etching solution including hydrogen fluoride; as well as A dielectric layer is deposited over the first gate spacer and the gate stack, the dielectric layer sealing a gas spacer in the first opening.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The etching solution further includes a catalyst, wherein the catalyst includes water.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: The flow rate of the hydrogen fluoride in the etching solution is 50 SCCM to 700 SCCM, and the flow rate of the water in the etching solution is 300 MGM to 1800 MGM.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: The etching solution further includes a catalyst, wherein the catalyst includes ethanol.

5. The method for manufacturing a semiconductor device according to claim 4, wherein: The flow rate of the hydrogen fluoride in the etching solution is 50 SCCM to 700 SCCM, and the flow rate of the ethanol in the etching solution is 100 SCCM to 800 SCCM.

6. The method for manufacturing a semiconductor device according to claim 1, wherein: The etching process includes one to three etching cycles, and a purge is performed after each of the etching cycles.

7. The method for manufacturing a semiconductor device according to claim 1, wherein: During the etching process, a solid etching film is formed on surfaces of the gate stack and the first gate spacer, and a liquid etching film is formed on a surface of the second gate spacer.

8. A method for manufacturing a semiconductor device, comprising: forming a gate stack on a semiconductor substrate; forming a first gate spacer on a sidewall of the gate stack; forming a second gate spacer on a sidewall of the first gate spacer; Epitaxially growing a plurality of source / drain regions on both sides of the gate stack; removing the second gate spacer using an etching process, wherein the removal of the second gate spacer forms a plurality of first openings, wherein during the etching process, a solid etching film is formed on surfaces of the gate stack, the first gate spacer, and the source / drain regions, and a liquid etching film is formed on surfaces of the second gate spacer; as well as A first dielectric layer is deposited to seal the first opening and define a gas spacer on the sidewall of the first gate spacer.

9. The method for manufacturing a semiconductor device according to claim 8, wherein: The second gate spacer includes a silicon oxide layer and a silicon nitride layer, and the first gate spacer includes silicon carbide nitride.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: The gate stack includes a second dielectric layer and a metal gate covering the second dielectric layer, and the second gate spacer is removed after forming the gate stack.

11. The method for manufacturing a semiconductor device according to claim 8, wherein: The etching process uses an etching solution including hydrogen fluoride and ethanol.

12. The method for manufacturing a semiconductor device according to claim 8, wherein: The etching process uses an etching solution including hydrogen fluoride and water.

13. The method for manufacturing a semiconductor device according to claim 8, wherein: The etching process is performed at a temperature of -30°C to 0°C.

14. A method for manufacturing a semiconductor device, the method comprising: forming a dummy gate on a semiconductor substrate; depositing a first spacer layer above the dummy gate; depositing a second spacer layer over the first spacer layer; depositing a third spacer layer over the second spacer layer; patterning the first spacer layer, the second spacer layer, and the third spacer layer to form a first gate spacer, a second gate spacer, and a third gate spacer, respectively; epitaxially growing a plurality of source / drain regions on both sides of the dummy gate adjacent to the third gate spacer; replacing the dummy gate with a metal gate; as well as After replacing the dummy gate, the second gate spacer and the third gate spacer are removed using an etching process at a temperature below 0° C. The removal of the second gate spacer and the third gate spacer forms a gap that exposes the first gate spacer and the surface of the source / drain region.

15. The method for manufacturing a semiconductor device according to claim 14, further comprising: forming an interlayer dielectric over the source / drain regions and the dummy gate; planarizing the interlayer dielectric and the dummy gate; Etching back the interlayer dielectric to form a first opening; as well as The first opening is filled with a hard mask, wherein the second gate spacer and the third gate spacer are removed after the first opening is filled. 16 . The method for fabricating a semiconductor device according to claim 15 , further comprising forming a dielectric layer over the hard mask, the metal gate, and the gap, wherein the dielectric layer seals the gap to form an air spacer adjacent to the first gate spacer.

17. The method for manufacturing a semiconductor device according to claim 16, wherein: A portion of the air spacer extends below a portion of the source / drain regions in a direction perpendicular to a main surface of the semiconductor substrate.

18. The method for manufacturing a semiconductor device as described in claim 16 further includes performing a second planarization to planarize the dielectric layer, the interlayer dielectric, the first gate spacer and the metal gate and removing the hard mask, wherein before the second planarization, the gate height of the metal gate is 10nm to 60nm, and wherein after the second planarization, the gate height of the metal gate is 10nm to 30nm.

19. The method for manufacturing a semiconductor device according to claim 14, wherein: The etching process uses an etching solution including hydrogen fluoride and water.

20. The method for manufacturing a semiconductor device according to claim 14, wherein: The etching process uses an etching solution including hydrogen fluoride and ethanol.

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