Semiconductor devices

Abstract

A semiconductor device is provided which does not cause problems even when there is a temperature change. The device is constructed by burying a heat dissipation layer (3) carrying semiconductor elements (1a, 1b) inside a resin seal (9), a portion of a copper plate (7) fixed to the heat dissipation layer (3) via a resin insulating layer (6), a portion of a first lead frame (4a) bonded to the heat dissipation layer (3) via a bonding material (5b), and a portion of a second lead frame (4b) bonded to the semiconductor elements (1a, 1b) via bonding materials (5a1, 5ab), bonding a portion of the copper plate (7) exposed from the resin seal (9) to a cooler (11) via a welding portion (10), and setting the thickness of the copper plate (7) to a value not less than 0.3 [mm] and not exceeding the thickness of the heat dissipation layer (3).

Description

Technical Field

[0001] The present application relates to a semiconductor device. Background Art

[0002] In recent years, semiconductor devices equipped with power semiconductor elements have been advancing towards larger capacity. In order to allow large currents to flow through power semiconductor elements, it is necessary to efficiently dissipate the heat generated in the semiconductor elements. Therefore, efforts are being made to reduce the thermal resistance of insulating components and bonding components between semiconductor elements and coolers such as heat sinks.

[0003] For example, in the conventional semiconductor device disclosed in Patent Document 1, a circuit portion including a semiconductor element formed on a lead frame is electrically insulated from a cooler for heat dissipation by using a specific structure including a heat diffusion plate, and is reinforced by an integrated structure using a resin mold. The semiconductor device thus constructed can ensure high reliability and reduce the thermal resistance of the device, and can provide a compact and highly reliable power semiconductor device at a low price.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Laid-Open No. 10-93015 Summary of the invention

[0007] Technical problem to be solved by the invention

[0008] Patent Document 1 describes fixing a power semiconductor element to a cooler, but does not touch upon the fixing method. Usually, when a power semiconductor element is connected to a cooler, silicone heat dissipation grease is used. Even practical silicone heat dissipation grease with high thermal conductivity is only at the 3 [W / mK] level, which is the main reason for the increase in thermal resistance of a semiconductor device including a cooler. In addition, silicone heat dissipation grease does not include the function of fixing a semiconductor element to a cooler, so a fixing member such as a screw is required separately.

[0009] Therefore, as a bonding method that satisfies the requirements of reducing the thermal resistance between the semiconductor element and the cooler and fixing the semiconductor element and the cooler, there is a method of bonding by soldering material. However, in this case, the entire semiconductor device is subjected to high temperature during the reflow process when soldering, so the resin insulation layer built into the semiconductor device may peel off due to the high temperature or have an adverse effect on the bonding material.

[0010] The present application discloses a technology for solving the above-mentioned problems, and an object of the present application is to provide a semiconductor device that does not cause problems even when subjected to high temperatures.

[0011] Technical solutions adopted to solve technical problems

[0012] The semiconductor device disclosed in the present application includes:

[0013] A power module; and a cooler joined to the power module via a welding portion composed of a welding material, wherein the semiconductor device is characterized in that:

[0014] The power module comprises:

[0015] Semiconductor components;

[0016] a heat dissipation layer having the semiconductor element mounted on one surface portion thereof via a bonding material;

[0017] a first lead frame, the first lead frame serving as a main terminal coupled to the heat dissipation layer via a bonding material;

[0018] a second lead frame serving as a main terminal joined to the semiconductor element via a joining material;

[0019] a copper plate having one surface portion bonded to another surface portion of the heat dissipation layer opposite to the one surface portion via a resin insulating layer; and

[0020] a resin sealant that seals the semiconductor element, the heat dissipation layer, a portion of the first lead frame, a portion of the second lead frame, the resin insulating layer, and a portion of the copper plate other than the other surface portion that is opposite to the one surface portion,

[0021] In the power module, the other surface portion of the copper plate exposed from the resin sealing body abuts against the welding portion and is joined to the cooler.

[0022] The thickness of the copper plate is set to a value not less than 0.3 [mm] and not exceeding the thickness of the heat dissipation layer.

[0023] In addition, the semiconductor device disclosed in the present application includes:

[0024] A power module; and a cooler joined to the power module via a welding portion composed of a welding material, wherein the semiconductor device is characterized in that:

[0025] The power module comprises:

[0026] Semiconductor components;

[0027] a first lead frame serving as a main terminal including a portion on one surface of which the semiconductor element is mounted via a bonding material and a portion having a thickness dimension different from that of the portion;

[0028] a second lead frame serving as a main terminal joined to the semiconductor element via a joining material;

[0029] a copper plate having one surface portion bonded to another surface portion of the first lead frame, opposite to the one surface portion, of the portion where the semiconductor element is mounted, via a resin insulating layer; and

[0030] a resin sealant that seals the semiconductor element, the portion of the first lead frame on which the semiconductor element is mounted, a portion of the second lead frame, the resin insulating layer, and a portion of the copper plate other than the other surface portion that is opposite to the one surface portion,

[0031] In the power module, the other surface portion of the copper plate exposed from the resin sealing body abuts against the welding portion and is joined to the cooler.

[0032] The thickness of the copper plate is set to a value not less than 0.3 [mm] and not exceeding the thickness of the portion of the first lead frame where the semiconductor element is mounted.

[0033] Effects of the Invention

[0034] According to the semiconductor device disclosed in the present application, it is possible to obtain a semiconductor device that does not cause problems even when subjected to high temperatures. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 This is a cross-sectional view of the semiconductor device according to the first embodiment.

[0036] Figure 2 It is a cross-sectional view showing an intermediate structure formed through steps in the manufacturing process for explaining the manufacturing process of the semiconductor device according to the first embodiment.

[0037] Figure 3 Yes means Figure 2 The intermediate structure shown is a cross-sectional view of the intermediate structure formed through subsequent steps.

[0038] Figure 4 Yes means Figure 3 The intermediate structure shown is a cross-sectional view of the intermediate structure formed through subsequent steps.

[0039] Figure 5 Yes means Figure 4 The intermediate structure shown is a cross-sectional view of a semiconductor device finally manufactured through subsequent steps.

[0040] Figure 6 This is a cross-sectional view of a semiconductor device according to the second embodiment.

[0041] Figure 7 This is a cross-sectional view of a semiconductor device according to a third embodiment.

[0042] Figure 8 This is a cross-sectional view of a semiconductor device according to a fourth embodiment.

[0043] Fig. 9 It is an explanatory diagram showing data of examples of semiconductor devices according to embodiments 1 to 4 and data of comparative examples.

[0044] Fig.10 Yes means Fig. 9 Graphs illustrating evaluation results of Examples and Comparative Examples shown. DETAILED DESCRIPTION

[0045] A semiconductor device according to each embodiment of the present application will be described below with reference to the drawings.

[0046] Implementation method 1.

[0047] First, the structure of the power semiconductor device according to the first embodiment will be described. Figure 1 This is a cross-sectional view of the semiconductor device according to the first embodiment. Figure 1 In the embodiment, the semiconductor device 100 includes a power module 101 and a cooler 11. One surface portion 11a of the cooler 11 is joined to the power module 101 through a welding portion 10. A plurality of heat dissipation fins 11c are provided on the other surface portion 11b of the cooler 11 on the opposite side of the power module. In the embodiment 1, the cooler 11 is formed of a metal flat plate-shaped heat sink, but may also be a liquid-cooled cooler including a flow path for passing a coolant therein.

[0048] The power module 101 includes a semiconductor element 1a as a switching element, a semiconductor element 1b as a rectifying element, a heat spreader 3, a first lead frame 4a, a second lead frame 4b, a resin insulating layer 6 containing an inorganic filler in the resin, a copper plate 7, a bonding wire 8, and a resin seal 9. The semiconductor element 1a as a switching element is bonded to one surface portion of the heat spreader 3 through a chip-under bonding material 2a. The semiconductor element 1b as a rectifying element is bonded to one surface portion of the heat spreader 3 through a chip-under bonding material 2b. The other surface portion of the heat spreader 3 opposite to the one surface portion is fixed to one surface portion of the copper plate 7 via the resin insulating layer 6.

[0049] The other surface portion of the copper plate 7 opposite to the one surface portion is exposed from the lower surface portion 94 opposite to the upper surface portion 93 of the resin sealing body 9 of the power module 101, and is joined to the one surface portion 11a of the cooler 11 via the welding portion 10. Thus, the power module 101 and the cooler 11 are integrally joined to form the semiconductor device 100.

[0050] The first lead frame 4a is bonded to one surface portion of the heat dissipation layer 3 via a wire bonding material 5b. In order to ensure electrical conduction between the heat dissipation layer 3 and the first lead frame 4a, the wire bonding material 5b is formed by bonding of a solder material or metal bonding by ultrasonic wave, and the heat dissipation layer 3 is integrally bonded to the first lead frame 4a. The second lead frame 4b is bonded to the semiconductor element 1a via an on-chip bonding material 5a1, and is bonded to the semiconductor element 1b via an on-chip bonding material 5a2. The bonding wire 8 connects the semiconductor element 1a as a switching element to a plurality of third lead frames 4c ( Figure 1 The third lead frame 4c is partially embedded and fixed in a resin sealant 9 described later and is separated from the first lead frame 4a.

[0051] The resin sealing body 9 is constructed to include the above-mentioned semiconductor elements 1a, 1b, the heat dissipation layer 3, a part of the first lead frame 4a, a part of the second lead frame 4b, a part of the third lead frame 4c, the resin insulating layer 6, a part of the copper plate 7, the bonding wire 8, the under-chip bonding material 2a, 2b, the on-chip bonding material 5a1, 5a2 and the lead bonding material 5b, and they are sealed from the outside.

[0052] The first lead frame 4a includes a first portion 4a1 and a second portion 4a2. The first portion 4a1 is vertically led out from one side portion 91 of the resin seal 9 to the outside of the resin seal 9, and the second portion 4a2 is bent at a right angle in a direction away from the cooler 11 at a predetermined position of the first portion 4a1 and extends in a direction away from the cooler 11. The third lead frame 4c also includes a first portion 4c1 (not shown) and a second portion 4c2 (not shown) in the same manner as the first lead frame 4a. The second lead frame 4b includes a first portion 4b1 and a second portion 4b2. The first portion 4b1 is vertically led out from the other side portion 92 of the resin seal 9 opposite to the one side portion 91, and the second portion 4b2 is bent at a right angle in a direction away from the cooler 11 at a predetermined position of the first portion 4b1 and extends in a direction away from the cooler 11. The second portion 4a2 of the first lead frame 4a and the second portion 4b2 of the second lead frame 4b are connected to an external electrical circuit. The second portion (not shown) of the third lead frame 4 c is connected to a signal wiring and a control wiring to be described later.

[0053] In the semiconductor device 100 according to the first embodiment configured as described above, heat generated when the semiconductor elements 1 a and 1 b operate is dissipated to the cooler 11 via the under-die bonding materials 2 a and 2 b , the heat dissipation layer 3 , the resin insulating layer 6 , the copper plate 7 , and the soldering portion 10 .

[0054] Next, the electrical connection between the power module 101 and the outside is described in more detail. The semiconductor elements 1a and 1b include an active surface portion corresponding to the surface portion and a surface portion on the opposite side of the active surface portion, that is, a back portion. The back portions of the semiconductor elements 1a and 1b are bonded to one surface portion of the heat dissipation layer 3 through chip underbonding materials 2a and 2b composed of solder materials or the like. The second portion 4a2 of the first lead frame 4a becomes an external terminal of the first lead frame 4a.

[0055] The second lead frame 4b serving as a main terminal is bonded to the active surface of the semiconductor elements 1a and 1b via die bonding materials 5a1 and 5a2 made of solder etc. The second portion 4b2 of the second lead frame 4b serves as an external terminal of the second lead frame 4b.

[0056] The semiconductor element 1a as a switching element needs to be electrically connected to a signal wiring related to a signal for switching, and a control wiring related to a control for monitoring temperature or current, etc. Since the amount of current flowing through the signal wiring and the control wiring is not large, the semiconductor element 1a as a switching element is connected to a plurality of third lead frames 4c as signal terminals using bonding wires 8. Examples of the material of the bonding wire 8 include aluminum, copper, and gold, but aluminum is preferred because of its high bonding reliability.

[0057] The power module 101 is a semiconductor chip equipped with a semiconductor element 1a as a switching element and a semiconductor element 1b as a rectifying element. The semiconductor element 1a is composed of a semiconductor switching element such as an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). As described above, the power module 101 includes a semiconductor element 1b as a rectifying element composed of a diode or the like.

[0058] The IGBT constituting the semiconductor element 1a is an element that drives a load by passing a large current. The power module 101 equipped with the semiconductor element 1a constituted by the IGBT operates as a power module. The semiconductor elements 1a and 1b are preferably formed of silicon (Si), for example, but are not limited to silicon. For example, the semiconductor chip constituting the semiconductor elements 1a and 1b is more preferably formed of a material selected from the group consisting of silicon carbide (SiC), gallium nitride materials [such as gallium nitride (GaN)], and diamond. The semiconductor elements 1a and 1b are so-called wide bandgap semiconductor materials with a wider bandgap than silicon. Compared with semiconductor elements using silicon semiconductor materials such as MOSFET, the semiconductor elements 1a and 1b formed using such wide bandgap semiconductor materials can be used for operation at high temperatures. That is, the wide bandgap semiconductor material is a semiconductor material used for flowing a large current.

[0059] As described above, the second lead frame 4b serving as a main terminal is bonded to the active surface portion of the semiconductor elements 1a and 1b via the on-chip bonding materials 5a1 and 5a2 made of solder material or the like. Figure 1 In the embodiment, the semiconductor element 1a as a switching element and the semiconductor element 1b as a rectifying element are arranged one by one with a gap between them, but the arrangement is not limited to this. The number of semiconductor elements 1a and 1b arranged in one power module 101 is arbitrary. That is, only one of the semiconductor element 1a and the semiconductor element 1b may be arranged, or three or more semiconductor elements 1a may be arranged, or three or more semiconductor elements 1b may be arranged, or three or more semiconductor elements 1a and semiconductor elements 1b may be arranged in a mixed manner.

[0060] In addition, the semiconductor element 1a as the switching element can use RC-IGBT (Reverse Conducting IGBT). RC-IGBT contains IGBT and diode in one semiconductor chip. The active surface portion opposite to the back surface portion bonded to the heat dissipation layer 3 of the semiconductor elements 1a and 1b is partially plated with nickel-gold.

[0061] The heat dissipation layer 3, the first lead frame 4a, and the second lead frame 4b use a metal with good electrical conductivity. From the viewpoints of electrical impedance, processability, cost, etc., copper is the most preferred metal even among metals with good electrical conductivity. Here, the copper material refers to pure copper or a copper alloy with copper as the main component. The entire power module 101 is sealed by a resin sealant 9. As the resin sealant 9, a resin having a linear expansion coefficient close to the linear expansion coefficient of the heat dissipation layer 3, the first lead frame 4a, and the second lead frame 4b can be used.

[0062] The linear expansion coefficient of pure copper ranges from 16 [ppm / K] to 17 [ppm / K], so the linear expansion coefficient of the resin sealant 9 may also range from 15 [ppm / K] to 19 [ppm / K]. The linear expansion coefficient of the resin sealant 9 is a value of the linear expansion coefficient in the temperature range below the glass transition temperature Tg. The glass transition temperature Tg of the resin sealant 9 may be above the temperature reached when the semiconductor elements 1a and 1b are in operation. If the glass transition temperature Tg is low, the physical properties of the resin sealant 9 change greatly during the operation of the semiconductor elements 1a and 1b. This situation sometimes causes a decrease in the electrical insulation and mechanical strength of the resin sealant 9. Preferably, since the semiconductor elements 1a and 1b operate at a maximum of 175 [℃] when formed of silicon, the resin sealant 9 preferably has a glass transition temperature Tg of 175 [℃] or above.

[0063] The resin insulating layer 6 is required to transfer the heat generated when the semiconductor elements 1a and 1b are operated to the cooler 11 and dissipate the heat while ensuring electrical insulation. The resin insulating layer 6 is formed by filling an inorganic filler, which is an insulating inorganic filler material with high thermal conductivity, into a thermosetting resin, and bonding the heat dissipation layer 3 and the copper plate 7 by the thermosetting response of the resin.

[0064] The power module 101 is joined to a cooler 11 including heat dissipation fins 11c through a welding portion 10 to dissipate the heat generated when the semiconductor elements 1a and 1b are in operation. The cooler 11 requiring high cooling performance may be a water-cooled type or an air-cooled type. The cooler 11 is preferably selected from a group consisting of copper, aluminum, and an alloy of copper or aluminum, or may be formed of any one of them. Among them, aluminum or an aluminum alloy that is lightweight and has excellent processability is preferably used as the material of the cooler 11.

[0065] The cooler 11 connected to the power module 101 is provided with a plurality of heat dissipation fins 11c to improve the cooling performance of the semiconductor device 100. The cooler 11 has a complex shape and is manufactured by die casting or extrusion. As aluminum alloys used for die casting or extrusion, ADC10 and ADC12 of Al-Si-Cu type, A6061 or A6063 of Al-Mg-Si type, etc. are preferred.

[0066] Next, a method for manufacturing the semiconductor device 100 according to Embodiment 1 will be described. First, a die bonding step in the method for manufacturing the semiconductor device 100 according to Embodiment 1 will be described. Figure 2 1 is a cross-sectional view showing an intermediate structure formed by steps in the manufacturing process for explaining the method for manufacturing a semiconductor device according to Embodiment 1, and shows an intermediate structure formed by a die bonding step. Figure 2As shown, a semiconductor element 1a as a switching element and a semiconductor element 1b as a rectifying element are bonded to one surface portion 31 of the heat dissipation layer 3 at intervals from each other via under-die bonding materials 2a and 2b. Figure 2 The process shown is called a chip mounting process. The semiconductor element 1a as a switching element is formed of silicon, for example, and a semiconductor chip with an IGBT mounted thereon is used. The semiconductor element 1b as a rectifying element is formed of silicon, for example, and a semiconductor chip with a diode mounted thereon is used.

[0067] Figure 2 The figure shows a state where the two semiconductor elements 1a and 1b are spaced apart from each other and are combined with the heat dissipation layer 3. The thickness dimension of the heat dissipation layer 3 is from 1.0 [mm] to 3.0 [mm]. When the thickness dimension of the heat dissipation layer 3 is less than 1.0 [mm], the effect of diffusing the heat generated by the semiconductor elements 1a and 1b in the lateral direction of the heat dissipation layer 3, that is, the expansion direction of the surface of the heat dissipation layer 3 is insufficient to reduce the thermal resistance of the power module 101. On the other hand, if the thickness dimension of the heat dissipation layer 3 is greater than 3.0 [mm], the heat diffusion effect will be saturated. In addition, the thickness dimension becomes larger, which will cause problems such as an increase in the weight of the power module 101. Therefore, the thickness dimension of the heat sink 3 is preferably from 1.0 [mm] to 3.0 [mm].

[0068] Here, for example, the size of the semiconductor element 1a as a switching element equipped with an IGBT (rated 1200 [V], 300 [A]) in a plan view is 13 [mm] × 13 [mm] × 0.12 [mm]. For example, the size of the semiconductor element 1b as a rectifying element equipped with a diode (rated 1200 [V], 300 [A]) in a plan view is 13 [mm] × 10 [mm] × 0.12 [mm].

[0069] The heat dissipation layer 3 with a size of 35 [mm] × 20 [mm] × 2.5 [mm] is made of oxygen-free copper. Figure 2 As shown, a semiconductor element 1 a as a switching element and a semiconductor element 1 b as a rectifying element are fixed to desired positions of the heat dissipation layer 3 via a die-bonding material 2 a and a die-bonding material 2 b , respectively.

[0070] The chip-under-bonding materials 2a and 2b are preferably any bonding materials selected from the group consisting of soldering materials, sinterable fillers with silver as the main component, solder with silver as the main component, materials with copper dispersed in tin, and gold-based alloys such as gold-tin and gold-germanium with gold as the main component. These bonding materials are bonding materials with high thermal conductivity and electrical conductivity. As the chip-under-bonding materials 2a and 2b, for example, sintered silver is preferably used. Sintered silver does not melt again after bonding, and fewer voids are generated in the bonding layer, and no hot spots of local heating of the chip are generated. Therefore, it is a preferred material as the chip-under-bonding materials 2a and 2b. The thickness dimension of the chip-under-bonding materials 2a and 2b is set to 0.05 [mm].

[0071] Figure 3 Yes means Figure 2 The cross-sectional view of the intermediate structure formed by the subsequent process shows the intermediate structure formed by the process of bonding the first lead frame 4a and the second lead frame 4b to the semiconductor elements 1a, 1b and the heat dissipation layer 3. Figure 3 As shown, in the intermediate structure, a first lead frame 4 a serving as a main terminal, a second lead frame 4 b serving as a main terminal, and a third lead frame 4 c serving as a signal terminal are bonded to the semiconductor elements 1 a and 1 b and the heat dissipation layer 3 .

[0072] That is, the first lead frame 4a, which will become the main terminal, is bonded to one surface portion 31 of the heat dissipation layer 3 using the wire bonding material 5b. In addition, the second lead frame 4b, which will become the main terminal, is bonded to the active surface of the semiconductor element 1a, which is a switching element, using the on-chip bonding material 5a1, and the second lead frame 4b, which will become the main terminal, is bonded to the active surface of the semiconductor element 1b, which is a rectifying element, using the on-chip bonding material 5a2. Furthermore, the third lead frame 4c, which will become the signal terminal, is connected to the semiconductor element 1a, which is a switching element, using the bonding wire 8. In the process of bonding the first lead frame 4a and the second lead frame 4b to the semiconductor elements 1a, 1b and the heat dissipation layer 3, the connection operation of each lead frame is not prioritized.

[0073] The heat dissipation layer 3 and the first lead frame 4a are connected using a wire bonding material 5b composed of a solder material, but other bonding methods such as ultrasonic bonding and welding may also be used. The semiconductor elements 1a, 1b and the second lead frame 4b are bonded using chip bonding materials 5a1, 5a2 composed of a solder material. In addition, the chip bonding materials 5a1, 5a2 do not need to be solder materials, and may be sintered silver. In the case where solder materials are used for the chip bonding materials 5a1, 5a2 and the wire bonding material 5b, as described later, care must be taken not to melt again during the reflow process in the process of bonding the cooler 11 and the power module 101 through the soldering portion 10.

[0074] As described above, the semiconductor element 1a as a switch element and the third lead frame 4c as a signal terminal are electrically connected using the bonding wire 8. The aluminum bonding wire 8 used here has a substantially circular cross section with a diameter of 0.20 [mm] in a direction perpendicular to its extending direction.

[0075] Figure 4 Yes means Figure 3 The cross-sectional view of the intermediate structure formed by the subsequent process of the intermediate structure shown in FIG. 1 shows the process of completing the power module 101. Figure 3 After the process shown, Figure 4 In the process shown in FIG. 1 , first, a copper plate 7 and a resin insulating layer 6 are integrated in a transfer molding mold. At this time, the copper plate 7 is arranged below the resin insulating layer 6. Next, the semiconductor elements 1a and 1b mounted on the heat dissipation layer 3 are bonded to the first lead frame 4a, the second lead frame 4b, and the third lead frame 4c. Figure 3 The intermediate structure obtained by the process is set in the above-mentioned mold. At this time, the other surface portion 32 (refer to Figure 2 , Figure 3 ) is in contact with the upper surface portion of the resin insulation layer 6.

[0076] Next, a thermosetting resin is injected into the mold, and the semiconductor elements 1a, 1b, the heat dissipation layer 3, the first lead frame 4a, the second lead frame 4b, a portion of the third lead frame 4c, the resin insulating layer 6, and a portion of the copper plate 7 are sealed by the resin sealant 9 composed of the thermosetting resin. At this time, the copper plate 7 is formed so that the surface portion 71 on the opposite side of the resin insulating layer 6 is exposed from the resin sealant 9.

[0077] Here, the resin insulating layer 6 is composed of a material having heat dissipation, insulation and adhesion, and has a structure in which a thermosetting resin such as epoxy resin contains inorganic powder filling materials such as ceramic particles with high thermal conductivity. As inorganic filling materials with high thermal conductivity, ceramic particles such as aluminum nitride, silicon nitride, boron nitride, aluminum oxide (alumina), silicon oxide (silicon dioxide), magnesium oxide, zinc oxide, and titanium oxide are used. In addition, it is not necessary to use any of these inorganic filling materials alone, and multiple types can be mixed and used. The thickness of the resin insulating layer 6 is preferably 50 [μm] or more and 500 [μm] or less.

[0078] The maximum particle size of the inorganic filler material used in the resin insulating layer 6 is preferably not less than 50 [μm] and not more than 150 [μm]. Here, the maximum particle size of the inorganic filler material is the maximum value of the size of the straight line pointing to the inside of the inorganic filler material (the size of the linear shape of the inside of the inorganic filler under the projection). Therefore, if the resin insulating layer 6 is thinner than 50 [μm], the maximum particle size of the inorganic powder filler contained therein also becomes thinner, which sometimes causes the insulation of the resin insulating layer 6 to be significantly reduced. On the other hand, in the case where the resin insulating layer 6 has a thickness dimension greater than 500 [μm], the insulation is better but the thermal resistance becomes larger, which sometimes causes a decrease in heat dissipation performance. From these viewpoints, the thickness dimension of the resin insulating layer 6 is preferably not less than 50 [μm] and not more than 500 [μm]. In addition, the resin insulating layer 6 does not need to be composed of a single layer, for example, it can be a structure of stacked layers with different thermal conductivity.

[0079] Furthermore, the resin insulating layer 6 based on the resin material also has the function of an adhesive material. Therefore, when the resin sealant 9 is thermally cured in the sealing process of the power module 101 described later, the resin insulating layer 6 bonds the heat dissipation layer 3 and the copper plate 7 so that they are in close contact with each other. Therefore, it is not necessary to apply an adhesive material to one surface portion and the other surface portion of the resin insulating layer 6. The adhesive material is the cause of the increase in thermal resistance, so the adhesive material is not applied to one surface portion and the other surface portion of the resin insulating layer 6, thereby suppressing the increase in thermal resistance between the resin insulating layer 6 and the heat dissipation layer 3 and the first lead frame 4a, the second lead frame 4b, the third lead frame 4c, the copper plate 7 and the resin sealant 9, and obtaining a power module 101 with high heat dissipation performance.

[0080] The copper plate 7 is made of pure copper or a copper alloy with copper as the main component, similar to the heat dissipation layer 3 and the first lead frame 4a, the second lead frame 4b, and the third lead frame 4c. The thickness of the copper plate 7 is 0.3 [mm] or more and is less than the thickness of the heat sink 3 sandwiching the resin insulating layer 6. If the thickness of the copper plate 7 is thinner than 0.3 [mm], the rigidity of the copper material constituting the copper plate 7 is weak, so the resin insulating layer 6 may be damaged and peeled off according to the thermal history in the welding process as a subsequent process. On the other hand, if the thickness of the copper plate 7 exceeds the thickness of the heat dissipation layer 3, the weight of the power module 101 increases, the workability of the component in which the copper plate 7 and the resin insulating layer 6 are integrated becomes poor, and in the reflow process of the welding portion 10, the heat capacity of the copper plate 7 increases and the heat is easy to escape, so it is easy to cause poor bonding of the welding portion 10. The optimal thickness of the heat dissipation layer 3 is 1.0 [mm] to 3.0 [mm]. Therefore, the thickness of the copper plate 7 is preferably in the range of 0.3 [mm] to 1.0 [mm].

[0081] The resin sealant 9 has a structure similar to the resin insulating layer 6 in which an inorganic filler is contained in a thermosetting resin such as epoxy resin. In addition, in the transfer molding process, the resin sealant 9 and the resin insulating layer 6 are hardened. For example, the temperature of the mold is set to 180 [°C], the internal pressure of the mold is set to 10 [MPa], and the heating time is set to 3 [minutes]. The heating time in the transfer molding process can be appropriately set to any time according to the reactivity of the resin sealant 9 and the resin insulating layer 6. In addition, the resin insulating layer 6 is melted by heating, and further hardened by further heating in the transfer molding process.

[0082] The resin seal 9 does not need high thermal conductivity, so the inorganic filler contained in the thermosetting resin such as epoxy resin has good fluidity when contained in the thermosetting resin, and fused silica is the best among silicon oxide (silicon dioxide) whose linear expansion coefficient is easy to adjust. The power module 101 is mostly made of copper, so the linear expansion coefficient of copper matches the linear expansion coefficient of the resin seal 9, that is, the linear expansion coefficient of the resin seal 9 is the same or similar to the linear expansion coefficient of copper, so as to try to reduce the internal stress of the power module 101, so the amount of inorganic filler is adjusted so that the linear expansion coefficient of the resin seal 9 is 15 [ppm / K] to 19 [ppm / K]. This has the effect of improving the reliability of temperature cycling.

[0083] Figure 5 Yes means Figure 4 The intermediate structure shown is a cross-sectional view of a semiconductor device finally manufactured through subsequent processes. Figure 4 The power module 101 shown in the figure is subjected to cutting and bending of the first lead frame 4a, the second lead frame 4b, and the third lead frame 4c in the subsequent process, so that the first lead frame 4a, the second lead frame 4b, and the third lead frame 4c, which are main terminals, are formed. Figure 4 As shown in the figure, the first lead frame 4a, the second lead frame 4b, and the third lead frame 4c extending vertically from the opposite side portions of the resin seal 9 are cut into predetermined lengths. Furthermore, as described above, the first lead frame 4a, the second lead frame 4b, and the third lead frame 4c are bent to form the first portions 4a1, 4b1, and 4c1 and the second portions 4a2, 4b2, and 4c2.

[0084] After that, the power module 101 and the cooler 11 are joined using the welding part 10. The material of the cooler 11 is set to aluminum alloy, for example, A6063 of the Al-Mg-Si type. The welding part 10 uses, for example, a lead-free solder material (tin 95.5 [weight %], silver 2 [weight %], copper 0.5 [weight %], bismuth 2 [weight %], liquidus 221 [℃]). The cooler 11 is made by extrusion molding.

[0085] In the welding process, the power module 101 and the cooler 11 need to be heated to a temperature range where the welding portion 10 melts. At this time, the welding material used in the power module 101 may also melt. If the welding material melts, the resin sealing body 9 may crack due to the volume expansion from solid to liquid. Therefore, it is necessary to set a melting point difference between the welding material used inside the power module 101 and the welding portion 10 for joining the cooler 11 and the power module 101.

[0086] For example, when a solder material having a liquidus line of 243°C of 95 wt% tin and 5 wt% antimony is used as the die bonding materials 5a1 and 5a2 and the wire bonding material 5b used in the power module 101, and a solder material having a liquidus line of 221°C of 95.5 wt% tin, 2 wt% silver, 0.5 wt% copper, and 2 wt% bismuth is used as the bonding portion 10, the difference in melting point of the solder material is 22°C. In addition, when a solder material having a liquidus line of 266°C of 90 wt% tin and 10 wt% antimony is used as the die bonding materials 5a1 and 5a2 and the wire bonding material 5b, and a solder material having a liquidus line of 221°C of 95.5 wt% tin, 2 wt% silver, 0.5 wt% copper, and 2 wt% bismuth is used as the bonding portion 10, the difference in melting point of the solder material is 45°C. Therefore, a difference in melting point can be provided between the on-die bonding materials 5 a 1 and 5 a 2 and the wire bonding material 5 b , and the soldering portion 10 .

[0087] By using this melting point difference, the temperature setting during the reflow soldering process as the bonding process of the soldering portion 10 can prevent the solder material inside the power module 101 from melting again. The melting point difference between the solder material inside the power module 101 and the soldering portion 10 for bonding the cooler 11 and the power module 101 needs to be 20 [°C] or more. In addition, in the first embodiment, the under-chip bonding materials 2a and 2b need to use a sinterable filler containing silver as a main component in a material other than the solder that does not melt again in the reflow soldering process.

[0088] The semiconductor device according to the first embodiment described above is characterized in that the thickness of the copper plate 7 is set to be 0.3 [mm] or more and does not exceed the thickness of at least the portion where the semiconductor elements 1a and 1b are mounted in the copper heat dissipation layer 3 bonded to the copper first lead frame 4a, the second lead frame 4b, and the third lead frame 4c. With this structure, the power module 101 and the cooler 11 can be bonded using the soldering portion 10, and a semiconductor device with low thermal resistance, excellent heat dissipation, and high reliability against temperature cycles can be provided.

[0089] Implementation method 2.

[0090] Figure 6 This is a cross-sectional view of a semiconductor device according to the second embodiment. Figure 6 In the embodiment, the semiconductor device 100 according to the second embodiment includes a power module 101 and a cooler 11 as in the first embodiment. The cooler 11 is bonded to the power module 101 via a welding portion 10. The semiconductor device 100 according to the second embodiment is different from the semiconductor device according to the first embodiment in that a first lead frame 41 as a lead frame having a thickness dimension increased in part is used instead of the heat dissipation layer 3 used in the semiconductor device 100 according to the first embodiment.

[0091] That is, the first lead frame 41 as a different thickness lead frame includes a first portion 41a on which the semiconductor element 1a as a switching element and the semiconductor element 1b as a rectifying element are mounted, a second portion 41b extending obliquely upward from the first portion 41a, a third portion 41c extending in a curved direction in the horizontal direction of the figure from the second portion 41b, and a fourth portion 41d extending in a curved direction at a right angle from the third portion 41c away from the cooler 11, and these portions are formed integrally with the same material. The bonding wire 8 connects the semiconductor element 1a as a switching element to the plurality of third lead frames 4c ( Figure 6 The third lead frame 4c is partially embedded in the resin sealant 9 and fixed, and is separated from the first lead frame 41. The first lead frame 41 and the second lead frame 4b are main terminals, and the third lead frame 4c is a signal terminal.

[0092] The fourth lead frame 4d embedded in the resin seal 9 is bonded to the active surface of the semiconductor element 1a through the chip bonding material 5a1, and is bonded to the active surface of the semiconductor element 1b through the chip bonding material 5a2. A portion of the second lead frame 4b is embedded in the resin seal 9 and fixed to the resin seal 9, and is bonded to the fourth lead frame 4d through the wire bonding material 40 composed of a solder material. In addition, the bonding between the second lead frame 4b and the fourth lead frame 4d may be performed by ultrasonic bonding or welding, etc., instead of the wire bonding material 40 composed of a solder material.

[0093] The thickness dimension of the first portion 41a of the first lead frame 41 as a lead frame of different thickness, which is a portion on which the semiconductor elements 1a and 1b are mounted, is 1.0 [mm] to 2.0 [mm]. The first lead frame 41 is the same as the second lead frame 4b, the fourth lead frame 4d, and the third lead frame 4c, and is made of a copper alloy with pure copper or copper as a main component. The semiconductor device 100 involved in the second embodiment is characterized in that the thickness dimension of the copper plate 7 is 0.3 [mm] or more, and does not exceed the thickness dimension of the first portion 41a of the first lead frame 41 as a lead frame of different thickness made of copper, which is 1.0 [mm] to 2.0 [mm]. In addition, the other structures are the same as the semiconductor device involved in the first embodiment.

[0094] The thickness dimension of the copper plate 7 is 0.3 [mm] or more and is less than the thickness dimension of the first portion 41a of the first lead frame 41 on which the semiconductor elements 1a and 1b are mounted, sandwiching the resin insulating layer 6. If the thickness dimension of the copper plate 7 is thinner than 0.3 [mm], the rigidity of the copper material constituting the copper plate 7 is weak, and therefore the resin insulating layer 6 may be damaged and peeled off according to the thermal history in the welding process as a subsequent process. On the other hand, if the thickness dimension of the copper plate 7 exceeds the thickness dimension of the first portion 41a of the first lead frame 41 on which the semiconductor elements 1a and 1b are mounted, the weight of the power module 101 increases, the workability of the member in which the copper plate 7 and the resin insulating layer 6 are integrated deteriorates, and in the reflow process of the welding portion 10, the heat capacity of the copper plate 7 increases and the heat is easily dissipated, so that the welding portion 10 is prone to poor bonding. The thickness of the first portion 41a of the first lead frame 41, which is a copper lead frame of different thickness, on which the semiconductor elements 1a and 1b are mounted is 1.0 to 2.0 mm. Therefore, the thickness of the copper plate 7 is preferably in the range of 0.3 to 1.0 mm.

[0095] In the welding process, the power module 101 and the cooler 11 need to be heated to a temperature range where the welding portion 10 melts. At this time, the welding material used in the power module 101 may also melt. If the welding material melts, the resin sealing body 9 may crack due to the volume expansion from solid to liquid. Therefore, it is necessary to set a melting point difference between the welding material used inside the power module 101 and the welding portion 10 for joining the cooler 11 and the power module 101.

[0096] For example, when a solder material having a liquidus line of 243°C of 95 wt% tin and 5 wt% antimony is used as the on-chip bonding materials 5a1 and 5a2 used in the power module 101, and a solder material having a liquidus line of 221°C of 95.5 wt% tin, 2 wt% silver, 0.5 wt% copper, and 2 wt% bismuth is used as the bonding portion 10, the difference in melting point of the solder material is 22°C. In addition, when a solder material having a liquidus line of 266°C of 90 wt% tin and 10 wt% antimony is used as the on-chip bonding materials 5a1 and 5a2, and a solder material having a liquidus line of 221°C of 95.5 wt% tin, 2 wt% silver, 0.5 wt% copper, and 2 wt% bismuth is used as the bonding portion 10, the difference in melting point of the solder material is 45°C. Therefore, a difference in melting point can be provided between the on-die bonding materials 5 a 1 , 5 a 2 and the soldering portion 10 .

[0097] By using this melting point difference, the temperature setting during the reflow soldering process as the bonding process of the soldering portion 10 can prevent the solder material inside the power module 101 from melting again. The melting point difference between the solder material inside the power module 101 and the soldering portion 10 for bonding the cooler 11 and the power module 101 needs to be 20 [°C] or more. In addition, in the second embodiment, the under-chip bonding materials 2a and 2b need to use a sinterable filler containing silver as a main component in a material other than the solder that does not melt again in the reflow soldering process.

[0098] The semiconductor device according to the second embodiment has the above-described structure, and can bond the power module 101 and the cooler 11 using the soldering portion 10 , thereby providing a semiconductor device having low thermal resistance and high reliability against temperature cycles.

[0099] In the method for manufacturing a semiconductor device according to the second embodiment, the first portion 41a of the first lead frame 41 as a lead frame of different thickness is used instead of the heat dissipation layer 3 in the first embodiment, and in the first embodiment, the semiconductor elements 1a and 1b are bonded to the second lead frame 4b, whereas in the second embodiment, the fourth lead frame 4d is bonded to the semiconductor elements 1a and 1b, and the fourth lead frame 4d is bonded to the second lead frame 4b via a wire bonding material 40. The other steps are substantially the same as the corresponding steps in the method for manufacturing a semiconductor device according to the first embodiment.

[0100] Implementation method 3.

[0101] Figure 7 1 is a cross-sectional view of a semiconductor device according to Embodiment 3. A semiconductor device 100 according to Embodiment 3 includes a power module 101 and a cooler 11. The cooler 11 is bonded to the power module 101 via a welding portion 10. The semiconductor device 100 according to Embodiment 3 is different from the semiconductor device according to Embodiment 1 in that the resin sealing body 9 of the power module 101 includes hole portions 12a1, 12a2, and 12b.

[0102] The hole 12a1 is opened in the upper surface portion 93 of the resin seal 9 up to the surface portion of the chip bonding material 5a1 present in the resin seal 9. The hole 12a2 is opened in the upper surface portion 93 of the resin seal 9 up to the surface portion of the chip bonding material 5a2 present in the resin seal 9. The hole 12b is opened in the upper surface portion 93 of the resin seal 9 up to the surface portion of the wire bonding material 5b present in the resin seal 9. When the chip bonding material 5a1 composed of the solder material present in the resin seal 9 is melted again during the reflow soldering as the bonding process of the soldering portion 10, the volume of the chip bonding material 5a1 expands due to the phase change from solid to liquid, but the volume expansion is absorbed by the hole 12a1, so that no stress is generated on the resin seal 9, and the resin seal 9 is not damaged.

[0103] In addition, when the on-chip bonding material 5a2 composed of the solder material present in the resin sealant 9 is melted again during the reflow soldering as the bonding process of the soldering portion 10, the volume of the on-chip bonding material 5a2 expands due to the phase change from solid to liquid, but the volume expansion is absorbed by the hole 12a2, so no stress is generated on the resin sealant 9, and the resin sealant 9 is not damaged. Similarly, when the on-chip bonding material 5b composed of the solder material present in the resin sealant 9 is melted again during the reflow soldering as the bonding process of the soldering portion 10, the volume of the on-chip bonding material 5b expands due to the phase change from solid to liquid, but the volume expansion is absorbed by the hole 12b, so no stress is generated on the resin sealant 9, and the resin sealant 9 is not damaged.

[0104] In the above-mentioned first embodiment, a melting point difference is set between the chip bonding materials 5a1, 5a2 and the lead bonding material 5b and the soldering portion 10, and the temperature setting during the reflow soldering process as the bonding process of the soldering portion 10 is performed by utilizing this melting point difference, thereby preventing the soldering material existing inside the resin sealing body 9 of the power module 101 from melting again. However, the semiconductor device involved in the third embodiment is provided with the holes 12a1, 12a2, and 12b as described above, so that when selecting the soldering materials constituting the chip bonding materials 5a1, 5a2 and the lead bonding material 5b buried in the resin sealing body 9 of the power module 101 and the soldering portion 10, there is no restriction on the melting point, and the selection width of the respective soldering materials is expanded, and the processing redundancy of the reflow soldering process is also expanded.

[0105] As the size of the holes 12a1, 12a2, 12b, the diameter is preferably in the range of 1 [mm] to 3 [mm] in consideration of the volume expansion of the solder material. If the diameter of the holes 12a1, 12a2, 12b is set larger than 3 [mm], the sealing effect of the resin sealant 9 on the semiconductor elements 1a, 1b may be impaired, which is not preferred.

[0106] The method for making the holes 12a1, 12a2, and 12b is not particularly limited, but the following method can be cited as an example. After the power module 101 is made by transfer molding and covered with the resin sealant 9, the holes 12a1, 12a2, and 12b are formed from the outside of the resin sealant 9 by drilling or laser, etc. at positions corresponding to the chip bonding materials 5a1, 5a2 and the wire bonding material 5b composed of solder material buried inside the resin sealant 9 of the power module 101.

[0107] In addition, as another method, pins are arranged at positions corresponding to the holes 12a1, 12a2, and 12b in the mold during transfer molding, thereby forming the holes 12a1, 12a2, and 12b in the resin seal 9 after molding. In addition, as another method, pins can be arranged at positions corresponding to the holes 12a1, 12a2, and 12b in the mold during transfer molding, thereby performing trimming processing on the holes 12a1, 12a2, and 12b formed in the resin seal 9 after molding using drilling or laser. Alternatively, when corresponding pins are arranged at positions corresponding to the holes 12a1, 12a2, and 12b in the mold during transfer molding, they are shared with pins for pressurizing the heat dissipation layer 3 in order to ensure the sealing performance of the resin insulation layer 6.

[0108] According to the semiconductor device involved in embodiment 3, holes 12a1, 12a2, and 12b are provided in the resin sealing body 9 corresponding to the positions where the chip bonding materials 5a1, 5a2 and the wire bonding materials 5b composed of solder materials buried in the interior of the power module 101, i.e., the interior of the resin sealing body 9 exist, so that during the reflow soldering process for bonding the power module 101 to the cooler 11 using the soldering portion 10, the resin sealing body 9 will not be damaged even if the chip bonding materials 5a1, 5a2 and the wire bonding materials 5b melt and expand in volume.

[0109] Therefore, there is no need to provide a melting point difference between the on-chip bonding materials 5a1, 5a2 and the wire bonding material 5b and the soldering portion 10, which are composed of solder materials used inside the power module 101. Therefore, the selection of solder materials is expanded, and the processing margin of the reflow process is also expanded. In addition, the selection of solder materials is expanded, so that solder materials with excellent temperature cycle resistance can also be selected, and a semiconductor device with high reliability against temperature cycles can be provided.

[0110] Implementation method 4.

[0111] Figure 8 1 is a cross-sectional view of a semiconductor device according to a fourth embodiment. A semiconductor device 100 according to the fourth embodiment includes a power module 101 and a cooler 11. The cooler 11 is bonded to the power module 101 via a welding portion 10. The semiconductor device 100 according to the fourth embodiment is different from the semiconductor device according to the second embodiment in that the resin sealing body 9 of the power module 101 includes holes 12a1 and 12a2, and a heat sink 11 is provided. Figure 6 The second lead frame 4b shown is obtained by integrating the fourth lead frame 4d in the second embodiment.

[0112] The hole 12a1 is opened in the upper surface portion 93 of the resin seal 9 up to the surface portion of the on-chip bonding material 5a1 present in the resin seal 9. The hole 12a2 is opened in the upper surface portion 93 of the resin seal 9 up to the surface portion of the on-chip bonding material 5a2 present in the resin seal 9. When the on-chip bonding material 5a1 composed of the solder material present in the resin seal 9 is melted again during the reflow soldering as the bonding process of the soldering portion 10, the volume of the on-chip bonding material 5a1 expands due to the phase change from solid to liquid, but the volume expansion is absorbed by the hole 12a1, so that no stress is generated on the resin seal 9, and the resin seal 9 is not damaged.

[0113] In addition, during the reflow soldering as the joining process of the welding portion 10, when the chip bonding material 5a2 composed of the welding material existing inside the resin sealing body 9 is melted again, the volume of the chip bonding material 5a2 expands due to the phase change from solid to liquid, but the volume expansion is absorbed by the hole portion 12a2, so that no stress is generated on the resin sealing body 9, and thus the resin sealing body 9 is not damaged.

[0114] In the semiconductor device involved in the fourth embodiment, by providing the hole portions 12a1 and 12a2 as described above, there is no restriction on the melting point when selecting the on-chip bonding materials 5a1 and 5a2 and the welding material of the welding portion 10 that constitute the resin sealing body 9 buried in the power module 101, thereby having the advantages of expanding the selection range of the respective welding materials and also expanding the processing redundancy of the reflow soldering process.

[0115] As the size of the holes 12a1 and 12a2, the diameter is preferably in the range of 1 [mm] to 3 [mm] in consideration of the volume expansion of the solder material. If the diameter of the holes 12a1 and 12a2 is set larger than 3 [mm], the sealing effect of the resin seal 9 on the semiconductor elements 1a and 1b may be impaired, which is not preferred. The method for making the holes 12a1 and 12a2 is the same as that of the third embodiment described above.

[0116] According to the semiconductor device involved in embodiment 4, holes 12a1 and 12a2 are provided in the resin sealing body 9 corresponding to the positions where the on-chip bonding materials 5a1 and 5a2 composed of soldering materials buried in the interior of the power module 101, i.e., the interior of the resin sealing body 9 exist, so that in the reflow soldering process using the soldering portion 10 to connect with the cooler 11, even if the on-chip bonding materials 5a1 and 5a2 melt and expand in volume, the resin sealing body 9 will not be damaged.

[0117] Therefore, there is no need to provide a difference in melting point between the on-chip bonding materials 5a1 and 5a2 formed of the solder material used inside the power module 101 and the soldering portion 10, so that the selection of solder materials is expanded and the processing margin of the reflow process is also expanded. In addition, the selection of solder materials is expanded, so that solder materials with excellent temperature cycle resistance can also be selected, and a semiconductor device with high reliability against temperature cycles can be provided.

[0118] Fig. 9 It is an explanatory diagram showing specific data of examples of semiconductor devices according to embodiments 1 to 4 and specific data of comparative examples. Fig. 9 The "heat dissipation layer" corresponds to the above-mentioned embodiment 1 and embodiment 3. The thickness dimensions of the copper heat dissipation layer 3 and the copper plate 7 are set to the values ​​shown in Examples 1 to 5 and Comparative Examples 1 to 4, respectively, to produce a power module 101, and then these power modules 101 and the cooler 11 are joined through the soldering portion 10 via a reflow process. In this way, the semiconductor elements of Examples 1 to 5 and Comparative Examples 1 to 4 are manufactured, and the state of the resin insulating layer 6 and the soldering portion 10 in each semiconductor element is confirmed using an ultrasonic flaw detection device. In addition, a current flows through the semiconductor elements 1a and 1b, and the thermal resistance of the semiconductor device of each embodiment is calculated based on the power amount at this time and the temperature difference between the semiconductor elements 1a and 1b and the cooler 11.

[0119] also, Fig. 9 The "different-thickness lead frame" corresponds to the above-mentioned Embodiment 2 and Embodiment 4. The thickness dimensions of the first portion 41a in the first lead frame 41, which is a different-thickness lead frame made of copper, and the copper plate 7 are set to the values ​​shown in Embodiments 6 and 7, respectively, to produce a power module 101, and then these power modules 101 and the cooler 11 are joined through the welding portion 10 via a reflow soldering process. In this way, the semiconductor elements of Embodiments 6 and 7 are manufactured, and the states of the resin insulating layer 6 and the welding portion 10 in each semiconductor element are confirmed using an ultrasonic flaw detection device. In addition, current flows through the semiconductor elements 1a and 1b, and the thermal resistance of the semiconductor device of each embodiment is calculated based on the power amount at this time and the temperature difference between the semiconductor elements 1a and 1b and the cooler 11.

[0120] Fig.10 Yes means Fig. 9 Graphs illustrating evaluation results of Examples and Comparative Examples shown. Fig.10In the figure, the state of the resin insulating layer 6 is indicated by "○" when no peeling occurs, and by "×" when peeling occurs. In addition, the state of the soldering portion 10 is indicated by "○" when no poor bonding is observed, and by "×" when poor bonding is observed. The thermal resistance of the power module 101 is indicated by "○" when the thermal resistance is within 10[%] of the design value, and by "×" when the thermal resistance deviates from the design value by 10[%].

[0121] from Fig.10 It can be seen that in Comparative Examples 1 to 4, peeling of the resin insulating layer 6 or poor bonding of the soldering portion 10 was observed, resulting in an increase in thermal resistance. On the other hand, in Examples 1 to 7, it can be seen that the bonding state is good, and peeling of the resin insulating layer 6 or poor bonding of the soldering portion 10 is not confirmed, and as a result, the thermal resistance is also within 10 [%] of the design value.

[0122] Furthermore, the various embodiments may be combined, or the various embodiments may be appropriately modified or omitted.

[0123] Description of symbols

[0124] 1a, 1b Semiconductor components

[0125] 2a, 2b Bonding material under the chip

[0126] 3. Heat spreader

[0127] 4a, 41 first lead frame

[0128] 4b Second lead frame

[0129] 4c Third lead frame

[0130] 4d fourth lead frame

[0131] 5a1, 5a2 On-die bonding materials

[0132] 5b Wire Bonding Materials

[0133] 6 Resin insulation layer

[0134] 7 Copper Plate

[0135] 8 Bonding wire

[0136] 9 Resin seal

[0137] 10 Welding Department

[0138] 11 Cooler

[0139] 12a1, 12a2, 12b hole

[0140] 100 Semiconductor devices

[0141] 101 Power module.

Claims

1. A semiconductor device comprising: Power module; and a cooler joined to the power module via a welding portion made of a welding material, wherein the semiconductor device is characterized in that: The power module comprises: Semiconductor components; a heat dissipation layer having the semiconductor element mounted on one surface portion thereof via a bonding material; a first lead frame serving as a main terminal bonded to the heat dissipation layer via a bonding material; a second lead frame serving as a main terminal joined to the semiconductor element via a joining material; a copper plate having one surface portion bonded to another surface portion of the heat dissipation layer opposite to the one surface portion via a resin insulating layer; and a resin sealant that seals the semiconductor element, the heat dissipation layer, a portion of the first lead frame, a portion of the second lead frame, the resin insulating layer, and a portion of the copper plate other than the other surface portion that is opposite to the one surface portion, In the power module, the other surface portion of the copper plate exposed from the resin sealing body abuts against the welding portion and is joined to the cooler. The thickness of the copper plate is set to a value not less than 0.3 [mm] and not exceeding the thickness of the heat dissipation layer.

2. The semiconductor device according to claim 1, wherein The thickness of the heat dissipation layer is set to a value of 1.0 [mm] or more and 3.0 [mm] or less.

3. The semiconductor device according to claim 1 or 2, wherein: The resin sealing body includes a hole portion provided corresponding to the bonding material bonding the first lead frame to the semiconductor element and the bonding material bonding the second lead frame to the heat dissipation layer.

4. The semiconductor device according to claim 3, wherein: The diameter of the hole is set to 1 [mm] to 3 [mm].

5. A semiconductor device comprising: Power module; and a cooler joined to the power module via a welding portion made of a welding material, wherein the semiconductor device is characterized in that: The power module comprises: Semiconductor components; a first lead frame serving as a main terminal including a portion on one surface of which the semiconductor element is mounted via a bonding material and a portion having a thickness dimension different from that of the portion; a second lead frame serving as a main terminal joined to the semiconductor element via a joining material; a copper plate having one surface portion bonded to another surface portion of the first lead frame, opposite to the one surface portion, of the portion where the semiconductor element is mounted, via a resin insulating layer; and a resin sealant that seals the semiconductor element, the portion of the first lead frame on which the semiconductor element is mounted, a portion of the second lead frame, the resin insulating layer, and a portion of the copper plate other than the other surface portion that is opposite to the one surface portion, In the power module, the other surface portion of the copper plate exposed from the resin sealing body abuts against the welding portion and is joined to the cooler. The thickness of the copper plate is set to a value not less than 0.3 [mm] and not exceeding the thickness of the portion of the first lead frame where the semiconductor element is mounted.

6. The semiconductor device according to claim 5, wherein: The thickness dimension of the portion of the first lead frame where the semiconductor element is mounted is set to be greater than or equal to 1.0 [mm] and less than or equal to 2.0 [mm].

7. The semiconductor device according to claim 5 or 6, wherein: The resin sealing body includes a hole portion provided corresponding to the bonding material bonding the second lead frame and the semiconductor element.

8. The semiconductor device according to claim 7, wherein: The diameter of the hole is set to 1 [mm] to 3 [mm].

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