Packaging structure and manufacturing method thereof

Abstract

A packaging structure includes a circuit substrate and a semiconductor device. The semiconductor device is arranged on the circuit substrate and electrically connected to the circuit substrate. The semiconductor device includes an internal wiring structure, a semiconductor die, an insulating sealant, a protective layer and an electrical connector. The internal wiring structure has a first surface and a second surface. The semiconductor die is arranged on the first surface and electrically connected to the internal wiring structure. The insulating sealant seals the semiconductor die and partially covers the side wall of the internal wiring structure. The protective layer is arranged on the second surface of the internal wiring structure and partially covers the side wall of the internal wiring structure, wherein the protective layer contacts the insulating sealant. The electrical connector is arranged on the protective layer, wherein the internal wiring structure is electrically connected to the circuit substrate through a plurality of electrical connectors.

Description

Technical Field

[0001] The present disclosure relates to a packaging structure and a manufacturing method thereof. Background Art

[0002] Semiconductor devices and integrated circuits used in various electronic applications such as mobile phones and other mobile electronic devices are typically manufactured on a single semiconductor wafer. The die of the wafer can be processed and packaged together with other semiconductor devices or dies at the wafer level, and various technologies have been developed for wafer-level packaging. Summary of the invention

[0003] The embodiment of the present disclosure provides a packaging structure including a circuit substrate and a semiconductor device. The semiconductor device is placed on the circuit substrate and electrically connected to the circuit substrate. The semiconductor device includes an internal wiring structure, a semiconductor die, an insulating sealant, a protective layer, and a plurality of electrical connectors. The internal wiring structure has a first surface and a second surface opposite to the first surface. The semiconductor die is placed on the first surface and electrically connected to the internal wiring structure. The insulating sealant is placed on the first surface of the internal wiring structure and seals the semiconductor die, wherein the insulating sealant partially covers the side wall of the internal wiring structure. The protective layer is placed on the second surface of the internal wiring structure and partially covers the side wall of the internal wiring structure, wherein the protective layer is in contact with the insulating sealant. The electrical connector is placed on the protective layer, wherein the internal wiring structure is electrically connected to the circuit substrate through the plurality of electrical connectors.

[0004] Some other embodiments of the present disclosure provide a packaging structure including a circuit substrate, an interposer structure, at least one semiconductor die, an insulating sealant, and a polymer layer. The interposer structure is disposed on the circuit substrate, wherein the interposer structure includes a core substrate and a plurality of through holes formed in the core substrate. The semiconductor die is disposed on the back surface of the interposer structure, wherein the at least one semiconductor die is electrically connected to the plurality of through holes. The insulating sealant is disposed on the back surface of the interposer structure and covers the semiconductor die. The polymer layer is disposed on the top surface of the interposer structure, wherein the polymer layer includes a central portion and a side portion connected to the central portion, the central portion covers the top surface of the interposer structure and contacts the top surface of the interposer structure, and the side portion protrudes from the central portion and surrounds the interposer structure.

[0005] Another embodiment of the present disclosure describes a method for manufacturing a package structure. The method includes forming a semiconductor device by the following steps. An interconnect structure having a device area and a segmentation area surrounding the device area is provided. A semiconductor die is arranged on a first surface of the interconnect structure in the device area, wherein the semiconductor die is electrically connected to the interconnect structure. A first groove is formed on the first surface of the interconnect structure in the segmentation area, wherein the first groove surrounds the semiconductor die. An insulating seal is formed above the device area and the segmentation area on the first surface of the interconnect structure, wherein the insulating seal seals the semiconductor die and fills the first groove. A first segmentation process is performed by removing a portion of the interconnect structure and a portion of the insulating seal to form a second groove on a second surface of the interconnect structure in the segmentation area, the second surface being opposite to the first surface. A protective layer is formed above the device area and the segmentation area on the second surface of the interconnect structure, wherein the protective layer fills the second groove and contacts the insulating seal. A plurality of electrical connectors are formed on the protective layer, wherein the plurality of electrical connectors are electrically connected to the interconnect structure. The semiconductor device is placed on the circuit substrate, wherein the semiconductor device is electrically connected to the circuit substrate through the plurality of electrical connections. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the present disclosure are best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the critical dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figures 1A to 1K are schematic cross-sectional views of various stages in a method of fabricating a semiconductor device according to some exemplary embodiments of the present disclosure.

[0008] Figure 2A to Figure 2C are schematic cross-sectional views of various stages in a method of fabricating a semiconductor device according to some other exemplary embodiments of the present disclosure.

[0009] Figures 3A to 3D are schematic cross-sectional views of various stages in a method of fabricating a semiconductor device according to some other exemplary embodiments of the present disclosure.

[0010] Figure 4A and Figure 4Bare schematic cross-sectional views of various stages in a method of manufacturing a package structure according to some exemplary embodiments of the present disclosure.

[0011] Figure 5 is a schematic cross-sectional view of a package structure according to some other exemplary embodiments of the present disclosure.

[0012] Description of Figure Numbers

[0013] 21, 22: semiconductor die;

[0014] 21S, 22S: dorsal surface;

[0015] 100: Intermediary layer structure;

[0016] 102: core substrate;

[0017] 102a: first surface;

[0018] 102b: second surface;

[0019] 104: through hole;

[0020] 106: conductive pad;

[0021] 110: conductive bump;

[0022] 112, 410: bottom filler structure;

[0023] 114: Insulation seal;

[0024] 114-1: Part I;

[0025] 114-1S, 114-3S: flat top surface;

[0026] 114-2: second protruding part;

[0027] 114-2S: beveled top surface;

[0028] 114-3: third protruding part;

[0029] 114a, 114b: surface;

[0030] 116, 117: protective layer;

[0031] 116A, 117A: polymer layer / dielectric material layer;

[0032] 116A-1, 117A-1: center part;

[0033] 116A-2, 117A-2: side part;

[0034] 116B, 117B: conductive pattern;

[0035] 118: electrical connector;

[0036] 210, 220: main body;

[0037] 211, 221: active surface;

[0038] 212, 222: connecting pads;

[0039] 300: circuit substrate;

[0040] 310, 320: contact pads;

[0041] 330: metallization layer;

[0042] 340: Conductive ball;

[0043] 350: Passive components;

[0044] BVP: bevel portion;

[0045] CR: carrier;

[0046] DR: division region;

[0047] DV: device area;

[0048] FR: frame;

[0049] PK1, PK2: packaging structure;

[0050] SM1, SM2, SM3: semiconductor devices;

[0051] T1, T2: thickness;

[0052] TP: belt;

[0053] TR1: first groove;

[0054] TR2: Second groove. DETAILED DESCRIPTION

[0055] The following disclosure provides many different embodiments for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, a second feature is formed above or on a first feature, which may include an embodiment in which the second feature is formed in direct contact with the first feature, and may also include an embodiment in which an additional feature is formed between the second feature and the first feature so that the second feature may not be in direct contact with the first feature. In addition, the present disclosure may repeat figure numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0056] Additionally, for ease of description, spatially relative terms, such as "below," "beneath," "lower," "on," "over," "overlying," "above," "upper," and the like, may be used herein to describe the relationship of one element or feature to another element or feature illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0057] Other features and processes may also be included. For example, a test structure may be included to assist in verification testing of a 3D package or 3DIC device. The test structure may include, for example, a test pad formed in a redistribution layer or on a substrate that allows testing of the 3D package or 3DIC, the use of probes and / or probe cards, and the like. Verification testing may be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein may be used in conjunction with test methods that incorporate intermediate verification of known good dies to increase yield and reduce costs.

[0058] Figure 1A to Figure 1K Schematic cross-sectional views of various stages in a method of manufacturing a semiconductor device according to some exemplary embodiments of the present disclosure. Figure 1A , an interposer structure 100 (or an internal wiring structure) is provided. In some embodiments, the interposer structure 100 (or an internal wiring structure) includes a core substrate 102, and a plurality of through holes 104 and a conductive pad 106 formed therein. In some embodiments, the core substrate 102 may be a substrate such as a bulk semiconductor substrate, an SOI substrate, or a multilayer semiconductor material substrate. The semiconductor material of the substrate (core substrate 102) may be silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or a combination thereof. In some embodiments, the core substrate 102 may be doped or undoped.

[0059] In some embodiments, a conductive pad 106 is formed on a first surface 102a of the core substrate 102 (the first surface 102a of the interposer structure 100). In some embodiments, a via 104 is formed in the core substrate 102 and is connected to the conductive pad 106. In some embodiments, the via 104 extends into the core substrate 102 to a specific depth. In some embodiments, the via 104 is a substrate via. In some embodiments, when the core substrate 102 is a silicon substrate, the via 104 is a silicon via. In some embodiments, the via 104 can be formed by forming a hole or recess in the core substrate 102 and then filling the recess with a conductive material. In some embodiments, the recess can be formed by, for example, etching, milling, laser drilling, or the like. In some embodiments, the conductive material can be formed by an electrochemical plating process, chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD), and the conductive material can include copper, tungsten, aluminum, silver, gold, or a combination thereof. In some embodiments, the conductive pad 106 connected to the via 104 can be formed as a conductive portion of a redistribution layer formed on the interposer structure 100. In some embodiments, the conductive pad 106 includes under bump metallurgy (UBM). In certain embodiments, the interposer structure 100 can further include active or passive devices formed in the core substrate 102, such as transistors, capacitors, resistors, or diode passive devices.

[0060] As Figure 1A shown, the core substrate 102 has a plurality of device regions DV and partitioning regions DR separating each of the plurality of device regions DV. The via 104 and the conductive pad 106 are formed in the core substrate 102 within the device region DV. In some embodiments, semiconductor die 21 and semiconductor die 22 are disposed on the interposer structure 100 (interconnection structure), or on the core substrate 102 within the device region DV. For example, the semiconductor die 21 and the semiconductor die 22 are placed on the first surface 102a of the interposer structure 100. The semiconductor die 21 and the semiconductor die 22 are individual dies singulated from a wafer. In some embodiments, the semiconductor die 21 contains the same circuitry, such as devices and metallization patterns, or the semiconductor die 21 is the same type of die. In some embodiments, the semiconductor die 22 contains the same circuitry, or the semiconductor die 22 is the same type of die. In certain embodiments, the semiconductor die 21 and the semiconductor die 22 have different circuitry or are different types of dies. In alternative embodiments, the semiconductor die 21 and the semiconductor die 22 can have the same circuitry.

[0061] In some embodiments, semiconductor die 21 may be a main die, and semiconductor die 22 may be a branch die. In some embodiments, the main die is arranged on the core substrate 102 in the center position of each device region DV, and the branch die is arranged side by side and spaced apart from the main die. In some embodiments, the branch die is arranged next to the main die and surrounds or surrounds the main die. In one embodiment, four or six branch dies are arranged around one main die per device region DV. However, the number of semiconductor dies positioned on the interposer structure 100 is not limited thereto, and the number may be adjusted based on product requirements. For example, in an alternative embodiment, the number of dies positioned on the interposer structure 100 may be one or more than one.

[0062] Return to reference Figure 1A , semiconductor die 21 has a surface area greater than the surface area of ​​semiconductor die 22. In addition, in some embodiments, semiconductor die 21 and semiconductor die 22 may be of different sizes, including different surface areas and / or different thicknesses. In some embodiments, semiconductor die 21 may be a logic die, including a central processing unit (CPU) die, a graphics processing unit (GPU) die, a system-on-a-chip (SoC) die, a microcontroller, or the like. In some embodiments, semiconductor die 21 is a power management die such as a power management integrated circuit (PMIC) die. In some embodiments, semiconductor die 22 may be a memory die, including a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, or a high bandwidth memory (HBM) die. The present disclosure is not limited thereto, and the number, size, and type of semiconductor dies disposed on core substrate 102 may be appropriately adjusted based on product requirements.

[0063] In the illustrated embodiment, semiconductor die 21 includes a body 210 and connection pads 212 formed on an active surface 211 of body 210. In certain embodiments, connection pads 212 may further include pillar structures for bonding semiconductor die 21 to other structures. In some embodiments, semiconductor die 22 includes a body 220 and connection pads 222 formed on an active surface 221 of body 220. In other embodiments, connection pads 222 may further include pillar structures for bonding die 22 to other structures.

[0064] In some embodiments, the semiconductor die 21 and the semiconductor die 22 are attached to the first surface 102a of the core substrate 102, for example, by flip chip bonding with the aid of conductive bumps 110. Through the reflow process, the conductive bumps 110 are formed between the connection pads 212, the connection pads 222 and the conductive pads 106, so that the semiconductor die 21 and the semiconductor die 22 are electrically connected and physically connected to the core substrate 102 of the interposer structure 100. In some embodiments, the conductive bumps 110 are positioned between the semiconductor die 21, the semiconductor die 22 and the interposer structure 100 (or the interconnect structure). In certain embodiments, the semiconductor die 21 and the semiconductor die 22 are electrically connected to the through-holes 104 and the conductive pads 106 through the conductive bumps 110. In one embodiment, the conductive bumps 110 are micro-bumps, for example, micro-bumps having copper metal pillars. In another embodiment, the conductive bump 110 is a solder bump, a lead-free solder bump, or a microbump, such as a controlled collapse chip connection (C4) bump or a microbump containing a copper pillar. In some embodiments, the bond between the semiconductor die 21, the semiconductor die 22 and the core substrate 102 may be a solder bond. In some embodiments, the bond between the semiconductor die 21, the semiconductor die 22 and the core substrate 102 may be a direct metal-to-metal bond, such as a copper-to-copper bond.

[0065] refer to Figure 1BIn the next step, a bottom filler structure 112 may be formed to cover the plurality of conductive bumps 110 and fill the space between the semiconductor die 21, the semiconductor die 22 and the interposer structure 100. In some embodiments, the bottom filler structure 112 further covers the sidewalls of the semiconductor die 21, the semiconductor die 22 and is positioned in the device region DV. After the semiconductor die 21, the semiconductor die 22 are arranged and the bottom filler structure 112 is formed to protect the conductive bumps 110, the first trench TR1 is formed on the first surface 102a of the interposer structure 100 (internal wiring structure) in the segmentation region DR. In an exemplary embodiment, the first trench TR1 surrounds the semiconductor die 21, the semiconductor die 22. For example, from a top view (not shown) of the interposer structure 100, the semiconductor die 21, the semiconductor die 22 may be confined in the space surrounded by the first trench TR1. In some embodiments, the first trench TR1 may be formed by a laser cutting process, a mechanical sawing process, or other suitable processes. The present disclosure is not limited thereto.

[0066] refer to Figure 1C After forming the first trench TR1, an insulating sealant 114 is formed over the device region DV and the segmentation region DR on the first surface 102a of the interposer structure 100 (internal wiring structure). For example, the insulating sealant 114 is formed over the interposer structure 100 to seal the semiconductor die 21 and the semiconductor die 22, and fills into the first trench TR1. The insulating sealant 114 may further cover the bottom filler structure 112. In some embodiments, the insulating sealant 114 may have a first portion 114-1 surrounding the semiconductor die 21 and the semiconductor die 22, and a second protruding portion 114-2 surrounding the first portion 114-1 and partially surrounding the interposer structure 100. In some embodiments, the first portion 114-1 is positioned in the device region DV, and the second portion 114-2 is positioned in the segmentation region DR and fills into the first trench TR1.

[0067] In addition, in some embodiments, the insulating seal 114 is formed by, for example, a compression molding process or a transfer molding process. In one embodiment, a curing process is performed to cure the insulating seal 114. In some embodiments, the semiconductor die 21, the semiconductor die 22, and the conductive bump 110 are sealed by the insulating seal 114. In some embodiments, a planarization process including grinding or polishing may be performed to partially remove the insulating seal 114, thereby exposing the back side surfaces 21S and 22S of the semiconductor die 21 and the semiconductor die 22. Therefore, the back side surfaces 21S and 22S of the semiconductor die 21 and the semiconductor die 22 are flush with the surface 114a of the insulating seal 114. The surface 114a is opposite to the surface 114b of the insulating seal 114, wherein the surface 114b is in contact with the core substrate 102.

[0068] In some embodiments, the material of the insulating seal 114 includes a polymer (e.g., epoxy resin, phenolic resin, silicone resin or other suitable resin), a dielectric material with low dielectric constant (Dk) and low loss tangent (Df) properties, or other suitable materials. In alternative embodiments, the insulating seal 114 may include an acceptable insulating sealing material. In some embodiments, the insulating seal 114 may further include an inorganic filler or an inorganic compound (e.g., silicon dioxide, clay, etc.) that can be added thereto to optimize the coefficient of thermal expansion (CTE) of the insulating seal 114. The present disclosure is not limited thereto.

[0069] refer to Figure 1D ,Will Figure 1C The structure shown in FIG. 1 is turned upside down or flipped and placed on a carrier CR such that the carrier CR directly contacts the semiconductor die 21, the backside surface 21S of the semiconductor die 22, the backside surface 22S of the semiconductor die 22, and the surface 114a of the insulating seal 114. Figure 1C As shown in FIG. 1 , at this process stage, the interposer structure 100 (interconnect structure) has not been thinned and has a thickness T1 . In other words, the through-holes 104 are not exposed and are embedded in the core substrate 102 of the interposer structure 100 .

[0070] refer to Figure 1E , a thinning process is performed on the interposer structure 100 to partially remove or thin the core substrate 102 of the interposer structure 100 until the through hole 104 is exposed and the second surface 102b of the core substrate 102 is formed. In some embodiments, the thinning process may include a back grinding process, a polishing process, or an etching process. In some embodiments, after the thinning process, the interposer structure 100 is thinned to a thickness T2. In some embodiments, the ratio of the thickness T2 to the thickness T1 is in the range of about 0.1 to about 0.5.

[0071] refer to Figure 1F In the next step, a first segmentation process is performed by removing a portion of the interposer structure 100 (interconnect structure) and a portion of the insulating sealant 114 to form a second trench TR2 on the second surface 102b of the interposer structure 100 in the segmentation region DR. In some embodiments, the second protruding portion 114-2 of the insulating sealant 114 and the corner of the core substrate 102 are partially removed to form the second trench TR2. Figure 1F, the second trench TR2 is a bevel groove having a V-shaped profile (when viewed from a cross section). In some embodiments, the corner of the core substrate 102 is removed so that the core substrate 102 includes a bevel portion BVP. In addition, the second protruding portion 114-2 of the insulating seal 114 is removed so that the insulating seal 114 has a bevel top surface 114-2S. For example, the bevel top surface 114-2S is aligned with the surface of the bevel portion BVP. In some embodiments, the first portion 114-1 of the insulating seal 114 has a planar top surface 114-1S in contact with the first surface 102a (or backside surface) of the interposer structure 100.

[0072] refer to Figure 1G After forming the second trench TR2, a protective layer 116 is formed above the device region DV and the segmentation region DR on the second surface 102b (or top surface) of the interposer structure 100. In an exemplary embodiment, the protective layer 116 includes a polymer layer or a dielectric material layer 116A. For example, the polymer layer or the dielectric material layer 116A fills the second trench TR2 and is in physical contact with the insulating seal 114. In some embodiments, the polymer layer or the dielectric material layer 116A covers the bevel portion BVP of the core substrate 102 and covers the second protruding portion 114-2 (bevel top surface 114-2S) of the insulating seal 114. The polymer layer or the dielectric material layer 116A may be a polyimide layer, a polybenzoxazole (PBO) layer, a benzocyclobutene (BCB) layer, or other suitable polymer or dielectric layer. In some embodiments, the polymer layer or the dielectric material layer 116A and the core substrate 102 are made of different materials. In some embodiments, the polymer layer or dielectric material layer 116A may be formed by spin coating or deposition, including chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), high-density plasma CVD (HDP-CVD), or the like.

[0073] refer to Figure 1HIn the next step, the polymer layer or dielectric material layer 116A may be patterned using photolithography and one or more etching processes to form openings that expose the through-holes 104. Subsequently, a plurality of conductive patterns 116B may be filled in the openings and electrically connected to the through-holes 104. Any excess conductive material on the dielectric material layer 116A may be removed, for example, by using a chemical mechanical polishing process. In an exemplary embodiment, the dielectric material layer 116A and the conductive pattern 116B together constitute the protective layer 116. In some embodiments, the conductive pattern 116B is embedded in the dielectric material layer 116A. In some embodiments, the conductive pattern 116B includes copper, aluminum, tungsten, silver, or a combination thereof.

[0074] like Figure 1H As further shown in , a plurality of electrical connectors 118 are disposed on the conductive pattern 116B and electrically coupled to the through-hole 104. In some embodiments, the electrical connector 118 is placed on the top surface of the protective layer 116 and is electrically connected to the through-hole 104 through the conductive pattern 116B in the device region DV. In certain embodiments, the electrical connector 118 is located on the conductive pattern 116B and is physically attached to the conductive pattern 116B. In some embodiments, the electrical connector 118 includes a lead-free solder ball, a solder ball, a ball grid array package (BGA) ball, a bump, a C4 bump, or a microbump. In some embodiments, the electrical connector 118 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or a combination thereof. In some embodiments, the electrical connector 118 is formed by forming a solder paste on the protective layer 116 by, for example, evaporation, electroplating, printing, or solder transfer and then reflowing into a desired bump shape. In some embodiments, the electrical connector 118 is placed on the protective layer 116 by ball planting or the like. In other embodiments, the electrical connector 118 is formed by forming a solder-free metal pillar (e.g., a copper pillar) by sputtering, printing, electroless plating or electroplating or CVD and then forming a lead-free cap layer by electroplating on the metal pillar. The electrical connector 118 can be used to bond to external devices or additional electrical components. In some embodiments, the electrical connector 118 is used to bond to a circuit substrate, a semiconductor substrate, or a packaging substrate.

[0075] like Fig. 1I As shown in FIG, in a subsequent step, the carrier CR is peeled off. For example, the peeling process includes projecting light (such as laser or UV light) on a peeling layer (such as a light-to-heat conversion release layer) (not shown) attached to the carrier CR so that the carrier CR can be easily removed together with the peeling layer. Figure 1J As shown in FIG. , after the carrier CR is peeled off, Fig. 1IThe structure shown in FIG. 1 is attached to a tape TP (e.g., a dicing tape) supported by a frame FR. Subsequently, a second dicing process is performed to cut through the protective layer 116 and the insulating seal 114 in the dicing region DR. In some embodiments, the dicing process or singulation process generally involves dicing with a rotating blade or a laser beam. In other words, the dicing or singulation process is, for example, a laser cutting process, a mechanical sawing process, or other suitable process. After the second dicing process, the Figure 1K The individualized semiconductor component SM1 shown in FIG.

[0076] like Figure 1K As shown in , after the second singulation process, the insulating seal 114 is formed to partially cover the sidewalls of the interposer structure 100 (internal wiring structure), and the protective layer 116 partially covers the remaining sidewalls of the interposer structure 100. In some embodiments, the protective layer 116 or the polymer layer / dielectric material layer 116A is formed with a central portion 116A-1 and a side portion 116A-2 connected to the central portion 116A-1. In some embodiments, the central portion 116A-1 is formed to cover and physically contact the second surface 102b (top surface) of the interposer structure 100 (internal wiring structure). In certain embodiments, the side portion 116A-2 surrounds the central portion 116A-1 and protrudes from the central portion 116A-1. In addition, the side portion 116A-2 of the protective layer 116 covers and physically contacts the bevel portion BVP of the core substrate 102.

[0077] like Figure 1K As further shown in , in the singulated semiconductor device SM1, the first portion 114-1 of the insulating sealant 114 surrounds the semiconductor die 21, the semiconductor die 22, and the second protruding portion 114-2 surrounds the first portion 114-1 and partially surrounds the interposer structure 100 (internal wiring structure). In some embodiments, the first portion 114-1 of the insulating sealant 114 has a planar top surface 114-1S in contact with the core substrate 102 of the interposer structure 100 (internal wiring structure), and the second protruding portion 114-2 of the insulating sealant 114 has a beveled top surface 114-2S in contact with the side portion 116A-2 of the protective layer 116. In addition, the side surface of the side portion 116A-2 of the protective layer 116 is aligned with the side surface of the second protruding portion 114-2 of the insulating sealant 114. At this point, the semiconductor device SM1 according to some exemplary embodiments is completed.

[0078] Figure 2A to Figure 2C are schematic cross-sectional views of various stages in a method of fabricating a semiconductor device according to some other exemplary embodiments of the present disclosure. Figure 2A to Figure 2C The method shown in is similar to Figure 1A to Figure 1KTherefore, the same reference numerals will be used to refer to the same or similar components, and detailed descriptions thereof will not be repeated herein. The difference between the methods lies in the design of the protective layer (protective layer 116 / protective layer 117).

[0079] like Figure 1H As shown in FIG, the protective layer 116 is illustrated as including one layer of polymer layer / dielectric material layer 116A and one layer of conductive pattern 116B. However, the present disclosure is not limited thereto, and the number of polymer layer / dielectric material layer 116A and conductive pattern 116B may be adjusted based on product requirements.

[0080] For example, if Figure 2A As shown in Figure 1F After the step of forming the second trench TR2 shown in FIG. 1 , a protective layer 117 having multiple layers of a plurality of polymer layers / dielectric material layers 117A and conductive patterns 117B alternately stacked is formed over the interposer structure 100. In some embodiments, the polymer layer / dielectric material layer 117A is formed to fill in the second trench TR2. In some embodiments, the conductive pattern 117B may include a pad, a via, and / or a trace to internally connect the through hole 104 of the interposer structure 100. In certain embodiments, the protective layer 117 is a redistribution layer that electrically connects the semiconductor die 21, the semiconductor die 22, and the through hole 104 to one or more external devices. The materials of the polymer layer / dielectric material layer 117A and the conductive pattern 117B are similar to the above-mentioned polymer layer / dielectric material layer 116A and the conductive pattern 116B. Therefore, the details thereof are omitted herein.

[0081] refer to Figure 2B After forming the protective layer 117, Figure 1H to Figure 1J The same steps as described in the above are performed. For example, a plurality of electrical connectors 118 are disposed on the conductive pattern 117B and are electrically coupled to the through-holes 104 through the conductive pattern 117B. Subsequently, the carrier CR can be peeled off, and the entire structure is attached to a tape TP (e.g., a dicing tape) supported by a frame FR. Subsequently, a dicing process (a second dicing process) is performed to cut through the protective layer 117 and the insulating seal 114 in the dicing region DR. For example, the dicing process can cut through the plurality of polymer layers / dielectric material layers 117A. After the dicing process, a Figure 2C The individualized semiconductor component SM2 shown in FIG.

[0082] like Figure 2CAs shown in , in the singulated semiconductor device SM2, the insulating seal 114 is formed to partially cover the sidewalls of the interposer structure 100 (internal wiring structure), and the protective layer 117 (bottommost polymer layer / dielectric material layer 117A) partially covers the remaining sidewalls of the interposer structure 100. In some embodiments, the protective layer 117 or the bottommost polymer layer / dielectric material layer 117A is formed with a central portion 117A-1 and a side portion 117A-2 connected to the central portion 117A-1. In some embodiments, the central portion 117A-1 is formed to cover and physically contact the second surface 102b (top surface) of the interposer structure 100 (internal wiring structure). In some embodiments, the side portion 117A-2 surrounds the central portion 117A-1 and protrudes from the central portion 117A-1. In addition, the side portion 117A-2 of the protective layer 117 covers and physically contacts the bevel portion BVP of the core substrate 102.

[0083] Similarly, if Figure 2C As further shown in , the first portion 114-1 of the insulating sealant 114 surrounds the semiconductor die 21, the semiconductor die 22, and the second protruding portion 114-2 surrounds the first portion 114-1 and partially surrounds the interposer structure 100 (internal wiring structure). In some embodiments, the first portion 114-1 of the insulating sealant 114 has a planar top surface 114-1S in contact with the core substrate 102 of the interposer structure 100 (internal wiring structure), and the second protruding portion 114-2 of the insulating sealant 114 has a beveled top surface 114-2S in contact with the side portion 117A-2 of the protective layer 117. In addition, the side surface of the side portion 117A-2 of the protective layer 117 is aligned with the side surface of the second protruding portion 114-2 of the insulating sealant 114. At this point, the semiconductor device SM2 according to some exemplary embodiments is completed.

[0084] Figures 3A to 3D are schematic cross-sectional views of various stages in a method of fabricating a semiconductor device according to some other exemplary embodiments of the present disclosure. Figures 3A to 3D The method shown in is similar to Figure 1A to Figure 1K Therefore, the same reference numerals will be used to refer to the same or similar components, and detailed descriptions thereof will not be repeated herein. The difference between the methods lies in the design of the interposer structure 100.

[0085] exist Figure 1G In the embodiment shown in , the second trench TR2 is formed by removing the corner of the core substrate 102 so that the core substrate 102 includes the bevel portion BVP. However, the present disclosure is not limited thereto. Figure 3AIn the alternative embodiment illustrated in , the second trench TR2 is formed by removing a portion of the core substrate 102 through a first segmentation process, so that the interposer structure 100 includes a bevel portion BVP protruding from the core substrate 102. Moreover, in an exemplary embodiment, in addition to having the first portion 114-1 and the second protruding portion 114-2, the insulating seal 114 may further include a third protruding portion 114-3 positioned between the first portion 114-1 and the second portion 114-2 in the segmentation region DR. In some embodiments, the second trench TR2 is formed by partially removing the second protruding portion 114-2 in the segmentation region DR while retaining the first portion 114-1 and the third protruding portion 114-3.

[0086] refer to Figure 3A , after the first singulation process, the first portion 114-1 of the insulating seal 114 has a planar top surface 114-1S in contact with the first surface 102a (or backside surface) of the interposer structure 100. The second protruding portion 114-2 has a beveled top surface 114-2S aligned with the surface of the bevel portion BVP. In addition, the third protruding portion 114-3 couples the first portion 114-1 to the second protruding portion 114-2 and has a planar top surface 114-3S in contact with the surface of the protruding bevel portion BVP of the interposer structure 100.

[0087] refer to Figure 3B After forming the second trench TR2, Figure 1G to Figure 1J For example, a protection layer 116 including a polymer layer or a dielectric material layer 116A and a conductive pattern 116B embedded in the polymer layer or the dielectric material layer 116A may be formed over the interposer structure 100. Subsequently, a plurality of electrical connectors 118 are disposed on the conductive pattern 116B and electrically coupled to the through-holes 104 through the conductive pattern 116B.

[0088] refer to Figure 3C In the next step, the carrier CR may be peeled off and the entire structure may be attached to a tape TP (e.g., a dicing tape) supported by a frame FR. Subsequently, a dicing process (a second dicing process) is performed to cut through the protective layer 116 and the insulating seal 114 in the dicing region DR. For example, the dicing process may cut through the polymer layer / dielectric material layer 116A of the protective layer 116 and the second protruding portion 114-2 of the insulating seal 114. After the dicing process, a Figure 3D The individualized semiconductor component SM3 shown in FIG.

[0089] like Figure 3DAs shown in , in the singulated semiconductor device SM3, the insulating seal 114 (third protruding portion 114-3) is formed to partially cover the sidewalls of the interposer structure 100 (internal wiring structure), and the protective layer 116 covers the remaining sidewalls of the interposer structure 100 (the sidewalls of the bevel portion BVP). In some embodiments, the protective layer 116 is formed with a central portion 116A-1 and a side portion 116A-2 connected to the central portion 116A-1. In some embodiments, the central portion 116A-1 is formed to cover and physically contact the second surface 102b (top surface) of the interposer structure 100 (internal wiring structure). In certain embodiments, the side portion 116A-2 surrounds the central portion 116A-1 and protrudes from the central portion 116A-1. In addition, the side portion 116A-2 of the protective layer 116 covers and physically contacts the protruding bevel portion BVP of the interposer structure 100.

[0090] Similarly, if Figure 3D As further shown in , the first portion 114-1 of the insulating seal 114 surrounds the semiconductor die 21, the semiconductor die 22, and the second protruding portion 114-2 surrounds the first portion 114-1 and partially surrounds the interposer structure 100 (internal connection structure). In addition, the third protruding portion 114-3 is positioned between the first portion 114-1 and the second protruding portion 114-2, thereby partially surrounding the interposer structure 100 and bonding the first portion 114-1 to the second protruding portion 114-2. In some embodiments, the first portion 114-1 of the insulating seal 114 has a planar top surface 114-1S in contact with the core substrate 102 of the interposer structure 100 (internal connection structure), and the second protruding portion 114-2 of the insulating seal 114 has a beveled top surface 114-2S in contact with the side portion 116A-2 of the protective layer 116. In some embodiments, the side surface of the side portion 116A-2 of the protective layer 116 is aligned with the side surface of the second protruding portion 114-2 of the insulating sealing body 114. In addition, the third protruding portion 114-3 has a planar top surface 114-3S in contact with the surface of the protruding bevel portion BVP. The planar top surface 114-3S has a step height difference with the planar top surface 114-1S, and the planar top surface 114-3S is combined with the bevel top surface 114-2S. At this point, the semiconductor device SM3 according to some exemplary embodiments is completed.

[0091] Figure 4A and Figure 4B Schematic cross-sectional views of various stages in a method of manufacturing a package structure according to some exemplary embodiments of the present disclosure. Figure 4A As shown in FIG. , in an exemplary embodiment, Figure 1KThe semiconductor device SM1 obtained in the embodiment is mounted or attached to the circuit substrate 300 through the electrical connector 118. In some embodiments, the circuit substrate 300 includes a contact pad 310, a contact pad 320, a metallization layer 330, and a through hole (not shown). In some embodiments, the contact pad 310 and the contact pad 320 are respectively distributed on two opposite sides of the circuit substrate 300 and are exposed for electrical connection with the elements / features formed later. In some embodiments, the metallization layer 330 and the through hole are embedded in the circuit substrate 300 and together provide a wiring function for the circuit substrate 300, wherein the metallization layer 330 and the through hole are electrically connected to the contact pad 310 and the contact pad 320. In other words, at least some of the contact pads 310 are electrically connected to some of the contact pads 320 through the metallization layer 330 and the through hole. In some embodiments, the contact pad 310 and the contact pad 320 may include a metal pad or a metal alloy pad. In some embodiments, the material of the metallization layer 330 and the vias may be substantially the same or similar to the material of the contact pads 310 and 320 .

[0092] In an exemplary embodiment, if Figure 4A As shown in , the semiconductor device SM1 is bonded to the circuit substrate 300 by physically connecting the electrical connector 118 and the contact pad 310 to form a stacked structure, wherein the semiconductor device SM1 is physically and electrically connected to the circuit substrate 300. In some embodiments, the circuit substrate 300 is, for example, an organic flexible substrate or a printed circuit board. In such embodiments, the electrical connector 118 is, for example, a chip connector. In some embodiments, a plurality of conductive balls 340 are respectively formed on the substrate 300. For example, as Figure 4A As shown in , the conductive balls 340 are connected to the contact pads 320 of the circuit substrate 300. In other words, the conductive balls 340 are electrically connected to the circuit substrate 300 through the contact pads 320. Some of the conductive balls 340 are electrically connected to the semiconductor device SM1 (e.g., the semiconductor die 21 and the semiconductor die 22 included in the semiconductor device SM1) through the contact pads 310 and the contact pads 320. In some embodiments, the conductive balls 340 are, for example, solder balls or BGA balls. In some embodiments, the semiconductor device SM1 is bonded to the circuit substrate 300 by physically connecting the electrical connectors 118 and the contact pads 310 of the circuit substrate 300 via a chip on wafer on substrate (CoWoS) packaging process. In addition, as shown in FIG. Figure 4A As shown in FIG. 3 , one or more passive components 350 (or integrated passive devices) may be mounted on the circuit substrate 300. For example, the passive components 350 may be mounted on the contact pads 310 of the circuit substrate 300 by a soldering process. The present disclosure is not limited thereto.

[0093] refer to Figure 4B In the next step, a bottom filler structure 410 is formed to fill the space between the circuit substrate 300 and the semiconductor device SM1. In some embodiments, the bottom filler structure 410 fills the space between adjacent electrical connectors 118 and covers the electrical connectors 118. In some embodiments, the bottom filler structure 410 covers the protective layer 116 and is in physical contact with the protective layer 116. In some embodiments, the bottom filler structure 410 further covers and physically contacts the sidewalls of the insulating seal 114. In addition, the bottom filler structure 410 is physically separated from the interposer structure 100. In other words, the interposer structure 100 (or the interconnect structure) is isolated from the semiconductor device SM1 by the protective layer 116 and the insulating seal 114, and is not exposed at the outer surface of the semiconductor device SM1. In addition, the passive component 350 is exposed through the bottom filler structure 410 and maintains a spacing distance from the bottom filler structure 410. In other words, the bottom filler structure 410 does not cover the passive component 350. At this point, the package structure PK1 according to some embodiments of the present disclosure is completed.

[0094] In an exemplary embodiment, since the package structure PK1 includes an insulating seal 114 and a protective layer 116 surrounding and isolating the interposer structure 100 (or an interconnect structure), the interposer structure 100 can be protected from external components. For example, when the interposer structure 100 is a silicon interposer (with a coefficient of thermal expansion (CTE) of ˜2.5 ppm / ° C.), and when the underfill structure 410 is a thermosetting epoxy material (with a CTE of 20 ppm / ° C. to 65 ppm / ° C.), if the interposer structure 100 and the underfill structure 410 are brought into contact with each other, delamination problems and cracks on the underfill structure 410 may be observed due to the CTE mismatch of the materials used. On the other hand, in some embodiments, when the interposer structure 100 is protected by at least a protective layer 116 (e.g., a polyimide having a CTE of 20 ppm / °C to 100 ppm / °C), since the bottom filler structure 410 is in contact with the protective layer 116 having a similar CTE, delamination problems and cracks on the bottom filler structure 410 caused by CTE mismatch can be solved.

[0095] Figure 5 is a schematic cross-sectional view of a package structure according to some other exemplary embodiments of the present disclosure. Figure 5 The package structure PK2 shown in FIG. 1 is similar to Figure 4B Therefore, the same reference numerals are used to refer to the same or similar components, and their detailed descriptions will not be repeated herein. The differences between these packaging structures are Figure 5 In the embodiment, the semiconductor device SM2 is used instead of the semiconductor device SM1.

[0096] like Figure 5 As shown in Figure 2C The semiconductor device SM2 obtained is mounted or attached to the circuit substrate 300 through the electrical connector 118. Subsequently, a bottom filler structure 410 is formed to fill the space between the circuit substrate 300 and the semiconductor device SM2. In some embodiments, the bottom filler structure 410 covers the protective layer 117 and is in physical contact with the protective layer 117. For example, the bottom filler structure 410 covers and contacts the sidewalls of multiple polymer layers / dielectric material layers 117A. In some embodiments, the bottom filler structure 410 further covers and physically contacts the sidewalls of the insulating seal 114. In a similar manner, the bottom filler structure 410 is physically separated from the interposer structure 100. In other words, the interposer structure 100 (or the interconnect structure) is isolated from the semiconductor device SM2 by the protective layer 117 and the insulating seal 114, and is not exposed at the outer surface of the semiconductor device SM2. At this point, the package structure PK2 according to some embodiments of the present disclosure is completed.

[0097] In the above-mentioned embodiment, since the package structure includes a semiconductor device having an insulating sealant and a protective layer surrounding and covering the sidewalls of the interposer structure (internal connection structure), a protected interposer structure can be realized. Therefore, the interposer structure can be isolated (or physically separated) from the bottom filler structure used in the subsequent steps. Therefore, the delamination problem and cracks on the bottom filler structure caused by the mismatch in the coefficient of thermal expansion (CTE) of the material used for the internal connection structure and the bottom filler structure can be solved. In general, a package structure with better reliability can be obtained.

[0098] According to some embodiments of the present disclosure, a packaging structure includes a circuit substrate and a semiconductor device. The semiconductor device is disposed on the circuit substrate and electrically connected to the circuit substrate. The semiconductor device includes an internal wiring structure, a semiconductor die, an insulating sealant, a protective layer, and a plurality of electrical connectors. The internal wiring structure has a first surface and a second surface opposite to the first surface. The semiconductor die is disposed on the first surface and electrically connected to the internal wiring structure. The insulating sealant is disposed on the first surface of the internal wiring structure and seals the semiconductor die, wherein the insulating sealant partially covers the sidewalls of the internal wiring structure. The protective layer is disposed on the second surface of the internal wiring structure and partially covers the sidewalls of the internal wiring structure, wherein the protective layer is in contact with the insulating sealant. The electrical connector is disposed on the protective layer, wherein the internal wiring structure is electrically connected to the circuit substrate through the plurality of electrical connectors.

[0099] In some embodiments, the first portion of the insulating seal has a planar top surface in contact with the interconnect structure, and the second protruding portion of the insulating seal has a beveled top surface in contact with the protective layer. In some embodiments, the protective layer includes a dielectric material layer and a conductive pattern embedded in the dielectric material layer, and the conductive pattern is electrically connected to the interconnect structure and the plurality of electrical connectors.

[0100] According to some other embodiments of the present disclosure, a packaging structure includes a circuit substrate, an interposer structure, at least one semiconductor die, an insulating sealant, and a polymer layer. The interposer structure is disposed on the circuit substrate, wherein the interposer structure includes a core substrate and a plurality of through holes formed in the core substrate. The semiconductor die is disposed on the back surface of the interposer structure, wherein the at least one semiconductor die is electrically connected to the plurality of through holes. The insulating sealant is disposed on the back surface of the interposer structure and covers the semiconductor die. The polymer layer is disposed on the top surface of the interposer structure, wherein the polymer layer includes a central portion and a side portion connected to the central portion, the central portion covers the top surface of the interposer structure and contacts the top surface of the interposer structure, and the side portion protrudes from the central portion and surrounds the interposer structure.

[0101] In some embodiments, the first portion of the insulating seal has a planar top surface in contact with the backside surface of the interposer structure, and the second protruding portion of the insulating seal has a beveled top surface in contact with the side portion of the polymer layer. In some embodiments, the package structure further includes: a plurality of conductive bumps that electrically connect the at least one semiconductor die to the interposer structure; and an underfill structure positioned between the at least one semiconductor die and the interposer structure and covering the plurality of conductive bumps, wherein the insulating seal seals the underfill structure and the plurality of conductive bumps. In some embodiments, the package structure further includes: a plurality of electrical connectors that electrically connect the interposer structure to the circuit substrate; and an underfill structure positioned between the polymer layer and the circuit substrate and covering the plurality of electrical connectors, wherein the underfill structure is physically separated from the interposer structure.

[0102] According to another embodiment of the present disclosure, a method for manufacturing a package structure is described. The method includes forming a semiconductor device by the following steps. An internal wiring structure having a device area and a segmentation area surrounding the device area is provided. A semiconductor die is arranged on a first surface of the internal wiring structure in the device area, wherein the semiconductor die is electrically connected to the internal wiring structure. A first groove is formed on the first surface of the internal wiring structure in the segmentation area, wherein the first groove surrounds the semiconductor die. An insulating seal is formed above the device area and the segmentation area on the first surface of the internal wiring structure, wherein the insulating seal seals the semiconductor die and fills the first groove. A first segmentation process is performed by removing a portion of the internal wiring structure and a portion of the insulating seal to form a second groove on a second surface of the internal wiring structure in the segmentation area, wherein the second surface is opposite to the first surface. A protective layer is formed above the device area and the segmentation area on the second surface of the internal wiring structure, wherein the protective layer fills the second groove and contacts the insulating seal. A plurality of electrical connectors are formed on the protective layer, wherein the plurality of electrical connectors are electrically connected to the internal wiring structure. The semiconductor device is placed on the circuit substrate, wherein the semiconductor device is electrically connected to the circuit substrate through the plurality of electrical connections.

[0103] In some embodiments, the first segmentation process is performed to remove a portion of the interconnect structure, so that the interconnect structure includes a bevel portion, and the protective layer is filled into the second groove and covers the bevel portion of the interconnect structure. In some embodiments, the insulating seal is formed with a first portion surrounding the semiconductor die, and a second protruding portion surrounding the first portion and partially surrounding the interconnect structure. In some embodiments, the first segmentation process is performed to remove a portion of the insulating seal, so that the second protruding portion has a beveled top surface, and the protective layer is filled into the second groove and covers the beveled top surface. In some embodiments, the method for manufacturing a package structure further includes: forming a bottom filler structure covering the plurality of electrical connectors, wherein the bottom filler structure is in contact with the insulating seal and the protective layer. In some embodiments, the protective layer is formed with a central portion and a side portion connected to the central portion, the central portion is formed to cover and contact the second surface of the interconnect structure, and the side portion protrudes from the central portion and is formed to fill in the second groove.

[0104] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and those skilled in the art may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A packaging structure, include: Circuit substrate; a semiconductor device disposed on the circuit substrate and electrically connected to the circuit substrate, wherein the semiconductor device comprises: An internal connection structure having a first surface and a second surface opposite to the first surface, and the internal connection structure is formed of a semiconductor first material having a first thermal expansion coefficient value; a semiconductor die disposed on the first surface and electrically connected to the interconnect structure; an insulating sealant disposed on the first surface of the interconnect structure and sealing the semiconductor die, wherein the insulating sealant partially covers a sidewall of the interconnect structure; a protective layer disposed on the second surface of the interconnect structure and partially covering the sidewall of the interconnect structure, wherein the protective layer is in contact with the insulating sealant and is made of a second material having a second thermal expansion coefficient value, wherein the second thermal expansion coefficient value is a value within a second range, and the second range does not overlap with the first thermal expansion coefficient value; and a plurality of electrical connectors disposed on the protection layer, wherein the inner connection structure is electrically connected to the circuit substrate through the plurality of electrical connectors; and A bottom filler structure is arranged between the circuit substrate and the semiconductor device, wherein the bottom filler structure covers the multiple electrical connectors and is in contact with the insulating seal and the protective layer, wherein the bottom filler structure is made of a third material different from the second material and has a third thermal expansion coefficient value, wherein the third thermal expansion coefficient value is a value within a third range, and the third range overlaps with the second range. 2 . The package structure according to claim 1 , wherein the interconnect structure is physically separated from the underfill structure. 3 . The package structure according to claim 1 , wherein the interconnect structure comprises a slope portion, and the protection layer covers the slope portion. 4 . The package structure according to claim 1 , wherein the insulating sealant comprises a first portion surrounding the semiconductor die, and a second protruding portion surrounding the first portion and partially surrounding the interconnect structure. 5 . The package structure according to claim 4 , wherein the first portion of the insulating seal has a planar top surface in contact with the interconnect structure, and the second protruding portion of the insulating seal has a sloped top surface in contact with the protection layer.

6. The packaging structure according to claim 1, wherein the protection layer comprises a dielectric material layer as the second material and a conductive pattern embedded in the dielectric material layer, and the conductive pattern is electrically connected to the inner connection structure and the plurality of electrical connectors.

7. A packaging structure, include: Circuit substrate; an interposer structure disposed on the circuit substrate, wherein the interposer structure comprises a core substrate and a plurality of through holes formed in the core substrate, and the core substrate of the interposer structure comprises an inclined surface portion having a first inclined surface; At least one semiconductor die, disposed on a backside surface of the interposer structure, wherein the at least one semiconductor die is electrically connected to the plurality of vias; An insulating sealant, disposed on the backside surface of the interposer structure and surrounding the at least one semiconductor die, wherein the insulating sealant includes a bevel top surface aligned with the first bevel; A polymer layer, disposed on a top surface of the interposer structure, wherein the polymer layer includes a central portion and a side portion connected to the central portion, the central portion includes a conductive pattern embedded therein, and the conductive pattern is in direct contact with the plurality of vias of the interposer structure, and the central portion of the polymer layer covers and contacts the top surface of the interposer structure, the side portion protrudes from the central portion and surrounds the interposer structure, wherein the side portion has an inclined surface, the inclined surface covers and is in direct contact with the first bevel and the bevel top surface, and a side surface of the side portion is aligned with a side surface of the insulating sealant.

8. The package structure according to claim 7, wherein the bevel portion protrudes from the core substrate, and the side portion of the polymer layer covers the bevel portion.

9. The package structure according to claim 7, wherein the insulating sealant includes a first portion covering the at least one semiconductor die, and a second protruding portion surrounding the first portion and partially surrounding the interposer structure, wherein the second protruding portion has the bevel top surface.

10. The package structure according to claim 9, wherein the first portion of the insulating sealant has a flat top surface in contact with the backside surface of the interposer structure.

11. The package structure according to claim 7, further comprising: A plurality of conductive bumps for electrically connecting the at least one semiconductor die to the interposer structure; and An underfill structure, positioned between the at least one semiconductor die and the interposer structure, and covering the plurality of conductive bumps, wherein the insulating sealant seals the underfill structure and the plurality of conductive bumps.

12. The package structure according to claim 7, further comprising: A plurality of electrical connectors, disposed on the conductive pattern of the polymer layer, and for electrically connecting the interposer structure to the circuit substrate; and An underfill structure, positioned between the polymer layer and the circuit substrate, and covering the plurality of electrical connectors, wherein the underfill structure is physically separated from the interposer structure.

13. A method of manufacturing a package structure, comprising: Forming a semiconductor device, including: Providing an interconnect structure having a device region and a scribe region surrounding the device region; Disposing a semiconductor die on a first surface of the interconnect structure within the device region, wherein the semiconductor die is electrically connected to the interconnect structure; forming a first trench on the first surface of the interconnect structure in the segmentation region, wherein the first trench surrounds the semiconductor die; forming an insulating sealant over the device region and the segmentation region on the first surface of the interconnect structure, wherein the insulating sealant seals the semiconductor die and fills the first trench; Performing a first segmentation process to remove a portion of the interconnect structure and a portion of the insulating sealant to form a second groove on a second surface of the interconnect structure in the segmentation region, the second surface being opposite to the first surface; forming a protection layer above the device region and the segmentation region on the second surface of the interconnect structure, wherein the protection layer fills the second trench and contacts the insulating seal; forming a plurality of electrical connectors on the protective layer, wherein the plurality of electrical connectors are electrically connected to the inner wiring structure; performing a second singulation process to cut through the protection layer and the insulating sealant, wherein after the second singulation process, the insulating sealant partially covers the sidewalls of the interconnect structure and the protection layer partially covers the sidewalls of the interconnect structure; and The semiconductor device is mounted on a circuit substrate, wherein the semiconductor device is electrically connected to the circuit substrate through the plurality of electrical connections.

14. The method for manufacturing a packaging structure according to claim 13, wherein the first segmentation process is performed to remove a portion of the interconnect structure, so that the interconnect structure includes a slope portion, and the protection layer is filled into the second groove and covers the slope portion of the interconnect structure. 15 . The method for manufacturing a package structure according to claim 13 , wherein the insulating sealant is formed with a first portion surrounding the semiconductor die, and a second protruding portion surrounding the first portion and partially surrounding the interconnect structure. 16 . The method for manufacturing a package structure according to claim 15 , wherein the first segmentation process is performed to remove part of the insulating sealant so that the second protrusion has a beveled top surface, and the protection layer is filled into the second groove and covers the beveled top surface.

17. The method for manufacturing a package structure according to claim 13, further comprising: include: An underfill structure is formed covering the plurality of electrical connectors, wherein the underfill structure is in contact with the insulating seal and the protection layer.

18. The method for manufacturing a packaging structure according to claim 13, wherein the protection layer is formed with a central portion and a side portion connected to the central portion, the central portion is formed to cover and contact the second surface of the interconnect structure, and the side portion protrudes from the central portion and is formed to fill in the second groove.

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