Semiconductor device and manufacturing method

Abstract

In an embodiment, a semiconductor device includes: a first fin; a gate structure above the first fin; a first source / drain region adjacent to the gate structure; an etch stop layer above the first source / drain region; a conductive line above the etch stop layer, the conductive line being isolated from the first source / drain region by the etch stop layer, and having a top surface coplanar with a top surface of the gate structure; and a power rail contact extending through the first fin, the power rail contact being connected to the first source / drain region. Embodiments of the present invention also relate to methods of manufacturing semiconductor devices.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices and manufacturing methods. Background Art

[0002] Semiconductor devices are used in a variety of electronic devices, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are usually manufactured by depositing insulating layers or dielectric layers, conductive layers, and semiconductor material layers in sequence on a semiconductor substrate, and patterning each material layer using photolithography to form circuit components and elements thereon.

[0003] The semiconductor industry is increasing the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, thereby enabling more components to be integrated into a specific area. However, as the minimum feature size decreases, additional problems arise that should be addressed. Summary of the invention

[0004] According to one aspect of an embodiment of the present invention, a semiconductor device is provided, comprising: a first fin; a gate structure above the first fin; a first source / drain region adjacent to the gate structure; an etch stop layer above the first source / drain region; a conductive line above the etch stop layer, the conductive line being isolated from the first source / drain region by the etch stop layer, the top surface of the conductive line being coplanar with the top surface of the gate structure; and a power rail contact extending through the first fin, the power rail contact being connected to the first source / drain region.

[0005] According to another aspect of an embodiment of the present invention, a semiconductor device is provided, comprising: a back-side interconnect structure comprising a power rail; a front-side interconnect structure comprising an interconnect; and a device layer, between the back-side interconnect structure and the front-side interconnect structure, the device layer comprising a transistor, the transistor comprising: a first epitaxial source / drain region; a source / drain contact contact contacting the front side of the first epitaxial source / drain region, the interconnect being connected to the source / drain contact; a second epitaxial source / drain region; and a power rail contacting the back side of the second epitaxial source / drain region, the power rail being connected to the power rail contact, the front side of the second epitaxial source / drain region being completely covered by a dielectric material.

[0006] According to another aspect of an embodiment of the present invention, a method for manufacturing a semiconductor device is provided, comprising: depositing an etch stop layer on a first epitaxial source / drain region, a second epitaxial source / drain region, and a gate structure, the first epitaxial source / drain region and the second epitaxial source / drain region being arranged at opposite sides of the gate structure; depositing an interlayer dielectric (ILD) on the etch stop layer; etching a first opening through the ILD and the etch stop layer, the first opening exposing a front side of the first epitaxial source / drain region, after etching the first opening, the front side of the second epitaxial source / drain region remains covered by the etch stop layer; and forming a source / drain contact in the first opening, the source / drain contact contacting the first epitaxial source / drain region. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 An example of a simplified nanostructure field effect transistor (nanoFET) is shown in accordance with some embodiments.

[0009] Figures 2 to 19D are various views of intermediate stages in the fabrication of a semiconductor device according to some embodiments.

[0010] Figures 20 to 27D are various views of other intermediate stages in semiconductor device fabrication according to some embodiments.

[0011] FIG. 28A to FIG. 28D are various views of a semiconductor device according to some embodiments.

[0012] Fig.29 is a cross-sectional view of a semiconductor device according to some embodiments. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0014] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0015] According to various embodiments, a semiconductor device having a device layer arranged between two interconnect structures is formed. The device layer includes transistors, for example, nanostructured field effect transistors (nano FETs). One of the interconnect structures is located on the front side of the device layer and includes conductive components that interconnect the transistors of the device layer to form a functional circuit. The other interconnect structure is located on the back side of the device layer and includes conductive components for providing a power circuit for the device layer. Specifically, the backside interconnect structure includes a dedicated power rail for providing a reference voltage, a power supply voltage, etc. to the functional circuit. The power rail is attached to the back side of the source / drain region of the transistor in the device layer. In this way, contact with the front side of the source / drain region is undesirable and is not formed. Avoiding the formation of such contacts can improve the performance of the transistor and free up space in the device layer, which can be used for other purposes, such as forming additional conductive lines for interconnect wiring.

[0016] Figure 1 An example of a simplified nanoFET is shown in accordance with some embodiments. Figure 1 It is a three-dimensional cross-sectional view, and some components of the nano FET are omitted for clarity of illustration. The nano FET may be a nanosheet field effect transistor (NSFET), a nanowire field effect transistor (NWFET), a gate-all-around field effect transistor (GAAFET), etc.

[0017] The nanoFET includes a nanostructure 56 above a substrate 50, such as a fin 54 extending from the substrate 50. The nanostructure 56 is a semiconductor layer that acts as a channel region 68 of the nanoFET. An isolation region 60, such as a shallow trench isolation (STI) region, is arranged above the substrate 50 and between adjacent fins 54, which may protrude above and between adjacent isolation regions 60. Although the isolation region 60 is described / illustrated as being separate from the substrate 50, as used herein, the term "substrate" may refer to a separate substrate 50 or a combination of a substrate 50 and an isolation region 60. In addition, although the fin 54 is shown as a single continuous material with the substrate 50, the fin 54 and / or the substrate 50 may include a single material or multiple materials. In this article, the fin 54 refers to the portion extending above and between adjacent isolation regions 60.

[0018] The gate structure 100 is wrapped around the nanostructure 56 and arranged above the fin 54. The gate structure 100 includes a gate dielectric 102 and a gate electrode 104. The gate dielectric 102 is along the top surface, sidewalls and bottom surface of the nanostructure 56, and can extend along the sidewalls and / or top surface of the fin 54. The gate electrode 104 is on the gate dielectric 102. The epitaxial source / drain regions 92 are arranged on opposite sides of the gate structure 100. In an embodiment where multiple transistors are formed, the epitaxial source / drain regions 92 can be shared between the transistors. For example, adjacent epitaxial source / drain regions 92 can be electrically coupled, such as by epitaxially growing to coalesce the epitaxial source / drain regions 92, or by coupling the epitaxial source / drain regions 92 with the same source / drain contacts. One or more interlayer dielectric (ILD) layers (discussed in more detail below) are located above the epitaxial source / drain regions 92 and / or the gate structure 100, through which contacts are formed to the epitaxial source / drain regions 92 and the gate electrode 104 (discussed in more detail below). The epitaxial source / drain regions 92 and the gate electrode 104 are interconnected to form a functional circuit. As will be discussed in more detail below, a first subset of the epitaxial source / drain regions 92P will be connected to a dedicated power rail for providing a reference voltage, a power supply voltage, etc. to the circuit, and a second subset of the epitaxial source / drain regions 92S will not be connected to the dedicated power rail.

[0019] Some embodiments discussed herein are discussed in the context of nano-FETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Furthermore, some embodiments contemplate use in planar devices such as planar FETs or fin field effect transistors (FinFETs).

[0020] Figure 1 Reference cross-sectional views used in subsequent figures are further illustrated. Section AA is along the longitudinal axis of nanostructure 56 and along the direction of current flow, for example, between epitaxial source / drain regions 92. Section BB is perpendicular to section AA and along the longitudinal axis of gate structure 100. Section CC is perpendicular to section AA and extends through epitaxial source / drain regions 92S. Section DD is perpendicular to section AA and extends through epitaxial source / drain regions 92P. For clarity of description, subsequent figures refer to this reference cross-sectional view.

[0021] Figures 2 to 19D are various views of intermediate stages in the fabrication of a semiconductor device according to some embodiments. Specifically, the fabrication of a nanoFET device layer is shown. Figure 2 , Figure 3 , Figure 4 , Figure 5 and Figure 6 is shown with Figure 1 A 3D view of a similar 3D view. Fig. 7A , Fig. 8A , Fig. 9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A , Fig.15A , Fig.16A , Fig.17A and Fig.19A is along Figure 1 A cross-sectional view is shown in reference section AA. Fig. 10B , Fig. 11B , Fig. 13B and Fig.19B is along Figure 1 A cross-sectional view is shown in reference section BB. Figure 7B , Figure 8B , Fig. 9B and Fig. 9C is along Figure 1 The reference section CC or DD shows a cross-sectional view except that two fins are shown. Fig. 14B , Fig. 15B , Fig. 16B , Fig. 17B and Fig.19C is along Figure 1 Reference section CC shows a cross-sectional view except that two fins are shown. Fig. 14C , Fig. 15C , 16C , Fig. 17C and Fig.19D is along Figure 1 Reference section DD shows a cross-sectional view except that two fins are shown. Fig.18 It is a top view.

[0022] exist Figure 2 In the invention, a substrate 50 for forming a nano FET is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc., which may be doped or undoped (e.g., with a p-type or n-type dopant). The substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a semiconductor material layer formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate, which is typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof.

[0023] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device such as an NMOS transistor, for example, an n-type nano FET, and the p-type region 50P can be used to form a p-type device such as a PMOS transistor, for example, a p-type nano FET. The n-type region 50N can be physically separated from the p-type region 50P (not shown separately), and any number of device components (e.g., other active devices, doped channel regions, isolation structures, etc.) can be arranged between the n-type region 50N and the p-type region 50P.

[0024] The substrate 50 may be lightly doped with p-type or n-type impurities. An anti-punch-through (APT) implantation may be performed on the upper portion of the substrate 50 to form an APT region. During the APT implantation, dopants may be implanted into the n-type region 50N and the p-type region 50P. The dopants may have a conductivity type opposite to the conductivity type of the source / drain region that will be subsequently formed in each of the n-type region 50N and the p-type region 50P. The APT region may extend below the source / drain region that will be subsequently formed in the nanoFET, which will be formed in a subsequent process. The APT region may be used to reduce leakage from the source / drain region to the substrate 50. In some embodiments, the doping concentration in the APT region may be about 10 18 cm -3 to about 10 19 cm -3 within the range.

[0025] A multilayer stack 52 is formed over the substrate 50. The multilayer stack 52 includes alternating first semiconductor layers 52A and second semiconductor layers 52B. The first semiconductor layers 52A are formed of a first semiconductor material and the second semiconductor layers 52B are formed of a second semiconductor material. The semiconductor materials can each be selected from candidate semiconductor materials of the substrate 50. In the illustrated embodiment, the multilayer stack 52 includes four layers of each of the first semiconductor layers 52A and the second semiconductor layers 52B. It should be understood that the multilayer stack 52 may include any number of first semiconductor layers 52A and second semiconductor layers 52B.

[0026] In the illustrated embodiment, the second semiconductor layer 52B will be used to form the channel region of the nanoFET in both the n-type region 50N and the p-type region 50P. The first semiconductor layer 52A is a sacrificial layer (or dummy layer) that will be removed in subsequent processing to expose the top and bottom surfaces of the second semiconductor layer 52B in both regions. The second semiconductor material of the second semiconductor layer 52B is a material suitable for n-type and p-type nanoFETs, such as silicon; and the first semiconductor material of the first semiconductor layer 52A is a material having a high etching selectivity to the etching of the second semiconductor material, such as silicon germanium.

[0027] In another embodiment, the first semiconductor layer 52A will be used to form a channel region of a nanoFET in one region (e.g., the p-type region 50P), and the second semiconductor layer 52B will be used to form a channel region of a nanoFET in another region (e.g., the n-type channel region 50N). The first semiconductor material of the first semiconductor layer 52A can be suitable for a p-type nanoFET, such as silicon germanium (e.g., Si x Ge 1-x , where x can be between 0 and Figure 1 The first semiconductor material and the second semiconductor material may have high etching selectivity in mutual etching, so that the first semiconductor layer 52A may be removed without removing the second semiconductor layer 52B in the n-type region 50N, and the second semiconductor layer 52B may be removed without removing the first semiconductor layer 52A in the p-type region 50P.

[0028] Each layer of the multilayer stack 52 can be grown by processes such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), and deposited by processes such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). Each layer can be formed to a smaller thickness, such as a thickness in the range of about 5nm to about 30nm. In some embodiments, one group of layers (e.g., the second semiconductor layer 52B) is formed to be thinner than another group of layers (e.g., the first semiconductor layer 52A). For example, in an embodiment where the first semiconductor layer 52A is a sacrificial layer (or a virtual layer) and the second semiconductor layer 52B is used to form a channel region, the first semiconductor layer 52A can be formed to a first thickness T1, and the second semiconductor layer 52B can be formed to a second thickness T2, which is about 30% to about 60% less than the first thickness T1. Forming the second semiconductor layer 52B to a smaller thickness allows the channel region to be formed at a greater density.

[0029] exist Figure 3In the embodiment of the present invention, trenches are etched in the substrate 50 and the multilayer stack 52 to form fins 54 and nanostructures 56. The fins 54 are semiconductor strips patterned in the substrate 50. The nanostructures 56 include the rest of the multilayer stack 52 located on the fins 54. Specifically, the nanostructures 56 include alternating first nanostructures 56A and second nanostructures 56B. The first nanostructures 56A and the second nanostructures 56B are formed by the rest of the first semiconductor layer 52A and the second semiconductor layer 52B, respectively. After formation, the second nanostructures 56B at the middle level of the structure are arranged between the two first nanostructures 56A, respectively. Etching may be any feasible etching process, such as reactive ion etching (PIE), neutral atom beam etching (NBE), etc., or a combination thereof. Etching may be anisotropic.

[0030] The fins 54 and nanostructures 56 can be patterned by any suitable method. For example, the fins 54 and nanostructures 56 can be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Typically, the double patterning or multiple patterning process combines photolithography and self-alignment processes so that the formed pattern has, for example, a spacing that is smaller than the spacing that can be obtained using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed above the substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed and the remaining spacers are used as a mask to pattern the fins 54 and nanostructures 56.

[0031] The width of the fin 54 and the nanostructure 56 may be in the range of about 8 nm to about 40 nm. For ease of illustration, the fins 54 and the nanostructures 56 in the n-type region 50N and the p-type region 50P are shown as having substantially equal widths. In some embodiments, the fins 54 and the nanostructures 56 of one region (e.g., the n-type region 50N) may be wider or narrower than the fins 54 and the nanostructures 56 of another region (e.g., the p-type region 50P).

[0032] exist Figure 4In the embodiment, the STI region 60 is formed adjacent to the fin 54. The STI region 60 can be formed by depositing an insulating material over the substrate 50 and the nanostructure 56 and between adjacent fins 54. The insulating material can be an oxide such as silicon oxide, a nitride such as silicon nitride, or the like, or a combination thereof, and can be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), or the like, or a combination thereof. Other insulating materials formed by any feasible process can also be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In an embodiment, the insulating material is formed so that an excess of the insulating material covers the nanostructure 56. Although the insulating material is shown as a single layer, some embodiments can use multiple layers. For example, in some embodiments, a liner can first be formed along the surface of the substrate 50, the fin 54, and the nanostructure 56. Thereafter, a filling material such as described above can be formed above the liner.

[0033] A removal process is then applied to the insulating material to remove excess insulating material above the nanostructures 56. In some embodiments, a planarization process may be used, such as chemical mechanical polishing (CMP), an etch-back process, or a combination thereof. The planarization process exposes the nanostructures 56 so that after the planarization process is completed, the top surfaces of the nanostructures 56 and the insulating material are coplanar (within process variation).

[0034] The insulating material is then recessed to form an STI region 60. The insulating material is recessed so that at least a portion of the nanostructure 56 protrudes from between adjacent STI regions 60. In the illustrated embodiment, the top surface of the STI region 60 is coplanar with the top surface of the fin 54 (within the process variation range). In some embodiments, the top surface of the STI region 60 is above or below the top surface of the fin 54. In addition, the top surface of the STI region 60 may have a plane, a convex surface, a concave surface (such as a concave surface) or a combination thereof as shown in the figure. By suitable etching, the top surface of the STI region 60 may be formed to be flat, convex and / or concave. A feasible etching process (e.g., an etching process that is selective to the material of the insulating material) may be used to recess the STI region 60, for example, to selectively etch the insulating material of the STI region 60 at a faster rate than etching the material of the fin 54 and the nanostructure 56. For example, an oxide such as a dilute hydrofluoric acid (dHF) oxide may be used to remove the oxide.

[0035] The above process is just one example of how to form the fin 54 and the nanostructure 56. In some embodiments, the fin 54 and the nanostructure 56 can be formed by an epitaxial growth process. For example, a dielectric layer can be formed above the top surface of the substrate 50, and a groove can be etched through the dielectric layer to expose the underlying substrate 50. The epitaxial structure can be epitaxially grown in the groove, and the dielectric layer can be recessed so that the epitaxial structure protrudes from the dielectric layer to form the fin 54 and the nanostructure 56. The epitaxial structure may include the above-described alternating semiconductor materials, such as a first semiconductor material and a second semiconductor material. In embodiments where the epitaxial structure is epitaxially grown, the epitaxially grown material can be in-situ doped during growth, which can avoid previous and / or subsequent implants, although in-situ doping and implant doping can be used together.

[0036] In addition, suitable wells may be formed inside substrate 50, fins 54, and / or nanostructures 56. In some embodiments, a p-type well may be formed in n-type region 50N, and an n-type well may be formed in p-type region 50P. In another embodiment, a p-type well or an n-type well may be formed in both n-type region 50N and p-type region 50P.

[0037] In embodiments with different well types, photoresist or other masks may be used to implement different implantation steps for n-type region 50N and p-type region 50P. For example, a photoresist may be formed over fin 54, nanostructure 56, and STI region 60 in n-type region 50N. The photoresist is patterned to expose p-type region 50P. The photoresist may be formed using a spin coating technique and may be patterned using a feasible photolithography technique. Once the photoresist is patterned, an n-type impurity implantation is performed in p-type region 50P, and the photoresist may be used as a mask to substantially prevent n-type impurities from being implanted into n-type region 50N. The n-type impurity may be phosphorus, arsenic, antimony, etc., implanted into the region, with a concentration of about 10 13 cm -3 to about 10 14 cm -3 After implantation, the photoresist is removed, such as by a feasible ashing process.

[0038] After implanting the p-type region 50P, a photoresist is formed over the fin 54, nanostructure 56, and STI region 60 in the p-type region 50P. The photoresist is patterned to expose the p-type region 50N. The photoresist may be formed using a spin coating technique and may be patterned using a feasible photolithography technique. Once the photoresist is patterned, a p-type impurity implantation is performed in the n-type region 50P, and the photoresist may be used as a mask to substantially prevent the p-type impurity from being implanted into the p-type region 50N. The p-type impurity may be boron, boron fluoride, indium, etc., implanted into the region, and its concentration may be about 10 13 cm -3 to about 10 14 cm-3 After implantation, the photoresist may be removed, such as by a feasible ashing process.

[0039] After implanting n-type region 50N and p-type region 50P, annealing may be performed to repair implant damage and activate implanted p-type and / or n-type impurities. In some embodiments, the grown material of the epitaxial fin may be doped in situ during growth, which may eliminate implantation, although in situ doping and implantation doping may be used together.

[0040] exist Figure 5 In the embodiment of the present invention, a pseudo dielectric layer 62 is formed on the fin 54 and the nanostructure 56. The pseudo dielectric layer 62 may be, for example, silicon oxide, silicon nitride, or a combination thereof, and may be deposited or thermally grown according to a feasible technique. A pseudo gate layer 64 is formed above the pseudo dielectric layer 62, and a mask layer 66 is formed above the pseudo gate layer 64. The pseudo gate layer 64 may be deposited above the pseudo dielectric layer 62 and planarized, such as by CMP. The mask layer 66 may be deposited above the pseudo gate layer 64. The pseudo gate layer 64 may be a conductive or non-conductive material, and may be selected from a group including amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metal nitride, metal silicide, metal oxide, and metal. The pseudo gate layer 64 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing the selected material. The pseudo gate layer 64 may be made of a material having a high etch selectivity to the etching of insulating materials, for example, the material of the STI region 60 and / or the pseudo dielectric layer 62. The mask layer 66 may include one or more layers, for example, silicon nitride, silicon oxynitride, etc. In this example, a single pseudo gate layer 64 and a single mask layer 66 are formed across the n-type region 50N and the p-type region 50P. Although the pseudo dielectric layer 62 is shown as covering the STI region 60, it should be understood that the pseudo dielectric layer 62 may be formed in other ways. In some embodiments, such as when the pseudo dielectric layer 62 is thermally grown, the pseudo dielectric layer 62 is formed to cover only the fin 54 and the nanostructure 56.

[0041] exist Figure 6In the embodiment of the present invention, the mask layer 66 is patterned using feasible photolithography and etching techniques to form a mask 76. The pattern of the mask 76 is then transferred to the dummy gate layer 64 by a feasible etching technique to form a dummy gate 74. The pattern of the mask 76 can optionally be further transferred to the pseudo dielectric layer 62 by a feasible etching technique to form a pseudo dielectric 72. The dummy gate 74 covers the portion of the nanostructure 56 that will be exposed in subsequent processing to form a channel region. Specifically, the dummy gate 74 extends along the portion of the nanostructure 56 that will be used to form the channel region 68. The pattern of the mask 76 can be used to physically separate adjacent dummy gates 74. The dummy gate 74 may also have a length direction substantially perpendicular to the length direction of the fin 54 (within the process variation range). The mask 76 can be optionally removed after patterning, such as by a feasible etching technique.

[0042] 7A to 19D Other intermediate stages in nanoFET fabrication are shown. 7A to 19D This is applicable to both the n-type region 50N and the p-type region 50P. The differences in the structures of the n-type region 50N and the p-type region 50P, if any, are described in the text accompanying each figure.

[0043] exist Fig. 7A and Figure 7B In the embodiment, the gate spacer 80 is formed above the nanostructure 56 and the fin 54 and on the exposed sidewalls of the mask 76 (if present), the pseudo gate 74 and the pseudo dielectric 72. The gate spacer 80 can be formed by conformally forming an insulating material and then etching the insulating material. The insulating material of the gate spacer 80 can be silicon nitride, silicon carbon nitride, silicon carbide, or a combination thereof, and formed by thermal oxidation, deposition, or a combination thereof. The gate spacer 80 can be formed by a single layer of insulating material or a multilayer insulating material. In some embodiments, each gate spacer 80 includes a multilayer of silicon carbide, each layer of which can have a different silicon carbide component. In some embodiments, each gate spacer 80 includes a silicon oxide layer arranged between two layers of silicon nitride. Other spacer structures can be formed. The etching of the insulating material can be anisotropic. For example, the etching process can be a dry etching such as RIE, NBE, etc. After etching, the gate spacer 80 can have a straight sidewall or a curved sidewall. In the illustrated embodiment, gate spacers 80 are formed on the top surface of the STI regions 60 so that subsequent epitaxial growth can be prevented.

[0044] Prior to forming the gate spacer 80, an implantation of a lightly doped source / drain (LDD) region may be performed. In embodiments having different device types, similar to the implantation discussed above, a mask (such as a photoresist) may be formed over the n-type region 50N while exposing the p-type region 50P, and impurities of a suitable type (e.g., p-type) may be implanted into the nanostructures 56 and fins 54 exposed in the p-type region 50P. The mask may then be removed. Subsequently, a mask (such as a photoresist) may be formed over the p-type region 50P while exposing the n-type region 50N, and impurities of a suitable type (e.g., n-type) may be implanted into the nanostructures 56 and fins 54 exposed in the n-type region 50N. The mask may then be removed. The n-type impurity may be any of the n-type impurities discussed previously, and the p-type impurity may be any of the p-type impurities discussed previously. The impurity concentration of the lightly doped source / drain region may be about 10 15 cm -3 to about 10 19 cm -3 Annealing can be used to repair implantation damage and activate the implanted impurities. During implantation, the channel region 68 remains covered by the dummy gate 74 so that the channel region 68 is substantially free of impurities implanted into the LDD region.

[0045] Note that the above disclosure generally describes the formation process of spacers and LDD regions. Other processes and sequences may be used. For example, fewer or more spacers may be used, different step sequences may be used (such as additional spacers may be formed and removed, etc.), etc. Moreover, different structures and steps may be used to form n-type and p-type devices.

[0046] exist Fig. 8A and Figure 8B , source / drain recesses 82 are formed in nanostructure 56. In the illustrated embodiment, source / drain recesses 82 extend through nanostructure 56 to expose fin 54. Source / drain recesses 82 may also extend into substrate 50 and / or fin 54. In various embodiments, source / drain recesses 82 may extend to the top surface of substrate 50 without etching substrate 50; substrate 50 may be etched so that the bottom surface of source / drain recesses 82 is disposed below the top surface of STI region 60; and so on. Source / drain recesses 82 may be formed by etching nanostructure 56 by an anisotropic etching process (such as RIE, NBE, etc.). During the etching process for forming source / drain recesses 82, gate spacers 80 and dummy gates 74 collectively mask portions of nanostructure 56, fin 54, and substrate 50. A single etching process may be used to etch each nanostructure 56. In other embodiments, multiple etching processes may be used to etch nanostructure 56. After the source / drain recesses 82 reach a desired depth, a timed etching process may be used to stop etching the source / drain recesses 82 .

[0047] Optionally, the internal spacer 84 can be formed on the sidewalls of the remaining portion of the first nanostructure 56A, such as those sidewalls exposed by the source / drain recess 82. As will be discussed in more detail below, the source / drain region will be subsequently formed in the source / drain recess 82, and the first nanostructure 56A will be subsequently replaced by a corresponding gate structure. The internal spacer 84 serves as an isolation member between the subsequently formed source / drain region and the subsequently formed gate structure. Moreover, the internal spacer 84 can be used to prevent damage to the subsequently formed source / drain region by a subsequent etching process (such as an etching process for subsequently forming a gate structure).

[0048] As an example of forming an internal spacer 84, the source / drain recess 82 may be expanded laterally. Specifically, the portion of the sidewall of the first nanostructure 56A exposed by the source / drain recess 82 may be recessed. Although the sidewall of the first nanostructure 56A is shown as straight, the sidewall may also be concave or convex. A feasible etching process may be used to recess the sidewall, such as an etching process that is selective to the material of the first nanostructure 56A (e.g., selectively etching the material of the first nanostructure 56A at a faster rate than etching the material of the second nanostructure 56B and the fin 54). The etching may be isotropic. For example, when the fin 54 and the second nanostructure 56B are formed of silicon and the first nanostructure 56A is formed of silicon germanium, the etching process may be wet etching using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc. In another embodiment, the etching process may be dry etching using a fluorine-based gas such as HF. In some embodiments, the same etching process may be performed continuously to form the source / drain grooves 82 and to recess the sidewalls of the first nanostructure 56A. The internal spacer 84 may be formed by conformally forming an insulating material and then etching the insulating material. The insulating material may be a material such as silicon nitride or silicon oxynitride, although any suitable material (such as a low dielectric constant (low-k) material having a k value of less than about 3.5) may be used. The insulating material may be deposited by a conformal deposition process such as ALD, CVD, etc. The etching of the insulating material may be anisotropic. For example, the etching process may be a dry etch such as RIE, NBE, etc. Although the outer sidewalls of the internal spacer 84 are shown flush with the sidewalls of the gate spacer 80, the outer sidewalls of the internal spacer 84 may extend beyond the sidewalls of the gate spacer 80 or be recessed from the sidewalls of the gate spacer 80. In other words, the internal spacer 84 may partially fill, completely fill, or overfill the sidewall grooves. Furthermore, although the sidewalls of the inner spacer 84 are shown as being straight, the sidewalls of the inner spacer 84 may be concave or convex.

[0049] exist 9A to 9C, epitaxial source / drain regions 92 are formed in source / drain recesses 82. In some embodiments, epitaxial source / drain regions 92 apply stress to channel region 68, thereby improving performance. Epitaxial source / drain regions 92 are formed in source / drain recesses 82 so that each dummy gate 74 is disposed between adjacent pairs of epitaxial source / drain regions 92. In some embodiments, gate spacers 80 are used to space epitaxial source / drain regions 92 from dummy gates 74, and internal spacers 84 are used to space epitaxial source / drain regions 92 from first nanostructure 56A by a suitable lateral distance, so that epitaxial source / drain regions 92 do not short circuit with the gate of a subsequently formed nanoFET.

[0050] The epitaxial source / drain region 92 in the n-type region 50N can be formed by masking the p-type region 50P. Then, the epitaxial source / drain region 92 is epitaxially grown in the source / drain recess 82 in the n-type region 50N. The epitaxial source / drain region 92 may include any feasible material suitable for an n-type nano FET. For example, the epitaxial source / drain region 92 in the n-type region 50N may include a material that applies tensile strain on the channel region 68, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain region 92 in the n-type region 50N may have a face that protrudes from the corresponding faces of the second nanostructure 56B and the fin 54, and may have a small face.

[0051] The epitaxial source / drain region 92 in the p-type region 50P can be formed by masking the n-type region 50N. Then, the epitaxial source / drain region 92 is epitaxially grown in the source / drain recess 82 in the p-type region 50P. The epitaxial source / drain region 92 may include any feasible material suitable for a p-type nano FET. For example, the epitaxial source / drain region 92 in the p-type region 50P may include a material that applies compressive strain on the channel region 68, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, etc. The epitaxial source / drain region 92 in the p-type region 50P may have a face that protrudes from the corresponding faces of the second nanostructure 56B and the fin 54, and may have a small face.

[0052] The epitaxial source / drain regions 92, the second nanostructures 56B and / or the fins 54 may be implanted with dopants to form source / drain regions, similar to the formation process of lightly doped source / drain regions discussed above, followed by annealing. The impurity concentration of the source / drain regions may be about 10 19 cm -3 to about 10 21 cm -3 The n-type and / or p-type impurities of the source / drain regions may be any of the impurities discussed above. In some embodiments, the epitaxial source / drain regions 92 may be in-situ doped during growth.

[0053] Due to the epitaxial process of forming epitaxial source / drain regions 92 in n-type region 50N and p-type region 50P, epitaxial source / drain regions 92 have facets extending laterally outward beyond the sidewalls of second nanostructure 56B and fin 54. Fig. 9B As shown, after the epitaxial process is completed, adjacent epitaxial source / drain regions 92 remain separated. Fig. 9C As shown, these facets result in the merging of adjacent epitaxial source / drain regions 92 of the same nanoFET. In the embodiment shown, gate spacers 80 are formed on the top surface of STI regions 60, thereby preventing epitaxial growth. In some other embodiments, the spacer etch used to form gate spacers 80 can be adjusted to remove the spacer material so that the epitaxially grown region extends to the top surface of STI regions 60.

[0054] The epitaxial source / drain region 92 may include one or more semiconductor material layers. For example, the epitaxial source / drain region 92 may include a first semiconductor material layer, a second semiconductor material layer, and a third semiconductor material layer. The epitaxial source / drain region 92 may use any number of semiconductor material layers. Each of the first semiconductor material layer, the second semiconductor material layer, and the third semiconductor material layer may be formed of a different semiconductor material and may be doped to different dopant concentrations. In some embodiments, the first semiconductor material layer may have a dopant concentration that is less than the second semiconductor material layer and greater than the third semiconductor material layer. In an embodiment where the epitaxial source / drain region 92 includes three semiconductor material layers, a first semiconductor material layer may be deposited, a second semiconductor material layer may be deposited above the first semiconductor material layer, and a third semiconductor material layer may be deposited above the second semiconductor material layer.

[0055] exist Fig. 10A and Fig. 10B In the embodiment of the present invention, the first ILD 96 is deposited over the epitaxial source / drain regions 92, the gate spacer 80, the mask 76 (if present) or the dummy gate 74, and the STI region 60. The first ILD 96 may be formed of a dielectric material and may be deposited by any suitable method, such as CVD, plasma enhanced CVD (PECVD), FCVD, etc. The dielectric material may include phospho-silicate glass (PSG), borosilicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any feasible process may also be used.

[0056] In some embodiments, a contact etch stop layer (CESL) 94 is formed between the first ILD 96 and the epitaxial source / drain regions 92, the gate spacers 80, and the STI regions 60. The CESL 94 may be formed of a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, etc., which has a high etch selectivity to the first ILD 96. The CESL 94 may be formed by any suitable method, such as CVD, ALD, etc.

[0057] exist Fig.11A and Fig. 11B In the embodiment shown, a removal process is performed to make the top surface of the first ILD 96 flush with the top surface of the mask 76 (if present) or the dummy gate 74. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch-back process, or a combination thereof, may be used. The planarization process may also remove the mask 76 on the dummy gate 74, and portions of the gate spacer 80 along the sidewalls of the mask 76. After the planarization process, the top surfaces of the gate spacer 80, the first ILD 96, the CESL 94, and the mask 76 (if present) or the dummy gate 74 are coplanar (within process variation). Therefore, the top surface of the mask 76 (if present) or the dummy gate 74 is exposed through the first ILD 96. In the embodiment shown, the mask 76 is retained, and the planarization process makes the top surface of the first ILD 96 flush with the top surface of the mask 76.

[0058] exist Fig. 12A and Fig. 12B In the etching process, the mask 76 (if present) and the dummy gate 74 are removed to form a recess 98. The portion of the dummy dielectric 72 in the recess 98 may also be removed. In some embodiments, the dummy gate 74 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the dummy gate 74 at a faster rate than etching the first ILD 96 or the gate spacer 80. During the removal, the dummy gate 74 may be used as an etch stop layer when etching the dummy gate 74. The dummy dielectric 72 may then be removed after removing the dummy gate 74. Each recess 98 exposes and / or covers a portion of the channel region 68. The portion of the second nanostructure 56B used as the channel region 68 is arranged between adjacent pairs of epitaxial source / drain regions 92.

[0059] The remaining portion of the first nanostructure 56A is then removed to expand the recess 98. The remaining portion of the first nanostructure 56A may be removed by a feasible etching process that selectively etches the material of the first nanostructure 56A at a faster rate than etching the material of the second nanostructure 56B, the fin 54, and the STI region 60. The etching may be isotropic. For example, when the fin 54 and the second nanostructure 56B are formed of silicon and the first nanostructure 56A is formed of silicon germanium, the etching process may be a wet etch using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like. In some embodiments (discussed in more detail below), a trimming process is performed to reduce the thickness of the exposed portion of the second nanostructure 56B.

[0060] exist Fig.13A and Fig. 13B , a gate dielectric 102 and a gate electrode 104 are formed to replace the gate. The gate dielectric 102 is conformally deposited in the recess 98, such as deposited on the top surface and sidewalls of the fin 54 and the top surface, sidewalls and bottom surface of the second nanostructure 56B. The gate dielectric 102 may also be deposited on the top surface of the first ILD 96, the gate spacer 80 and the STI region 60. The gate dielectric 102 includes one or more dielectric layers, such as oxides, metal oxides, metal silicates, etc. or combinations thereof. In some embodiments, the gate dielectric 102 includes silicon oxide, silicon nitride or multiple layers thereof. In some embodiments, the gate dielectric 102 includes a high-k dielectric material, and in these embodiments, the gate dielectric 102 may have a k value greater than about 7.0 and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead and combinations thereof. The gate dielectric 102 may be multilayered. For example, in some embodiments, each gate dielectric 102 may include a silicon oxide interface layer formed by thermal oxidation or chemical oxidation and a metal oxide layer over the interface layer. The material of the gate dielectric 102 may be formed by molecular beam deposition (MBD), ALD, PECVD, or the like.

[0061] The gate electrode 104 is deposited over the gate dielectric 102, respectively, and fills the rest of the recess 98. The gate electrode 104 may include a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, a combination thereof, or a multilayer thereof. For example, although a single-layer gate electrode 104 is shown, the gate electrode 104 may include any number of liner layers, any number of work function tuning layers, and filler materials. Any combination of layers constituting the gate electrode 104 may be deposited in the region between the second nanostructure 56B and between the fin 54 and the second nanostructure 56B. The material of the gate electrode 104 may be formed by ALD, PECVD, or the like.

[0062] After filling the recess 98, a planarization process such as CMP may be performed to remove excess portions of the gate dielectric 102 and gate electrode 104 material that are above the top surfaces of the first ILD 96 and gate spacers 80. Thus, the remaining portions of the gate dielectric 102 and gate electrode 104 material form a replacement gate for the resulting nanoFET. The gate dielectric 102 and gate electrode 104 may be collectively referred to as a gate structure 100 or a "gate stack."

[0063] The gate dielectric 102 in the n-type region 50N and the p-type region 50P may be formed simultaneously, such that the gate dielectric 102 in each region is formed of the same material, and the gate electrode 104 may be formed simultaneously, such that the gate electrode 104 in each region is formed of the same material. In some embodiments, the gate dielectric 102 in each region may be formed by different processes, such that the gate dielectric 102 may be a different material, and / or the gate electrode 104 in each region may be formed by different processes, such that the gate electrode 104 may be a different material. When different processes are used, different masking steps may be used to cover and expose appropriate regions.

[0064] exist FIG. 14A to FIG. 14C , source / drain contact openings 106 are formed through the first ILD 96 and the CESL 94, thereby exposing a subset of the epitaxial source / drain regions 92S. The source / drain contact openings 106 may be initially formed in the first ILD 96 using feasible photolithography and etching techniques, such as using an etching process that is selective to the first ILD 96 (e.g., etching the material of the first ILD 96 at a faster rate than etching the material of the CESL 94). For example, the source / drain contact openings 106 may be initially formed through the first ILD 96 by dry etching using ammonia (NH3) and hydrogen fluoride (HF) gases. The source / drain contact openings 106 are then extended through the CESL 94 using feasible etching techniques, such as using an etching process that is selective to the CESL 94 (e.g., etching the material of the CESL 94 at a faster rate than etching the material of the epitaxial source / drain regions 92S). For example, the source / drain contact openings 106 may be extended through the CESL 94 by dry etching using a fluorine-based gas (e.g., C4F6) and hydrogen (H2) or oxygen (O2). In some embodiments, the etching process parameters (e.g., etchant, duration, environment, etc.) for etching the source / drain contact openings 106 through the first ILD 96 are different from the etching process parameters for etching the source / drain contact openings 106 through the CESL 94.

[0065] During the process for forming source / drain contact openings 106, a mask 108 having a pattern of the source / drain contact openings 106 is formed over the first ILD 96. The mask 108 is used as an etching mask during the etching process for etching the source / drain contact openings 106 through the first ILD 96 and the CESL 94.

[0066] In some embodiments, the mask 108 is formed of a photoresist, such as a single-layer photoresist, a double-layer photoresist, a triple-layer photoresist, etc. For example, the mask 108 can be a triple-layer photoresist, including a bottom layer (e.g., a bottom anti-reflective coating (BARC) layer), an intermediate layer (e.g., a hard mask), and a top layer (e.g., a photoresist). The type of photoresist used (e.g., a single-layer photoresist, a double-layer photoresist, a triple-layer photoresist, etc.) can depend on the photolithography process subsequently used to pattern the photoresist. For example, in an extreme ultraviolet (EUV) photolithography process, the mask 108 can be a single-layer photoresist or a double-layer photoresist. The photoresist can be formed by spin coating, a deposition process such as CVD, or a combination thereof, and can be patterned using a feasible photolithography technique to have a pattern of the source / drain contact opening 106.

[0067] In some embodiments, the mask 108 is formed of spacers. For example, a sacrificial layer can be formed above the first ILD 96 and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the remaining spacers are used as the mask 108. Other types of masks can also be used to etch the source / drain contact openings 106.

[0068] Source / drain contacts will then be formed in source / drain contact openings 106 and attached to the front side of epitaxial source / drain regions 92S. As described above, a first subset of epitaxial source / drain regions 92P will be connected to a dedicated power rail, while a second subset of epitaxial source / drain regions 92S will not be connected to a dedicated power rail. As will be discussed in more detail below, the power rail will then be attached to the back side of epitaxial source / drain regions 92P. Therefore, contact with the front side of epitaxial source / drain regions 92P is undesirable. According to various embodiments, source / drain contact openings 106 are formed above the front side of epitaxial source / drain regions 92S and expose the front side of epitaxial source / drain regions 92P, while the front side of epitaxial source / drain regions 92P remains completely covered by dielectric material (e.g., CESL 94). In other words, the entire front side of each epitaxial source / drain region 92P is covered by dielectric material (e.g., CESL 94). Formation of source / drain contact openings 106 over epitaxial source / drain regions 92P may be avoided in several ways.

[0069] In some embodiments, a single patterning process is used to pattern mask 108. When the mask 108 is formed of a photoresist, a single patterning can be used. In such embodiments, the photoresist can be formed to have an opening pattern above the epitaxial source / drain region 92S rather than on the epitaxial source / drain region 92P. The photoresist can be patterned by exposure to a patterned energy source (e.g., a patterned light source) to cause a chemical reaction, thereby causing physical changes in those portions of the photoresist exposed to the patterned light source. The patterned energy source has only a pattern of the epitaxial source / drain region 92S, but not a pattern of the epitaxial source / drain region 92P. The photoresist can then be developed by applying a developer to the exposed photoresist to utilize physical changes and selectively remove the exposed portion of the photoresist or the unexposed portion of the photoresist according to the desired pattern.

[0070] In some embodiments, a multiple patterning process is used to pattern the mask 108. Multiple patterning can be used when the mask 108 is formed of spacers. In such embodiments, the mask 108 can initially be formed with an opening pattern over all of the epitaxial source / drain regions 92P, 92S. The portion of the opening pattern over the epitaxial source / drain region 92P is then covered or filled so that only the portion of the opening pattern over the epitaxial source / drain region 92S remains in the mask 108. The openings over the epitaxial source / drain region 92P can be covered or filled by forming an additional mask, such as a patterned photoresist, a patterned hard mask, etc.

[0071] Selectively forming source / drain contact openings 106 above epitaxial source / drain regions 92S may include additional processing steps, particularly when a multi-patterning process is used to pattern mask 108. However, as described above, contact with the front side of epitaxial source / drain regions 92P is undesirable. Therefore, contact with the front side of epitaxial source / drain regions 92P is undesirable. If an undesirable contact is formed on the front side of epitaxial source / drain regions 92P, the contact will remain isolated and unused, thereby increasing the parasitic capacitance of the nanoFET. Therefore, although avoiding the formation of a front contact to the epitaxial source / drain regions 92P includes additional processing steps, the performance of the nanoFET can be improved by avoiding the formation of the contact.

[0072] exist FIG. 15A to FIG. 15C In the embodiment of the present invention, the mask 108 is removed. When the mask 108 includes a photoresist, the photoresist can be removed by, for example, a feasible ashing process. When the mask 108 includes other layers (eg, a BARC layer, a hard mask, a spacer, etc.), these layers can be removed by a feasible etching process.

[0073] The metal-semiconductor alloy region 110 may be optionally formed in the source / drain contact opening 106, such as on the portion of the epitaxial source / drain region 92S exposed by the source / drain contact opening 106. The metal-semiconductor alloy region 110 may be a silicide region formed of a metal silicide (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), a germanide region formed of a metal germanide (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.), a silicon-germanium-silicon region formed of both a metal silicide and a metal germanide, etc. The metal-semiconductor alloy region 110 may be formed by depositing a metal in the source / drain contact opening 106 and then performing a thermal annealing process. The metal may be a metal-semiconductor alloy that is capable of reacting with the semiconductor material (e.g., silicon, silicon-germanium, germanium, etc.) of the epitaxial source / drain region 92S to form a low-resistance, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals, or alloys thereof. The metal may be deposited by a deposition process such as ALD, CVD, PVD, etc. In an embodiment, the metal-semiconductor alloy region 110 is a silicide region formed of titanium-silicon. After the thermal annealing process, a cleaning process (such as a wet clean) may be performed to remove any residual metal from the source / drain contact openings 106 (such as from the top surface of the first ILD 96).

[0074] Then, a lower source / drain contact 112 is formed in the source / drain contact opening 106. A liner such as a diffusion barrier layer, an adhesion layer, and a conductive material are formed in the source / drain contact opening 106. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The liner may be deposited by a conformal deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc. In some embodiments, the liner may include an adhesion layer, and at least a portion of the adhesion layer may be processed to form a diffusion barrier layer. The conductive material may be tungsten, cobalt, ruthenium, aluminum, nickel, copper, copper alloy, silver, gold, etc. The conductive material may be deposited by ALD, CVD, PVD, etc. A planarization process such as CMP may be performed to remove excess material from the top surface of the first ILD 96. The remaining liner and conductive material in the source / drain contact opening 106 form the lower source / drain contact 112. The lower source / drain contacts 112 are physically and electrically coupled to the front side of the metal-semiconductor alloy region 110 (if present) or the epitaxial source / drain region 92S. The top surfaces of the lower source / drain contacts 112, the gate electrode 104, the first ILD 96, and the gate spacers 80 are coplanar (within process variations).

[0075] exist FIG. 16A to FIG. 16CIn the embodiment of the present invention, a trench 114 is formed through the first ILD 96, thereby exposing a portion of the CESL 94 above the epitaxial source / drain region 92P. The trench 114 can be formed in the first ILD 96 using feasible photolithography and etching techniques, such as using an etching process that is selective to the first ILD 96 (such as etching the material of the first ILD 96 at a faster rate than etching the material of the CESL 94). For example, the trench 114 through the first ILD 96 can be formed by dry etching using NH3 and HF. In some embodiments, the trench 114 can be formed in the first ILD 96 using etching process parameters similar to the etching process parameters used to initially form the source / drain contact openings 106 through the first ILD 96.

[0076] During the process for forming the trench 114, a mask 116 having a pattern of the source / drain trench 114 is formed over the first ILD 96. The mask 116 is used as an etching mask during an etching process of etching the trench 114 through the first ILD 96. The mask 116 may be formed by FIG. 14A to FIG. 14C The mask 108 discussed above is made of similar materials and is formed in a similar manner. Fig. 16C As shown, the trench 114 extends across multiple adjacent epitaxial source / drain regions 92P. In other words, the trench 114 extends across multiple fins 54 (or across multiple groups of fins 54 when adjacent epitaxial source / drain regions 92 of the same nanoFET have been merged, such as Fig. 9C shown).

[0077] exist FIG. 17A to FIG. 17C In the embodiment of the present invention, the mask 116 is removed. When the mask 116 includes photoresist, the photoresist can be removed by, for example, a feasible ashing process. When the mask 116 includes other layers (eg, BARC layer, hard mask, spacer, etc.), these layers can be removed by a feasible etching process.

[0078] Then, a conductive line 118 is formed in the trench 114. A liner such as a diffusion barrier layer, an adhesion layer, and a conductive material are formed in the trench 114. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, and the like. The liner may be deposited by a conformal deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), and the like. In some embodiments, the liner may include an adhesion layer, and at least a portion of the adhesion layer may be processed to form a diffusion barrier layer. The conductive material may be tungsten, cobalt, ruthenium, aluminum, nickel, copper, copper alloy, silver, gold, and the like. The conductive material may be deposited by ALD, CVD, PVD, and the like. A planarization process such as CMP may be performed to remove excess material from the top surface of the first ILD 96. The remaining liner and conductive material in the trench 114 form a conductive line 118. The top surfaces of the conductive line 118 , the lower source / drain contacts 112 , the gate electrode 104 , the first ILD 96 , and the gate spacers 80 are coplanar (within process variations).

[0079] No metal-semiconductor alloy region is formed in the trench 114, and the conductive line 118 is physically and electrically isolated from the epitaxial source / drain region 92P by the CESL 94. As described above, contact with the front side of the epitaxial source / drain region 92P is undesirable. Therefore, the portion of the first ILD 96 above the epitaxial source / drain region 92P can be used for other purposes. Specifically, the conductive line 118 is formed in the portion of the first ILD 96 above the epitaxial source / drain region 92P, while the front side of the epitaxial source / drain region 92P remains completely covered by a dielectric material (e.g., CESL 94), which is arranged between the conductive line 118 and the front side of the epitaxial source / drain region 92P. As discussed in more detail below, the conductive line 118 can be used for additional wiring. For example, the conductive line 118 can be used to route signals from an overlying interconnect structure (discussed in more detail below).

[0080] Conductive line 118 extends across a plurality of adjacent epitaxial source / drain regions 92P and has a portion above STI region 60 (e.g., between and adjacent to epitaxial source / drain regions 92P). The portion of conductive line 118 above STI region 60 has a greater height than the portion of conductive line 118 above epitaxial source / drain region 92P. For example, the portion of conductive line 118 above epitaxial source / drain region 92P may have a height H1 in a range of about 5 nm to about 30 nm, while the portion of conductive line 118 above STI region 60 may have a height H2 in a range of about 50 nm to about 100 nm. Because lower source / drain contact 112 is formed through CESL 94, but conductive line 118 is not, the height of lower source / drain contact 112 is greater than the portion of conductive line 118 above epitaxial source / drain region 92P. For example, the lower source / drain contact 112 may have a height H3 in the range of about 10 nm to about 40 nm. The height H3 is greater than the height H1 and less than the height H2.

[0081] Fig.18 is in FIG. 17A to FIG. 17C 1, except that more gate structures 100 are shown and some features are omitted for clarity of illustration. As shown, lower source / drain contacts 112 are arranged above corresponding fins 54. Conductive lines 118 extend across multiple fins 54 (or Fig. 9C As shown, extending through multiple fins 54, when adjacent epitaxial source / drain regions 92 of the same nanoFET have been merged). Each conductive line 118 may extend only through the n-type region 50N, only through the p-type region 50P, or through both the n-type region 50N and the p-type region 50P. The conductive line 118 has a greater length than the lower source / drain contact 112 in a direction parallel to the longitudinal axis of the gate structure 100. For example, the lower source / drain contact 112 may have a length L1 in the range of about 15nm to about 50nm, and the conductive line 118 may have a length L2 in the range of about 50nm to about 150nm. In some embodiments, the conductive line 118 and the lower source / drain contact 112 have the same width in a direction parallel to the longitudinal axis of the fin 54. For example, the lower source / drain contact 112 and the conductive line 118 may each have a width W1 in the range of about 10nm to about 30nm.

[0082] exist 19A to 19DIn the embodiment of the present invention, the second ILD 122 is deposited over the first ILD 96, the gate electrode 104, the lower source / drain contact 112, and the conductive line 118. The second ILD 122 can be formed of a material selected from the same group of candidate materials as the first ILD 96, and can be deposited using a method selected from the same group of candidate methods used to deposit the first ILD 96. The first ILD 96 and the second ILD 122 can be formed of the same material, or can include materials that do not contain. After formation, the second ILD 122 can be planarized, such as by CMP. In some embodiments, an etch stop layer is formed between the first ILD 96 and the second ILD 122. The etch stop layer can include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, etc., whose etching rate is different from the etching rate of the material of the second ILD 122.

[0083] Then, a gate contact 124, an upper source / drain contact 126, and a line contact 128 extending through the second ILD 122 are formed. A contact opening is formed through the second ILD 122. The contact opening can be formed by feasible photolithography and etching techniques. Then, a liner such as a diffusion barrier layer, an adhesion layer, and a conductive material are formed in the contact opening. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The liner may be deposited by a conformal deposition process such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc. In some embodiments, the liner may include an adhesion layer, and at least a portion of the adhesion layer may be processed to form a diffusion barrier layer. The conductive material may be tungsten, cobalt, ruthenium, aluminum, nickel, copper, copper alloy, silver, gold, etc. The conductive material may be deposited by ALD, CVD, PVD, etc. A planarization process such as CMP may be performed to remove excess material from the top surface of the second ILD 122. The remaining liner and conductive material in the contact opening form a gate contact 124, an upper source / drain contact 126, and a line contact 128. The gate contact 124 is physically and electrically coupled to the gate electrode 104. The upper source / drain contact 126 is physically and electrically coupled to the lower source / drain contact 112. The line contact 128 is physically and electrically coupled to the conductive line 118.

[0084] As will be discussed in more detail below, a first interconnect structure (e.g., a front interconnect structure) is formed over substrate 50. Some or all of substrate 50 is then removed and replaced with a second interconnect structure (e.g., a back interconnect structure). Thus, a device layer 130 of active devices is formed between the front interconnect structure and the back interconnect structure. Both the front and back interconnect structures include conductive features that are electrically connected to the nanoFETs of device layer 130. The conductive features of the front interconnect structure (e.g., a metallization pattern, also referred to as an interconnect) will be electrically connected to the front of the epitaxial source / drain region 92S and the gate electrode 104 to form functional circuits, logic circuits, memory circuits, image sensor circuits, etc. The conductive features of the back interconnect structure (e.g., a power rail) will be electrically connected to the back of the epitaxial source / drain region 92P to provide a reference voltage, a power supply voltage, etc. to the functional circuits. Although device layer 130 is described as having nanoFETs, other embodiments may include device layers 130 having different types of transistors (e.g., planar FETs, FinFETs, TFTs, etc.).

[0085] Figures 20 to 27D are various views of other intermediate stages in the fabrication of a semiconductor device according to some embodiments. Specifically, the fabrication of front and back interconnect structures for a nano-FET is shown. Fig. 20 , Fig.21 , Fig. 22 , Fig.23 , Fig.24 , Fig.25 , Fig.26 and Fig.27A is along Figure 1 A cross-sectional view is shown in reference section AA. Fig.27B is along Figure 1 A cross-sectional view is shown in reference section BB. Fig.27C is along Figure 1 Reference section CC shows a cross-sectional view except that two fins are shown. Fig.27D is along Figure 1 Reference section DD shows a cross-sectional view except that two fins are shown.

[0086] exist Fig. 20 , interconnect structure 140 is formed on device layer 130, for example, on second ILD 122. Interconnect structure 140 may also be referred to as a front-side interconnect structure because it is formed on the front side of substrate 50 / device layer 130 (eg, the side of substrate 50 where device layer 130 is located).

[0087] The interconnect structure 140 may include one or more layers of conductive features 142 formed in one or more stacked dielectric layers 144. Each dielectric layer 144 may include a dielectric material, such as a low-k dielectric material, an ultra-low-k dielectric (ELK) material, etc. The dielectric layers 144 may be deposited using a suitable process, such as CVD, ALD, PVD, PECVD, etc.

[0088] Conductive component 142 may include conductive wires and conductive vias interconnecting conductive wire layers. The conductive vias may extend through the corresponding dielectric layers in dielectric layer 144 to provide vertical connections between conductive wire layers. Conductive component 142 may be formed by any feasible process. For example, conductive component 142 may be formed by a damascene process (such as a single damascene process, a dual damascene process, etc.). In the damascene process, a combination of photolithography and etching techniques is used to pattern the respective dielectric layers 144 to form grooves corresponding to the desired pattern of conductive component 142. An optional diffusion barrier layer and / or an optional adhesion layer may be deposited, and then the grooves may be filled with a conductive material. Suitable materials for the barrier layer include titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, titanium oxide, or other alternatives, and suitable materials for the conductive material include copper, silver, gold, tungsten, aluminum, or a combination thereof. In an embodiment, conductive component 142 may be formed by depositing a seed layer of copper or a copper alloy and filling the grooves by electroplating. A chemical mechanical planarization (CMP) process or the like may be used to remove excess conductive material from the surface of the dielectric layer 144 and planarize the surface for subsequent processing.

[0089] In the example, five layers of conductive features 142 and dielectric layers 144 are shown. However, it should be understood that the interconnect structure 140 may include any number of conductive features arranged in any number of dielectric layers. The conductive features 142 of the interconnect structure 140 are electrically connected to the gate contact 124, the upper source / drain contact 126, and the line contact 128 to form a functional circuit. In other words, the conductive features 142 interconnect the conductive wire 118, the epitaxial source / drain region 92, and the gate electrode 104. In some embodiments, the functional circuit formed by the interconnect structure 140 may include a logic circuit, a memory circuit, an image sensor circuit, etc. The second ILD 122, the gate contact 124, the upper source / drain contact 126, and the line contact 128 may also be considered as part of the interconnect structure 140 (such as part of the first level conductive features of the interconnect structure 140).

[0090] As described above, the conductive wires 118 can be used for additional routing. Therefore, each conductive wire 118 is coupled to a plurality of wire contacts 128, so that one conductive wire 118 is connected to a plurality of conductive components 142 of the interconnect structure 140. The conductive wire 118 can be used as an additional interconnect of the interconnect structure 140. For example, a signal carrier of a first conductive component 142 can be routed down to the conductive wire 118 and then routed back to a second conductive component 142. Thus, the flexibility of signal routing can be increased.

[0091] exist Fig.21 In the embodiment, carrier substrate 146 is bonded to the top surface of interconnect structure 140 through bonding layer 148 (e.g., including bonding layers 148A, 148B). Carrier substrate 146 can be a glass carrier substrate, a ceramic carrier substrate, a semiconductor substrate (e.g., a silicon substrate), a wafer (e.g., a silicon wafer), etc. Carrier substrate 146 can provide structural support in the subsequent processing steps and in the completed device. Carrier substrate 146 is substantially free of any active or passive devices.

[0092] In various embodiments, the carrier substrate 146 may be bonded to the interconnect structure 140 by a suitable technique such as dielectric bonding. The dielectric bonding may include depositing bonding layers 148A, 148B on the interconnect structure 140 and the carrier substrate 146, respectively. In some embodiments, the bonding layer 148A includes silicon oxide (e.g., high density plasma (HDP) oxide, etc.) deposited by CVD, ALD, PVD, etc. The bonding layer 148B may also be an oxide layer formed prior to bonding using, for example, CVD, ALD, PVD, thermal oxidation, etc. Other suitable materials may also be used for the bonding layers 148A, 148B.

[0093] The dielectric bonding process also includes surface treatment of one or more bonding layers 148. The surface treatment may include plasma treatment. The plasma treatment may be performed in a vacuum environment. After the plasma treatment, the surface treatment may further include a cleaning process (e.g., rinsing with deionized water, etc.) that may be applied to one or more bonding layers 148. The carrier substrate 146 is then aligned with the interconnect structure 140 and pressed against each other to initiate pre-bonding of the carrier substrate 146 with the interconnect structure 140. The pre-bonding may be performed at room temperature (e.g., in the range of about 20°C to about 25°C). After the pre-bonding, an annealing process may be applied by, for example, heating the interconnect structure 140 and the carrier substrate 146 to a temperature of about 170°C.

[0094] exist Fig. 22In the embodiment of the present invention, the intermediate structure is flipped so that the back side of the substrate 50 faces upward. The back side of the substrate 50 refers to the side opposite to the front side of the substrate 50 on which the device layer 130 is formed. The substrate 50 is then thinned (or at least its thickness is reduced) to remove the back side portion of the substrate 50. The thinning process may include a planarization process (e.g., mechanical grinding, chemical mechanical polishing (CMP)), an etch-back process, or a combination thereof. The thinning process exposes the surface of the STI region 60 and the fin 54 on the back side of the device layer 130.

[0095] A dielectric layer 152 is then deposited over the back side of the device layer 130, such as over the fins 54 and the STI regions 60. The dielectric layer 152 is part of an interconnect structure formed on the device layer 130. The dielectric layer 152 may physically contact the surface of the rest of the fins 54 and the STI regions 60. The dielectric layer 152 may be formed of a material selected from the same set of candidate materials as the first ILD 96, and may be deposited using a method selected from the same set of candidate methods used to deposit the first ILD 96. The first ILD 96 and the dielectric layer 152 may be formed of the same material, or may include different materials.

[0096] exist Fig.23 , power rail contact openings 154 are formed through dielectric layer 152 and fins 54. Power rail contact openings 154 may be formed in dielectric layer 152 using mask 134 as an etch mask by acceptable photolithography and etching techniques, such as using an etching process that is selective to dielectric layer 152 (e.g., etches the material of dielectric layer 152 at a faster rate than etches the material of fins 54). For example, power rail contact openings 154 may be initially formed through dielectric layer 152 by dry etching using NH3 and HF gases. Then, power rail contact openings 154 are extended through fins 54 using acceptable photolithography and etching techniques, such as an etching process that is selective to fins 54 (e.g., etches the material of fins 54 at a faster rate than etches the material of epitaxial source / drain regions 92P). For example, power rail contact openings 154 may be extended through fins 54 by dry etching using a fluorine-based gas such as HF.

[0097] exist Fig.24In the embodiment of the present invention, a metal-semiconductor alloy region 156 is optionally formed in the power rail contact opening 154, such as a portion of the epitaxial source / drain region 92P exposed to the power rail contact opening 154. The metal-semiconductor alloy region 156 can be a silicide region formed by a metal silicide (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), a germanide region formed by a metal germanide (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.), a silicon-germanium-silicon region formed by both a metal silicide and a metal germanide, etc. The metal-semiconductor alloy region 156 can be formed by depositing a metal in the power rail contact opening 154 and then performing a thermal annealing process. The metal can be any metal that can react with the semiconductor material (e.g., silicon, silicon-germanium, germanium, etc.) of the epitaxial source / drain region 92P to form a low-resistance metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals, or alloys thereof. The metal can be deposited by a deposition process such as ALD, CVD, PVD, etc. In an embodiment, the metal-semiconductor alloy region 156 is a silicide region formed of titanium-silicon.After the thermal annealing process, a cleaning process (such as wet cleaning) may be performed to remove any residual metal of the power rail contact opening 154 (eg, the top surface of the dielectric layer 152 and the STI region 60).

[0098] A power rail contact 158 ​​is then formed in the power rail contact opening 154. A liner such as a diffusion barrier layer, an adhesion layer, and a conductive material liner formed in the power rail contact opening 154 may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The liner may be deposited by a conformal deposition process such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc. In some embodiments, the liner may include an adhesion layer, and at least a portion of the adhesion layer may be processed to form a diffusion barrier layer. The conductive material may be tungsten, cobalt, ruthenium, aluminum, nickel, copper, copper alloy, silver, gold, etc. The conductive material may be deposited by ALD, CVD, PVD, etc. A planarization process such as CMP may be performed to remove excess material from the top surface of the dielectric layer 152 and the STI region 60. The remaining liner and conductive material in the power rail contact opening 154 form the power rail contact 158. Power rail contact 158 ​​is physically and electrically coupled to the backside of metal-semiconductor alloy region 156 (if present) or epitaxial source / drain region 92P. The top surfaces of power rail contact 158, dielectric layer 152, and STI region 60 are coplanar (within process variation).

[0099] exist Fig.251 , a conductive feature 160 and a dielectric layer 162 are formed over the dielectric layer 162 and the power rail contacts 158. The dielectric layer 162 and the conductive feature 160 are also part of an interconnect structure formed on the device layer 130. The dielectric layer 162 can be formed of a material selected from the same set of candidate materials as the first ILD 96 and can be deposited using a method selected from the same set of candidate methods used to deposit the first ILD 96. The first ILD 96 and the dielectric layer 162 can be formed of the same material, or can include different materials.

[0100] Conductive component 160 is formed in dielectric layer 162 and may be a conductive line. Forming conductive component 160 may include patterning a groove in dielectric layer 162 using a combination of photolithography and etching processes. The pattern of the opening in dielectric layer 162 may correspond to the pattern of conductive component 160. Conductive component 160 is then formed by depositing a conductive material in the groove. In some embodiments, conductive component 160 includes a metal layer, which may be a single layer or a composite layer including multiple sublayers formed of different materials. In some embodiments, conductive component 160 includes copper, aluminum, cobalt, tungsten, titanium, tantalum, ruthenium, etc. Before filling the groove with conductive material, an optional diffusion barrier layer and / or an optional adhesion layer may be deposited. Suitable materials for barrier layer / adhesion layer include titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, titanium oxide, etc. The material of conductive component 160 may be formed using, for example, CVD, ALD, PVD, electroplating, etc. Conductive features 160 are electrically connected to epitaxial source / drain regions 92P through metal-semiconductor alloy regions 156 (if present) and power rail contacts 158. A planarization process (eg, CMP, grinding, etch back, etc.) may be performed to remove excess portions of conductive features 160 formed over dielectric layer 162.

[0101] Some or all of the conductive features 160 are power rails 160P, which are conductive lines that electrically connect the epitaxial source / drain regions 92P to a reference voltage, a power supply voltage, etc. Advantages may be obtained by placing the power rails 160P on the back side of the device layer 130 rather than on the front side of the device layer 130. For example, the gate density of the nanoFETs and / or the interconnect density of the interconnect structure 140 may be increased. In addition, the back side of the device layer 130 may accommodate wider power rails, thereby reducing resistance and improving the efficiency of power transfer to the nanoFETs. For example, the width of the conductive features 160 may be at least twice the width of the first level conductive lines (e.g., conductive lines 142A) of the interconnect structure 140.

[0102] exist Fig.26, the remainder of the interconnect structure 150 is formed on the back side of the device layer 130, such as above the dielectric layer 162 and the conductive component 160. The interconnect structure 150 may also be referred to as a backside interconnect structure because it is formed on the back side of the device layer 130. The remainder of the interconnect structure 150 may be similar to the interconnect structure 140. For example, the interconnect structure 150 may include similar materials and be formed using a similar process to the interconnect structure 140. In particular, the interconnect structure 150 may include a stacked layer of conductive components 164 formed in a stacked dielectric layer 166. The conductive component 164 may include a wiring line (e.g., for wiring between a contact pad and an external connector formed subsequently). The conductive component 164 may also include a conductive via extending in the dielectric layer 166 to provide vertical interconnection between the stacked layers of conductive lines. Therefore, the interconnect structure 150 includes dielectric layers 152, 162, 166 and conductive components 160, 164. Power rail contacts 158 extend between the interconnect structure 150 and the device layer 130 .

[0103] In some embodiments, the conductive features of the interconnect structure 150 may be patterned to include one or more embedded passive devices, such as resistors, capacitors, inductors, etc. The embedded passive devices may be integrated with the conductive features 160 , 164 (e.g., power rails 160P) to provide circuits (e.g., power circuits) on the back side of the device layer 130 .

[0104] exist FIG. 27A to FIG. 27D , a passivation layer 172, a UBM 174, and an external connector 176 are formed over the interconnect structure 150. The passivation layer 172 may include a polymer such as polyimide, polybenzoxazole (PBO), a benzocyclobutene (BCB)-based polymer, etc. Alternatively, the passivation layer 172 may include an inorganic dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, etc. The material of the passivation layer 172 may be deposited by, for example, CVD, ALD, PVD, etc.

[0105] UBM 174 is formed as a conductive component 164 that penetrates through passivation layer 172 and interconnect structure 150, and external connector 176 is formed on UBM 174. UBM 174 may include one or more layers of copper, nickel, gold, etc. formed by electroplating process, etc. External connector 176 (e.g., solder ball) is formed on UBM 174. The formation of external connector 176 may include placing solder balls on exposed portions of UBM 174 and then reflowing the solder balls. In an optional embodiment, the formation of external connector 176 includes performing an electroplating step to form a solder area above the uppermost conductive component 164 and then reflowing the solder area. In another embodiment, external connector 176 is a metal connector with substantially vertical sidewalls, such as a microbump. UBM 174 and external connector 176 can be used to provide input / output connections for other electronic components (such as other device dies, redistribution structures, printed circuit boards (PCBs), motherboards, etc.). UBM 174 and external connector 176 , which may also be referred to as backside input / output pads, may provide signal, reference voltage, supply voltage, and / or ground connections for the nanoFETs of device layer 130 .

[0106] FIG. 28A to FIG. 28D are various views of semiconductor devices according to some embodiments. FIG. 27A to FIG. 27D The embodiment of the present invention is similar to that of the embodiment of the present invention, except that the conductive wire 118 and the wire contact 128 are omitted, so that the portion of the first ILD 96 above / below the epitaxial source / drain region 92P has no conductive components arranged thereon. When no additional wiring is required, the conductive wire 118 and the wire contact 128 can be omitted. Omitting the conductive wire 118 and the wire contact 128 helps to further reduce the parasitic capacitance of the nano FET, thereby improving its performance.

[0107] Fig.29 is a cross-sectional view of a semiconductor device according to some embodiments. In addition to trimming the second nanostructure 56B, this embodiment is similar to Fig.27A By trimming, the thickness of the second nanostructure 56B is reduced from the second thickness T2 (described above with respect to Figure 2 The trimming may be performed simultaneously with the formation of the groove 98 (discussed in detail in the accompanying drawings). Fig. 12A and Fig. 12B98 is discussed above), or may be performed after the formation of the recess 98. The exposed portions of the second nanostructure 56B and the fin 54 may be trimmed by a feasible etching process that selectively etches the material of the second nanostructure 56B and the fin 54 at a faster rate than the material of the first nanostructure 56A, the inner spacer 84, and the gate spacer 80. The etching may be isotropic. For example, when the fin 54 and the second nanostructure 56B are formed of silicon and the first nanostructure 56A is formed of silicon germanium, the etching process may be a wet etch using a dilute ammonium hydroxide-hydrogen peroxide mixture (APM), a sulfuric acid-hydrogen peroxide mixture (SPM), or the like.

[0108] Embodiments can achieve advantages. Because power rail 160P is attached to the back side of epitaxial source / drain region 92P, contact with the front side of epitaxial source / drain region 92P is undesirable. Avoiding the formation of undesirable contacts on the front side of epitaxial source / drain region 92P helps the resulting semiconductor device not have isolated, unused contacts. Therefore, the parasitic capacitance of the nanoFETs of device layer 130 can be reduced to improve their performance. Moreover, avoiding the formation of such contacts frees up space in first ILD 96 that can be used for other purposes. For example, conductive line 118 can be formed and used for additional wiring. Therefore, the flexibility of signal routing can be improved.

[0109] In an embodiment, a device includes: a first fin; a gate structure above the first fin; a first source / drain region adjacent to the gate structure; an etch stop layer above the first source / drain region; a conductive line above the etch stop layer, the conductive line being isolated from the first source / drain region by the etch stop layer, a top surface of the conductive line being coplanar with a top surface of the gate structure; and a power rail contact extending through the first fin, the power rail contact being connected to the first source / drain region.

[0110] In some embodiments, the device further comprises: a second source / drain region adjacent to the gate structure, an etch stop layer disposed above the second source / drain region; and a source / drain contact extending through the etch stop layer, the source / drain contact connected to the second source / drain region, the top surface of the source / drain contact being coplanar with the top surface of the conductive line and the top surface of the gate structure. In some embodiments, the device further comprises: a dielectric layer above the gate structure and the conductive line; and an interconnect in the dielectric layer, the interconnect connecting the conductive line, the source / drain contact and the gate structure. In some embodiments of the device, the conductive line has a first portion and a second portion, the first portion being disposed above the first source / drain region, and the second portion being disposed adjacent to the first source / drain region. In some embodiments of the device, the first portion of the conductive line has a first height, the second portion of the conductive line has a second height, and the source / drain contact has a third height, the third height being greater than the first height and less than the second height. In some embodiments of the device, the conductive line has a first length, the source / drain contact has a second length, and the first length is greater than the second length, each of the first length and the second length being measured in a direction parallel to the longitudinal axis of the gate structure. In some embodiments of the device, the conductive line has a first width and the source / drain contact has a first width, and the first width is measured in a direction parallel to the longitudinal axis of the first fin. In some embodiments, the device further includes: a second fin, the gate structure is above the second fin; and a second source / drain region, adjacent to the gate structure and inside the second fin, the etch stop layer is arranged above the second source / drain region, and the conductive line extends across the first source / drain region and the second source / drain region. In some embodiments, the device further includes: a nanostructure, above the first fin, and the gate structure surrounds the nanostructure.

[0111] In an embodiment, a device includes: a back-side interconnect structure including a power rail; a front-side interconnect structure including an interconnect; and a device layer, between the back-side interconnect structure and the front-side interconnect structure, the device layer including a transistor, the transistor including: a first epitaxial source / drain region; a source / drain contact contacting the front side of the first epitaxial source / drain region, the interconnect connected to the source / drain contact; a second epitaxial source / drain region; and a power rail contacting the back side of the second epitaxial source / drain region, the power rail connected to the power rail of the power rail contact, the front side of the second epitaxial source / drain region being completely covered by a dielectric material layer.

[0112] In some embodiments of the device, the device layer further includes: a conductive line, a dielectric material is arranged between the conductive line and the front side of the second epitaxial source / drain region, and the surface of the conductive line is coplanar with the surface of the source / drain. In some embodiments of the device, the conductive line has the same width as the source / drain contact in a first direction, and the conductive line has a greater length than the source / drain contact in a second direction, and the second direction is perpendicular to the first direction. In some embodiments of the device, the front interconnect structure further includes: a plurality of wire contacts contacting the conductive line, and the interconnect is connected to the wire contacts. In some embodiments of the device, the interconnect includes a conductive line, and the width of the power rail is greater than the width of the conductive line.

[0113] In an embodiment, a method includes: depositing an etch stop layer on a first epitaxial source / drain region, a second epitaxial source / drain region, and a gate structure, the first epitaxial source / drain region and the second epitaxial source / drain region being arranged at opposite sides of the gate structure; depositing an interlayer dielectric (ILD) on the etch stop layer; etching a first opening through the ILD and the etch stop layer, the first opening exposing a front side of the first epitaxial source / drain region, after etching the first opening, the front side of the second epitaxial source / drain region remains covered by the etch stop layer; and forming a source / drain contact in the first opening, the source / drain contact contacting the first epitaxial source / drain region.

[0114] In some embodiments of the method, etching the first opening includes: patterning a mask over the ILD, the mask having an opening pattern over the first epitaxial source / drain region and the second epitaxial source / drain region; after patterning, covering a portion of the opening pattern over the second epitaxial source / drain region; and after covering, using the mask as an etching mask to etch the ILD and the etching stop layer. In some embodiments of the method, etching the first opening includes: patterning a mask over the ILD, the mask having an opening pattern over the first epitaxial source / drain region but not over the second epitaxial source / drain region; after patterning, using the mask as an etching mask to etch the ILD and the etching stop layer. In some embodiments, the method includes: etching a second opening through the ILD, the second opening exposing the etching stop layer; and forming a conductive line in the second opening, the conductive line contacting the etching stop layer. In some embodiments of the method, etching the first opening includes etching the ILD using a first etching process parameter and etching the etching stop layer using a second etching process parameter, the second etching process parameter being different from the first etching process parameter. In some embodiments of the method, etching the second opening includes etching the ILD using the first etching process parameters and does not include etching the etch stop layer.

[0115] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, comprising: first fin; a gate structure, above the first fin; a first source / drain region, adjacent to the gate structure; an etch stop layer, above the first source / drain region; a conductive line, above the etch stop layer, the conductive line being isolated from the first source / drain region by the etch stop layer, the top surface of the conductive line being coplanar with the top surface of the gate structure; a power rail contact extending through the first fin, the power rail contact connected to the first source / drain region; a second source / drain region adjacent to the gate structure, the etch stop layer being arranged above the second source / drain region; as well as a source / drain contact extending through the etch stop layer, the source / drain contact connected to the second source / drain region, the top surface of the source / drain contact being coplanar with the top surface of the conductive line and the top surface of the gate structure, The conductive line has a first length, the source / drain contact has a second length, and the first length is greater than the second length, each of the first length and the second length being measured in a direction parallel to a longitudinal axis of the gate structure.

2. The semiconductor device according to claim 1, wherein The power rail contacts are connected to power rails in a backside interconnect structure.

3. The semiconductor device according to claim 1, further comprising: a dielectric layer over the gate structure and the conductive line; as well as An interconnect, in the dielectric layer, interconnecting the conductive line, the source / drain contacts, and the gate structure.

4. The semiconductor device according to claim 1, wherein: The conductive line has a first portion and a second portion, the first portion being arranged above the first source / drain region and the second portion being arranged adjacent to the first source / drain region.

5. The semiconductor device according to claim 4, wherein: The first portion of the conductive line has a first height, the second portion of the conductive line has a second height, and the source / drain contact has a third height that is greater than the first height and less than the second height.

6. The semiconductor device according to claim 1, wherein The etch stop layer is formed of a dielectric material.

7. The semiconductor device according to claim 1, wherein The conductive line has a first width and the source / drain contacts have the first width, the first width being measured in a direction parallel to a longitudinal axis of the first fin.

8. The semiconductor device according to claim 1, further comprising: a second fin, the gate structure being above the second fin; as well as A second source / drain region is adjacent to the gate structure and in the second fin, the etch stop layer is disposed over the second source / drain region, and the conductive line extends across the first source / drain region and the second source / drain region.

9. The semiconductor device according to claim 1, further comprising: The nanostructure is above the first fin, and the gate structure surrounds the nanostructure.

10. A semiconductor device comprising: backside interconnect structures, including power rails; a front interconnect structure, including an interconnect; as well as A device layer, between the backside interconnect structure and the frontside interconnect structure, the device layer comprising a transistor, the transistor comprising: a first epitaxial source / drain region; a source / drain contact contacting a front surface of the first epitaxial source / drain region, the interconnect being connected to the source / drain contact; a second epitaxial source / drain region; a power rail contacting a back side of the second epitaxial source / drain region, the power rail being connected to the power rail contact, the front side of the second epitaxial source / drain region being completely covered by a dielectric material; and A conductive line, the dielectric material is arranged between the conductive line and the front side of the second epitaxial source / drain region, the surface of the conductive line is coplanar with the surface of the source / drain contact, the conductive line and the source / drain contact have the same width in a first direction, and the conductive line has a greater length than the source / drain contact in a second direction, and the second direction is perpendicular to the first direction.

11. The semiconductor device according to claim 10, wherein: The transistor further comprises: first fin; A gate structure, above the first fin, The first epitaxial source / drain region is adjacent to the gate structure.

12. The semiconductor device according to claim 11, wherein The nanostructure is above the first fin, and the gate structure surrounds the nanostructure.

13. The semiconductor device according to claim 11, wherein The front interconnect structure further comprises: A plurality of wire contacts contact the conductive wires, and the interconnects are connected to the wire contacts.

14. The semiconductor device according to claim 10, wherein: The width of the power rail is greater than the width of the conductive line.

15. A method for manufacturing a semiconductor device, comprising: depositing an etch stop layer on a first epitaxial source / drain region, a second epitaxial source / drain region, and a gate structure, wherein the first epitaxial source / drain region and the second epitaxial source / drain region are arranged at opposite sides of the gate structure; depositing an interlayer dielectric on the etch stop layer; etching a first opening through the interlayer dielectric and the etch stop layer, the first opening exposing a front side of the first epitaxial source / drain region, the front side of the second epitaxial source / drain region remaining covered by the etch stop layer after etching the first opening; forming a source / drain contact in the first opening, the source / drain contact contacting the first epitaxial source / drain region; etching a second opening through the interlayer dielectric, the second opening exposing the etch stop layer; as well as A conductive line is formed in the second opening, the conductive line contacts the etch stop layer, the conductive line has the same width as the source / drain contact in a first direction, and the conductive line has a greater length than the source / drain contact in a second direction, the second direction being perpendicular to the first direction.

16. The method according to claim 15, wherein: Etching the first opening includes: patterning a mask over the interlayer dielectric, the mask having an opening pattern over the first epitaxial source / drain region and the second epitaxial source / drain region; After the patterning, covering a portion of the opening pattern above the second epitaxial source / drain region; and After the covering, the interlayer dielectric and the etch stop layer are etched using the mask as an etch mask.

17. The method according to claim 15, wherein: Etching the first opening includes: patterning a mask over the interlayer dielectric, the mask having an opening pattern over the first epitaxial source / drain region but not over the second epitaxial source / drain region; After the patterning, the interlayer dielectric and the etch stop layer are etched using the mask as an etch mask.

18. The method according to claim 15, wherein: The etch stop layer is formed of a dielectric material.

19. The method according to claim 18, wherein: Etching the first opening includes etching the interlayer dielectric using first etching process parameters and etching the etch stop layer using second etching process parameters, the second etching process parameters being different from the first etching process parameters.

20. The method according to claim 19, wherein: Etching the second opening includes etching the interlayer dielectric using the first etching process parameters and does not include etching the etch stop layer.

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