Display panel and display device including the same

Abstract

A display panel and a display device including the display panel are provided. The display panel includes a 1-1st sub-pixel and a 1-2nd sub-pixel arranged in a first row, a 2-1st sub-pixel arranged in a second row, and a 3-1st sub-pixel and a 3-2nd sub-pixel arranged in a third row. A first data line extends from the first row to the third row and electrically connects a pixel circuit of the 1-1st sub-pixel, a pixel circuit of the 2-1st sub-pixel, and a pixel circuit of the 3-1st sub-pixel. The 2-1st data line is electrically connected to the pixel circuit of the 1-2nd sub-pixel. The 2-2nd data line is electrically connected to the pixel circuit of the 3-2nd sub-pixel. A first bridge line is arranged on a layer different from the first data line, the 2-1st data line, and the 2-2nd data line and contacts the 2-1st data line and the 2-2nd data line and includes an overlapping portion extending along at least a portion of the first data line.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority benefit of Korean Patent Application No. 10-2020-0007378 filed on January 20, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] One or more exemplary embodiments of the inventive concept relate to a display panel and a display apparatus including the same, and more particularly, to a display panel having an extended display area for displaying an image and a display apparatus including the same. Background Art

[0004] A display panel generally includes sub-pixels that are uniformly arranged to display various images. The display panel is widely used in various electronic devices because of its thinness and light weight.

[0005] Since the display apparatus is used in various electronic devices, various methods may be applied to design the shape of the display apparatus.

[0006] However, in the existing display panel, when the display panel includes components as electronic elements, the area of ​​a display region for displaying an image is limited. Summary of the invention

[0007] One or more exemplary embodiments include a display panel and a display device including the display panel, the display panel having an extended display area so as to display an image even in an area where a component as an electronic element is arranged. However, it should be understood that the exemplary embodiments described herein should be regarded as descriptive only and not for limiting the present invention.

[0008] Additional aspects will be set forth in part in the detailed description which follows and, in part, will be obvious from the description, or may be learned by practice of the disclosed embodiments.

[0009] According to one or more exemplary embodiments, the display panel includes a 1-1 sub-pixel and a 1-2 sub-pixel arranged in a first row. The 2-1 sub-pixel is arranged in a second row. The 3-1 sub-pixel and the 3-2 sub-pixel are arranged in a third row. The first data line is configured to electrically connect the pixel circuit of the 1-1 sub-pixel, the pixel circuit of the 2-1 sub-pixel, and the pixel circuit of the 3-1 sub-pixel. The 2-1 data line is configured to electrically connect the pixel circuit of the 1-2 sub-pixel. The 2-2 data line is configured to electrically connect the pixel circuit of the 3-2 sub-pixel. The first bridge wire is arranged on a layer different from the first data line, the 2-1 data line, and the 2-2 data line. The first bridge wire has a first side in contact with the 2-1 data line and a second side in contact with the 2-2 data line. The first bridge wire has a portion extending along at least a portion of the first data line.

[0010] The 1-1th sub-pixel, the 1-2th sub-pixel, the 2-1th sub-pixel, the 3-1th sub-pixel and the 3-2nd sub-pixel may be arranged on a substrate, wherein an orthogonal projection image of a portion of the first bridging line extending along at least a portion of the first data line on the top surface of the substrate may overlap with an orthogonal projection image of the first data line on the top surface of the substrate.

[0011] The display panel may further include: 1-3 sub-pixels and 1-4 sub-pixels in a first row, wherein the 1-3 sub-pixels are located in a direction opposite to the 1-2 sub-pixels relative to the 1-1 sub-pixels, and the 1-4 sub-pixels are located between the 1-1 sub-pixels and the 1-2 sub-pixels; 2-2 sub-pixels in a second row; 3-3 sub-pixels and 3-4 sub-pixels in a third row, wherein the 3-3 sub-pixel is located in a direction opposite to the 3-2 sub-pixel relative to the 3-1 sub-pixel, and the 3-4 sub-pixel is located between the 3-1 sub-pixel and the 3-2 sub-pixel; and the 1-3 sub-pixels are located in a direction opposite to the 3-2 sub-pixel relative to the 3-1 sub-pixel, and the 3-4 sub-pixel is located between the 3-1 sub-pixel and the 3-2 sub-pixel. A third data line electrically connected to the pixel circuit of the pixel, the pixel circuit of the 2-2 sub-pixel and the pixel circuit of the 3-3 sub-pixel; a 4-1 data line electrically connected to the pixel circuit of the 1-4 sub-pixels; a 4-2 data line electrically connected to the pixel circuit of the 3-4 sub-pixels; and a second bridge line, wherein the second bridge line is located on a different layer from the third data line, the 4-1 data line and the 4-2 data line, the second bridge line has one side in contact with the 4-1 data line and the other side in contact with the 4-2 data line, and the second bridge line has a portion extending along at least a portion of the third data line.

[0012] The 1-3 sub-pixel, the 1-4 sub-pixel, the 2-2 sub-pixel, the 3-3 sub-pixel and the 3-4 sub-pixel may be located on a substrate, wherein an orthogonal projection image of a portion of the second bridging line extending along at least a portion of the third data line on the top surface of the substrate may overlap with an orthogonal projection image of the third data line on the top surface of the substrate.

[0013] The third data line, the 4-1 data line, and the 4-2 data line may be located on the same layer as the first data line, the 2-1 data line, and the 2-2 data line, and the second bridge line may be located on the same layer as the first bridge line.

[0014] The first bridge line and the second bridge line may be located on an insulating layer covering the first data line, the 2-1 data line, the 2-2 data line, the third data line, the 4-1 data line, and the 4-2 data line.

[0015] The display panel may include a component area and a main display area surrounding the component area, wherein the 1-1th subpixel, the 1-2th subpixel, the 3-1th subpixel, and the 3-2nd subpixel may be located in the main display area, and the 2-1th subpixel may be located in the component area.

[0016] The component area may include a transmissive area outside the 2-1th sub-pixel.

[0017] The display panel may further include an additional data line electrically connected to the pixel circuit of one sub-pixel in the component area, wherein the additional data line may extend along an edge of the transmission area.

[0018] The resolution of the widget area may be 1 / 2 or less than 1 / 2 of the resolution of the main display area.

[0019] The display panel may also include an auxiliary driving voltage line electrically connected to the pixel circuit of the 2-1th sub-pixel to apply a driving voltage to the pixel circuit of the 2-1th sub-pixel, wherein the auxiliary driving voltage line may be located in the component area and on a different layer from the first data line and the first bridge line and overlap with the first data line and the first bridge line.

[0020] The auxiliary driving voltage line may be located below the first data line and the first bridge line.

[0021] The display panel may further include: a driving voltage line in the main display area, the driving voltage line being electrically connected to the pixel circuit of the 1-1th sub-pixel to apply a driving voltage to the pixel circuit of the 1-1th sub-pixel.

[0022] The driving voltage line may be located on a layer where the first data line is located.

[0023] The width of the auxiliary driving voltage line may be greater than the width of the driving voltage line.

[0024] The display panel may also include: 1st-5th sub-pixels in the first row; 3rd-5th sub-pixels in the third row; and a fifth data line electrically connecting the pixel circuits of the 1st-5th sub-pixels with the pixel circuits of the 3rd-5th sub-pixels, wherein the display panel may include a component area and a main display area surrounding the component area, wherein the 1-1st sub-pixel, 1-2nd sub-pixel, 1-5th sub-pixel, 3-1st sub-pixel, 3-2nd sub-pixel and 3-5 sub-pixel may be located in the main display area, and the 2-1st sub-pixel may be located in the component area, wherein the fifth data line may span the component area but may not be connected to the pixel circuits of the sub-pixels in the component area.

[0025] The display panel may also include: 1st-6th sub-pixels in the first row; 3rd-6th sub-pixels in the third row; 6-1st data line electrically connected to the 1st-6th sub-pixels; 6-2nd data line electrically connected to the 3rd-6th sub-pixels; and a third bridge line on a different layer from the 6-1st data line and the 6-2nd data line, the third bridge line having one side in contact with the 6-1st data line and the other side in contact with the 6-2nd data line, the third bridge line having a portion extending along at least a portion of the fifth data line.

[0026] The 6-1st data line and the 6-2nd data line may be located on a layer where the first data line, the 2-1st data line, and the 2-2nd data line are located, and the third bridge line may be located on a layer where the first bridge line is located.

[0027] The first bridge line and the third bridge line may be located on an insulating layer covering the first data line, the 2-1st data line, the 2-2nd data line, the 6-1st data line, and the 6-2nd data line.

[0028] According to one or more exemplary embodiments, a display device includes: a display panel including a component area and a main display area surrounding the component area, and an electronic component arranged to correspond to the component area of ​​the display panel. The display panel includes a 1-1 sub-pixel and a 1-2 sub-pixel arranged in a first row. The 2-1 sub-pixel is arranged in a second row. The 3-1 sub-pixel and the 3-2 sub-pixel are arranged in a third row. The first data line is configured to electrically connect the pixel circuit of the 1-1 sub-pixel, the pixel circuit of the 2-1 sub-pixel, and the pixel circuit of the 3-1 sub-pixel. The 2-1 data line is configured to electrically connect the pixel circuit of the 1-2 sub-pixel. The 2-2 data line is configured to electrically connect the pixel circuit of the 3-2 sub-pixel. The first bridge line is arranged on a layer different from the first data line, the 2-1 data line, and the 2-2 data line. The first bridge line has a first side in contact with the 2-1 data line and a second side in contact with the 2-2 data line. The first bridge line has a portion extending along at least a portion of the first data line.

[0029] The electronic component may include an imaging device.

[0030] According to an exemplary embodiment of the inventive concept, a display panel includes a component area surrounded by a main display area. The component area has a plurality of auxiliary sub-pixels and a transmission area surrounding the plurality of auxiliary sub-pixels. The transmission area is configured so that light is transmitted through the transmission area. The main display area has a first plurality of main sub-pixels arranged in a lower row adjacent to a lower side of the component area and a second plurality of main sub-pixels arranged in an upper row adjacent to an upper side of the component area. At least one first data line extends from the lower row across the component area to the upper row. Each of the at least one first data line is configured to electrically connect the sub-pixels in the lower row and the upper row to the first auxiliary sub-pixel. At least one lower second data line is configured to electrically connect the sub-pixels in the lower row. At least one upper second data line is configured to electrically connect the sub-pixels in the upper row. Each of the at least one bridge line has a first end connected to one of the at least one lower second data lines and a second end connected to one of the at least one upper second data lines. The at least one bridge line is disposed on a different layer from the at least one first data line, and each of the at least one bridge line has an overlapping portion extending along at least a portion of one of the at least one first data line.

[0031]

[0011] Other aspects, features and advantages in addition to those described above will be apparent from the detailed description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and other aspects, features and advantages of exemplary embodiments of the inventive concept will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0033] Figure 1 is a perspective view of a display device according to an exemplary embodiment of the inventive concept;

[0034] Figure 2 is an exemplary embodiment according to the present inventive concept. Figure 1 A cross-sectional view of the display device taken along line AA';

[0035] Figure 3 is an exemplary embodiment according to the inventive concept and may include Figure 1 A plan view of a display panel in a display device;

[0036] Figure 4 is a diagram showing an exemplary embodiment according to the concept of the present invention Figure 3 A plan view of a pixel arrangement structure in a main display area of ​​a display panel;

[0037] Figure 5 and Figure 6 is a diagram showing an exemplary embodiment according to the concept of the present invention Figure 3 A plan view of a pixel arrangement structure in a component area of ​​a display panel;

[0038] Figure 7 and Figure 8 According to an exemplary embodiment of the present inventive concept Figure 3 An equivalent circuit diagram of a pixel circuit of a sub-pixel in a display panel;

[0039] Fig. 9 is an exemplary embodiment according to the present inventive concept. Figure 4 The line I-I' and Figure 6 A cross-sectional view of the pixel arrangement structure taken along line II-II';

[0040] Fig.10 and Fig.11 is a diagram showing an exemplary embodiment according to the concept of the present invention Figure 3 A plan view of the arrangement of sub-pixels and circuit lines of a display panel;

[0041] Fig.12 is an exemplary embodiment according to the present inventive concept. Fig.10 and Fig.11 A cross-sectional view of the arrangement of sub-pixels and line lines taken along line III-III';

[0042] Fig.13 is a diagram showing an exemplary embodiment according to the concept of the present invention Figure 3 A plan view of an arrangement of driving voltage lines and auxiliary driving voltage lines of a display panel;

[0043] Fig.14 and Fig.15 is a plan view showing an arrangement of sub-pixels and wiring lines of a display panel according to an exemplary embodiment of the inventive concept; and

[0044] Fig.16 and Fig.17 is a plan view illustrating an arrangement of sub-pixels and wiring lines of a display panel according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0045] Reference will now be made in detail to embodiments, examples of which are shown in the accompanying drawings, in which similar reference numerals always indicate similar elements. In this regard, exemplary embodiments of the inventive concept may have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, exemplary embodiments of the inventive concept are described below only by reference to the accompanying drawings to explain various aspects of the inventive concept. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. Throughout the disclosure, the expression "at least one of a, b, or c" means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0046] Although exemplary embodiments of the inventive concept are shown in the drawings and described in the detailed description thereof, the exemplary embodiments of the inventive concept may have different modified embodiments. When referring to the exemplary embodiments described with reference to the drawings, the effects and features of the inventive concept and the methods for achieving these will be apparent. However, the inventive concept may be implemented in many different forms and should not be construed as being limited to the exemplary embodiments set forth herein.

[0047] One or more exemplary embodiments of the inventive concept will be described in more detail below with reference to the accompanying drawings. Regardless of the reference numerals, those components that are the same or corresponding are denoted by the same reference numerals, and redundant explanations are omitted for convenience of explanation.

[0048] It will be understood that when a layer, region, or component is referred to as being "formed on" or "arranged on" another layer, region, or component, it may be formed directly or indirectly on the other layer, region, or component. For example, there may be an intermediate layer, region, or component. However, when a layer, region, or component is referred to as being "directly formed on" or "directly arranged on" another layer, region, or component, there may be no intermediate layer, region, or component. For convenience of explanation, the size of the elements in the drawings may be exaggerated. For example, since the size and thickness of the components in the drawings are arbitrarily shown for convenience of explanation, the following embodiments are not limited thereto.

[0049] In the following exemplary embodiments, the x-axis, y-axis, and z-axis are not limited to the three axes of the rectangular coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other.

[0050] Figure 1 is a schematic perspective view of a display apparatus 1 according to an exemplary embodiment of the inventive concept.

[0051] Reference Figure 1In an exemplary embodiment, the display device 1 includes a display area DA and a peripheral area PA outside the display area DA. The display area DA includes a component area CA and a main display area MDA at least partially surrounding the component area CA. In an exemplary embodiment, the component area CA and the main display area MDA may display images individually or together. The peripheral area PA may be a non-display area in which display elements are not arranged. The display area DA may be completely surrounded by the peripheral area PA. However, exemplary embodiments of the inventive concept are not limited thereto. For example, in other exemplary embodiments, the display area DA may extend to at least one edge of the display device 1 and may not be surrounded by the peripheral area PA on at least one side.

[0052] Figure 1 It is shown that one component area CA is located in the main display area MDA. However, exemplary embodiments of the inventive concept are not limited thereto. For example, in other exemplary embodiments, the display device 1 may have a plurality of component areas CA. The shape and size of each of the plurality of component areas CA may be the same, or the shape and size of at least one of the plurality of component areas CA may be different from each other. The plurality of component areas CA may be arranged in the display area DA in various different arrangements.

[0053] Hereinafter, an organic light-emitting display device will be described as a display device 1 according to an exemplary embodiment of the inventive concept. However, the exemplary embodiments of the inventive concept are not limited thereto. For example, in other exemplary embodiments, the display device 1 may be an inorganic light-emitting display device (or an inorganic electroluminescence (EL) display device), a quantum dot light-emitting display device, etc. For example, the emission layer of the display element of the display device 1 may include an organic material, an inorganic material, a quantum dot, an organic material and a quantum dot, or an inorganic material and a quantum dot.

[0054] exist Figure 1 In the exemplary embodiment of the present invention, the component area CA is shown to have a substantially circular shape. However, exemplary embodiments of the inventive concept are not limited thereto, and when viewed in a direction substantially perpendicular to the upper surface of the substrate (e.g., in a plan view in a plane defined by the x-direction and the y-direction), the component area CA may have one of various shapes including an ellipse, a polygon (such as a square, a star, and a diamond), an irregular shape, and the like.

[0055] exist Figure 1In an exemplary embodiment, when viewed in a direction substantially perpendicular to the upper surface of the substrate (e.g., in a plan view in a plane defined by the x-direction and the y-direction), the component area CA is arranged at the center (e.g., in the x-direction) of the upper side (+y-direction) of the main display area MDA having a substantially rectangular shape. However, exemplary embodiments of the inventive concept are not limited thereto. For example, the component area CA may be arranged in various different areas of the main display area MDA, such as on one side (e.g., the upper right side or the upper left side) of the main display area MDA having a substantially rectangular shape in the x-direction. Although the main display area MDA is Figure 1 In the exemplary embodiment of the present invention, the main display area MDA is shown to have a substantially rectangular shape, but the exemplary embodiments of the inventive concept are not limited thereto. In other exemplary embodiments, the main display area MDA may have various shapes including a spherical shape, a polygonal shape, and an irregular shape.

[0056] The display apparatus 1 may provide an image using a plurality of main sub-pixels Pm arranged in the main display area MDA and a plurality of auxiliary sub-pixels Pa arranged in the component area CA.

[0057] As shown below Figure 2 As described in the exemplary embodiment of the present invention, the component 20 as an electronic component may be arranged below the component area CA. In the exemplary embodiment, the component 20 is a camera using infrared light or visible light and may include an imaging device. Alternatively, the component 20 may have a function of receiving sound. In order to reduce the functional limitations of the component 20, the component area CA may include a transmission area TA for transmitting light and / or sound output from the component 20 to the outside and / or transmitting light and / or sound from the outside to the component 20. The transmission area TA may not include pixels or sub-pixels. By the display panel 10 according to the exemplary embodiment of the inventive concept and the display device 1 having the display panel 10 according to the exemplary embodiment of the inventive concept, when infrared light is transmitted through the component area CA, the transmittance may be about 10% or more, for example, about 20% or more, about 25% or more, about 50% or more, about 85% or more, or about 90% or more.

[0058] A plurality of auxiliary sub-pixels Pa may be arranged in the component area CA. The plurality of auxiliary sub-pixels Pa may emit light to generate an image. The image displayed in the component area CA is an auxiliary image and may have a lower resolution than the image displayed in the main display area MDA. Since the component area CA includes a transmission area TA capable of transmitting light and sound and no sub-pixels are arranged in the transmission area TA, the number of auxiliary sub-pixels Pa that may be arranged per unit area may be less than the number of main sub-pixels Pm arranged per unit area in the main display area MDA.

[0059] Figure 2 is an exemplary embodiment according to the present inventive concept. Figure 1 Schematic cross-sectional view of a portion of the display device 1 taken along line AA′.

[0060] Reference Figure 2 In an exemplary embodiment, the display device 1 may include a display panel 10 and a component 20, wherein the display panel 10 includes a display element, and the component 20 is located below the display panel 10 (for example, in the -z direction) and is an electronic component corresponding to the component area CA.

[0061] The display panel 10 may include a substrate 100, a display element layer 200 arranged on the substrate 100, and a thin film encapsulation layer 300 that seals the display element layer 200. The display panel 10 may also include various components. For example, Figure 2 As shown in the exemplary embodiment of FIG. 1 , the display panel 10 may further include a lower protective film 175 and the like arranged under the substrate 100 .

[0062] In an exemplary embodiment, the substrate 100 may include glass or a polymer resin. For example, the substrate 100 may include a polymer resin, such as at least one compound selected from polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, and cellulose acetate propionate. The substrate 100 including the polymer resin may be flexible, rollable, or bendable. The substrate 100 may have a multilayer structure including a layer including the aforementioned polymer resin and an inorganic layer. For example, the substrate 100 may include two layers including the aforementioned polymer resin and an inorganic barrier layer interposed therebetween. However, exemplary embodiments of the inventive concept are not limited thereto.

[0063] The display element layer 200 may include a circuit layer including a thin film transistor TFT, an organic light emitting diode OLED as a display element, and an insulating layer IL between the circuit layer and the organic light emitting diode OLED.

[0064] The main sub-pixel Pm is arranged in the main display area MDA. The main sub-pixel Pm includes a pixel circuit including a thin film transistor TFT and an organic light emitting diode OLED electrically connected to the pixel circuit. In addition, a line line electrically connected to the main sub-pixel Pm and the auxiliary sub-pixel Pa may be arranged in the main display area MDA.

[0065] In the component area CA, an auxiliary sub-pixel Pa is arranged, and the auxiliary sub-pixel Pa includes a pixel circuit including a thin film transistor TFT and an organic light emitting diode OLED electrically connected to the pixel circuit. In addition, the component area CA may have a transmission area TA that does not include a thin film transistor TFT and in which no sub-pixel is arranged. The transmission area TA is an area through which light / sound / signal emitted from the component 20 or light / sound / signal incident to the component 20 (for example, from the external environment) may at least partially pass.

[0066] The component 20 located below the display panel 10 (for example, in the -z direction) may be positioned to correspond to the component area CA. The component 20 may be an electronic component that uses light or sound. For example, the component 20 may be an imaging device such as a camera, a sensor that receives and uses light (such as an infrared sensor), a sensor that outputs and senses light or sound to measure distance or recognize fingerprints or the like, a small lamp that outputs light, or a speaker that outputs sound. However, exemplary embodiments of the inventive concept are not limited thereto. Electronic components that use light may use light in different bands, such as visible light, infrared light, and ultraviolet light. In the component area CA, one component 20 may be arranged or a plurality of components 20 may be arranged. For example, a first component (such as a light emitting element) and a second component (such as a light receiving element) may be arranged to correspond to one component area CA. Alternatively, one component 20 may include a light emitting portion and a light receiving portion, and may be arranged to correspond to one component area CA.

[0067] In exemplary embodiments, the thin film encapsulation layer 300 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. Figure 2 It is illustrated as an example that the thin film encapsulation layer 300 (eg, in the z direction) includes a first inorganic encapsulation layer 310, a second inorganic encapsulation layer 330, and an organic encapsulation layer 320 therebetween. However, exemplary embodiments of the inventive concept are not limited thereto.

[0068] In an exemplary embodiment, the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include one or more inorganic insulating materials selected from aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The organic encapsulation layer 320 may include a polymer material. For example, the polymer material may include polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, hexamethyldisiloxane, acrylic resin (e.g., polymethyl methacrylate or polyacrylic acid) or any combination thereof.

[0069] The lower protective film 175 may be attached to the lower surface of the substrate 100 and may support and protect the substrate 100. Figure 2As shown in the exemplary embodiment of , the upper surface of the lower protective film 175 may directly contact the lower surface of the substrate 100. The lower protective film 175 may have an opening 175OP corresponding to the component area CA. Since the lower protective film 175 has the opening 175OP, light / sound passing through the component area CA may be guided to the component 20, or light / sound from the component 20 may enter the component area CA. In an exemplary embodiment, the lower protective film 175 may include polyethylene terephthalate or polyimide.

[0070] The area of ​​the component region CA (for example, the area in the x-direction and the y-direction) may be larger than the area where the components 20 are arranged. Figure 2 The opening 175OP in the middle component area CA and the lower protection film 175 has the same area, but this is only an example. The area of ​​the opening 175OP in the lower protection film 175 may not be equal to the area of ​​the component area CA. For example, the area of ​​the opening 175OP may be smaller than the area of ​​the component area CA.

[0071] Although Figure 2 Although not shown in the figure, an input sensing member for sensing a touch input may be arranged on the display panel 10. In addition, an anti-reflection member including a polarizer and a retarder or including a color filter and a black matrix may be arranged on the display panel 10. Furthermore, a component such as a cover having a transparent window may be arranged on the display panel 10.

[0072] exist Figure 2 As described above, the thin film encapsulation layer 300 is used as an encapsulation member for sealing the display element layer 200. However, exemplary embodiments of the inventive concept are not limited thereto. For example, an encapsulation substrate coupled to the substrate 100 by a sealant or a frit may be used as a member for sealing the display element layer 200.

[0073] Figure 3 is an exemplary embodiment according to the inventive concept and may include Figure 1 Schematic plan view of a display panel 10 in a display device 1 of FIG.

[0074] Reference Figure 3 In an exemplary embodiment, various components constituting the display panel 10 are arranged on a substrate 100. The substrate 100 includes a display area DA and a peripheral area PA surrounding the display area DA (e.g., in the x-direction and the y-direction). The display area DA includes a main display area MDA and a component area CA, wherein a main image is displayed on the main display area MDA, the component area CA includes a transmissive area TA, and an auxiliary image is displayed on the component area CA. In an exemplary embodiment, the auxiliary image may form an integral image together with the main image, and the auxiliary image may be an image independent of the main image.

[0075] A plurality of main sub-pixels Pm are arranged in the main display area MDA. Each of the plurality of main sub-pixels Pm may include a display element, such as an organic light emitting diode OLED. Each of the plurality of main sub-pixels Pm may emit, for example, red light, green light, blue light, or white light. However, exemplary embodiments of the inventive concept are not limited thereto. As described above with reference to Figure 2 As described, the thin film encapsulation layer 300 may cover the main display area MDA for protecting it from ambient air or moisture.

[0076] The component area CA may be arranged within the main display area MDA, and a plurality of auxiliary sub-pixels Pa may be arranged in the component area CA. Each of the plurality of auxiliary sub-pixels Pa may include a display element such as an organic light emitting diode. Each of the plurality of auxiliary sub-pixels Pa may emit, for example, red light, green light, blue light, or white light. However, exemplary embodiments of the inventive concept are not limited thereto. As described above with reference to Figure 2 As described, the thin film encapsulation layer 300 may cover the component area CA for protecting it from ambient air or moisture.

[0077] The component area CA may include a transmission area TA. The transmission area TA may be arranged to surround the plurality of auxiliary sub-pixels Pa. Alternatively, the transmission area TA may be arranged in a lattice shape with the plurality of auxiliary sub-pixels Pa (see Fig.10 ).

[0078] Since the component area CA includes the transmissive area TA, the resolution of the component area CA may be lower than that of the main display area MDA. For example, in an exemplary embodiment, the resolution of the component area CA may be about 1 / 2, about 3 / 8, about 1 / 3, about 1 / 4, about 2 / 9, about 1 / 8, about 1 / 9, about 1 / 16, or the like of the resolution of the main display area MDA. For example, in an exemplary embodiment, the resolution of the main display area MDA may be about 400 ppi or more, and the resolution of the component area CA may be about 200 ppi or about 100 ppi.

[0079] Each of the main subpixel Pm and the auxiliary subpixel Pa may be electrically connected to an external circuit arranged in the peripheral area PA. The first scan driving circuit 110, the second scan driving circuit 120, the terminal 140, the first power line 160, and the second power line 170 may be arranged in the peripheral area PA.

[0080] The first scan driving circuit 110 may apply a scan signal to each of the main sub-pixels Pm and the auxiliary sub-pixels Pa through the scan lines SL. In addition, the first scan driving circuit 110 may apply an emission control signal to each pixel through the emission control line EL. The second scan driving circuit 120 may be located on an opposite side of the first scan driving circuit 110 relative to the main display area MDA (e.g., in the +x direction), and may be substantially parallel to the first scan driving circuit 110. The first plurality of main sub-pixels Pm in the main display area MDA may be electrically connected to the first scan driving circuit 110, and the remaining main sub-pixels Pm (e.g., the second plurality of main sub-pixels Pm) may be electrically connected to the second scan driving circuit 120. The second scan driving circuit 120 may apply a scan signal and an emission control signal to the main sub-pixels Pm electrically connected to the second scan driving circuit 120 among the main sub-pixels Pm in the main display area MDA via the scan lines SL and the emission control lines EL. The first plurality of auxiliary sub-pixels Pa in the component area CA may be electrically connected to the first scan driving circuit 110, and the remaining auxiliary sub-pixels Pa (e.g., the second plurality of auxiliary sub-pixels Pa) may be electrically connected to the second scan driving circuit 120. The second scan driving circuit 120 may apply scan signals and emission control signals to the auxiliary sub-pixels Pa electrically connected to the second scan driving circuit 120 among the auxiliary sub-pixels Pa in the component area CA via the scan lines SL and the emission control lines EL.

[0081] Alternatively, each of the main sub-pixels Pm in the main display area MDA may be electrically connected to both the first scan driving circuit 110 and the second scan driving circuit 120, and thus may receive a scan signal via a scan line SL connected to both the first scan driving circuit 110 and the second scan driving circuit 120 and receive an emission control signal via an emission control line EL connected to both the first scan driving circuit 110 and the second scan driving circuit 120. Each of the auxiliary sub-pixels Pa in the component area CA may also be electrically connected to both the first scan driving circuit 110 and the second scan driving circuit 120, and thus may receive a scan signal via a scan line SL connected to both the first scan driving circuit 110 and the second scan driving circuit 120 and receive an emission control signal via an emission control line EL connected to both the first scan driving circuit 110 and the second scan driving circuit 120.

[0082] However, exemplary embodiments of the inventive concept are not limited thereto, and in some exemplary embodiments the second scan driving circuit 120 may be omitted. In such an embodiment, all main sub-pixels Pm in the main display area MDA may be electrically connected to the first scan driving circuit 110, and similarly, all auxiliary sub-pixels Pa in the component area CA may be electrically connected to the first scan driving circuit 110.

[0083] For reference, although in Figure 3 1 and 12. The first scan drive circuit 110 is shown as one component, but exemplary embodiments of the inventive concept are not limited thereto. For example, the first scan drive circuit 110 may include a first scan signal drive circuit and a first emission control drive circuit that are separated from each other (e.g., in the x-direction and / or the y-direction). In this embodiment, the first scan signal drive circuit may be electrically connected to the scan line SL, and the first emission control drive circuit may be electrically connected to the emission control line EL. The second scan drive circuit 120 may also include a second scan signal drive circuit and a second emission control drive circuit that are separated from each other. In this embodiment, the second scan signal drive circuit may be electrically connected to the scan line SL, and the second emission control drive circuit may be electrically connected to the emission control line EL.

[0084] The terminal 140 may be arranged on one side of the substrate 100. For example, Figure 3 As shown in the exemplary embodiment of , the terminal 140 may be arranged on the lower side (e.g., in the -y direction) of the substrate 100. The terminal 140 may be exposed by not being covered by the insulating layer and electrically connected to the printed circuit board PCB. The terminal PCB-P of the printed circuit board PCB may be electrically connected to the terminal 140 of the display panel 10. The printed circuit board PCB transmits a signal or power of the controller to the display panel 10. The control signal generated by the controller may be transmitted to each of the first scan driving circuit 110 and the second scan driving circuit 120 through the printed circuit board PCB. The controller may transmit the first power supply voltage ELVDD (see Figure 7 and Figure 8 ) is provided to the first power line 160, and the second power voltage ELVSS (see Figure 7 and Figure 8 ) is provided to the second power line 170. The first power voltage ELVDD may be applied to each of the main sub-pixel Pm and the auxiliary sub-pixel Pa through the driving voltage line PL connected to the first power line 160, and the second power voltage ELVSS may be applied to the opposite electrode of each of the main sub-pixel Pm and the auxiliary sub-pixel Pa connected to the second power line 170. The first power voltage ELVDD may be referred to as a driving voltage. Hereinafter, for convenience, the first power voltage ELVDD is referred to as a driving voltage.

[0085] The data driving circuit 150 is electrically connected to the data line DL. The data signal of the data driving circuit 150 may be applied to the main sub-pixel Pm and the auxiliary sub-pixel Pa through the connection line 151 connected to the terminal 140 and the data line DL connected to the connection line 151. Figure 3The exemplary embodiment of the present invention shows that the data driving circuit 150 is arranged on the printed circuit board PCB, but the exemplary embodiments of the inventive concept are not limited thereto, and in other exemplary embodiments, the data driving circuit 150 may be arranged on the substrate 100. For example, the data driving circuit 150 may be arranged between the terminal 140 and the first power line 160 (e.g., in the y direction).

[0086] The first power line 160 may include a first sub-line 162 and a second sub-line 163 extending in the x-axis direction and spaced apart from the first power line 160 in the y-axis, wherein the main display area MDA is located between the first sub-line 162 and the second sub-line 163. The second sub-line 163 located in the +y direction of the main display area MDA may be electrically connected to the first sub-line 162 located in the -y direction of the main display area MDA via some of the driving voltage lines PL extending along the y-axis so as to cross the main display area MDA, as shown in FIG. Figure 3 For example, some of the driving voltage lines PL may be electrically connected to only the first sub-line 162, some of the driving voltage lines PL may be electrically connected to only the second sub-line 163, and some of the driving voltage lines PL may be electrically connected to the first sub-line 162 and the second sub-line 163. Alternatively, a line may be located in the peripheral area PA so that the line may electrically connect the second sub-line 163 to the first sub-line 162.

[0087] The second power line 170 may have a loop shape having one open side (eg, a lower side in the y direction) and partially surrounding the main display area MDA.

[0088] Figure 4 It is shown Figure 3 A schematic plan view of a pixel arrangement structure in a main display area MDA of a display panel 10 is shown, and Figure 5 and Figure 6 is a diagram showing an exemplary embodiment according to the concept of the present invention Figure 3 1 is a schematic plan view of a pixel arrangement structure in a component area CA of a display panel 10.

[0089] like Figure 4 As shown in the exemplary embodiment of , a plurality of main sub-pixels Pm may be arranged in the main display area MDA. Each of the plurality of main sub-pixels Pm may include a display element such as an organic light emitting diode. Each of the plurality of main sub-pixels Pm may emit one of red light, green light, blue light, and white light. However, the exemplary embodiments of the inventive concept are not limited thereto. For example, the plurality of main sub-pixels Pm may include a main sub-pixel Pr that emits red light, a main sub-pixel Pg that emits green light, and a main sub-pixel Pb that emits blue light. Figure 4In the exemplary embodiment of the present invention, the plurality of main sub-pixels Pm are arranged in a pentile type. However, the exemplary embodiments of the inventive concept are not limited thereto. For example, in other exemplary embodiments, the plurality of main sub-pixels Pm may be arranged in a stripe shape or various other shapes.

[0090] like Figure 5 As shown in the exemplary embodiment of , a plurality of auxiliary sub-pixels Pa may be arranged in the component area CA. Each of the plurality of auxiliary sub-pixels Pa may include a display element such as an organic light emitting diode. Each of the plurality of auxiliary sub-pixels Pa may emit one of red light, green light, blue light, and white light. However, exemplary embodiments of the inventive concept are not limited thereto.

[0091] The component area CA may include a pixel group PG including at least one auxiliary sub-pixel Pa and a transmission area TA. Figure 5 As shown in the exemplary embodiment of FIG. 1 , the pixel groups PG and the transmission areas TA may be alternately arranged in the x-axis direction and the y-axis direction, and, for example, may be arranged in a lattice shape. However, the exemplary embodiments of the inventive concept are not limited thereto. Figure 5 As shown in the exemplary embodiment of FIG. 1 , the component area CA may include a plurality of pixel groups PG and a plurality of transmission areas TA.

[0092] The pixel group PG may be defined as a sub-pixel set in which a plurality of auxiliary sub-pixels Pa or main sub-pixels Pm are grouped in a preset unit. Figure 5 and Figure 6 In the exemplary embodiment of FIG. 1 , one pixel group PG includes eight auxiliary sub-pixels Pa. In other words, in Figure 5 and Figure 6 , one pixel group PG includes a red sub-pixel Pr, a green sub-pixel Pg, a blue sub-pixel Pb, and a green sub-pixel Pg arranged in the x-axis direction in a first row, and a blue sub-pixel Pb, a green sub-pixel Pg, a red sub-pixel Pr, and a green sub-pixel Pg arranged in parallel in the x-axis direction in a second row different from the first row. However, exemplary embodiments of the inventive concept are not limited thereto. For example, the number or arrangement of the auxiliary sub-pixels Pa included in the pixel group PG may be modified according to the resolution of the component area CA. In addition, it is understood that Figure 5 A pixel group PG shown in does not refer to one pixel, but includes a plurality of pixels. Figure 4As shown in the exemplary embodiment of , for the main sub-pixel Pm in the main display area MDA, the pixel group PG can be defined in the same manner. The description of the pixel group PG of the auxiliary sub-pixel Pa to be described later can also be applied to the pixel group PG of the main sub-pixel Pm. However, the exemplary embodiments of the inventive concept are not limited thereto, and in some exemplary embodiments, the pixel group PG for the main sub-pixel Pm may have a different number of sub-pixels or a different sub-pixel arrangement than the pixel group PG for the auxiliary sub-pixel Pa.

[0093] As described above, the pixel group PG may include eight auxiliary sub-pixels Pa, and Figure 5 The auxiliary sub-pixels Pa are shown to be arranged in a pentile type. However, the auxiliary sub-pixels Pa may be arranged in a stripe shape or other various shapes.

[0094] The transmission area TA may be arranged on one side of the pixel group PG. Figure 5 As shown in the exemplary embodiment of FIG. 1 , a plurality of transmission areas TA and a plurality of pixel groups PG are alternately arranged in a lattice shape. Figure 6 As shown, a plurality of transmission areas TA may be arranged to surround one pixel group PG. In this embodiment, the plurality of transmission areas TA may be adjacent to each other in the x direction and / or the y direction, and the transmission areas TA and the pixel group PG are not arranged in a lattice shape.

[0095] The transmission area TA is a portion of the component area CA where at least some of the components included in the auxiliary sub-pixel Pa are not arranged. For example, at least some of the pixel electrode included in the organic light emitting diode OLED, the intermediate layer including the emission layer, and the opposite electrode, or at least a portion of the pixel circuit electrically connected to the organic light emitting diode OLED may not be arranged in the transmission area TA. The data line DL, the scan line SL, and the emission control line EL (see Figure 3 ) connected to provide signals to the auxiliary sub-pixels Pa located in the component area CA may be arranged to cross the transmission area TA. However, even in this embodiment, the data lines DL, the scan lines SL, and the emission control lines EL may be arranged to be biased toward the edge of the transmission area TA rather than toward the center of the transmission area TA to increase light / sound transmission in the transmission area TA.

[0096] Although Figure 5 and Figure 6 Although not shown in the exemplary embodiment of FIG. 1 , the metal layer may be arranged on the substrate 100 to form a pixel group PG corresponding to the component area CA. For example, the metal layer may be arranged (e.g., in the z direction) between the thin film transistor TFT of the auxiliary sub-pixel Pa and the substrate 100. The metal layer may block light emitted from the component 20 or external light guided to the component 20 from entering the pixel circuit PC of the auxiliary sub-pixel Pa (see FIG. 1 ). Figure 7 and Figure 8 ). In addition, the metal layer can prevent light diffraction caused by a fine gap between one line and another line, or reduce the degree of light diffraction. A constant voltage or signal can be applied to the metal layer to prevent damage to the pixel circuit PC due to electrostatic discharge. In an exemplary embodiment, a plurality of metal layers may be arranged in the component area CA, and in some cases, different voltages may be applied to at least one of the plurality of metal layers. A single metal layer in the form of a lattice may be located in the component area CA.

[0097] Figure 7 and Figure 8 According to an exemplary embodiment of the present inventive concept Figure 3 1 is an equivalent circuit diagram of a pixel circuit PC of a sub-pixel in the display panel 10.

[0098] Reference Figure 7 According to an exemplary embodiment, each of the main sub-pixel Pm or the auxiliary sub-pixel Pa includes a pixel circuit PC electrically connected to the scan line SL and the data line DL, and an organic light emitting diode OLED electrically connected to the pixel circuit PC.

[0099] The pixel circuit PC includes a driving thin film transistor T1, a switching thin film transistor T2 and a storage capacitor Cst. The switching thin film transistor T2 is electrically connected to the scan line SL and the data line DL, and is configured to transmit a data signal Dm received via the data line DL to the driving thin film transistor T1 according to a scan signal Sn received via the scan line SL.

[0100] The storage capacitor Cst is electrically connected to the switching thin film transistor T2 and the driving voltage line PL. The storage capacitor Cst stores a voltage corresponding to a difference between a voltage received from the switching thin film transistor T2 and a driving voltage ELVDD supplied to the driving voltage line PL.

[0101] The driving thin film transistor T1 is electrically connected to the driving voltage line PL and the storage capacitor Cst, and can control the driving current flowing from the driving voltage line PL to the organic light emitting diode OLED according to the voltage stored in the storage capacitor Cst. The organic light emitting diode OLED can emit light with a certain brightness based on the magnitude of the driving current.

[0102] Although in Figure 7 The pixel circuit PC shown in the exemplary embodiment of FIG. 1 includes two thin film transistors and one storage capacitor, but the exemplary embodiments of the inventive concept are not limited thereto. Figure 8 As shown in the exemplary embodiment of FIG. 1 , the pixel circuit PC may include seven thin film transistors and one storage capacitor. Figure 7In the exemplary embodiment shown in FIG. 1 , the pixel circuit PC includes one storage capacitor, but in other exemplary embodiments, the pixel circuit PC may include two or more storage capacitors. Figure 7 The driving thin film transistor T1 and the switching thin film transistor T2 shown in the exemplary embodiment each have a single gate electrode, but in other exemplary embodiments, at least one of the transistors may have a double gate electrode or the like.

[0103] Reference Figure 8 In an exemplary embodiment of the present invention, each main subpixel Pm or auxiliary subpixel Pa includes a pixel circuit PC and an organic light emitting diode OLED electrically connected to the pixel circuit PC. The pixel circuit PC may include a plurality of thin film transistors and a storage capacitor Cst. The thin film transistor and the storage capacitor Cst may be electrically connected to signal lines such as a scan line SL, a previous scan line SL-1, an emission control line EL, and a data line DL. The thin film transistor and the storage capacitor Cst may also be electrically connected to an initialization voltage line VL and a driving voltage line PL.

[0104] Although in Figure 8 In the exemplary embodiment of the present invention, each main sub-pixel Pm or auxiliary sub-pixel Pa is electrically connected to the signal line, the initialization voltage line VL, and the driving voltage line PL, but the exemplary embodiments of the inventive concept are not limited thereto. For example, at least one of the signal line, the initialization voltage line VL, and the driving voltage line PL may be shared by adjacent sub-pixels.

[0105] The signal lines include a scan line SL configured to transmit a scan signal Sn, a previous scan line SL-1 transmitting a previous scan signal Sn-1 to the first initialization thin film transistor T4 and the second initialization thin film transistor T7, an emission control line EL transmitting an emission control signal En to the operation control thin film transistor T5 and the emission control thin film transistor T6, and a data line DL intersecting the scan line SL and transmitting a data signal Dm. The driving voltage line PL is configured to transmit a driving voltage ELVDD to the driving thin film transistor T1, and the initialization voltage line VL transmits an initialization voltage Vint to the first initialization thin film transistor T4 and the second initialization thin film transistor T7, wherein the initialization voltage Vint initializes the driving thin film transistor T1 and the pixel electrode of the organic light emitting diode OLED.

[0106] The driving thin film transistor T1 includes a driving gate electrode G1 connected to the lower electrode CE1 of the storage capacitor Cst, a driving source electrode S1 connected to the driving voltage line PL via the operation control thin film transistor T5, and a driving drain electrode D1 electrically connected to the pixel electrode of the organic light emitting diode OLED via the emission control thin film transistor T6. The driving thin film transistor T1 receives the data signal Dm according to the switching operation of the switching thin film transistor T2, and converts the driving current IOLED Provided to the organic light emitting diode OLED.

[0107] The switching thin film transistor T2 includes a switching gate electrode G2 connected to the scan line SL, a switching source electrode S2 connected to the data line DL, and a switching drain electrode D2, wherein the switching drain electrode D2 is connected to the driving source electrode S1 of the driving thin film transistor T1 and is also connected to the driving voltage line PL via the operation control thin film transistor T5. The switching thin film transistor T2 is turned on according to the scan signal Sn received via the scan line SL, and performs a switching operation of transmitting the data signal Dm received from the data line DL to the driving source electrode S1 of the driving thin film transistor T1.

[0108] The compensation thin film transistor T3 includes a compensation gate electrode G3 connected to the scan line SL, a compensation source electrode S3 connected to the driving drain electrode D1 of the driving thin film transistor T1 and also connected to the pixel electrode of the organic light emitting diode OLED via the emission control thin film transistor T6, and a lower electrode CE1 connected to the storage capacitor Cst, the first initialization drain electrode D4 of the first initialization thin film transistor T4, and the compensation drain electrode D3 of the driving gate electrode G1 of the driving thin film transistor T1. The compensation thin film transistor T3 is turned on according to the scan signal Sn received via the scan line SL, and electrically connects the driving gate electrode G1 and the driving drain electrode D1 of the driving thin film transistor T1 to each other, so that the driving thin film transistor T1 is diode-connected. Figure 8 As shown in the exemplary embodiment of FIG. 1 , the compensation gate electrode G3 may be a double gate electrode.

[0109] The first initialization thin film transistor T4 includes a first initialization gate electrode G4 connected to the previous scan line SL-1, a first initialization source electrode S4 connected to the second initialization drain electrode D7 of the second initialization thin film transistor T7 and the initialization voltage line VL, and a first initialization drain electrode D4 connected to the lower electrode CE1 of the storage capacitor Cst, the compensation drain electrode D3 of the compensation thin film transistor T3, and the driving gate electrode G1 of the driving thin film transistor T1. The first initialization thin film transistor T4 is turned on according to the previous scan signal Sn-1 received via the previous scan line SL-1, and is configured to transmit the initialization voltage Vint to the driving gate electrode G1 of the driving thin film transistor T1, thereby initializing the voltage of the driving gate electrode G1 of the driving thin film transistor T1. Figure 8 As shown in the exemplary embodiment of FIG. 1 , the first initialization thin film transistor T4 may be a dual gate electrode.

[0110] The operation control thin film transistor T5 includes an operation control gate electrode G5 connected to the emission control line EL, an operation control source electrode S5 connected to the driving voltage line PL, and an operation control drain electrode D5, wherein the operation control drain electrode D5 is connected to the driving source electrode S1 of the driving thin film transistor T1 and the switching drain electrode D2 of the switching thin film transistor T2.

[0111] The emission control thin film transistor T6 includes an emission control gate electrode G6 connected to the emission control line EL, an emission control source electrode S6 connected to the driving drain electrode D1 of the driving thin film transistor T1 and the compensation source electrode S3 of the compensation thin film transistor T3, and an emission control drain electrode D6, wherein the emission control drain electrode D6 is electrically connected to the second initialization source electrode S7 of the second initialization thin film transistor T7 and the pixel electrode of the organic light emitting diode OLED.

[0112] The operation control thin film transistor T5 and the emission control thin film transistor T6 are simultaneously turned on according to the emission control signal En received via the emission control line EL, and thus the driving voltage ELVDD is transmitted to the organic light emitting diode OLED so that the driving current I OLED Can flow in organic light emitting diodes OLED.

[0113] The second initialization thin film transistor T7 includes a second initialization gate electrode G7 connected to the previous scan line SL-1, a second initialization source electrode S7 connected to the emission control drain electrode D6 of the emission control thin film transistor T6 and the pixel electrode of the organic light emitting diode OLED, and a second initialization drain electrode D7 connected to the first initialization source electrode S4 of the first initialization thin film transistor T4 and the initialization voltage line VL. The second initialization thin film transistor T7 is turned on according to the previous scan signal Sn-1 received via the previous scan line SL-1, and initializes the pixel electrode of the organic light emitting diode OLED.

[0114] Although in Figure 8 In the exemplary embodiment of the present invention, the first initialization thin film transistor T4 and the second initialization thin film transistor T7 are connected to the previous scan line SL-1, but the exemplary embodiments of the inventive concept are not limited thereto. For example, in other exemplary embodiments, the first initialization thin film transistor T4 may be connected to the previous scan line SL-1 and operate according to the previous scan signal Sn-1, and the second initialization thin film transistor T7 may be connected to a separate signal line (e.g., a subsequent scan line, etc.) and operate according to a signal transmitted from the separate signal line.

[0115] The upper electrode CE2 of the storage capacitor Cst is connected to the driving voltage line PL, and the opposite electrode of the organic light emitting diode OLED is connected to the second power supply voltage ELVSS. Therefore, the organic light emitting diode OLED can receive the driving current I from the driving thin film transistor T1. OLED And emits light, thereby displaying an image.

[0116] Although in Figure 8 In the exemplary embodiment of FIG. 5 , each of the compensation thin film transistor T3 and the first initialization thin film transistor T4 has a double gate electrode, but in other exemplary embodiments, at least one of the compensation thin film transistor T3 and the first initialization thin film transistor T4 may have a single gate electrode.

[0117] Fig. 9 is an exemplary embodiment according to the present inventive concept. Figure 4 The line I-I' and Figure 6 A schematic cross-sectional view of the pixel arrangement structure taken along line II-II'.

[0118] As described above, the display panel 10 includes the main display area MDA and the component area CA. A plurality of main sub-pixels Pm are arranged in the main display area MDA, and a plurality of auxiliary sub-pixels Pa are arranged in the component area CA. The component area CA includes the transmission area TA.

[0119] The main subpixel Pm may include a main thin film transistor TFT, a main storage capacitor Cst, and an organic light emitting diode OLED. The auxiliary subpixel Pa may include an auxiliary thin film transistor TFT', an auxiliary storage capacitor Cst', and an organic light emitting diode OLED'. The display panel 10 may have a transmission hole TAH corresponding to the transmission area TA.

[0120] The first metal layer BSM1 may be arranged below the main thin film transistor TFT of the main sub-pixel Pm (e.g., in the -z direction) to overlap the main thin film transistor TFT. The second metal layer BSM2 may be arranged below the auxiliary thin film transistor TFT' of the auxiliary sub-pixel Pa (e.g., in the -z direction) to overlap the auxiliary thin film transistor TFT'. However, exemplary embodiments of the inventive concept are not limited thereto, and the display panel 10 may have various modifications. For example, the first metal layer BSM1 arranged to overlap the main thin film transistor TFT may be omitted.

[0121] Hereinafter, a stack structure of the display panel 10 will be described.

[0122] As described above, the substrate 100 may include a polymer resin. Fig. 9As shown in the exemplary embodiment of , the substrate 100 includes a first base layer 101, a first inorganic layer 102, a second base layer 103, and a second inorganic layer 104 stacked in sequence (e.g., in the z direction). The first base layer 101 and the second base layer 103 may each include a polymer resin as described above. Each of the first inorganic layer 102 and the second inorganic layer 104 is a barrier layer that prevents impurities from penetrating from the outside. In an exemplary embodiment, the first inorganic layer 102 and the second inorganic layer 104 may include an inorganic material such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON), and may have a single-layer structure or a multi-layer structure.

[0123] The buffer layer 111 may be disposed on the substrate 100 to prevent or reduce penetration of impurities from the bottom of the substrate 100, and may also be used to provide a flat surface on the substrate 100 to planarize it. In an exemplary embodiment, the buffer layer 111 may include an inorganic material such as an oxide or a nitride, an organic material, or an organic-inorganic compound. The buffer layer 111 may have a single-layer structure or may have a multi-layer structure.

[0124] As described above, the first metal layer BSM1 and the second metal layer BSM2 may be disposed (e.g., in the z direction) between the substrate 100 and the buffer layer 111. For example, the first metal layer BSM1 and the second metal layer BSM2 may be disposed directly between the second inorganic layer 104 and the buffer layer 111. However, exemplary embodiments of the inventive concept are not limited thereto, and in other exemplary embodiments, the first metal layer BSM1 and the second metal layer BSM2 may be disposed below the second inorganic layer 104. For example, the first metal layer BSM1 and the second metal layer BSM2 may be disposed directly between the second base layer 103 and the second inorganic layer 104. Alternatively, the first metal layer BSM1 and the second metal layer BSM2 may be arranged on different layers.

[0125] Each of the first metal layer BSM1 and the second metal layer BSM2 may be connected to a conductive line CL arranged on another layer through a contact hole. In an exemplary embodiment, a constant voltage or signal may be applied from the conductive line CL to the first metal layer BSM1 and the second metal layer BSM2. For example, a driving voltage ELVDD or a scan signal may be applied to the first metal layer BSM1 and the second metal layer BSM2. By applying a constant voltage or signal to the first metal layer BSM1 and the second metal layer BSM2, the probability of the pixel circuit PC being damaged by electrostatic discharge may be significantly reduced. However, exemplary embodiments of the inventive concept are not limited thereto, and in other exemplary embodiments, an electrical signal may not be applied to the first metal layer BSM1 and the second metal layer BSM2. In another exemplary embodiment, one of the first metal layer BSM1 and the second metal layer BSM2 may be electrically floating, and an electrical signal may be applied to the other metal layer.

[0126] In an exemplary embodiment, each of the first metal layer BSM1 and the second metal layer BSM2 may include at least one metal selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). In addition, the first metal layer BSM1 and the second metal layer BSM2 may each have a single-layer structure or a multi-layer structure.

[0127] The main thin film transistor TFT and the auxiliary thin film transistor TFT′ may be disposed on the buffer layer 111. For example, Fig. 9 As shown in the exemplary embodiment of , the main thin film transistor TFT and the auxiliary thin film transistor TFT' are directly arranged on the buffer layer 111. The main thin film transistor TFT includes a first semiconductor layer A1, a first gate electrode G1, a first source electrode S1, and a first drain electrode D1. The auxiliary thin film transistor TFT' includes a second semiconductor layer A2, a second gate electrode G2, a second source electrode S2, and a second drain electrode D2. The main thin film transistor TFT can be electrically connected to the organic light emitting diode OLED of the main sub-pixel Pm in the main display area MDA to drive the organic light emitting diode OLED. The auxiliary thin film transistor TFT' can be electrically connected to the organic light emitting diode OLED' of the auxiliary sub-pixel Pa in the component area CA to drive the organic light emitting diode OLED'.

[0128] In an exemplary embodiment, the first semiconductor layer A1 and the second semiconductor layer A2 may be disposed on the buffer layer 111, and may each include polycrystalline silicon or amorphous silicon. However, exemplary embodiments of the inventive concept are not limited thereto. For example, in another exemplary embodiment, each of the first semiconductor layer A1 and the second semiconductor layer A2 may include an oxide of at least one material selected from indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). Each of the first semiconductor layer A1 and the second semiconductor layer A2 may include a channel region and a source region and a drain region doped with impurities.

[0129] The first semiconductor layer A1 may overlap the first metal layer BSM1 (e.g., in the z direction) with the buffer layer 111 therebetween. The area of ​​the first semiconductor layer A1 (e.g., on a plane defined by the x direction and the y direction) may be smaller than the area of ​​the first metal layer BSM1, and thus, when viewed in a direction perpendicular to the substrate 100 (e.g., in the -z direction), the entire portion of the first semiconductor layer A1 may overlap the first metal layer BSM1.

[0130] The second semiconductor layer A2 may overlap with the second metal layer BSM2 (e.g., in the z direction) with the buffer layer 111 therebetween. The area of ​​the second semiconductor layer A2 (e.g., on a plane defined by the x direction and the y direction) may be smaller than the area of ​​the second metal layer BSM2, and therefore, when viewed in a direction perpendicular to the substrate 100 (e.g., in the -z direction), the entire portion of the second semiconductor layer A2 may overlap with the second metal layer BSM2.

[0131] The first gate insulating layer 112 covers the first semiconductor layer A1 and the second semiconductor layer A2. Fig. 9 As shown in the exemplary embodiment of the present invention, the lower surface of the first gate insulating layer 112 may be directly disposed on the upper surfaces of the buffer layer 111, the first semiconductor layer A1, and the second semiconductor layer A2. In the exemplary embodiment, the first gate insulating layer 112 may include an inorganic insulating material, such as a silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) and zinc oxide (ZnO 2 ). The first gate insulating layer 112 may have a single-layer structure or may have a multi-layer structure.

[0132] The first gate electrode G1 and the second gate electrode G2 are arranged on the first gate insulating layer 112 to overlap the first semiconductor layer A1 and the second semiconductor layer A2, respectively (e.g., in the z direction). In an exemplary embodiment, each of the first gate electrode G1 and the second gate electrode G2 may include Mo, Al, Cu, Ti, and the like, and may have a single-layer structure or a multi-layer structure. For example, each of the first gate electrode G1 and the second gate electrode G2 may have a single-layer structure including Mo.

[0133] The second gate insulating layer 113 covers the first gate electrode G1 and the second gate electrode G2. Fig. 9 As shown in the exemplary embodiment of the present invention, the lower surface of the second gate insulating layer 113 may directly contact the upper surfaces of the first gate insulating layer 112, the first gate electrode G1 and the second gate electrode G2. In the exemplary embodiment, the second gate insulating layer 113 may include an inorganic insulating material, such as a material selected from SiO 2 、SiN x 、SiON、Al 2 O 3 、TiO 2 、2 O 5 , HfO 2 and ZnO 2 The second gate insulating layer 113 may have a single layer structure or a multi-layer structure.

[0134] The first upper electrode CE2 of the main storage capacitor Cst and the second upper electrode CE2′ of the auxiliary storage capacitor Cst′ may be disposed on the second gate insulating layer 113. For example, Fig. 9 As shown in the exemplary embodiment of FIG. 1 , lower surfaces of the first upper electrode CE2 and the second upper electrode CE2 ′ may directly contact an upper surface of the second gate insulating layer 113 .

[0135] In the main display area MDA, the first upper electrode CE2 may overlap the first gate electrode G1 thereunder (e.g., in the z direction). The first gate electrode G1 and the first upper electrode CE2 overlapping each other may form a main storage capacitor Cst, wherein the second gate insulating layer 113 is located between the first gate electrode G1 and the first upper electrode CE2. Fig. 9 As shown in the exemplary embodiment of FIG. 1 , the first gate electrode G1 may be the first lower electrode CE1 of the main storage capacitor Cst. In the component area CA, the second upper electrode CE2′ may overlap the second gate electrode G2 thereunder (e.g., in the z direction). The second gate electrode G2 and the second upper electrode CE2′ overlapping each other may form an auxiliary storage capacitor Cst′, wherein the second gate insulating layer 113 is located between the second gate electrode G2 and the second upper electrode CE2′. Fig. 9 As shown in the exemplary embodiment of FIG. 1 , the first gate electrode G1 may be the second lower electrode CE1 ′ that assists the storage capacitor Cst′.

[0136] In exemplary embodiments, each of the first upper electrode CE2 and the second upper electrode CE2' may include at least one compound selected from Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, and Cu, and may have a single-layer structure or a multi-layer structure.

[0137] The interlayer insulating layer 115 may be formed to cover the first upper electrode CE2 and the second upper electrode CE2'. Fig. 9 As shown in the exemplary embodiment of the present invention, the lower surface of the interlayer insulating layer 115 may directly contact the upper surfaces of the first upper electrode CE2, the second upper electrode CE2' and the second gate insulating layer 113. In the exemplary embodiment, the interlayer insulating layer 115 may include a material selected from SiO 2 、SiN X 、SiON、Al 2 O 3 、TiO2 、 2 O 5 , HfO 2 、ZnO 2 and at least one compound of the group consisting of .

[0138] The first gate insulating layer 112, the second gate insulating layer 113, and the interlayer insulating layer 115 are collectively referred to as the inorganic insulating layer IL. The inorganic insulating layer IL may have a first hole H1 corresponding to the transmission area TA. The first hole H1 may expose a portion of the upper surface of the buffer layer 111 or the substrate 100. The first hole H1 may be formed by overlapping an opening of the first gate insulating layer 112, an opening of the second gate insulating layer 113, and an opening of the interlayer insulating layer 115 formed to correspond to the transmission area TA. The openings may be formed separately by separate processes, or may be formed simultaneously by the same process. When the openings are formed by a separate process, the inner surface of the first hole H1 is not smooth and may have a stair-like step.

[0139] However, in other exemplary embodiments, the inorganic insulating layer IL may have a groove instead of the first hole H1 exposing the buffer layer 111. Alternatively, the inorganic insulating layer IL may not have the first hole H1 or the groove corresponding to the transmission area TA. The inorganic insulating layer IL includes an inorganic insulating material that generally has excellent light transmittance, and therefore, has sufficient transmittance even if it does not have a hole or a groove corresponding to the transmission area TA. Therefore, even in an embodiment in which the first hole H1 or the groove is not included in the inorganic insulating layer IL, the component 20 (see Figure 2 ) can also transmit / receive sufficient amounts of light.

[0140] The first source electrode S1 and the second source electrode S2 and the first drain electrode D1 and the second drain electrode D2 are arranged on the interlayer insulating layer 115. Each of the first source electrode S1 and the second source electrode S2 and each of the first drain electrode D1 and the second drain electrode D2 may include a conductive material including Mo, Al, Cu, Ti, and the like, and may have a multilayer structure or a single layer structure. For example, each of the first source electrode S1 and the second source electrode S2 and each of the first drain electrode D1 and the second drain electrode D2 may have a multilayer structure of Ti / Al / Ti.

[0141] The first planarization layer 117 covers the first source electrode S1 and the second source electrode S2 and the first drain electrode D1 and the second drain electrode D2. Fig. 9As shown in the exemplary embodiment of , the lower surface of the first planarization layer 117 may directly contact the first source electrode S1 and the second source electrode S2 and the upper surface of the interlayer insulating layer 115. The first planarization layer 117 may have an upper surface having a substantially flat shape (e.g., substantially extending along the x-direction). The second planarization layer 118 may be arranged on the first planarization layer 117 (e.g., directly on the first planarization layer 117 in the z-direction). A plurality of contact metal layers CM and CM' may be arranged between the first planarization layer 117 and the second planarization layer 118 (e.g., in the z-direction). The plurality of contact metal layers CM and CM' may electrically connect the first pixel electrode 221 and the second pixel electrode 221' to the corresponding first drain electrode D1 and the second drain electrode D2 through contact holes formed in the first planarization layer 117 and the second planarization layer 118, respectively.

[0142] In an exemplary embodiment, each of the first planarization layer 117 and the second planarization layer 118 may include an organic material or an inorganic material, and may have a single-layer structure or a multi-layer structure. For example, each of the first planarization layer 117 and the second planarization layer 118 may include a commercial polymer such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA) or polystyrene (PS), a polymer derivative with phenols, an acrylic polymer, an imide polymer, an aromatic ether polymer, an amide polymer, a fluorine polymer, a paraxylene polymer, a vinyl alcohol polymer, a blend thereof, or the like. In an exemplary embodiment, each of the first planarization layer 117 and the second planarization layer 118 may include a material selected from SiO 2 、SiN X 、SiON、Al 2 O 3 、TiO 2 、 2 O 5 , HfO 2 、ZnO 2 In an exemplary embodiment, when the first planarization layer 117 and the second planarization layer 118 are formed, chemical mechanical polishing may be performed on the top surface of each layer to provide a flat top surface after each layer is formed.

[0143] The first and second planarization layers 117 and 118 may have second holes H2 corresponding to the transmission areas TA. The second holes H2 may overlap with the first holes H1 (eg, in the z direction). Fig. 9In an exemplary embodiment, the area of ​​the second hole H2 is larger than the area of ​​the first hole H1 (for example, in a plane defined by the x-direction and the y-direction). However, exemplary embodiments of the inventive concept are not limited thereto. For example, in another exemplary embodiment, the first planarization layer 117 and the second planarization layer 118 may be arranged on the side edge of the first hole H1 of the inorganic insulating layer IL to cover the edge of the first hole H1, and therefore, the area of ​​the second hole H2 may be smaller than the area of ​​the first hole H1.

[0144] The first planarization layer 117 and the second planarization layer 118 may have an opening exposing one of the first source electrode S1 and the first drain electrode D1 of the main thin film transistor TFT, and the first pixel electrode 221 may be electrically connected to the main thin film transistor TFT through the opening by contacting the first source electrode S1 or the first drain electrode D1. In addition, the first planarization layer 117 and the second planarization layer 118 may have an opening exposing one of the second source electrode S2 and the second drain electrode D2 of the auxiliary thin film transistor TFT', and the second pixel electrode 221' may be electrically connected to the auxiliary thin film transistor TFT' through the opening by contacting the second source electrode S2 or the second drain electrode D2.

[0145] In an exemplary embodiment, each of the first pixel electrode 221 and the second pixel electrode 221' may include a conductive oxide such as selected from indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), at least one compound of indium gallium oxide (IGO) and aluminum zinc oxide (AZO). Each of the first pixel electrode 221 and the second pixel electrode 221' may include a reflective layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr or a compound thereof. For example, each of the first pixel electrode 221 and the second pixel electrode 221' may have the following structure: a reflective layer including ITO, IZO, ZnO or In above or below the reflective layer; 2 O 3 In this embodiment, each of the first pixel electrode 221 and the second pixel electrode 221 ′ may have a stack structure of ITO / Ag / ITO.

[0146] The pixel defining layer 119 may cover the side edge of each of the first pixel electrode 221 and the second pixel electrode 221'. The pixel defining layer 119 has a first opening OP1 and a second opening OP2 overlapping the first pixel electrode 221 and the second pixel electrode 221', respectively, and defines the emission area of ​​the sub-pixel. The pixel defining layer 119 increases the distance between the edges of the first pixel electrode 221 and the second pixel electrode 221' and the opposing electrode 223 thereon, thereby preventing arcs from occurring in the edges of the first pixel electrode 221 and the second pixel electrode 221'. In an exemplary embodiment, the pixel defining layer 119 may include an organic insulating material such as at least one compound selected from polyimide, polyamide, acrylic resin, BCB, HMDSO, and phenol resin, and may be formed by spin coating or the like.

[0147] The pixel defining layer 119 may have a third hole H3 located in the transmission area TA. The third hole H3 may overlap the first hole H1 and the second hole H2. Fig. 9 As shown in the exemplary embodiment of the present invention, the area of ​​the third hole H3 (for example, in a plane defined by the x-direction and the y-direction) may be greater than the area of ​​the second hole H2. However, exemplary embodiments of the inventive concept are not limited thereto. The light transmittance in the transmission area TA may be improved by the first hole H1 to the third hole H3. A portion of the opposing electrode 223, which will be described later, may be arranged on the inner surface of the first hole H1 to the third hole H3.

[0148] The first intermediate layer 222a is arranged to cover the pixel defining layer 119. The first intermediate layer 222a may have a single-layer structure or a multi-layer structure. The first intermediate layer 222a may include a hole transport layer (HTL) having a single-layer structure. Alternatively, the first intermediate layer 222a may include a hole injection layer (HIL) and the HTL. The first intermediate layer 222a may be integrally formed in the main sub-pixel Pm and the auxiliary sub-pixel Pa respectively included in the main display area MDA and the component area CA.

[0149] First and second emission layers 222b and 222b' corresponding to first and second pixel electrodes 221 and 221', respectively, are arranged on first intermediate layer 222a. In an exemplary embodiment, each of first and second emission layers 222b and 222b' may include a polymer material or a low molecular material and may emit red, green, blue, or white light.

[0150] The second intermediate layer 222c may be located on the first emission layer 222b and the second emission layer 222b'. The second intermediate layer 222c may have a single-layer structure or a multi-layer structure. The second intermediate layer 222c may include an electron transport layer (ETL) and / or an electron injection layer (EIL). The second intermediate layer 222c may be integrally formed in the main sub-pixel Pm and the auxiliary sub-pixel Pa respectively included in the main display area MDA and the component area CA. However, exemplary embodiments of the inventive concept are not limited thereto, and in some exemplary embodiments, the display panel 10 may not include at least one of the first intermediate layer 222a and the second intermediate layer 222c.

[0151] The opposing electrode 223 is arranged on the second intermediate layer 222c. The opposing electrode 223 may include a conductive material having a low work function. For example, in an exemplary embodiment, the opposing electrode 223 may include a (semi) transparent layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca or an alloy thereof. Alternatively, the opposing electrode 223 may further include a (semi) transparent layer including ITO, IZO, ZnO or In on the (semi) transparent layer including the above materials. 2 O 3 The opposing electrode 223 may be integrally formed to correspond to the main sub-pixel Pm and the auxiliary sub-pixel Pa respectively arranged in the main display area MDA and the component area CA.

[0152] The layers formed from the first pixel electrode 221 to the opposite electrode 223 in the main display area MDA may form a main organic light emitting diode OLED. The layers formed from the second pixel electrode 221' to the opposite electrode 223 in the component area CA may form an organic light emitting diode OLED'.

[0153] The cover layer 250 may be disposed on the opposite electrode 223 (e.g., directly thereon in the z direction). In an exemplary embodiment, the cover layer 250 may include LiF. Alternatively, the cover layer 250 may include an inorganic insulating material such as silicon nitride and / or an organic insulating material. However, exemplary embodiments of the inventive concept are not limited thereto, and in some exemplary embodiments, the display panel 10 may not include the cover layer 250.

[0154] The first intermediate layer 222a, the second intermediate layer 222c, the opposite electrode 223, and the cover layer 250 may have a transmissive hole TAH corresponding to the transmissive area TA. For example, the first intermediate layer 222a, the second intermediate layer 222c, the opposite electrode 223, and the cover layer 250 may have openings corresponding to the transmissive area TA, respectively, which together form the transmissive hole TAH. In an exemplary embodiment, the areas of the openings of the first intermediate layer 222a, the second intermediate layer 222c, the opposite electrode 223, and the cover layer 250 may be substantially the same. The area of ​​the opening of the opposite electrode 223 may be substantially the same as the area of ​​the transmissive hole TAH. However, exemplary embodiments of the inventive concept are not limited thereto. For example, in another exemplary embodiment, the area of ​​the opening of the first intermediate layer 222a (for example, in a plane defined by the x-direction and the y-direction), the area of ​​the opening of the second intermediate layer 222c, the area of ​​the opening of the opposite electrode 223, and the area of ​​the opening of the cover layer 250 may be different, and the area of ​​any one of the openings may be smaller or larger than the area of ​​the other openings. For example, the inner surface of the opening of the first intermediate layer 222a may be located in the transmissive hole TAH, and thus, a portion defining the opening of the first intermediate layer 222a may have a shape protruding into the transmissive hole TAH.

[0155] The correspondence of the transmissive hole TAH and the transmissive area TA means that the transmissive hole TAH overlaps the transmissive area TA. In an exemplary embodiment, the area of ​​the transmissive hole TAH may be smaller than the area of ​​the first hole H1 formed in the inorganic insulating layer IL. Fig. 9 As shown in the exemplary embodiment of , the width Wt of the transmissive hole TAH (e.g., the length in the x direction) is smaller than the width W1 of the first hole H1 (e.g., the length in the x direction). In this embodiment, the area of ​​the transmissive hole TAH may be defined by the opening with the smallest size among the overlapping openings of the layers located in the transmissive part among the layers of the panel. The area of ​​the first hole H1 may also be defined as the area of ​​the opening with the smallest area among the openings constituting the first hole H1.

[0156] Due to the transmission hole TAH, a portion of the relative electrode 223 does not exist in the transmission area TA, and thus the transmittance in the transmission area TA can be significantly improved. The relative electrode 223 can be formed in various ways. For example, by forming a layer of a material for the relative electrode 223 and then removing a portion corresponding to the transmission area TA by laser stripping, the relative electrode 223 having an opening can be formed. Alternatively, the relative electrode 223 having an opening can be formed by patterning a fine metal mask. However, exemplary embodiments of the inventive concept are not limited thereto.

[0157] The organic light emitting diode OLED in the main display area MDA and the organic light emitting diode OLED′ in the component area CA may be sealed by the thin film encapsulation layer 300. The thin film encapsulation layer 300 may be disposed on the cover layer 250. For example, Fig. 9 As shown in the exemplary embodiment of FIG. 2 , the lower surface of the thin film encapsulation layer 300 may directly contact the upper surface of the cover layer 250. The thin film encapsulation layer 300 may prevent external moisture or foreign matter from penetrating into the organic light emitting diodes OLED and OLED′.

[0158] The thin film encapsulation layer 300 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. Fig. 9 In the exemplary embodiment shown in , the thin film encapsulation layer 300 has a structure in which a first inorganic encapsulation layer 310, an organic encapsulation layer 320, and a second inorganic encapsulation layer 330 are stacked continuously (e.g., in the z direction). However, exemplary embodiments of the inventive concept are not limited thereto, and in other exemplary embodiments, the number of organic encapsulation layers, the number of inorganic encapsulation layers, and the stacking order may be changed.

[0159] In an exemplary embodiment, each of the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include one or more inorganic insulating materials such as aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride and / or silicon oxynitride, and may be formed by chemical vapor deposition (CVD). The organic encapsulation layer 320 may include a polymer material. Examples of polymer materials may include silicon resins, acrylic resins, epoxy resins, polyimides, and polyethylene. However, exemplary embodiments of the inventive concept are not limited thereto.

[0160] The first inorganic encapsulation layer 310, the organic encapsulation layer 320, and the second inorganic encapsulation layer 330 may be integrally formed to cover the main display area MDA and the component area CA. Therefore, the first inorganic encapsulation layer 310, the organic encapsulation layer 320, and the second inorganic encapsulation layer 330 may also be arranged in the transmission hole TAH. Fig. 9As shown in the exemplary embodiment of , the lower surface of the first inorganic encapsulation layer 310 may directly contact the upper surface of the buffer layer 111 in the transmission hole TAH, and the organic encapsulation layer 320 and the second inorganic encapsulation layer 330 are continuously stacked thereon. However, exemplary embodiments of the inventive concept are not limited thereto. For example, in some exemplary embodiments, the organic encapsulation layer 320 may be integrally formed to cover the main display area MDA and the component area CA, but may not be arranged in the transmission area TA. For example, the organic encapsulation layer 320 may have an opening corresponding to the transmission area TA. In this embodiment, the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may directly contact each other in the transmission hole TAH.

[0161] Fig.10 and Fig.11 is a diagram showing an exemplary embodiment according to the concept of the present invention Figure 3 Schematic plan view of the arrangement of sub-pixels and circuit lines of the display panel 10. Since the plan view only shows a portion of the display panel 10, many sub-pixels are omitted. Moreover, since the plan view only shows the circuit lines required for description, many circuit lines are omitted for convenience of explanation. The plan view shows part of the component area CA and part of the main display area MDA outside the component area CA. Fig.10 The arrangement of the sub-pixels and the line lines shown in the exemplary embodiment includes a first data line D among the line lines. 1 , 2nd-1st data line D 2-1 , 2-2 data line D 2-2 , the third data line D 3 , 4-1 data line D 4-1 and 4-2 data line D 4-2 . Fig.11 The arrangement of sub-pixels shown in the exemplary embodiment of FIG. 1 shows that the first bridge line B among the line lines 1 and the second bridge wire B 2 .exist Fig.10 and Fig.11 In the exemplary embodiment, for convenience of explanation, the first data line D 1 , 2nd-1st data line D 2-1 , 2-2 data line D 2-2 , the third data line D 3 , 4-1 data line D 4-1 and 4-2 data line D 4-2 、First bridge connection B 1 and the second bridge wire B 2It is shown as passing through the center of the sub-pixel. However, the line line can be modified in various ways, such as passing through the edge of the sub-pixel, etc. The line line shown in the drawings in conjunction with the exemplary embodiments and modifications thereof described below can also be modified in various ways and is not limited by the illustrations thereof.

[0162] like Fig.10 and Fig.11 As shown in the exemplary embodiment of FIG. 1-1, the sub-pixels are arranged in a plurality of rows extending along the x-axis direction. 1-1 and the 1st-2nd sub-pixel Sub 1-2 Located in the first row R 1 The first row R 1 Positioned adjacent to the lower side (eg, in the y direction) of the component area CA. 1 The 2-1st sub-pixel Sub is adjacent to the lower side of the component area CA in the -y direction. 2-1 Located in the second row R 2 In which the second row R 2 Located in the component area CA (eg, below the central portion of the component area CA in the −y direction) and aligned with the first row R in the +y direction 1 The 3-1st sub-pixel Sub 3-1 and the 3-2nd sub-pixel Sub 3-2 Located in the third row R 3 In the third row, R 3 Positioned adjacent to the upper side (eg, in the y direction) of the component area CA. 3 The upper side of the component area CA is adjacent to the upper side of the component area CA in the +y direction and is adjacent to the second row R in the +y direction. 2 Spaced apart.

[0163] exist Fig.10 In the exemplary embodiment, the first row R 1 , second row R 2 and the third row R 3 Each of the diagrams is shown as including two rows extending in the x-axis direction and spaced apart in the y-direction. 3 In the case of Fig.10 The red sub-pixel Pr shown in the upper left corner of the exemplary embodiment of FIG. 1 and the green sub-pixel Pg shown in the +x direction from the red sub-pixel Pr, the blue sub-pixel Pb shown in the -y direction from the red sub-pixel Pr, and the green sub-pixel Pg shown in the +x direction from the blue sub-pixel Pb may constitute one pixel. Fig.10 In the exemplary embodiment, the third row R 3 is shown as comprising two rows extending in the x-axis direction. This also applies to the first row R 1 or the second row R2 However, exemplary embodiments of the inventive concept are not limited thereto. For example, in another exemplary embodiment, the first row R 1 , second row R 2 and the third row R 3 Each of the pixels may include a row extending in the x-axis direction, and the red sub-pixel Pr, the green sub-pixel Pg located in the +x direction from the red sub-pixel Pr, and the blue sub-pixel Pb located in the +x direction from the green sub-pixel Pg may be repeatedly arranged in a row. In this exemplary embodiment, the red sub-pixel Pr, the green sub-pixel Pg located in the +x direction from the red sub-pixel Pr, and the blue sub-pixel Pb located in the +x direction from the green sub-pixel Pg may constitute one pixel. In other exemplary embodiments, the arrangement of the sub-pixels forming a pixel may be changed. Hereinafter, for the convenience of explanation, the sub-pixels in the pixel will be described. Fig.10 The sub-pixel arrangement is shown in FIG.

[0164] Sub-pixel 1-1 1-1 , 1st-2nd sub-pixel Sub 1-2 , 3-1st sub-pixel Sub 3-1 and the 3-2nd sub-pixel Sub 3-2 may be located in the main display area MDA, and the 2-1st sub-pixel Sub 2-1 may be located in the component area CA. In this exemplary embodiment, when the component area CA is at the center, the 1-1th sub-pixel Sub 1-1 and the 1st-2nd sub-pixel Sub 1-2 The first row R located adjacent to the lower side of the component area CA (eg, adjacent in the -y direction) 1 3-1st sub-pixel Sub 3-1 and the 3-2nd sub-pixel Sub 3-2 The third row R located adjacent to the upper side of the component area CA (eg, adjacent in the +y direction) 3 Therefore, the component area CA has a first row R 1 With the second row R 2 Between and in the second row R 2 With the third row R 3 Therefore, the component area CA has a transmissive area TA arranged at the 2-1st sub-pixel Sub 2-1 The transmissive area TA is located outside (eg, outside in the -y and +y directions and in the -x and +x directions).

[0165] The first data line D 1 Basically in the +y direction from the first row R 1 Extends across component area CA to the third row R 3, and the 1-1th sub-pixel Sub in the main display area MDA 1-1 The pixel circuit, the 2-1st sub-pixel Sub in the component area CA 2-1 The pixel circuit and the 3-1st sub-pixel Sub in the main display area MDA 3-1 The pixel circuit is electrically connected.

[0166] No. 2-1 Data Line D 2-1 It also extends in the +y direction and is connected to the 1-2 sub-pixel Sub located in the main display area MDA. 1-2 However, the 2-1 data line D 2-1 Not connected to the auxiliary sub-pixel Pa located in the component area CA. For example, the 2-1st data line D 2-1 The 2-1st data line D may be terminated in a portion of the main display area MDA adjacent to the lower side of the component area CA (eg, adjacent in the -y direction) or located in the component area CA. 2-1 May not extend to the second row R 2 and the third row R 3 .

[0167] No. 2-2 Data Line D 2-2 The y direction extends and is aligned with the 3-2nd sub-pixel Sub in the main display area MDA. 3-2 The pixel circuit is electrically connected. The 2-2 data line D 2-2 Not connected to the auxiliary sub-pixel Pa located in the component area CA. For example, the 2-2nd data line D 2-2 The 2-2nd data line D may be terminated in a portion of the main display area MDA that is adjacent to the upper side of the component area CA (eg, adjacent in the +y direction) or located in the component area CA. 2-2 May not extend to the first row R 1 and the second row R 2 .

[0168] As mentioned above, refer to Figure 3 In the exemplary embodiment of the present invention, the data line DL transmits the data signal Dm from the data driving circuit 150 located outside the main display area MDA (eg, in the −y direction) to the main sub-pixel Pm and the auxiliary sub-pixel Pa.

[0169] The 1-1 sub-pixel Sub in the main display area MDA 1-1 , the 2-1st sub-pixel Sub in the component area CA 2-1 and the 3-1st sub-pixel Sub in the main display area MDA 3-1 and the first data line D extending across the component area CA in the +y direction. 1The 1-2nd sub-pixel Sub is electrically connected to the data driving circuit 150 and can thus receive the data signal Dm from the data driving circuit 150. The 1-2nd sub-pixel Sub is located in a portion of the main display area MDA adjacent to the lower side of the component area CA (eg, adjacent in the -y direction). 1-2 With the 2-1 data line D 2-1 The 3-2nd sub-pixel Sub located in a portion of the main display area MDA adjacent to the upper side of the component area CA (eg, adjacent in the +y direction) is electrically connected and thus may receive the data signal Dm from the data driving circuit 150. 3-2 With the 2-2 data line D 2-2 However, the 2-2 data line D 2-2 The data line extends toward the component area CA in the −y direction, but does not extend across the component area CA to the main display area MDA located adjacent to the lower side of the component area CA (e.g., adjacent in the −y direction). Therefore, in this configuration, the data signal Dm is not applied through the data line to the 3-2nd sub-pixel Sub located in a portion of the main display area MDA adjacent to the upper side of the component area CA (e.g., adjacent in the +y direction). 3-2 .

[0170] However, since the display device 1 according to the concept of the present invention includes Fig.11 The first bridge wire B shown in the exemplary embodiment 1 Therefore, the data signal Dm may also be applied to the 3-2nd sub-pixel Sub located in a portion of the main display area MDA adjacent to the upper side of the component area CA (eg, adjacent in the +y direction). 3-2 For example, the first bridge line B 1 The first side contacts the first row R located adjacent to the lower side of the component area CA (eg, adjacent in the −y direction). 1 The 2-1 data line D 2-1 , and the first bridge wire B 1 The second side of the third row R located adjacent to the upper side of the component area CA (eg, adjacent in the +y direction) 3 The 2-2 data line D 2-2 Therefore, the 2-2 data line D 2-2 With the 2-1 data line D 2-1 Therefore, the data signal Dm can be transmitted through the 2-2 data line D 2-2 Applied to the 3-2nd sub-pixel Sub 3-2 .

[0171] First bridge connection B 1 Located at the first data line D 1 , 2nd-1st data line D 2-1 and 2-2 data line D2-2 For example, in an exemplary embodiment, the first data line D 1 , 2nd-1st data line D 2-1 and 2-2 data line D 2-2 Can be arranged in Fig. 9 In the exemplary embodiment shown in FIG. 1 , the interlayer insulating layer 115 is formed, and the first bridge line B 1 Can be arranged to cover the first data line D 1 , 2nd-1st data line D 2-1 and 2-2 data line D 2-2 The first planarization layer 117 (see Fig. 9 In this exemplary embodiment, the first data line D 1 , 2nd-1st data line D 2-1 and 2-2 data line D 2-2 The first bridge line B may be formed of the same material as the first source electrode S1, the first drain electrode D1, the second source electrode S2, and the second drain electrode D2 and may be formed simultaneously with the first source electrode S1, the first drain electrode D1, the second source electrode S2, and the second drain electrode D2. 1 The first bridge line B may be formed of the same material as the plurality of contact metal layers CM and CM' and simultaneously with the plurality of contact metal layers CM and CM'. 1 The 2-1 data line D located under the first planarization layer 117 can be connected to the first planarization layer 117 through the contact hole formed in the first planarization layer 117. 2-1 and 2-2 data line D 2-2 Each electrical connection in.

[0172] The display device 1 according to this exemplary embodiment can display a high-resolution image in a portion of the main display area MDA that is positioned adjacent to the lower side of the component area CA (for example, adjacent in the -y direction), and can also display a high-resolution image in a portion of the main display area MDA that is positioned adjacent to the upper side of the component area CA (for example, adjacent in the +y direction).

[0173] First bridge connection B 1 It may have a first data line D 1 Therefore, the first bridging line B 1 Along the first data line D 1 The orthogonal projection image of the portion extending from at least a portion of the substrate 100 in a direction perpendicular to the top surface of the substrate 100 (eg, in the z direction) is aligned with the first data line D 1 The orthogonal projection images of the first bridge line B in the direction perpendicular to the top surface of the substrate 100 (z direction) overlap. This is possible because the first bridge line B 1 Located at the first data line D 1On different layers. Fig.10 and Fig.11 In an exemplary embodiment, the first bridge line B 1 The first data line D is substantially adjacent to the edge of the upper side of the component area CA in all areas except for the area adjacent to the edge of the lower side of the component area CA. 1 overlap (e.g., in the z-direction).

[0174] By this configuration, the display device 1 according to the present exemplary embodiment can display a high-resolution image even in a portion of the main display area MDA located adjacent to the upper side of the component area CA (e.g., adjacent in the +y direction). In the component area CA, the light transmission area of ​​the transmission area TA can have a large area (e.g., in a plane defined by the x direction and the y direction) because the first bridge line B 1 No loss is caused in the light transmission area of ​​the transmission area TA.

[0175] like Fig.10 and Fig.11 As shown in the exemplary embodiment, the 1st to 3rd sub-pixels Sub 1-3 and the 1st to 4th sub-pixels Sub 1-4 Can be located in the first row R 1 In the 2-2nd sub-pixel Sub 2-2 Can be located in the second row R 2 and the 3-3 sub-pixel Sub 3-3 and the 3rd-4th sub-pixel Sub 3-4 Can be located in the third row R 3 1st to 3rd sub-pixel Sub 1-3 In the -x direction, it is aligned with the 1-1 sub-pixel Sub 1-1 Adjacent positioning, where the -x direction is relative to the 1-1 sub-pixel Sub 1-1 Arrange the 1st-2nd sub-pixel Sub 1-2 The direction opposite to the direction (for example, the +x direction). 1-4 Located at the 1-1 sub-pixel Sub 1-1 and the 1st-2nd sub-pixel Sub 1-2 Between. 3rd-3rd sub-pixel Sub 3-3 In the -x direction, the 3-1st sub-pixel Sub 3-1 Adjacent positioning, where the -x direction is relative to the 3-1st sub-pixel Sub 3-1 Arrange the 3-2nd sub-pixel Sub 3-2 The direction opposite to the direction (for example, the +x direction). 3-4 Located at the 3-1st sub-pixel Sub 3-1 and the 3-2nd sub-pixel Sub3-2 between.

[0176] Therefore, the 1st to 3rd sub-pixels Sub 1-3 , 1st to 4th sub-pixel Sub 1-4 , 3-3 sub-pixel Sub 3-3 and the 3rd-4th sub-pixel Sub 3-4 The 2-2nd sub-pixel Sub may be located in the main display area MDA. 2-2 In addition, when the component area CA is at the center, the 1st to 3rd sub-pixels Sub 1-3 and the 1st to 4th sub-pixels Sub 1-4 is positioned adjacent to the lower side of the component area CA (eg, adjacent in the −y direction), and the 3-3rd sub-pixel Sub 3-3 and the 3rd-4th sub-pixel Sub 3-4 The component area CA has a 2-2 sub-pixel Sub arranged adjacent to the upper side of the component area CA (eg, adjacent in the +y direction). 2-2 The outer transmissive area TA.

[0177] The third data line D 3 Basically in the +y direction from the first row R 1 Extends across component area CA to the third row R 3 , and the 1st to 3rd sub-pixels Sub in the main display area MDA 1-3 The pixel circuit, the 2-2 sub-pixel Sub in the component area CA 2-2 The pixel circuit and the 3-3 sub-pixel Sub in the main display area MDA 3-3 The pixel circuit is electrically connected.

[0178] No. 4-1 Data Line D 4-1 Also extends in the +y direction and is connected to the 1st to 4th sub-pixels Sub located in the main display area MDA 1-4 However, the 4-1st data line D 4-1 Not connected to the auxiliary sub-pixel Pa located in the component area CA. For example, the 4-1st data line D 4-1 The 4-1st data line D may be terminated in a portion of the main display area MDA adjacent to the lower side of the component area CA (eg, adjacent in the -y direction) or located in the component area CA. 4-1 May not extend to the second row R 2 and the third row R 3 .

[0179] No. 4-2 Data Line D 4-2The y direction extends and is aligned with the 3rd to 4th sub-pixel Sub located in the main display area MDA. 3-4 The pixel circuit is electrically connected. 4-2 Not connected to the auxiliary sub-pixel Pa located in the component area CA. For example, the 4-2nd data line D 4-2 The 4-2nd data line D may be terminated in a portion of the main display area MDA adjacent to the upper side of the component area CA (eg, adjacent in the +y direction) or located in the component area CA. 4-2 May not extend to the first row R 1 and the second row R 2 .

[0180] Sub-pixels 1-3 in the main display area MDA 1-3 , the 2-2nd sub-pixel Sub in the component area CA 2-2 and the 3-3rd sub-pixel Sub in the main display area MDA 3-3 and the third data line D extending in the +y direction 3 The 1st to 4th sub-pixels Sub located in a portion of the main display area MDA adjacent to the lower side of the component area CA (eg, adjacent in the −y direction) are electrically connected and thus may receive the data signal Dm from the data driving circuit 150. 1-4 With the 4-1 data line D 4-1 The 3rd to 4th sub-pixels Sub located in a portion of the main display area MDA adjacent to the upper side of the component area CA (eg, adjacent in the +y direction) are electrically connected and thus may receive the data signal Dm from the data driving circuit 150. 3-4 With the 4-2 data line D 4-2 However, the 4-2 data line D 4-2 The data line extends toward the component area CA in the -y direction, but does not extend across the component area CA to the main display area MDA adjacent to the lower side of the component area CA (e.g., adjacent in the -y direction). Therefore, in this configuration, the data signal Dm is not applied through the data line to the 3rd to 4th sub-pixels Sub located in a portion of the main display area MDA adjacent to the upper side of the component area CA (e.g., adjacent in the +y direction). 3-4 .

[0181] However, since the display device 1 according to the concept of the present invention includes Fig.11 The second bridge wire B shown in the exemplary embodiment 2 Therefore, the data signal Dm may also be applied to the 3rd to 4th sub-pixels Sub located in a portion of the main display area MDA adjacent to the upper side of the component area CA (eg, adjacent in the +y direction). 3-4 For example, the second bridge wire B2 The first side contacts the first row R located adjacent to the lower side of the component area CA (eg, adjacent in the −y direction). 1 The 4-1 data line D 4-1 , and the second bridge wire B 2 The second side of the third row R located adjacent to the upper side of the component area CA (eg, adjacent in the +y direction) 3 The 4-2 data line D 4-2 Therefore, the 4-2 data line D 4-2 With the 4-1 data line D 4-1 Therefore, the data signal Dm can be connected to the 4-2 data line D 4-2 Applied to the 3rd-4th sub-pixel Sub 3-4 .

[0182] Second bridge connection B 2 The third data line D 3 , 4-1 data line D 4-1 and 4-2 data line D 4-2 For example, in an exemplary embodiment, the third data line D 3 , 4-1 data line D 4-1 and 4-2 data line D 4-2 Can be arranged in Fig. 9 In the exemplary embodiment shown in FIG. 1 , the interlayer insulating layer 115 is formed, and the second bridge line B 2 Can be arranged in Fig. 9 In the exemplary embodiment, the third data line D 3 , 4-1 data line D 4-1 and 4-2 data line D 4-2 The second bridge line B may be formed of the same material as the first source electrode S1, the first drain electrode D1, the second source electrode S2, and the second drain electrode D2 and may be formed at the same time. 2 The second bridge line B may be formed of the same material as the plurality of contact metal layers CM and CM' and at the same time. 2 The 4-1 data line D located under the first planarization layer 117 can be connected to the first planarization layer 117 through the contact hole formed in the first planarization layer 117. 4-1 and 4-2 data line D 4-2 Each electrical connection in.

[0183] The display device 1 according to this exemplary embodiment can display a high-resolution image in a portion of the main display area MDA that is positioned adjacent to the lower side of the component area CA (for example, adjacent in the -y direction), and can also display a high-resolution image in a portion of the main display area MDA that is adjacent to the upper side of the component area CA (for example, adjacent in the +y direction).

[0184] Second bridge connection B 2 There may be a third data line D 3 Therefore, the second bridging line B 2 Along the third data line D 3 The orthogonal projection image of the portion extending from at least a portion of the substrate 100 in the direction perpendicular to the top surface of the substrate 100 (z direction) is aligned with the third data line D 3 The orthogonal projection images of the second bridge line B in the direction perpendicular to the top surface of the substrate 100 (z direction) overlap. This is possible because the second bridge line B 2 The third data line D is arranged on the 3 The layers are on different layers. Fig.10 and Fig.11 In an exemplary embodiment, the second bridge line B 2 The third data line D is connected to the component area CA in all areas except for the area adjacent to the edge of the upper side of the component area CA and the area adjacent to the edge of the lower side of the component area CA. 3 substantially overlap (e.g., in the z-direction).

[0185] By this configuration, the display device 1 according to the present exemplary embodiment can display a high-resolution image even in a portion of the main display area MDA that is located adjacent to the upper side of the component area CA (e.g., adjacent in the +y direction). In the component area CA, the light transmission area of ​​the transmission area TA can have a large area because the second bridge line B 2 No loss is caused in the light transmission area of ​​the transmission area TA.

[0186] Fig.12 is an exemplary embodiment according to the present inventive concept. Fig.10 and Fig.11 A schematic cross-sectional view of the arrangement of sub-pixels and line lines taken along line III-III'. Fig.12 As shown in the exemplary embodiment, the third data line D 3 Arranged at the first data line D 1 The second bridge line B is disposed on the same layer (eg, disposed on the interlayer insulating layer 115), and the second bridge line B 2 Arranged in the first bridge connection B 1The first data line D 1 and the third data line D 3 It can also be located at the 2nd-1st data line D 2-1 , 2-2 data line D 2-2 , 4-1 data line D 4-1 and 4-2 data line D 4-2 On the same layer. Fig.12 As shown in the exemplary embodiment, the first bridge wire B 1 and the second bridge wire B 2 may have respective first data lines D 1 and the third data line D 3 The overlapping portions (eg, in the z direction) may reduce a loss in a light transmission area of ​​the transmission area TA.

[0187] The display panel 10 may include a first row R 1 In the -x direction, the 1st to 3rd sub-pixel Sub 1-3 The additional data line Da may be electrically connected to the pixel circuit of the adjacent sub-pixel. The additional data line Da may extend substantially in the +y direction and may extend into the component area CA. The additional data line Da may have a 1 In this exemplary embodiment, the additional data line Da is electrically connected to the pixel circuit of one sub-pixel in the component area CA, and then the additional data line Da may be electrically connected to the pixel circuit of the 2-1 sub-pixel Sub 2-1 The outer portion of the main display area MDA in the -x direction substantially extends in the +y direction along the edge of the transmission area TA. The additional data line Da may be connected to the third row R in a portion of the main display area MDA adjacent to the upper side of the component area CA (eg, adjacent in the +y direction). 3 The pixel circuits of the main sub-pixels Pm in the embodiment are electrically connected. Fig.10 As shown in the exemplary embodiment of FIG. 1 , the additional data line Da may be electrically connected to the 3-3 sub-pixel Sub in the third row R3 in the −x direction. 3-3 adjacent sub-pixels.

[0188] As described above, the driving voltage ELVDD is applied to the pixel circuit of each sub-pixel. Fig.13 FIG. 2 is a diagram showing a plurality of driving voltage lines PL1, PL2, PL3, PL4, and PL5 and FIG. Figure 3 FIG. 1 is a schematic plan view of an arrangement of auxiliary driving voltage lines PLca of a display panel 10. FIG.

[0189] From the first sub-line 162 (see Figure 3) is applied to the main sub-pixels Pm in a portion of the main display area MDA adjacent to the lower side of the component area CA (eg, adjacent in the -y direction). Figure 3 ) is applied to the main sub-pixels Pm in a portion of the main display area MDA adjacent to the upper side of the component area CA (e.g., adjacent in the +y direction). The driving voltage from the driving voltage line PL1 electrically connected to the first sub-line 162 and / or the second sub-line 163 is applied to the main sub-pixels Pm in the remaining portion of the main display area MDA.

[0190] In an exemplary embodiment, driving voltages from a plurality of driving voltage lines PL4 and PL5 electrically connected to the first sub-line 162 and / or the second sub-line 163 may also be applied to the auxiliary sub-pixels Pa in the component area CA. Fig.13 In another exemplary embodiment shown in , the driving voltage may be applied to the auxiliary sub-pixel Pa in the component area CA through the auxiliary driving voltage line PLca located in the component area CA.

[0191] The auxiliary driving voltage line PLca is arranged at the same position as the first data line D 1 and the first bridge connection B 1 For example, in an exemplary embodiment, the auxiliary driving voltage line PLca may be arranged on a different layer than the auxiliary driving voltage line PLca. Fig. 9 The auxiliary driving voltage line PLca may be disposed on the same layer as the first metal layer BSM1 and the second metal layer BSM2 shown in the exemplary embodiment of FIG. 1 and may be formed of the same material as the first metal layer BSM1 and the second metal layer BSM2. For example, the auxiliary driving voltage line PLca may be disposed directly on the second inorganic layer 104 ( Fig. 9 In this exemplary embodiment, the auxiliary driving voltage line PLca is located between the first data line D 1 and the first bridge connection B 1 A plurality of driving voltage lines PL1, PL2, PL3, PL4, and PL5 may be located adjacent to the first data line D 1 and the third data line D 3 On the same layer.

[0192] In addition, the auxiliary driving voltage line PLca may be connected to the first data line D (eg, in the z direction). 1 , the third data line D 3 、First bridge connection B 1 and the second bridge wire B 2 overlaps with the 2-1st sub-pixel Sub as the auxiliary sub-pixel Pa located in the component area CA. 2-1The pixel circuit of the 2-1st sub-pixel Sub may be electrically connected to the pixel circuit to apply a driving voltage to the pixel circuit. A contact hole may be formed in the buffer layer 111 or a similar layer so that the 2-1st sub-pixel Sub 2-1 The pixel circuit is electrically connected to the auxiliary driving voltage line PLca. In addition, the auxiliary driving voltage line PLca may be electrically connected to a plurality of driving voltage lines PL4 and PL5 located on a layer different from the auxiliary driving voltage line PLca through a contact hole at an edge of the component area CA.

[0193] The auxiliary driving voltage line PLca may protect the pixel circuit PC in the component area CA from light from the outside or from the component 20 (see FIG. Figure 2 In addition, due to the auxiliary driving voltage line PLca and the first data line D 1 , the third data line D 3 、First bridge connection B 1 and the second bridge wire B 2 The auxiliary driving voltage line PLca can prevent or reduce the voltage difference between the auxiliary driving voltage line PLca and the auxiliary driving voltage line PLca. 1 , the third data line D 3 、First bridge connection B 1 and the second bridge wire B 2 ), which may cause light diffraction due to the small gaps between the components 20 and the imaging device, and this light diffraction may cause noise in the data collected by the component 20 (such as an imaging device). Fig.13 As shown in the exemplary embodiment of FIG. 1 , the width (eg, length in the x-direction) of the auxiliary driving voltage line PLca may be greater than the width of each of the plurality of driving voltage lines PL1 , PL2 , PL3 , PL4 , and PL5 .

[0194] exist Fig.10 and Fig.11 In the exemplary embodiment of FIG. 1 , the auxiliary sub-pixels Pa in the component area CA are shown to be arranged in a zigzag shape along the y-axis direction. However, the exemplary embodiments of the inventive concept are not limited thereto. For example, Fig.14 and Fig.15 As shown in the exemplary embodiment ( Fig.14 and Fig.15 2 is a schematic plan view showing the arrangement of sub-pixels and wiring lines of a display panel according to another exemplary embodiment), the auxiliary sub-pixels Pa in the component area CA may be arranged in a matrix shape. Figure 14 to Figure 15 As shown in the exemplary embodiment of Figure 10 to Figure 11Unlike the exemplary embodiment of the embodiment of FIG. 1 , the auxiliary sub-pixels Pa are arranged in a plurality of aligned rows and columns in the component area CA. Therefore, a portion of the transmission area TA disposed between adjacent columns of the auxiliary sub-pixels Pa may extend from an upper edge of the component area CA to a lower edge of the component area CA. A portion of the transmission area TA disposed between adjacent rows may extend from an edge of the component area CA in the +x direction to an edge of the component area CA in the −x direction.

[0195] because Fig.14 and Fig.15 The exemplary embodiment of the present invention only shows a portion of the display panel, so many sub-pixels are omitted. Moreover, since the plan view only shows the line lines required for description, many line lines are omitted. The plan view shows the component area CA and a portion of the main display area MDA outside the component area CA. Fig.14 The first data line D among the lines is shown. 1 , 2nd-1st data line D 2-1 , 2-2 data line D 2-2 , the third data line D 3 , 4-1 data line D 4-1 and 4-2 data line D 4-2 ,and Fig.15 The first bridge line B among the lines is shown 1 and the second bridge wire B 2 .exist Fig.14 and Fig.15 In the exemplary embodiment, for the convenience of illustration, the first data line D 1 , 2nd-1st data line D 2-1 , 2-2 data line D 2-2 , the third data line D 3 , 4-1 data line D 4-1 , 4-2 data line D 4-2 、First bridge connection B 1 and the second bridge wire B 2 It is only shown as passing through the center of the sub-pixel. However, the exemplary embodiments of the inventive concept are not limited thereto, and the line line may pass through any portion of the corresponding sub-pixel. For example, the line line may be modified in various ways, such as passing through the edge of the sub-pixel, etc. This also applies to the line lines shown in the accompanying drawings in conjunction with the embodiments and modifications thereof described below.

[0196] According to the above reference Figures 10 to 13 The description of the display device 1 of the exemplary embodiment described can be applied to the Figure 14 to Figure 15 A display device according to an exemplary embodiment of the present invention.

[0197] For example, Fig.14As shown in the exemplary embodiment, the first data line D 1 The first row R of the main display area MDA extends substantially in the +y direction across the component area CA and 1 The 1-1 sub-pixel Sub 1-1 The pixel circuit of the second row R in the component area CA 2 The 2-1st sub-pixel Sub 2-1 The pixel circuit and the third row R in the main display area MDA 3 The 3-1st sub-pixel Sub 3-1 The pixel circuit is electrically connected.

[0198] No. 2-1 Data Line D 2-1 It also extends in the +y direction and is aligned with the first row R in the main display area MDA. 1 Subpixel 1-2 in 1-2 However, the 2-1 data line D 2-1 is not connected to the auxiliary sub-pixel Pa located in the component area CA, and the 2-1st data line D 2-1 It ends in a portion of the main display area MDA that is adjacent to the lower side of the component area CA (eg, adjacent in the −y direction) or is located in the component area CA.

[0199] No. 2-2 Data Line D 2-2 The third row R located in the main display area MDA extends in the -y direction and is aligned with the third row R located in the main display area MDA. 3 Subpixel 3-2 in 3-2 However, the 2-2 data line D 2-2 is not connected to the auxiliary sub-pixel Pa located in the component area CA, and the 2-2nd data line D 2-2 It ends in a portion of the main display area MDA that is adjacent to the upper side of the component area CA (eg, adjacent in the +y direction) or is located in the component area CA.

[0200] like Fig.15 As shown in the exemplary embodiment, the first bridge wire B 1 The first side of the 2-1 data line D is located adjacent to the lower side of the component area CA (eg, adjacent in the −y direction relative to the component area CA). 2-1 , and the first bridge wire B 1 The second side of the 2-2 data line D is adjacent to the upper side of the component area CA (eg, adjacent to the component area CA in the +y direction). 2-2 , and therefore, the 2-2 data line D 2-2 With the 2-1 data line D 2-1Therefore, the data signal Dm can be transmitted through the 2-2 data line D 2-2 Applied to the 3-2nd sub-pixel Sub 3-2 .

[0201] Reference above Figures 10 to 13 The description given of the exemplary embodiments can be applied to Figure 14 to Figure 15 The third data line D in the exemplary embodiment of 3 , 4-1 data line D 4-1 , 4-2 data line D 4-2 and the second bridge wire B 2 .

[0202] When the first data line D 1 When extending substantially in the +y direction, the first data line D 1 Passing near the transmission area TA. In this embodiment, the area of ​​the transmission area TA needs to be increased. Fig.14 As shown in the exemplary embodiment, the first data line D 1 The third data line D extending in a straight line shape in the +y direction may be appropriately bent when passing between the auxiliary sub-pixels Pa in the component area CA, and thus, may be as close as possible to the third data line D extending in a straight line shape in the +y direction. 3 .like Fig.15 As shown in the exemplary embodiment of the present invention, this structure can also be applied to the first bridge line B 1 and the second bridge wire B 2 For example, the first bridge line B 1 The second bridge line B extending in a straight line shape in the +y direction may be appropriately bent when passing between the auxiliary sub-pixels Pa in the component area CA, and thus, may be as close as possible to the second bridge line B extending in a straight line shape in the +y direction. 2 .

[0203] So far, the pixel group PG composed of the auxiliary sub-pixels Pa in the component area CA has been described (see Figure 5 and Figure 6 ) has a pixel group PG composed of main sub-pixels Pm in the main display area MDA (see Figure 4 ) are exemplary embodiments of the same configuration. However, the exemplary embodiments of the inventive concept are not limited thereto.

[0204] For example, Fig.16 and Fig.17 As shown in the exemplary embodiment ( Fig.16 and Fig.17) is a schematic plan view showing the arrangement of sub-pixels and wiring lines of a display panel according to another exemplary embodiment, the pixel group PG in the main display area MDA may include a total of eight main sub-pixels Pm, including a red sub-pixel Pr, a green sub-pixel Pg, a blue sub-pixel Pb, and a green sub-pixel Pg arranged sequentially in the +x direction in one row, and a blue sub-pixel Pb, a green sub-pixel Pg, a red sub-pixel Pr, and a green sub-pixel Pg arranged sequentially in the +x direction in a row below it. In contrast, the pixel group PG in the component area CA may include a total of six auxiliary sub-pixels Pa, including a red sub-pixel Pr, a green sub-pixel Pg, and a blue sub-pixel Pb arranged sequentially in the +x direction in one row, and a blue sub-pixel Pb, a green sub-pixel Pg, and a red sub-pixel Pr arranged sequentially in the +x direction in a row below it. Through this configuration, a transmission area TA with a larger area can be ensured in the component area CA.

[0205] In this embodiment, the 1st to 5th sub-pixels Sub 1-5 The pixel circuit and the 3rd to 5th sub-pixels Sub 3-5 The pixel circuit is connected to the fifth data line D 5 are electrically connected to each other, wherein the 1st to 5th sub-pixels Sub 1-5 The first row R adjacent to the lower side of the component area CA (eg, adjacent in the -y direction) 1 The main sub-pixel Pm, the 3rd to 5th sub-pixels Sub 3-5 The third row R is adjacent to the upper side of the component area CA (for example, adjacent in the +y direction). 3 The fifth data line D 5 The fifth data line D crosses the component area CA but is not connected to the pixel circuit of the auxiliary sub-pixel Pa located in the component area CA. Because the number of main sub-pixels Pm included in the pixel group PG in the main display area MDA is greater than the number of auxiliary sub-pixels Pa included in the pixel group PG in the component area CA, the fifth data line D 5 The pixel circuit is not connected to the auxiliary sub-pixel Pa.

[0206] No. 6-1 Data Line D 6-1 and R in the first row 1 Subpixels 1-6 in 1-6 However, the 6-1 data line D 6-1 The 6-1st data line D extends in the +y direction in the main display area MDA, but does not extend across the component area CA. 6-1The 6-2 data line D may be terminated in a portion of the main display area MDA that is adjacent to the lower side of the component area CA (eg, adjacent in the -y direction) or located in the component area CA. 6-2 and the 3rd to 6th sub-pixels Sub in the third row R3 3-6 However, the 6-2 data line D 6-2 The 6-2nd data line D extends in the -y direction in the main display area MDA, but does not extend across the component area CA. 6-2 The main display area MDA may be terminated in a portion adjacent to the upper side of the component area CA (eg, adjacent in the +y direction) or located in the component area CA.

[0207] like Fig.17 As shown in the exemplary embodiment, the 6-1 data line D 6-1 and 6-2 data line D 6-2 Through the third bridge connection B 3 are electrically connected to each other, wherein the third bridge wire B 3 Located with the 6-1 data line D 6-1 and 6-2 data line D 6-2 on different layers and has a 6-1 data line D 6-1 One side of the contact and the 6-2 data line D 6-2 In addition, the third bridge wire B 3 Along the fifth data line D 5 The third bridging line B extends from at least a portion of the transmission area TA, and thus, the area of ​​the transmission area TA may be large. 3 It does not pass through the portion of the component area CA occupied by the auxiliary sub-pixel Pa, and extends substantially in the +y direction along the outside of the auxiliary sub-pixel Pa (eg, in the +x direction).

[0208] Reference above Fig.10 and Fig.11 The exemplary embodiment of the 4-1 data line D 4-1 , 4-2 data line D 4-2 and the second bridge wire B 2 The description given is applicable to the 6-1 data line D 6-1 , 6-2 data line D 6-2 and the third bridge connection B 3 For example, the 6-1 data line D 6-1 and 6-2 data line D 6-2 Can be located at the first data line D 1 , 2nd-1st data line D 2-1 and 2-2 data line D 2-2 On the same layer, and the third bridge wire B 3Can be located with the first bridge connection B 1 On the same layer. The first bridge wire B 1 The third bridge line B3 may be located to cover the first data line D 1 , 2nd-1st data line D 2-1 , 2-2 data line D 2-2 , No. 6-1 data line D 6-1 and 6-2 data line D 6-2 on the insulation layer.

[0209] Referenced Fig.16 and Fig.17 The exemplary embodiment of the present invention describes an embodiment in which the number of main sub-pixels Pm included in the pixel group PG in the main display area MDA is greater than the number of auxiliary sub-pixels Pa included in the pixel group PG in the component area CA. Fig.16 and Fig.17 The description given of the exemplary embodiment of the main display area MDA is applicable to the exemplary embodiment in which the number of main sub-pixels Pm included in the pixel group PG in the main display area MDA is equal to the number of auxiliary sub-pixels Pa included in the pixel group PG in the component area CA. For example, the resolution in the component area CA is lower than about 1 / 2 of the resolution in the main display area MDA.

[0210] Exemplary embodiments of the present inventive concept are not limited to Figures 10 to 17 For example, in an exemplary embodiment, the display panel may include at least one first data line extending from a lower row (such as the first row R) adjacent to the lower side of the component area CA (e.g., adjacent in the −y direction). 1 ) extends across the component area CA to an upper row (such as the third row R) adjacent to the upper side of the component area CA (eg, adjacent in the +y direction). 3 ). The at least one first data line electrically connects the main sub-pixels Pm in the lower row and the upper row with the auxiliary sub-pixels Pa in the component area CA. At least one lower second data line is electrically connected to the main sub-pixels Pm in the lower row and does not extend across the component area CA. At least one upper second data line is electrically connected to the main sub-pixels Pm in the upper row and does not extend across the component area CA. The display panel includes at least one bridge line having a first end connected to a lower second data line and a second end connected to an upper second data line. The at least one bridge line is arranged on a different layer from the at least one first data line, and each of the at least one bridge line has an overlapping portion extending along at least a portion of a first data line as described above.

[0211] The data line electrically connected to the pixel circuit of the main sub-pixel Pm located in a portion of the main display area MDA adjacent to the lower side of the component area CA (e.g., adjacent in the -y direction) can be electrically connected to a data line electrically connected to the pixel circuit of the main sub-pixel Pm located in a portion of the main display area MDA adjacent to the upper side of the component area CA (e.g., adjacent in the +y direction) through a bridge line located on a layer different from the data line. The bridge line has a portion extending along at least a portion of the data line across the component area CA, and therefore, the area of ​​the transmission area TA can be large. In addition, since the resolution in the component area CA is lower than about 1 / 2 of the resolution in the main display area MDA, the bridge line does not pass through the portion occupied by the auxiliary sub-pixel Pa in the component area CA, and extends substantially in the +y direction along the outside of the auxiliary sub-pixel Pa.

[0212] So far, a display device having a display panel 10 and a component 20 as an electronic element has been described. However, exemplary embodiments of the inventive concept are not limited thereto. For example, the display panel 10 itself as described above is also within the scope of the inventive concept.

[0213] According to one or more exemplary embodiments of the inventive concept, a display panel and a display device including the display panel can be realized, wherein the display panel has an expanded display area so as to display an image even in an area where components as electronic elements are arranged. However, the scope of the inventive concept is not limited by these effects.

[0214] It should be understood that the exemplary embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. The description of features or aspects in each exemplary embodiment should generally be considered as other similar features or aspects that can be used in other exemplary embodiments. Although one or more exemplary embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and details may be made without departing from the scope and spirit as defined in the appended claims.

Claims

1. A display panel, comprising: A 1-1th sub-pixel and a 1-2th sub-pixel, wherein the 1-1th sub-pixel and the 1-2th sub-pixel are arranged in a first row; a 2-1th sub-pixel, the 2-1th sub-pixel being arranged in a second row; A 3-1st sub-pixel and a 3-2nd sub-pixel, wherein the 3-1st sub-pixel and the 3-2nd sub-pixel are arranged in a third row; a first data line configured to electrically connect a pixel circuit of the 1-1th sub-pixel, a pixel circuit of the 2-1th sub-pixel, and a pixel circuit of the 3-1th sub-pixel; a 2-1st data line, the 2-1st data line being configured to be electrically connected to a pixel circuit of the 1-2nd sub-pixel; a 2-2nd data line, the 2-2nd data line being configured to be electrically connected to a pixel circuit of the 3-2nd sub-pixel; as well as A first bridge wire, the first bridge wire is arranged on a layer different from the first data line, the 2-1 data line and the 2-2 data line, the first bridge wire has a first side in contact with the 2-1 data line and a second side in contact with the 2-2 data line, and the first bridge wire has a portion extending along at least a portion of the first data line.

2. The display panel according to claim 1, wherein: The 1-1th sub-pixel, the 1-2th sub-pixel, the 2-1th sub-pixel, the 3-1th sub-pixel and the 3-2nd sub-pixel are arranged on a substrate, The orthogonal projection image of the portion of the first bridge line extending along the at least a portion of the first data line on the top surface of the substrate overlaps with the orthogonal projection image of the first data line on the top surface of the substrate.

3. The display panel according to claim 1, further comprising: a 1-3th sub-pixel and a 1-4th sub-pixel, wherein the 1-3th sub-pixel and the 1-4th sub-pixel are arranged in the first row, wherein the 1-3th sub-pixel and the 1-2th sub-pixel are adjacent to the 1-1th sub-pixel in opposite directions, and the 1-4th sub-pixel is arranged between the 1-1th sub-pixel and the 1-2th sub-pixel; a 2-2 th sub-pixel, wherein the 2-2 th sub-pixel is arranged in the second row; a 3-3rd sub-pixel and a 3-4th sub-pixel, the 3-3rd sub-pixel and the 3-4th sub-pixel being arranged in the third row, wherein the 3-3rd sub-pixel and the 3-2nd sub-pixel are adjacent to the 3-1st sub-pixel in opposite directions, and the 3-4th sub-pixel is arranged between the 3-1st sub-pixel and the 3-2nd sub-pixel; a third data line, the third data line being configured to electrically connect the pixel circuit of the 1-3 sub-pixel, the pixel circuit of the 2-2 sub-pixel, and the pixel circuit of the 3-3 sub-pixel; A 4-1st data line, the 4-1st data line being electrically connected to a pixel circuit of the 1-4th sub-pixel; a 4-2nd data line, the 4-2nd data line being electrically connected to a pixel circuit of the 3-4th sub-pixel; and A second bridge wire, the second bridge wire is arranged on a layer different from the third data line, the 4-1 data line and the 4-2 data line, the second bridge wire has a first side in contact with the 4-1 data line and a second side in contact with the 4-2 data line, and the second bridge wire has a portion extending along at least a portion of the third data line.

4. The display panel according to claim 3, wherein: The 1-3rd sub-pixel, the 1-4th sub-pixel, the 2-2nd sub-pixel, the 3-3rd sub-pixel and the 3-4th sub-pixel are arranged on a substrate, The orthogonal projection image of the portion of the second bridge line extending along the at least a portion of the third data line on the top surface of the substrate overlaps with the orthogonal projection image of the third data line on the top surface of the substrate.

5. The display panel according to claim 3, wherein: The third data line, the 4-1 data line, and the 4-2 data line are arranged on the same layer as the first data line, the 2-1 data line, and the 2-2 data line; and The second bridge line is arranged on the same layer as the first bridge line.

6. The display panel according to claim 5, wherein: The first bridge line and the second bridge line are arranged on an insulating layer covering the first data line, the 2-1st data line, the 2-2nd data line, the third data line, the 4-1st data line, and the 4-2nd data line.

7. The display panel according to claim 1, wherein: The display panel includes a component area and a main display area surrounding the component area, wherein the 1-1th sub-pixel, the 1-2th sub-pixel, the 3-1th sub-pixel and the 3-2th sub-pixel are located in the main display area, and the 2-1th sub-pixel is located in the component area.

8. The display panel according to claim 7, wherein: The component region includes a transmissive region located outside the 2-1 th sub-pixel.

9. The display panel according to claim 8, further comprising: an additional data line electrically connected to a pixel circuit of a sub-pixel in the component area, Wherein, the additional data line extends along the edge of the transmission area.

10. The display panel according to claim 7, wherein: The resolution of the component area is 1 / 2 or less than 1 / 2 of the resolution of the main display area.

11. The display panel according to claim 7, further comprising: an auxiliary driving voltage line, the auxiliary driving voltage line being configured to be electrically connected to the pixel circuit of the 2-1th sub-pixel to apply a driving voltage to the pixel circuit of the 2-1th sub-pixel, The auxiliary driving voltage line is located in the component area, arranged on a layer different from the first data line and the first bridge line, and overlaps with the first data line and the first bridge line.

12. The display panel according to claim 11, wherein: The auxiliary driving voltage line is arranged below the first data line and the first bridge line. 13 . The display panel according to claim 11 , further comprising a driving voltage line in the main display area, the driving voltage line being configured to be electrically connected to the pixel circuit of the 1-1th sub-pixel to apply a driving voltage to the pixel circuit of the 1-1th sub-pixel.

14. The display panel according to claim 13, wherein: The driving voltage line and the first data line are arranged on the same layer.

15. The display panel according to claim 13, wherein: The width of the auxiliary driving voltage line is greater than the width of the driving voltage line.

16. The display panel according to claim 1, further comprising: 1st to 5th sub-pixels, the 1st to 5th sub-pixels are arranged in the first row; 3rd to 5th sub-pixels, the 3rd to 5th sub-pixels are arranged in the third row, and a fifth data line, the fifth data line being configured to electrically connect the pixel circuits of the 1st to 5th sub-pixels with the pixel circuits of the 3rd to 5th sub-pixels, The display panel includes a component area and a main display area surrounding the component area, wherein the 1-1th sub-pixel, the 1-2th sub-pixel, the 1-5th sub-pixel, the 3-1th sub-pixel, the 3-2nd sub-pixel and the 3-5th sub-pixel are located in the main display area, and the 2-1st sub-pixel is located in the component area, The fifth data line crosses the component area and is not connected to the pixel circuit of the sub-pixel in the component area.

17. The display panel according to claim 16, further comprising: 1st to 6th sub-pixels, the 1st to 6th sub-pixels are arranged in the first row; 3rd to 6th sub-pixels, the 3rd to 6th sub-pixels are arranged in the third row; a 6-1st data line, the 6-1st data line being configured to be electrically connected to the 1-6th sub-pixel; A 6-2 data line, the 6-2 data line being configured to be electrically connected to the 3-6 sub-pixel; as well as a third bridge wire, the third bridge wire being arranged on a layer different from the 6-1 data line and the 6-2 data line, the third bridge wire having a first side in contact with the 6-1 data line and a second side in contact with the 6-2 data line, the third bridge wire having a portion extending along at least a portion of the fifth data line.

18. The display panel according to claim 17, wherein: The 6-1st data line, the 6-2nd data line, the first data line, the 2-1st data line and the 2-2nd data line are arranged on the same layer; and The third bridge line and the first bridge line are arranged on the same layer.

19. The display panel according to claim 18, wherein: The first bridge line and the third bridge line are arranged on an insulating layer covering the first data line, the 2-1st data line, the 2-2nd data line, the 6-1st data line, and the 6-2nd data line.

20. A display device comprising: A display panel, the display panel comprising a component area and a main display area surrounding the component area; as well as electronic components, the electronic components being arranged to correspond to the component areas of the display panel, Wherein, the display panel comprises: A 1-1th sub-pixel and a 1-2th sub-pixel, wherein the 1-1th sub-pixel and the 1-2th sub-pixel are arranged in a first row; a 2-1th sub-pixel, the 2-1th sub-pixel being arranged in a second row; A 3-1st sub-pixel and a 3-2nd sub-pixel, wherein the 3-1st sub-pixel and the 3-2nd sub-pixel are arranged in a third row; a first data line configured to electrically connect a pixel circuit of the 1-1th sub-pixel, a pixel circuit of the 2-1th sub-pixel, and a pixel circuit of the 3-1th sub-pixel; a 2-1st data line, the 2-1st data line being configured to be electrically connected to a pixel circuit of the 1-2nd sub-pixel; a 2-2nd data line, the 2-2nd data line being configured to be electrically connected to a pixel circuit of the 3-2nd sub-pixel; and A first bridge wire, the first bridge wire is arranged on a layer different from the first data line, the 2-1 data line and the 2-2 data line, the first bridge wire has a first side in contact with the 2-1 data line and a second side in contact with the 2-2 data line, and the first bridge wire has a portion extending along at least a portion of the first data line.

21. The display device according to claim 20, wherein: The electronic component includes an imaging device.

22. A display panel comprising: a component area, the component area being surrounded by the main display area, the component area having a plurality of auxiliary sub-pixels and a transmission area surrounding the plurality of auxiliary sub-pixels, the transmission area being configured such that light is transmitted through the transmission area; the primary display area having a first plurality of primary sub-pixels arranged in a lower row adjacent to a lower side of the component area and a second plurality of primary sub-pixels arranged in an upper row adjacent to an upper side of the component area; at least one first data line extending from the lower row across the component area to the upper row, and each of the at least one first data line being configured to electrically connect sub-pixels in the lower row and the upper row with a first auxiliary sub-pixel; at least one lower second data line, the at least one lower second data line being configured to be electrically connected to the sub-pixels in the lower row; at least one upper second data line, the at least one upper second data line configured to be electrically connected to the sub-pixels in the upper row; at least one bridge line, each of the at least one bridge line having a first end connected to one of the at least one lower second data line and a second end connected to one of the at least one upper second data line, The at least one bridge line is disposed on a different layer from the at least one first data line, and each of the at least one bridge line has an overlapping portion extending along at least a portion of one of the at least one first data line.

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