A silicon carbide power device terminal structure and preparation method thereof

Abstract

The present invention relates to the field of semiconductor technology, and discloses a terminal structure of a silicon carbide power device and a preparation method thereof, wherein the terminal structure comprises: an N-type silicon carbide substrate; an N-type silicon carbide epitaxial layer formed on one side of the N-type silicon carbide substrate, a P+ region, a first JTE region and a second JTE region arranged in a direction parallel to the N-type silicon carbide substrate are formed on the side of the N-type silicon carbide epitaxial layer away from the N-type silicon carbide substrate, and the first JTE region and the second JTE region are arranged in different layers; a dielectric passivation layer formed on the side of the N-type silicon carbide epitaxial layer away from the N-type silicon carbide substrate, and the first JTE region or the second JTE region is in contact with the dielectric passivation layer. In the above-mentioned terminal structure, the first JTE region and the second JTE region are located in different layers, and one of the first JTE region and the second JTE region is in contact with the dielectric passivation layer, which reduces the contact area between the JTE region and the dielectric passivation layer, and can reduce the influence of the interface charge of the dielectric passivation layer on the withstand voltage of the JTE terminal.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a silicon carbide power device terminal structure and a preparation method thereof. Background Art

[0002] Silicon carbide (SiC) is one of the third-generation wide bandgap semiconductors. It has excellent physical properties such as wide bandgap, high breakdown electric field, high thermal conductivity, high temperature resistance, high voltage resistance, and radiation resistance. Therefore, SiC power devices are very suitable for high temperature, high voltage, and high power power electronics application systems. It has broad application prospects in electric vehicles, photovoltaic inverters, rail transit, wind power generation, motor drives and other application fields.

[0003] The terminal structure of silicon carbide power devices generally includes junction terminal extension (JTE), field limiting ring (FLR) and field plate (FP). The advantage of the field limiting ring terminal is that the P+ field limiting ring can be made together with the P+ ion implantation of the SiC active area, but because the field limiting ring spacing of SiC power devices is small, the withstand voltage is sensitive to the field limiting ring spacing, and the manufacturing process accuracy of the ion implantation mask is required to be high. The JTE terminal does not require high precision in the manufacturing process of the implantation mask, and requires a low ion implantation concentration for the JTE terminal, but the withstand voltage characteristics of the JTE terminal are sensitive to the interface charge of the passivation layer, which will affect the process repeatability. Summary of the invention

[0004] The present invention provides a silicon carbide power device terminal structure and a preparation method thereof, so as to solve the technical problem that "the withstand voltage characteristics of the JTE terminal are sensitive to the interface charge of the passivation layer, which will affect the process repeatability".

[0005] In order to achieve the above object, the present invention provides the following technical solutions:

[0006] A silicon carbide power device terminal structure, comprising:

[0007] N-type silicon carbide substrate;

[0008] An N-type silicon carbide epitaxial layer is formed on one side of the N-type silicon carbide substrate, wherein a P+ region, a first junction terminal extension JTE region and a second junction terminal extension JTE region are formed on a side of the N-type silicon carbide epitaxial layer away from the N-type silicon carbide substrate, the first JTE region is connected to the P+ region, and the first JTE region and the second JTE region are arranged in different layers;

[0009] A dielectric passivation layer is formed on the side of the N-type silicon carbide epitaxial layer away from the N-type silicon carbide substrate, when the first JTE region is located on the side of the second JTE region away from the N-type silicon carbide substrate, the first JTE region is in contact with the dielectric passivation layer; when the second JTE region is located on the side of the first JTE region away from the N-type silicon carbide substrate, the second JTE region is in contact with the dielectric passivation layer.

[0010] In the above-mentioned silicon carbide power device terminal structure, the silicon carbide power device terminal structure includes an N-type silicon carbide substrate, an N-type silicon carbide epitaxial layer and a dielectric passivation layer, wherein a P+ region, a first junction terminal extension JTE region and a second junction terminal extension JTE region arranged in a direction parallel to the N-type silicon carbide substrate are formed in the N-type silicon carbide epitaxial layer, the first JTE region is connected to the P+ region, and the first JTE region and the second JTE region are arranged in different layers. When the first JTE region is located on the side of the second JTE region away from the N-type silicon carbide substrate, the first JTE region is in contact with the dielectric passivation layer; when the second JTE region is located on the side of the first JTE region away from the N-type silicon carbide substrate, the second JTE region is in contact with the dielectric passivation layer.

[0011] In the silicon carbide power device terminal structure provided by the present invention, the first JTE region and the second JTE region are located in different layers, and one of the first JTE region and the second JTE region is in contact with the dielectric passivation layer, thereby reducing the contact area between the JTE region and the dielectric passivation layer, and reducing the influence of the interface charge of the dielectric passivation layer on the withstand voltage of the JTE terminal.

[0012] Therefore, the above-mentioned silicon carbide power device terminal structure can reduce the influence of the interface charge of the dielectric passivation layer on the JTE terminal withstand voltage, so as to improve the process repeatability and device reliability.

[0013] Preferably, the P+ region includes a first P+ region and a second P+ region, the first P+ region is arranged on a side of the second P+ region facing the N-type silicon carbide substrate, and the first JTE region is arranged in the same layer as the first P+ region, and the second JTE region is arranged in the same layer as the second P+ region.

[0014] Preferably, the second JTE region is located between the first JTE region and the N-type silicon carbide substrate.

[0015] Preferably, it also includes a front metal electrode formed between the P+ region and the dielectric passivation layer and a back metal electrode formed on the side of the N-type silicon carbide substrate away from the N-type silicon carbide epitaxial layer, and the front metal electrode is electrically in contact with the P+ region.

[0016] It also includes a polyimide passivation layer formed on a side of the dielectric passivation layer away from the N-type silicon carbide substrate.

[0017] The present invention also provides a method for preparing a silicon carbide power device terminal structure, which is used to prepare any one of the silicon carbide power device terminal structures provided by the above technical solution, comprising:

[0018] forming an N-type silicon carbide substrate;

[0019] An N-type silicon carbide epitaxial layer is formed on the N-type silicon carbide substrate, wherein a P+ region, a first junction terminal extension JTE region and a second junction terminal extension JTE region are arranged in a direction parallel to the N-type silicon carbide substrate on a side of the N-type silicon carbide epitaxial layer away from the N-type silicon carbide substrate, the first JTE region is connected to the P+ region, and the first JTE region and the second JTE region are arranged in different layers;

[0020] A dielectric passivation layer is formed on the N-type silicon carbide epitaxial layer, and when the first JTE region is located on the side of the second JTE region away from the N-type silicon carbide substrate, the first JTE region is in contact with the dielectric passivation layer; when the second JTE region is located on the side of the first JTE region away from the N-type silicon carbide substrate, the second JTE region is in contact with the dielectric passivation layer.

[0021] Preferably, when the P+ region includes a first P+ region and a second P+ region, the method of forming the first P+ region, the second P+ region, the first JTE region and the second JTE region in the N-type silicon carbide epitaxial layer includes:

[0022] Epitaxially growing on the N-type silicon carbide substrate to form an N-type silicon carbide epitaxial layer;

[0023] Depositing a first ion implantation mask layer, dry-etching the first ion implantation mask layer to expose an ion implantation region of the first ion implantation mask layer, and implanting P-type dopant ions into the ion implantation region of the first ion implantation mask layer to form a first P+ region;

[0024] removing the first ion implantation mask layer;

[0025] Depositing a second ion implantation mask layer, dry-etching the second ion implantation mask layer to expose an ion implantation region of the second ion implantation mask layer, and implanting P-type dopant ions into the ion implantation region of the second ion implantation mask layer to form a first JTE region;

[0026] removing the second ion implantation mask layer;

[0027] epitaxially growing the N-type silicon carbide epitaxial layer again on a side of the N-type silicon carbide epitaxial layer away from the N-type silicon carbide substrate;

[0028] Depositing a third ion implantation mask layer, dry-etching the third ion implantation mask layer to expose an ion implantation region of the third ion implantation mask layer, and implanting P-type doping ions into the ion implantation region of the third ion implantation mask layer to form a second P+ region;

[0029] removing the third ion implantation mask layer;

[0030] Depositing a fourth ion implantation mask layer, dry-etching the fourth ion implantation mask layer to expose an ion implantation region of the fourth ion implantation mask layer, and implanting P-type dopant ions into the ion implantation region of the fourth ion implantation mask layer to form a second JTE region;

[0031] removing the fourth ion implantation mask layer and preparing a carbon film as a high temperature activated protective layer;

[0032] The P-type doping ions are activated at high temperature, and the carbon film is removed after activation.

[0033] Preferably, when the second JTE region is located between the first JTE region and the N-type silicon carbide substrate, the method of forming a P+ region, the first JTE region and the second JTE region in the N-type silicon carbide epitaxial layer includes:

[0034] Epitaxially growing on the N-type silicon carbide substrate to form the N-type silicon carbide epitaxial layer;

[0035] Depositing a first ion implantation mask layer, dry-etching the first ion implantation mask layer to expose an ion implantation region of the first ion implantation mask layer, and implanting P-type dopant ions into the ion implantation region of the first ion implantation mask layer to form a second JTE region;

[0036] removing the first ion implantation mask layer;

[0037] epitaxially growing an N-type silicon carbide epitaxial layer again on a side of the N-type silicon carbide epitaxial layer away from the N-type silicon carbide substrate;

[0038] Depositing a second ion implantation mask layer, dry-etching the second ion implantation mask layer to expose an ion implantation region of the second ion implantation mask layer, and implanting P-type dopant ions into the ion implantation region of the second ion implantation mask layer to form a P+ region;

[0039] removing the second ion implantation mask layer;

[0040] Depositing a third ion implantation mask layer, dry-etching the third ion implantation mask layer to expose an ion implantation region of the third ion implantation mask layer, and implanting P-type dopant ions into the ion implantation region of the third ion implantation mask layer to form a first JTE region;

[0041] removing the third ion implantation mask layer and preparing a carbon film as a high temperature activated protective layer;

[0042] The P-type doping ions are activated at high temperature, and the carbon film is removed after activation.

[0043] Preferably, the carbon film is prepared by photoresist carbonization or sputtering.

[0044] Preferably, it also includes:

[0045] forming a front metal electrode on the P+ region;

[0046] A back metal electrode is formed on a side of the N-type silicon carbide substrate away from the N-type silicon carbide epitaxial layer.

[0047] Preferably, it also includes:

[0048] Depositing a dielectric passivation layer on the front metal electrode and the N-type silicon carbide epitaxial layer;

[0049] A polyimide passivation layer is prepared on the dielectric passivation layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 A schematic structural diagram of a silicon carbide power device terminal structure provided by an embodiment of the present invention;

[0051] Figure 2 Another structural schematic diagram of a silicon carbide power device terminal structure provided by an embodiment of the present invention;

[0052] Figure 3 A flow chart of a method for preparing a terminal structure of a silicon carbide power device provided by an embodiment of the present invention;

[0053] Figure 4a-4j for Figure 1 Schematic diagram of the film preparation of the medium structure;

[0054] Figure 5 Another flow chart of the method for preparing the terminal structure of a silicon carbide power device provided in an embodiment of the present invention.

[0055] Icon: 1-N-type silicon carbide substrate; 2-N-type silicon carbide epitaxial layer; 3-P+ region; 31-first P+ region; 32-second P+ region; 4-first JTE region; 5-second JTE region; 6-front metal electrode; 7-back metal electrode; 8-dielectric passivation layer; 9-polyimide passivation layer. DETAILED DESCRIPTION

[0056] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0057] Please refer to Figure 1 The present invention provides a silicon carbide power device terminal structure, comprising:

[0058] N-type silicon carbide substrate 1;

[0059] An N-type silicon carbide epitaxial layer 2 is formed on one side of an N-type silicon carbide substrate 1, a P+ region 3, a first junction terminal extension JTE region, and a second junction terminal extension JTE region are formed on the side of the N-type silicon carbide epitaxial layer 2 facing away from the N-type silicon carbide substrate 1, the first JTE region 4 is connected to the P+ region 3, and the first JTE region 4 and the second JTE region 5 are arranged in different layers;

[0060] A dielectric passivation layer 8 is formed on the side of the N-type silicon carbide epitaxial layer 2 away from the N-type silicon carbide substrate 1. When the first JTE region 4 is located on the side of the second JTE region 5 away from the N-type silicon carbide substrate 1, the first JTE region 4 is in contact with the dielectric passivation layer 8; when the second JTE region 5 is located on the side of the first JTE region 4 away from the N-type silicon carbide substrate 1, the second JTE region 5 is in contact with the dielectric passivation layer 8.

[0061] In the above-mentioned silicon carbide power device terminal structure, the silicon carbide power device terminal structure includes an N-type silicon carbide substrate 1, an N-type silicon carbide epitaxial layer 2 and a dielectric passivation layer 8, wherein a P+ region 3, a first JTE region 4 and a second JTE region 5 arranged in a direction parallel to the N-type silicon carbide substrate 1 are formed in the N-type silicon carbide epitaxial layer 2, the first JTE region 4 is connected to the P+ region 3, and the first JTE region 4 and the second JTE region 5 are arranged in different layers, when the first JTE region 4 is located on the side of the second JTE region 5 away from the N-type silicon carbide substrate 1, the first JTE region 4 is in contact with the dielectric passivation layer 8; when the second JTE region 5 is located on the side of the first JTE region 4 away from the N-type silicon carbide substrate 1, the second JTE region 5 is in contact with the dielectric passivation layer 8.

[0062] In the silicon carbide power device terminal structure provided by the present invention, the first JTE region 4 and the second JTE region 5 are located in different layers, and one of the first JTE region 4 and the second JTE region 5 is in contact with the dielectric passivation layer 8, thereby reducing the contact area between the JTE region and the dielectric passivation layer 8, and reducing the influence of the interface charge of the dielectric passivation layer 8 on the JTE terminal withstand voltage.

[0063] Therefore, the above-mentioned silicon carbide power device terminal structure can reduce the influence of the interface charge of the dielectric passivation layer 8 on the JTE terminal withstand voltage, so as to improve the process repeatability and device reliability.

[0064] For an optional implementation, please continue to refer to Figure 1 The P+ region 3 includes a first P+ region 31 and a second P+ region 32 , the first P+ region 31 is arranged on a side of the second P+ region 32 facing the N-type silicon carbide substrate 1 , and the first JTE region 4 is arranged in the same layer as the first P+ region 31 , and the second JTE region 5 is arranged in the same layer as the second P+ region 32 .

[0065] Based on the above technical solutions, please continue to refer to Figure 1 The silicon carbide power device terminal structure provided by the present invention also includes a front metal electrode 6 formed between the P+ region 3 and the dielectric passivation layer 8 and a back metal electrode 7 formed on the side of the N-type silicon carbide substrate 1 away from the N-type silicon carbide epitaxial layer 2, and the front metal electrode 6 is electrically in contact with the P+ region 3.

[0066] Based on the above technical solutions, please continue to refer to Figure 1 The silicon carbide power device terminal structure provided by the present invention further includes a polyimide passivation layer 9 formed on a side of the dielectric passivation layer 8 away from the N-type silicon carbide substrate 1 .

[0067] For another alternative implementation, please refer to Figure 2 , the second JTE region 5 is located between the first JTE region 4 and the N-type silicon carbide substrate 1 .

[0068] Based on the above technical solutions, please continue to refer to Figure 2 The silicon carbide power device terminal structure provided by the present invention also includes a front metal electrode 6 formed between the P+ region 3 and the dielectric passivation layer 8 and a back metal electrode 7 formed on the side of the N-type silicon carbide substrate 1 away from the N-type silicon carbide epitaxial layer 2, and the front metal electrode 6 is electrically in contact with the P+ region 3.

[0069] Based on the above technical solutions, please continue to refer to Figure 2 The silicon carbide power device terminal structure provided by the present invention further includes a polyimide passivation layer 9 formed on a side of the dielectric passivation layer 8 away from the N-type silicon carbide substrate 1 .

[0070] Please refer to Figure 3 The present invention also provides a method for preparing a terminal structure of a silicon carbide power device, which is used to prepare any one of the terminal structures of a silicon carbide power device provided by the above technical solution, comprising:

[0071] forming an N-type silicon carbide substrate 1;

[0072] An N-type silicon carbide epitaxial layer 2 is formed on an N-type silicon carbide substrate 1, a P+ region 3, a first junction terminal extension JTE region, and a second junction terminal extension JTE region arranged in a direction parallel to the N-type silicon carbide substrate 1 are formed on the side of the N-type silicon carbide epitaxial layer 2 facing away from the N-type silicon carbide substrate 1, a first JTE region 4 is connected to the P+ region 3, and the first JTE region 4 and the second JTE region 5 are arranged in different layers;

[0073] A dielectric passivation layer 8 is formed on the N-type silicon carbide epitaxial layer 2. When the first JTE region 4 is located on the side of the second JTE region 5 away from the N-type silicon carbide substrate 1, the first JTE region 4 is in contact with the dielectric passivation layer 8; when the second JTE region 5 is located on the side of the first JTE region 4 away from the N-type silicon carbide substrate 1, the second JTE region 5 is in contact with the dielectric passivation layer 8.

[0074] In the terminal structure of the silicon carbide power device manufactured by the preparation method provided by the present invention, the first JTE region 4 and the second JTE region 5 are located in different layers, and one of the first JTE region 4 and the second JTE region 5 is in contact with the dielectric passivation layer 8, thereby reducing the contact area between the JTE region and the dielectric passivation layer 8, and reducing the influence of the interface charge of the dielectric passivation layer 8 on the JTE terminal withstand voltage, so as to improve the process repeatability and device reliability.

[0075] For an alternative implementation, please refer to Figure 1 When the P+ region 3 includes the first P+ region 31 and the second P+ region 32, the method of forming the first P+ region 31, the second P+ region 32, the first JTE region 4 and the second JTE region 5 in the N-type silicon carbide epitaxial layer 2 includes:

[0076] Please refer to Figure 4a , epitaxially growing on the N-type silicon carbide substrate 1 to form an N-type silicon carbide epitaxial layer 2;

[0077] Please refer to Figure 4b , depositing a first ion implantation mask layer, dry-etching the first ion implantation mask layer to expose an ion implantation region of the first ion implantation mask layer, and implanting P-type dopant ions into the ion implantation region of the first ion implantation mask layer to form a first P+ region 31;

[0078] removing the first ion implantation mask layer;

[0079] Please refer to Figure 4c , depositing a second ion implantation mask layer, dry-etching the second ion implantation mask layer to expose the ion implantation region of the second ion implantation mask layer, and implanting P-type dopant ions into the ion implantation region of the second ion implantation mask layer to form a first JTE region 4;

[0080] removing the second ion implantation mask layer;

[0081] Please refer to Figure 4d, epitaxially growing an N-type silicon carbide epitaxial layer 2 again on the side of the N-type silicon carbide epitaxial layer 2 away from the N-type silicon carbide substrate 1;

[0082] Please refer to Figure 4e , depositing a third ion implantation mask layer, dry-etching the third ion implantation mask layer to expose an ion implantation region of the third ion implantation mask layer, and implanting P-type dopant ions into the ion implantation region of the third ion implantation mask layer to form a second P+ region 32;

[0083] removing the third ion implantation mask layer;

[0084] Please refer to Figure 4f , depositing a fourth ion implantation mask layer, dry-etching the fourth ion implantation mask layer to expose an ion implantation region of the fourth ion implantation mask layer, and implanting P-type dopant ions into the ion implantation region of the fourth ion implantation mask layer to form a second JTE region 5;

[0085] removing the fourth ion implantation mask layer and preparing a carbon film as a high temperature activation protection layer;

[0086] The P-type doping ions are activated at high temperature, and the carbon film is removed after activation, such as Figure 4g .

[0087] In another optional embodiment, when the second JTE region 5 is located between the first JTE region 4 and the N-type silicon carbide substrate 1, the method of forming the P+ region 3, the first JTE region 4 and the second JTE region 5 in the N-type silicon carbide epitaxial layer 2 includes:

[0088] Epitaxially growing an N-type silicon carbide epitaxial layer 2 on an N-type silicon carbide substrate 1;

[0089] Depositing a first ion implantation mask layer, dry-etching the first ion implantation mask layer to expose an ion implantation region of the first ion implantation mask layer, and implanting P-type dopant ions into the ion implantation region of the first ion implantation mask layer to form a second JTE region 5;

[0090] removing the first ion implantation mask layer;

[0091] epitaxially growing an N-type silicon carbide epitaxial layer 2 again on the side of the N-type silicon carbide epitaxial layer 2 away from the N-type silicon carbide substrate 1;

[0092] Depositing a second ion implantation mask layer, dry-etching the second ion implantation mask layer to expose an ion implantation region of the second ion implantation mask layer, and implanting P-type doping ions into the ion implantation region of the second ion implantation mask layer to form a P+ region 3;

[0093] removing the second ion implantation mask layer;

[0094] Depositing a third ion implantation mask layer, dry-etching the third ion implantation mask layer to expose an ion implantation region of the third ion implantation mask layer, and implanting P-type doping ions into the ion implantation region of the third ion implantation mask layer to form a first JTE region 4;

[0095] removing the third ion implantation mask layer and preparing a carbon film as a high temperature activation protection layer;

[0096] The P-type doping ions are activated at high temperature, and the carbon film is removed after activation.

[0097] Based on the above two implementations, specifically, the preparation material of the N-type silicon carbide substrate 1 is silicon carbide (SiC), and the doping concentration is 1e18-2e19cm -3 The N-type silicon carbide epitaxial layer 2 formed by epitaxial growth on the N-type silicon carbide substrate 1 has a thickness of 5 to 100 μm, the preparation material of the N-type silicon carbide epitaxial layer 2 is silicon carbide (SiC), and the N-type doping concentration is 1e15 to 5e16 cm -3 The ion implantation mask layer is SiO2 or polysilicon, or a combination of the two, with a thickness of 0.2 to 4 μm. The ion implantation process is a single-step or multi-step high-temperature ion implantation process, the P-type doping ions are Al ions, and the doping concentration when forming the P+ region 3 (including the first P+ region 31 and the second P+ region 32) is 5e17 to 7e18 cm -3 The doping concentration when forming the first JTE region 4 or the second JTE region 5 is 5e16-5e17cm -3 .

[0098] It should be noted that the ion implantation mask layer includes the first ion implantation mask layer, the second ion implantation mask layer, the third ion implantation mask layer and the fourth ion implantation mask layer in the first embodiment, or includes the first ion implantation mask layer, the second ion implantation mask layer and the third ion implantation mask layer in the second embodiment. It is worth noting that the preparation material and thickness of each ion implantation mask layer in each embodiment can be the same or different, and the specific situation can be set according to the usage.

[0099] Specifically, the depth of the first JTE region 4 can be set to 0.2-1.5 μm; the depth of the second JTE region 5 can be set to 0.2-1.5 μm; and the depth of the P+ region 3 can be set to 0.2-3 μm.

[0100] In addition, the thickness of the N-type silicon carbide epitaxial layer 2 formed by the secondary epitaxial growth is 0.2-1.5 μm, and the N-type doping concentration is 1e15-5e16 cm -3 The preparation material is silicon carbide (SiC). It is worth noting that in the first embodiment, the ion implantation depth when forming the second JTE region 5 does not exceed the thickness of the N-type silicon carbide epitaxial layer 2 formed by the secondary epitaxial growth.

[0101] On the basis of the above technical solution, the carbon film is prepared by photoresist carbonization or sputtering.

[0102] Specifically, the carbon film thickness is 0.05-2 μm, and the activation temperature is 1500-1900° C.

[0103] On the basis of the above technical solution, the method for preparing the terminal structure of a silicon carbide power device provided by the present invention further includes:

[0104] Please refer to Figure 4h as well as Figure 5 , before forming the dielectric passivation layer 8 on the N-type silicon carbide epitaxial layer 2:

[0105] A front metal electrode 6 is formed on the P+ region 3;

[0106] A back metal electrode 7 is formed on a side of the N-type silicon carbide substrate 1 away from the N-type silicon carbide epitaxial layer 2 .

[0107] It should be noted that the preparation materials, thicknesses and preparation methods of the front metal electrode 6 and the back metal electrode 7 are selected according to actual device requirements.

[0108] On the basis of the above technical solution, the method for preparing the terminal structure of a silicon carbide power device provided by the present invention further includes:

[0109] Please refer to Figure 4i , depositing a dielectric passivation layer 8 on the front metal electrode 6 and the N-type silicon carbide epitaxial layer 2;

[0110] Please refer to Figure 4j , a polyimide passivation layer 9 is prepared on the dielectric passivation layer 8.

[0111] It should be noted that the preparation materials of the dielectric passivation layer 8 include but are not limited to SiO, SiO2, SiN, SiON or any combination thereof, and the deposition methods include but are not limited to Plasma Enhanced Chemical Vapor Deposition (PECVD), Low Pressure Chemical Vapor Deposition (LPCVD), and Atomic Layer Deposition (ALD), and its thickness is 50 to 2000 nm.

[0112] In addition, the thickness of the polyimide passivation layer 9 (ie, the PI passivation layer) after curing is 1-5 μm.

[0113] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A silicon carbide power device terminal structure, characterized in that: include: N-type silicon carbide substrate; An N-type silicon carbide epitaxial layer is formed on one side of the N-type silicon carbide substrate, wherein a P+ region, a first JTE region, and a second JTE region are arranged in a direction parallel to the N-type silicon carbide substrate on a side of the N-type silicon carbide epitaxial layer away from the N-type silicon carbide substrate, wherein the first JTE region is connected to the P+ region, and the first JTE region and the second JTE region are arranged in different layers; a dielectric passivation layer formed on a side of the N-type silicon carbide epitaxial layer away from the N-type silicon carbide substrate, wherein when the first JTE region is located on a side of the second JTE region away from the N-type silicon carbide substrate, the first JTE region is in contact with the dielectric passivation layer; When the second JTE region is located on a side of the first JTE region away from the N-type silicon carbide substrate, the second JTE region is in contact with the dielectric passivation layer; An orthographic projection of the first JTE region on the N-type silicon carbide substrate and an orthographic projection of the second JTE region on the N-type silicon carbide substrate have no overlap.

2. The silicon carbide power device terminal structure according to claim 1, characterized in that: The P+ region includes a first P+ region and a second P+ region, wherein the first P+ region is disposed on a side of the second P+ region facing the N-type silicon carbide substrate; When the second JTE region is located on a side of the first JTE region away from the N-type silicon carbide substrate, the first JTE region and the first P+ region are arranged in the same layer, and the second JTE region and the second P+ region are arranged in the same layer.

3. The silicon carbide power device terminal structure according to claim 1, characterized in that: When the first JTE region is located on a side of the second JTE region away from the N-type silicon carbide substrate, the second JTE region is located between the first JTE region and the N-type silicon carbide substrate.

4. The silicon carbide power device terminal structure according to claim 2 or 3, characterized in that: It also includes a front metal electrode formed between the P+ region and the dielectric passivation layer and a back metal electrode formed on the side of the N-type silicon carbide substrate away from the N-type silicon carbide epitaxial layer, and the front metal electrode is electrically in contact with the P+ region.

5. The silicon carbide power device terminal structure according to claim 4, characterized in that: It also includes a polyimide passivation layer formed on a side of the dielectric passivation layer away from the N-type silicon carbide substrate.

6. A method for preparing a silicon carbide power device terminal structure, used for preparing the silicon carbide power device terminal structure as claimed in any one of claims 1 to 5, characterized in that: include: forming an N-type silicon carbide substrate; An N-type silicon carbide epitaxial layer is formed on the N-type silicon carbide substrate, wherein a P+ region, a first JTE region and a second JTE region are arranged in a direction parallel to the N-type silicon carbide substrate on a side of the N-type silicon carbide epitaxial layer away from the N-type silicon carbide substrate, the first JTE region is connected to the P+ region, and the first JTE region and the second JTE region are arranged in different layers; forming a dielectric passivation layer on the N-type silicon carbide epitaxial layer, wherein when the first JTE region is located on a side of the second JTE region away from the N-type silicon carbide substrate, the first JTE region is in contact with the dielectric passivation layer; When the second JTE region is located at a side of the first JTE region away from the N-type silicon carbide substrate, the second JTE region is in contact with the dielectric passivation layer.

7. The preparation method according to claim 6, characterized in that: When the P+ region includes a first P+ region and a second P+ region, a method for forming the first P+ region, the second P+ region, the first JTE region and the second JTE region in the N-type silicon carbide epitaxial layer includes: Epitaxially growing on the N-type silicon carbide substrate to form the N-type silicon carbide epitaxial layer; Depositing a first ion implantation mask layer, dry-etching the first ion implantation mask layer to expose an ion implantation region of the first ion implantation mask layer, and implanting P-type dopant ions into the ion implantation region of the first ion implantation mask layer to form a first P+ region; removing the first ion implantation mask layer; Depositing a second ion implantation mask layer, dry-etching the second ion implantation mask layer to expose an ion implantation region of the second ion implantation mask layer, and implanting P-type dopant ions into the ion implantation region of the second ion implantation mask layer to form a first JTE region; removing the second ion implantation mask layer; epitaxially growing an N-type silicon carbide epitaxial layer again on a side of the N-type silicon carbide epitaxial layer away from the N-type silicon carbide substrate; Depositing a third ion implantation mask layer, dry-etching the third ion implantation mask layer to expose an ion implantation region of the third ion implantation mask layer, and implanting P-type doping ions into the ion implantation region of the third ion implantation mask layer to form a second P+ region; removing the third ion implantation mask layer; Depositing a fourth ion implantation mask layer, dry-etching the fourth ion implantation mask layer to expose an ion implantation region of the fourth ion implantation mask layer, and implanting P-type dopant ions into the ion implantation region of the fourth ion implantation mask layer to form a second JTE region; removing the fourth ion implantation mask layer and preparing a carbon film as a high temperature activated protective layer; The P-type doping ions are activated at high temperature, and the carbon film is removed after activation.

8. The preparation method according to claim 6, characterized in that: When the second JTE region is located between the first JTE region and the N-type silicon carbide substrate, the method of forming a P+ region, the first JTE region, and the second JTE region in the N-type silicon carbide epitaxial layer includes: Epitaxially growing on the N-type silicon carbide substrate to form the N-type silicon carbide epitaxial layer; Depositing a first ion implantation mask layer, dry-etching the first ion implantation mask layer to expose an ion implantation region of the first ion implantation mask layer, and implanting P-type dopant ions into the ion implantation region of the first ion implantation mask layer to form a second JTE region; removing the first ion implantation mask layer; epitaxially growing an N-type silicon carbide epitaxial layer again on a side of the N-type silicon carbide epitaxial layer away from the N-type silicon carbide substrate; Depositing a second ion implantation mask layer, dry-etching the second ion implantation mask layer to expose an ion implantation region of the second ion implantation mask layer, and implanting P-type dopant ions into the ion implantation region of the second ion implantation mask layer to form a P+ region; removing the second ion implantation mask layer; Depositing a third ion implantation mask layer, dry-etching the third ion implantation mask layer to expose an ion implantation region of the third ion implantation mask layer, and implanting P-type dopant ions into the ion implantation region of the third ion implantation mask layer to form a first JTE region; removing the third ion implantation mask layer and preparing a carbon film as a high temperature activated protective layer; The P-type doping ions are activated at high temperature, and the carbon film is removed after activation.

9. The preparation method according to any one of claims 7 or 8, characterized in that: The carbon film is prepared by photoresist carbonization or sputtering.

10. The preparation method according to claim 9, characterized in that: Also includes: forming a front metal electrode on the P+ region; A back metal electrode is formed on a side of the N-type silicon carbide substrate away from the N-type silicon carbide epitaxial layer.

11. The preparation method according to claim 10, characterized in that: Also includes: Depositing a dielectric passivation layer on the front metal electrode and the N-type silicon carbide epitaxial layer; A polyimide passivation layer is prepared on the dielectric passivation layer.

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