Clock and Data Recovery Circuit and Its Signal Processing Method

Abstract

The present invention provides a clock and data recovery (CDR) circuit and a signal processing method thereof. The clock and data recovery circuit includes a first phase detector, a controller, and a phase filter. In the operation of the CDR circuit, the first phase detector compares the phase of an input signal and the phase of a clock signal to generate a first phase detection result. The controller generates a control signal according to the first phase detection result. The phase filter receives the control signal and an auxiliary signal to generate a clock signal, wherein the auxiliary signal is generated according to the first phase detection result.

Description

Technical Field

[0001] The present invention relates to a clock and data recovery (CDR) circuit, and more particularly, to a clock and data recovery circuit suitable for high-speed applications and a signal processing method thereof. Background Art

[0002] In conventional digital-based clock and data recovery (CDR) circuits, loop latency is controlled by a digital controller within the digital-based CDR. The speed of the digital controller is usually limited by conventional semiconductor processes, resulting in a relatively long loop latency for the digital-based CDR circuit. Therefore, conventional digital-based CDR circuits are not suitable for high-speed applications. Summary of the invention

[0003] Therefore, an object of the present invention is to provide a digital-based CDR circuit, which can reduce the overall loop delay time to solve the above-mentioned problems.

[0004] According to one embodiment of the present invention, a clock and data recovery (CDR) circuit is provided, and the clock and data recovery circuit includes a first phase detector, a controller and a phase filter. In the operation of the CDR, the first phase detector compares the phase of the input signal and the phase of the clock signal to generate a first phase detection result. The controller generates a control signal according to the first phase detection result. The phase filter receives the control signal and an auxiliary signal to generate a clock signal, wherein the auxiliary signal is generated according to the first phase detection result.

[0005] According to another embodiment of the present invention, a signal processing method for a clock and data recovery circuit is provided, comprising: comparing the phase of an input signal and the phase of a clock signal to generate a phase detection result; generating a low-frequency control signal through a controller according to the phase detection result, wherein the control signal includes frequency and phase information; generating a high-frequency auxiliary signal according to the phase detection result, wherein the auxiliary signal includes phase information; and using a phase filter to receive the control signal and the auxiliary signal to generate the clock signal, wherein the phase filter has a first path and a second path, the first path is used to receive the control signal to generate the clock signal, and the second path uses the auxiliary signal to adjust the phase of the clock signal to reduce the overall delay of the CDR circuit.

[0006] In the CDR circuit of the present invention, the total delay time of the CDR circuit can be effectively reduced through the auxiliary signal in the second path, thereby improving the performance of the CDR circuit.

[0007] These and other objects of the present invention will no doubt become apparent to those skilled in the art after reading the following detailed description of the preferred embodiments illustrated in the various drawings and figures. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Various embodiments of the present invention, presented as examples, will be described in detail with reference to the following drawings, in which like reference numerals represent like elements, and:

[0009] Figure 1 is a schematic diagram showing a CDR circuit according to a first embodiment of the present invention.

[0010] Figure 2 is a schematic diagram showing a CDR circuit according to a second embodiment of the present invention.

[0011] Figure 3 is a schematic diagram showing a CDR circuit according to a third embodiment of the present invention.

[0012] Figure 4 A flow chart of a signal processing method of a CDR circuit according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0013] Certain words are used in the specification and claims to refer to specific components. It should be understood by those skilled in the art that electronic equipment manufacturers may use different terms to refer to the same component. The specification and claims do not distinguish components by differences in name, but by differences in the functions of the components. The term "including" mentioned throughout the specification and claims is an open-ended term and should be interpreted as "including but not limited to". In addition, the term "coupled" is used herein to include any direct and indirect electrical connection means. Therefore, if the text describes a first device as being electrically connected to a second device, it means that the first device can be directly connected to the second device, or indirectly connected to the second device through other devices or connection means.

[0014] Figure 1 1 is a schematic diagram showing a CDR circuit 100 according to a first embodiment of the present invention. Figure 1 As shown, the CDR circuit 100 includes a phase detector 110, a controller 120, and a phase filter 130, wherein the phase filter 130 includes a phase interpolator 132, a phase detector 134, a loop filter 136, and an oscillator 138. In addition, the phase detector 134 in the phase filter 130 can be replaced by a phase and frequency detector.

[0015] In the operation of the CDR circuit 100, the phase detector 110 receives the input signal (input serial data) Din and the clock signal CLK to generate a phase detection result V_pd1, wherein the phase detection result V_pd1 indicates the phase information of the input signal Din and the clock signal CLK, that is, the clock signal CLK is phase-lead (phase-lead) or phase-lag (phase-lag) relative to the input signal Din and / or the phase difference information of the two. Then, the controller 120 implemented by the digital circuit receives the phase detection result V_pd1 and generates a control signal Vc1, thereby controlling the phase interpolator 132 to adjust the phase of the clock signal CLK to generate a phase-shifted (phase-shifted) clock signal CLK'. Among them, the controller 120 can be a digital filter for filtering the phase detection result V_pd1 in frequency. In this embodiment, the control signal Vc1 is a digital code generated based on the phase information of the input signal Din and the clock signal CLK, and the phase interpolator 132 uses the control signal Vc1 to compensate for the phase error of the clock signal CLK to generate a phase-shifted clock signal CLK'. Then, the phase detector 134 compares the phase of the phase-shifted clock signal CLK' with the phase of the reference clock signal CLK_REF to generate a phase detection result V_pd2, wherein the phase detection result V_pd2 indicates the phase information (phase difference information) of the phase-shifted clock signal CLK' and the reference clock signal CLK_REF. The loop filter 136 receives the phase detection result V_pd2 to generate a filtered signal Vc2. Finally, the oscillator 138 receives the filtered signal Vc2 and generates a clock signal CLK as an output clock signal of the CDR circuit 100.

[0016] The above operations of the phase detector 110, the controller 120, the phase interpolator 132, the phase detector 134, the loop filter 136 and the oscillator 138 can be regarded as the first path of the CDR circuit 100. Since the speed of the controller 120 is usually limited by the semiconductor process, the first path has a longer loop delay, which deteriorates the performance of the CDR circuit 100. Specifically, since the operating frequency of the controller 120 in the first path is relatively low, the phase detection result V_pd1 and the control signal Vc1 are both low-speed signals with a relatively slow frequency, and the control signal Vc1 contains both frequency and phase information. In order to solve the problem of the longer loop delay of the first path, the phase detector 110 further generates an auxiliary signal V_aux to the oscillator 138, so that the oscillator 138 generates a clock signal CLK based on both the filter signal Vc2 and the auxiliary signal V_aux to reduce the total delay time of the CDR circuit 100. In detail, the auxiliary signal V_aux can be a pulse signal indicating the phase information of the input signal Din and the clock signal CLK (for example, the auxiliary signal V_aux can be generated based on the phase detection result V_pd1), and the auxiliary signal V_aux can be a high-speed signal with a faster frequency, which only contains phase information. The oscillator 138 can simultaneously refer to both the auxiliary signal V_aux and the filtered signal Vc2 to determine the frequency of the clock signal CLK (that is, both the auxiliary signal V_aux and the filtered signal Vc2 can control / adjust the frequency of the clock signal CLK).

[0017] exist Figure 1 In the illustrated embodiment, the phase detector 110 and the oscillator 138 further form a second path, which uses the auxiliary signal V_aux to adjust the phase of the clock signal CLK. Therefore, since the delay time of the second path is much smaller without passing through the controller, the loop delay time of the first path and the total delay time of the CDR circuit 100 can be effectively reduced, thereby improving the performance of the CDR circuit 100.

[0018] Figure 2 2 is a schematic diagram showing a CDR circuit 200 according to a second embodiment of the present invention. Figure 2 As shown, the CDR circuit 200 includes a phase detector 210, a controller 220, a phase filter 230, and a phase interpolator 240, wherein the phase filter 230 includes a phase interpolator 232, a phase detector 234, a loop filter 236, and an oscillator 238. In addition, the phase detector 234 in the phase filter 230 can be replaced by a phase and frequency detector.

[0019] In the operation of the CDR circuit 200, the phase detector 210 receives the input signal Din and the clock signal CLK to generate a phase detection result V_pd1, wherein the phase detection result V_pd1 indicates the phase information of the input signal Din and the clock signal CLK, that is, whether the clock signal CLK is phase-lead or phase-lag relative to the input signal Din and / or the phase difference information of the two. Then, the controller 220 implemented by the digital circuit receives the phase detection result V_pd1 and generates a control signal Vc1, thereby controlling the phase interpolator 232 to adjust the phase of the clock signal CLK to generate a phase-shifted clock signal CLK'. In this embodiment, the control signal Vc1 is a digital code generated based on the phase information of the input signal Din and the clock signal CLK, and the phase interpolator 232 uses the control signal Vc1 to compensate for the phase error of the clock signal CLK to generate a phase-shifted clock signal CLK'. The control signal Vc1 is a low-speed signal with a slower frequency, and the control signal Vc1 contains both frequency and phase information. In addition, the phase detector 210 also generates a phase control signal Vc3 to control the phase interpolator 240 to adjust the phase of the reference clock signal, thereby generating a phase-shifted reference clock signal as an auxiliary signal V_aux, wherein the phase control signal Vc3 can be generated according to the phase information of the input signal Din and the clock signal CLK (for example, the phase control signal Vc3 can be generated based on the phase detection result V_pd1). The phase control signal Vc3 can be a high-speed signal with a faster frequency, which only contains phase information. Then, the phase detector 234 compares the phase of the phase-shifted clock signal CLK' with the phase of the auxiliary signal V_aux to generate a phase detection result V_pd2, wherein the phase detection result V_pd2 indicates the phase information (phase difference information) of the phase-shifted clock signal CLK' and the auxiliary signal V_aux. The loop filter 236 receives the phase detection result V_pd2 to generate a filtered signal Vc2. Finally, the oscillator 238 receives the filtered signal Vc2 and generates a clock signal CLK as an output clock signal of the CDR circuit 200 .

[0020] The above operations of the phase detector 210, the controller 220, the phase interpolator 232, the phase detector 234, the loop filter 236, and the oscillator 238 can be regarded as the first path of the CDR circuit 200. Since the speed of the controller 220 is usually limited by the semiconductor process, the first path has a longer loop delay time, which deteriorates the performance of the CDR circuit 200. To solve the problem of the longer loop delay time of the first path, the phase detector 210, the phase interpolator 240, the phase detector 234, the loop filter 236, and the oscillator 238 form the second path of the CDR circuit 200. Figure 2 As shown, because the second path can be regarded as using the auxiliary signal V_aux to adjust the phase of the clock signal CLK, and the second path has a smaller delay time, the loop delay time of the first path and the total delay time of the CDR circuit 200 can be effectively reduced, and thus the performance of the CDR circuit 200 can be improved.

[0021] Figure 3 is a schematic diagram showing a CDR circuit 300 according to a third embodiment of the present invention. Figure 3 As shown, the CDR circuit 300 includes a phase detector 310, a controller 320, and a phase filter 330, wherein the phase filter 330 includes a phase interpolator 332, a phase detector 334, a loop filter 336, an oscillator 338, and a phase interpolator 339. In addition, the phase detector 334 in the phase filter 330 can be replaced by a phase and frequency detector.

[0022] In the operation of the CDR circuit 300, the phase detector 310 receives the input signal Din and the clock signal CLK' to generate a phase detection result V_pd1, wherein the phase detection result V_pd1 indicates the phase information of the input signal Din and the clock signal CLK', that is, whether the clock signal CLK' is phase-leading (phase-lead) or phase-lag (phase-lag) relative to the input signal Din and / or the phase difference information of the two. Then, the controller 320 implemented by a digital circuit receives the phase detection result V_pd1 and generates a control signal Vc1, thereby controlling the phase interpolator 332 to adjust the phase of the clock signal CLK to generate a phase-shifted clock signal CLK'. In this embodiment, the control signal Vc1 is a digital code (digital code) generated based on the phase information of the input signal Din and the clock signal CLK. code), and the phase interpolator 332 uses the control signal Vc1 to compensate for the phase error of the clock signal CLK to generate a phase-shifted clock signal CLK'. The control signal Vc1 is a low-speed signal with a slower frequency, and the control signal Vc1 contains both frequency and phase information. Then, the phase detector 334 compares the phase of the phase-shifted clock signal CLK' with the phase of the reference clock signal REF_CLK to generate a phase detection result V_pd2, wherein the phase detection result V_pd2 indicates the phase information (phase difference information) of the phase-shifted clock signal CLK' and the reference clock signal REF_CLK. The loop filter 336 receives the phase detection result V_pd2 to generate a filtered signal Vc2. The oscillator 338 receives the filtered signal Vc2 and generates a clock signal CLK as the output clock signal of the CDR circuit 300.

[0023] In addition, the phase detector 310 also generates an auxiliary signal V_aux to control the phase interpolator 339 to adjust the phase of the clock signal CLK, thereby generating a clock signal CLK", wherein the auxiliary signal V_aux can be generated based on the phase information of the input signal Din and the clock signal CLK" (for example, the auxiliary signal V_aux can be generated based on the phase detection result V_pd1). The auxiliary signal V_aux can be a high-speed signal with a faster frequency, which only contains phase information.

[0024] The above operations of the phase detector 310, the controller 320, the phase interpolator 332, the phase detector 334, the loop filter 336, the oscillator 338, and the phase interpolator 339 can be regarded as the first path of the CDR circuit 300. Since the speed of the controller 320 is usually limited by the semiconductor process, the first path has a longer loop delay time, which deteriorates the performance of the CDR circuit 300. To solve the problem of the longer loop delay time of the first path, the phase detector 310 and the phase interpolator 339 form the second path of the CDR circuit 300. Figure 3 In the illustrated embodiment, because the second path can be regarded as using the auxiliary signal V_aux to adjust the phase of the clock signal CLK, and the second path has a smaller delay time, the loop delay time of the first path and the overall delay time of the CDR circuit 200 can be effectively reduced, and thus the performance of the CDR circuit 300 can be improved.

[0025] Figure 4 FIG. 4 is a flow chart showing a signal processing method of a CDR circuit according to an embodiment of the present invention. Figures 1 to 3 In the above embodiment shown, the process is described as follows.

[0026] Step 400: Start.

[0027] Step 402: Compare the phase of the input signal with the phase of the clock signal to generate a phase detection result.

[0028] Step 404: Generate a low-frequency control signal through a controller according to the phase detection result, wherein the control signal includes frequency and phase information.

[0029] Step 406: Generate a high-frequency auxiliary signal including only phase information according to the phase detection result without passing through the controller.

[0030] Step 408: Use a phase filter to receive the control signal and the auxiliary signal to generate a clock signal, wherein the phase filter has a first path for receiving the control signal and generating the clock signal, and the phase filter also has a second path for using the auxiliary signal to reduce the total delay time of the CDR circuit.

[0031] In short, in the CDR circuit of the present invention, the CDR circuit has a first path and a second path, wherein the first path is a conventional loop with a higher delay time, and the second path has a smaller delay time so that the total delay time of the CDR circuit is effectively reduced. Therefore, the performance of the CDR can be improved.

[0032] Those skilled in the art will readily recognize that various modifications and variations can be made to the apparatus and method while maintaining the teachings of the present invention. Therefore, the above disclosure should be interpreted as being limited only by the appended claims.

Claims

1. A clock and data recovery (CDR) circuit, comprising: a first phase detector for comparing the phase of an input signal and the phase of a clock signal to generate a first phase detection result; a controller coupled to the first phase detector for generating a control signal according to the first phase detection result; and a phase filter coupled to the controller for receiving the control signal and an auxiliary signal to generate the clock signal, wherein the auxiliary signal is generated according to the first phase detection result; wherein the phase filter includes: a first phase interpolator for adjusting the phase of the clock signal with reference to the control signal to generate a phase-shifted clock signal; a second phase detector coupled to the first phase interpolator for comparing the phase of the phase-shifted clock signal and the phase of the auxiliary signal to generate a second phase detection result; a loop filter coupled to the second phase detector for receiving the second phase detection result to generate a filtered signal; and an oscillator coupled to the loop filter for receiving the filtered signal to generate the clock signal.

2. The CDR circuit according to claim 1, further comprising: a second phase interpolator coupled to the first phase detector and the phase filter for adjusting the phase of a reference clock signal with a phase control signal generated based on the first phase detection result to generate a phase-shifted reference clock signal as the auxiliary signal.

3. A clock and data recovery (CDR) circuit, comprising: a first phase detector for comparing the phase of an input signal and the phase of a clock signal to generate a first phase detection result; a controller coupled to the first phase detector for generating a control signal according to the first phase detection result; and a phase filter coupled to the controller for receiving the control signal and an auxiliary signal to generate the clock signal, wherein the auxiliary signal is generated according to the first phase detection result; wherein the phase filter includes: a first phase interpolator for adjusting the phase of an intermediate clock signal with reference to the control signal to generate a phase-shifted clock signal; a second phase detector coupled to the first phase interpolator for comparing the phase of the phase-shifted clock signal and the phase of a reference clock signal to generate a second phase detection result; a loop filter coupled to the second phase detector for receiving the second phase detection result to generate a filtered signal; an oscillator coupled to the loop filter for receiving the filtered signal to generate the intermediate clock signal; and a second phase interpolator coupled to the oscillator and the first phase detector for adjusting the phase of the intermediate clock signal with reference to the auxiliary signal to generate the clock signal.

4. The CDR circuit according to claim 3, wherein the auxiliary signal is generated by the first phase detector, the auxiliary signal contains phase difference information of the input signal and the clock signal, and the frequency of the auxiliary signal is higher than the frequency of the control signal.

5. A signal processing method for a clock and data recovery circuit, comprising: Compare the phases of the input signal and the clock signal to generate a phase detection result; Generate a low-frequency control signal through a controller according to the phase detection result, where the control signal includes frequency and phase information; A first phase detector generates a high-frequency auxiliary signal according to the phase detection result, where the auxiliary signal includes phase information; And Use a phase filter to receive the control signal and the auxiliary signal to generate the clock signal, where the phase filter includes: A first phase interpolator for adjusting the phase of the clock signal with reference to the control signal to generate a phase-shifted clock signal; A second phase detector coupled to the first phase interpolator for comparing the phase of the phase-shifted clock signal and the phase of the auxiliary signal to generate a second phase detection result; A loop filter coupled to the second phase detector for receiving the second phase detection result to generate a filtered signal; and An oscillator coupled to the loop filter for receiving the filtered signal to generate the clock signal; Alternatively, the phase filter includes: A first phase interpolator for adjusting the phase of an intermediate clock signal with reference to the control signal to generate a phase-shifted clock signal; A second phase detector coupled to the first phase interpolator for comparing the phase of the phase-shifted clock signal and the phase of a reference clock signal to generate a second phase detection result; A loop filter coupled to the second phase detector for receiving the second phase detection result to generate a filtered signal; An oscillator coupled to the loop filter for receiving the filtered signal to generate the intermediate clock signal; and A second phase interpolator coupled to the oscillator and the first phase detector for adjusting the phase of the intermediate clock signal with reference to the auxiliary signal to generate the clock signal.

Images