Scan driver and display device including the same

Abstract

A scan driver and a display device including the scan driver are provided. The display device includes a scan driver, wherein the scan driver includes a first stage and a second stage, wherein the first stage includes a first output terminal connected to a first carry line, a second output terminal connected to a first scan line, and a third output terminal connected to a first sensing line, and the second stage includes a first input terminal connected to the first carry line, a fourth output terminal connected to a second scan line, and a fifth output terminal connected to a second sensing line. In a sensing period, during a predetermined delay period before signals with a conduction level are respectively output from the fourth output terminal and the fifth output terminal, signals with a conduction level are respectively output from the first output terminal, the second output terminal, and the third output terminal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and all benefits derived from Korean Patent Application No. 10-2020-0002219, filed on January 7, 2020, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] Exemplary embodiments of the present invention relate to a scan driver and a display device including the scan driver. Background Art

[0004] As information technology develops, the importance of display devices as a connection medium between users and information has increased. Therefore, display devices such as liquid crystal display devices, organic light emitting display devices, and plasma display devices are increasingly being used.

[0005] Each of a plurality of pixels of the display device emits light having brightness corresponding to a data voltage supplied through a data line, and the display device displays an image frame by a combination of the light emitted from the pixels.

[0006] A pixel may be connected to each data line. Therefore, a scan driver that provides a scan signal for selecting a pixel to be supplied with a data voltage among a plurality of pixels is desirable. The scan driver is constructed in the form of a shift register to sequentially provide a scan signal having a conduction level in units of scan lines.

[0007] In addition, when necessary, a scan driver is desired that selectively supplies a scan signal having an on level only to a desired scan line in order to sense mobility information or threshold voltage information of a driving transistor of a pixel. Summary of the invention

[0008] Exemplary embodiments of the present invention provide a scan driver in which discharge does not occur during a sensing period and a display device including the scan driver.

[0009] An exemplary embodiment of the present invention provides a display device driven for at least one frame including a display period and a sensing period, the display device including a pixel unit and a scan driver, wherein the pixel unit includes a plurality of pixels, and the scan driver includes a plurality of stages each connected to each of the plurality of pixels, a scan line, and a sensing line, wherein the scan driver includes a first stage and a second stage, wherein the first stage includes a first output terminal connected to a first carry line, a second output terminal connected to a first scan line, and a third output terminal connected to a first sensing line, and the second stage includes a first input terminal connected to the first carry line, a fourth output terminal connected to a second scan line, and a fifth output terminal connected to a second sensing line, wherein in the sensing period, during a predetermined delay period before signals with an on level are respectively output from the fourth output terminal and the fifth output terminal, signals with an on level are respectively output from the first output terminal, the second output terminal, and the third output terminal.

[0010] In an exemplary embodiment, the display period may be a period for reproducing an input image on a screen by supplying a data voltage to each of a plurality of pixels, and the sensing period may be a period for performing a process of inputting a black data voltage to each of a plurality of pixels, initializing the plurality of pixels, sensing the plurality of pixels, and then inputting the black data voltage to the plurality of pixels again.

[0011] In an exemplary embodiment, the predetermined delay period may be a period until a sensing period of stages arranged adjacent to each other starts after a process of inputting a black data voltage again, and may be six horizontal periods or more. One horizontal period may be defined by one frame among at least one frame.

[0012] In an exemplary embodiment, in the sensing period, the time when the signals having the on level are respectively output from the first output terminal, the second output terminal, and the third output terminal may be 20 μs before the time when the signals having the on level are respectively output from the fourth output terminal and the fifth output terminal.

[0013] In an exemplary embodiment, the second output terminal may output a signal having an on-level in response to a signal provided from a first scan clock line connected to an input terminal of the first stage, the third output terminal may output a signal having an on-level in response to a signal provided from a first sensing clock line connected to the input terminal of the first stage, the fourth output terminal may output a signal having an on-level in response to a signal provided from a second scan clock line connected to an input terminal of the second stage, and the fifth output terminal may output a signal having an on-level in response to a signal provided from a second sensing clock line connected to the input terminal of the second stage.

[0014] In an exemplary embodiment, in the sensing period, the second output terminal may output a signal having an on level at least three times before signals having an on level are output from the fourth output terminal and the fifth output terminal, respectively.

[0015] In an exemplary embodiment, in the sensing period, the on-level of the signal from the third output terminal may be maintained during a period from when the second output terminal starts to provide the signal with the on-level for the first time to when the second output terminal ends to provide the signal with the on-level for the second time.

[0016] In an exemplary embodiment, in the sensing period, the on-level of the signal from the second output terminal may be maintained for six horizontal periods or more or 20 μs or more before signals having an on-level are output from the fourth and fifth output terminals, respectively.

[0017] In an exemplary embodiment, in the sensing period, the first output terminal and the second output terminal may output a signal having an on level for the same duration.

[0018] In an exemplary embodiment, the display device may further include a sensor, wherein the sensor is connected to each of the plurality of pixels through a receiving line, and the sensor measures degradation information of the plurality of pixels according to a received current or voltage.

[0019] In an exemplary embodiment, the degradation information may include mobility information of the driving transistor, threshold voltage information of the driving transistor, and degradation information of the light emitting device.

[0020] In an exemplary embodiment, each of the plurality of pixels may include a first transistor, a second transistor, a third transistor, and a light emitting device, wherein the first transistor includes a first gate electrode connected to a first node, a first electrode connected to a first power line, and a second electrode connected to a second node, the second transistor includes a second gate electrode connected to a scan line, a third electrode connected to a data line, and a fourth electrode connected to the first node, the third transistor includes a third gate electrode connected to a sensing line, a fifth electrode connected to a receiving line, and a sixth electrode connected to the second node, and the light emitting device includes an anode connected to the second node and a cathode connected to the second power line.

[0021] In an exemplary embodiment, the pixel unit may include a display substrate, a plurality of transistors arranged on the display substrate, a plurality of organic light emitting diodes arranged on the plurality of transistors, a wavelength conversion pattern arranged on the plurality of organic light emitting diodes, and a color filter arranged on the wavelength conversion pattern.

[0022] In example embodiments, the wavelength conversion pattern may include quantum dots.

[0023] In an exemplary embodiment, the scan driver may be arranged as an oxide semiconductor thin film transistor gate (OSG) driver circuit at one side of the pixel unit.

[0024] In an exemplary embodiment, in the sensing period, the time when the off-level of the signals output from the fourth output terminal and the fifth output terminal respectively changes to the on-level coincides with the time when the on-level of the signals output from the first output terminal, the second output terminal and the third output terminal respectively changes to the off-level.

[0025] In an exemplary embodiment, the first stage may be arranged on the Nth row, and the second stage may be arranged on the N+2th row.

[0026] In an exemplary embodiment, each of the first stage and the second stage may include an input terminal connected to the first power line, the second power line, and the third power line.

[0027] In an exemplary embodiment, each of the first stage and the second stage may include a P-type transistor.

[0028] An exemplary embodiment of the present invention provides a scan driver for driving at least one frame including a display period and a sensing period, the scan driver including a first stage and a second stage, wherein the first stage includes a first output terminal connected to a first carry line, a second output terminal connected to a first scan line, and a third output terminal connected to a first sensing line, and the second stage includes a first input terminal connected to the first carry line, a fourth output terminal connected to a second scan line, and a fifth output terminal connected to a second sensing line, wherein in the sensing period, before a predetermined delay period before signals with a turn-on level are respectively output from the fourth output terminal and the fifth output terminal, signals with a turn-on level are respectively output from the first output terminal, the second output terminal, and the third output terminal, wherein the predetermined delay period is equal to or less than 20 μs. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Exemplary embodiments will now be described more fully below with reference to the accompanying drawings; however, the present invention may be implemented in different forms and should not be construed as limited to the exemplary embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the exemplary embodiments to those skilled in the art.

[0030] Figure 1 is a schematic block diagram showing an exemplary embodiment of a display device according to the present invention.

[0031] Figure 2is a diagram showing an exemplary embodiment of a scan driver according to the present invention.

[0032] Figure 3 is schematically shown connected to Figure 2 A diagram of the terminals of one stage is shown in FIG.

[0033] Figure 4 is a circuit diagram showing an exemplary embodiment of a stage group according to the present invention.

[0034] Figure 5 and Figure 6 is a timing diagram illustrating an exemplary driving method of the scan driver in a display period.

[0035] Figure 7 is an equivalent circuit diagram showing an exemplary embodiment of a pixel according to the present invention.

[0036] Figure 8 is a timing diagram illustrating an exemplary driving method of a scan driver in a sensing period.

[0037] Fig. 9 is a schematic cross-sectional view showing an exemplary embodiment of a pixel unit according to the present invention.

[0038] Fig.10 is a timing diagram illustrating another exemplary embodiment of a driving method of a scan driver in a sensing period of a display device according to the present invention.

[0039] Fig.11 is a diagram schematically showing another exemplary embodiment of a terminal connected to one stage of a display device according to the present invention. DETAILED DESCRIPTION

[0040] By referring to the following and attached Figure 1 With the detailed description of the exemplary embodiments, the effects and features of the present invention and the methods for achieving the effects and features will be clear. However, the present invention is not limited to the exemplary embodiments disclosed herein, but can be implemented in different forms. For example, the exemplary embodiments are only provided so that those of ordinary skill in the art can fully understand the features and scope of the present invention.

[0041] The term "on" used to indicate that an element or layer is on another element or layer includes both the case where the element or layer is directly on another element or layer and the case where the element or layer is on another element or layer via yet another element or layer. Throughout the description of the present invention, the same reference numerals are used for the same elements across the various drawings.

[0042] Although the terms "first", "second" and similar words are used to describe various components, these components are not limited to these terms. These terms are only used to distinguish one component from other components. Therefore, according to the technical concept of the present invention, the first component can be the second component, or vice versa.

[0043] In the accompanying drawings, dimensions may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being "between" two elements, the element may be the only element between the two elements, or one or more intermediate elements may also be present. Throughout the specification, similar reference numerals indicate similar elements.

[0044] As used herein, "about" or "approximately" includes stated values ​​and means within an acceptable range of deviation for a particular value as determined by one of ordinary skill in the art, taking into account the errors associated with the measurements and the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, 20%, 10%, 5% of the stated value.

[0045] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. It will also be understood that, unless explicitly defined as such herein, terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and the present invention, and will not be interpreted in an idealized or overly formal sense.

[0046] Exemplary embodiments are described herein with reference to schematically illustrated cross-sectional illustrations as idealized embodiments. As such, variations in the shapes of the illustrations resulting from, for example, manufacturing techniques and / or tolerances will be expected. Therefore, the embodiments described herein should not be construed as being limited to the specific shapes of the zones as shown herein, but rather include deviations in shape resulting from, for example, manufacturing. In exemplary embodiments, zones shown or described as flat may typically have rough and / or nonlinear features. In addition, the sharp corners shown may be rounded. Therefore, the zones shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the zones, and are not intended to limit the scope of the claims.

[0047] Hereinafter, exemplary embodiments will be described with reference to the accompanying drawings. Throughout the drawings, the same reference numerals are assigned to the same elements.

[0048] Figure 1 is a schematic block diagram showing an exemplary embodiment of a display device 10 according to the present invention.

[0049] Reference Figure 1 The display device 10 in the exemplary embodiment of the present invention may include a timing controller 11 , a data driver 12 , a scan driver 13 , a sensor 14 , and a pixel unit 15 .

[0050] The timing controller 11 may provide a grayscale value of each frame, a control signal, and the like to the data driver 12. Also, the timing controller 11 may provide a clock signal, a control signal, and the like to each of the scan driver 13 and the sensor 14.

[0051] The data driver 12 may generate data voltages to be supplied to the plurality of data lines D1, D2, D3, ... and Dq by grayscale values, control signals, and the like received from the timing controller 11. In an exemplary embodiment, for example, the data driver 12 may sample grayscale values ​​by a clock signal, and apply data voltages corresponding to grayscale values ​​to the plurality of data lines D1 to Dq in units of pixel rows (e.g., pixels connected to the same scan line). Here, q may be a natural number.

[0052] The scan driver 13 may generate scan signals to be provided to the plurality of scan lines SC1, SC2, ... and SCp by receiving a clock signal, a control signal and the like from the timing controller 11. In an exemplary embodiment, for example, the scan driver 13 may sequentially provide scan signals having pulses of an on level to the plurality of scan lines SC1 to SCp. In an exemplary embodiment, for example, the scan driver 13 may generate scan signals in a manner of sequentially transmitting pulses of an on level to the next scan level in response to the clock signal. Here, p may be a natural number. In an exemplary embodiment, for example, the scan driver 13 may be constructed in the form of a shift register.

[0053] Also, the scan driver 13 may generate a sensing signal to be supplied to the plurality of sensing lines SS1, SS2, ... and SSp. In an exemplary embodiment, for example, the scan driver 13 may sequentially supply a sensing signal having a pulse of an on level to the plurality of sensing lines SS1 to SSp. In an exemplary embodiment, for example, the scan driver 13 may generate a sensing signal in a manner of sequentially transmitting a pulse of an on level to a next stage in response to a clock signal.

[0054] However, the operation of the scan driver 13 is different from Figure 5 is related to the operation during the display period shown in , and Figure 8 The operations in the sensing period shown in will be described separately.

[0055] In an exemplary embodiment, for example, the display device 10 may be driven during a plurality of frames each including a display period and a sensing period. The display period corresponds to a period for reproducing an input image on a screen by supplying a data voltage to each pixel PXij. The sensing period corresponds to a period for performing the following processes: inputting a black data voltage to each pixel PXij, initializing the pixel PXij, sensing the pixel PXij, and then inputting the black data voltage to the pixel PXij again. The sensing period may be a period for performing external compensation.

[0056] In an exemplary embodiment, the scan driver 13 may be provided synchronously with the pixel PXij through a thin film process. The scan driver 13 may be arranged (e.g., installed) as an oxide semiconductor thin film transistor gate (OSG) driver circuit at one side of the pixel unit 15. The scan driver 13 may include a driver chip (not shown) and a flexible circuit board (not shown) on which the driver chip is arranged (e.g., installed). In another exemplary embodiment, the scan driver 13 may be arranged in a non-display area of ​​the display device 10 in a chip on glass (Chip On Glass, COG) manner.

[0057] The sensor 14 may measure the degradation information of the pixel PXij according to the current or voltage received through the plurality of receiving lines R1, R2, R3, ... and Rq. In an exemplary embodiment, for example, the degradation information of the pixel PXij may be mobility information of the driving transistor, threshold voltage information of the driving transistor, degradation information of the light-emitting device, etc. In addition, the sensor 14 may measure the characteristic information of the pixel PXij that changes depending on the environment according to the current or voltage received through the plurality of receiving lines R1 to Rq. In an exemplary embodiment, for example, the sensor 14 may measure the characteristic information of the pixel PXij that changes depending on the temperature or humidity.

[0058] The pixel unit 15 includes a plurality of pixels PXij. Each pixel PXij may be connected to a corresponding data line, a corresponding scan line, a corresponding sensing line, and a corresponding receiving line. Here, i may be a natural number equal to or less than p, and j may be a natural number equal to or less than q. In an exemplary embodiment, for example, the pixel PXij may mean a pixel circuit including a scan transistor connected to the i-th scan line and the j-th data line. The driving transistor of each pixel PXij (refer to Figure 7 The threshold voltage of M1 in FIG. 1 can be compensated by using an external compensation method, and the mobility deviation of the driving transistor can be compensated by using an internal compensation method.

[0059] Figure 2 is a diagram showing an exemplary embodiment of the scan driver 13 according to the present invention.

[0060] Reference Figure 2 , the scan driver 13 may include a plurality of stage groups STG(n-2), STG(n-1), STGn, STG(n+1) and STG(n+2). Figure 2 Only a portion of the scan driver 13 necessary for the description is shown.

[0061] Each of the plurality of stage groups STG(n-2), STG(n-1), STGn, STG(n+1), and STG(n+2) may include a first stage and a second stage. In an exemplary embodiment, the first stage may be an odd-numbered stage, and the second stage may be an even-numbered stage. In another exemplary embodiment, the first stage may be an even-numbered stage, and the second stage may be an odd-numbered stage. In an exemplary embodiment, for example, the stage group STG(n-2) may include a first stage ST(2n-5) and a second stage ST(2n-4), the stage group STG(n-1) may include a first stage ST(2n-3) and a second stage ST(2n-2), the stage group STGn may include a first stage ST(2n-1) and a second stage ST2n, the stage group STG(n+1) may include a first stage ST(2n+1) and a second stage ST(2n+2), and the stage group STG(n+2) may include a first stage ST(2n+3) and a second stage ST(2n+4). Here, n may be a natural number greater than 2.

[0062] Each of the plurality of stages ST(2n-5) to ST(2n+4) may be connected to a first control line CS1, a second control line CS2, a third control line CS3, a fourth control line CS4, a fifth control line CS5, and a sixth control line CS6. A common control signal may be applied to the plurality of stages ST(2n-5) to ST(2n+4) through the first control line CS1, the second control line CS2, the third control line CS3, the fourth control line CS4, the fifth control line CS5, and the sixth control line CS6.

[0063] Each of the multiple stages ST(2n-5) to ST(2n+4) can be connected to a corresponding clock line among multiple scan clock lines SCCK1, SCCK2, SCCK3, SCCK4, SCCK5 and SCCK6, multiple sense clock lines SSCK1, SSCK2, SSCK3, SSCK4, SSCK5 and SSCK6, and multiple carry clock lines CRCK1, CRCK2, CRCK3, CRCK4, CRCK5 and CRCK6.

[0064] In an exemplary embodiment, the first stage (hereinafter also referred to as a "scanning stage") ST (2n-5) may be connected to the scan clock line SCCK1, the sense clock line SSCK1, and the carry clock line CRCK1, and the second stage ST (2n-4) may be connected to the scan clock line SCCK2, the sense clock line SSCK2, and the carry clock line CRCK2. For example, the first stage ST (2n-3) may be connected to the scan clock line SCCK3, the sense clock line SSCK3, and the carry clock line CRCK3, and the second stage ST (2n-2) may be connected to the scan clock line SCCK4, the sense clock line SSCK4, and the carry clock line CRCK4. The first stage ST (2n-1) may be connected to the scan clock line SCCK5, the sense clock line SSCK5, and the carry clock line CRCK5, and the second stage ST2n may be connected to the scan clock line SCCK6, the sense clock line SSCK6, and the carry clock line CRCK6.

[0065] In addition, iteratively, the first stage ST (2n + 1) can be connected to the scan clock line SCCK1, the sense clock line SSCK1 and the carry clock line CRCK1, and the second stage ST (2n + 2) can be connected to the scan clock line SCCK2, the sense clock line SSCK2 and the carry clock line CRCK2. The first stage ST (2n + 3) can be connected to the scan clock line SCCK3, the sense clock line SSCK3 and the carry clock line CRCK3, and the second stage ST (2n + 4) can be connected to the scan clock line SCCK4, the sense clock line SSCK4 and the carry clock line CRCK4.

[0066] Input signals for the respective scan stages ST(2n-5) to ST(2n+4) are applied to the first to sixth control lines CS1 to CS6, a plurality of scan clock lines SCCK1 to SCCK6, a plurality of sense clock lines SSCK1 to SSCK6, and a plurality of carry clock lines CRCK1 to CRCK6.

[0067] Each of the plurality of scan stages ST(2n-5) to ST(2n+4) can be connected to a corresponding line among the plurality of scan lines SC(2n-5) to SC(2n+4), the plurality of sense lines SS(2n-5) to SS(2n+4), and the plurality of carry lines CR(2n-5) to CR(2n+4).

[0068] In an exemplary embodiment, for example, the first stage ST(2n-5) may be connected to the scan line SC(2n-5), the sense line SS(2n-5), and the carry line CR(2n-5), and the second stage ST(2n-4) may be connected to the scan line SC(2n-4), the sense line SS(2n-4), and the carry line CR(2n-4). The first stage ST(2n-3) may be connected to the scan line SC(2n-3), the sense line SS(2n-3), and the carry line CR(2n-3), and the second stage ST(2n-2) may be connected to the scan line SC(2n-2), the sense line SS(2n-2), and the carry line CR(2n-2).

[0069] The output signals generated by the corresponding plurality of scan stages ST(2n-5) to ST(2n+4) are applied to a plurality of scan lines SC(2n-5) to SC(2n+4), a plurality of sense lines SS(2n-5) to SS(2n+4), and a plurality of carry lines CR(2n-5) to CR(2n+4).

[0070] Figure 3 is schematically shown connected to Figure 2 A diagram of the terminals of a stage is shown in FIG. Figure 3 , for convenience of description, the N-th stage ST(N) arranged on the N-th row is shown. Here, N is a natural number greater than 2 and less than or equal to p.

[0071] Reference Figure 3 The Nth stage ST(N) may include input terminals respectively connected to the carry line CR(N-2), the scan clock line SCCK(N), the sense clock line SSCK(N) and the carry clock line CRCK(N), include output terminals respectively connected to the carry line CR(N), the scan line SC(N) and the sense line SS(N), and also include an input terminal connected to the power line VSS.

[0072] In some exemplary embodiments, the input terminal connected to the power line VSS may include input terminals respectively connected to a plurality of power lines. In an exemplary embodiment, for example, the input terminals respectively connected to the plurality of power lines may be input terminals respectively connected to the first power line VSS1, the second power line VSS2 (refer to Figure 4 ) and the third power supply line VSS3 (refer to Figure 4 ) are connected to the input terminals, which will be described later. Hereinafter, the case where the Nth stage ST(N) includes input terminals connected to the first power line VSS1, the second power line VSS2 and the third power line VSS3 is taken as an example for explanation.

[0073] In an exemplary embodiment, the carry signal output to the output terminal connected to the carry line CR(N) of the Nth stage ST(N) may be provided to the input terminal of the N+2th stage. That is, the carry signal provided to the input terminal connected to the carry line CR(N-2) of the Nth stage ST(N) may be a signal provided from the output terminal of the N-2th stage. However, the number of the next stage to which the carry signal is transmitted is not limited.

[0074] Figure 4 is a circuit diagram showing an exemplary embodiment of a stage group STGn according to the present invention. Figure 4 The circuit diagram of each stage shown in Figure 3 The drawings shown in FIG. 1 are exemplary circuit diagrams that can be applied, and another level of circuit diagram known in the art is an exemplary circuit diagram that can be applied.

[0075] Reference Figure 4 , exemplarily showing a stage group STGn including a first stage ST(2n-1) and a second stage ST2n. Figure 2 The other stage groups shown in FIG. 1 can be configured as Figure 4 The stage groups STGn shown in FIG. 1 are substantially the same, and therefore, repeated descriptions will be omitted.

[0076] exist Figure 4 In the accompanying drawings, it is assumed and described that the transistor is implemented with an N-type transistor (for example, an n-type metal oxide semiconductor (N-TypeMetal-Oxide-Semiconductor, NMOS) transistor), but those skilled in the art can implement the stage group STGn by replacing some or all of the multiple transistors with a P-type transistor (for example, a p-type metal oxide semiconductor (P-TypeMetal-Oxide-Semiconductor, PMOS) transistor).

[0077] A first electrode of the first transistor T1 may be connected to the scan line SC(2n-1), a second electrode of the first transistor T1 may be connected to the scan clock line SCCK5, and a gate electrode of the first transistor T1 may be connected to the third node N3.

[0078] A first electrode of the second transistor T2 may be connected to the sensing line SS(2n-1), a second electrode of the second transistor T2 may be connected to the sensing clock line SSCK5, and a gate electrode of the second transistor T2 may be connected to the third node N3.

[0079] A first electrode of the third transistor T3 may be connected to the sensing line SS2n, a second electrode of the third transistor T3 may be connected to the sensing clock line SSCK6, and a gate electrode of the third transistor T3 may be connected to the fourth node N4.

[0080] A first electrode of the fourth transistor T4 may be connected to the scan line SC2n, a second electrode of the fourth transistor T4 may be connected to the scan clock line SCCK6, and a gate electrode of the fourth transistor T4 may be connected to the fourth node N4.

[0081] A first electrode of the fifth transistor T5 may be connected to the first power line VSS1 , a second electrode of the fifth transistor T5 may be connected to the first electrode of the first transistor T1 , and a gate electrode of the fifth transistor T5 may be connected to the first node N1 .

[0082] A first electrode of the sixth transistor T6 may be connected to the first power line VSS1 , a second electrode of the sixth transistor T6 may be connected to the first electrode of the third transistor T3 , and a gate electrode of the sixth transistor T6 may be connected to the first node N1 .

[0083] A first electrode of the seventh transistor T7 may be connected to the first power line VSS1 , a second electrode of the seventh transistor T7 may be connected to the first transistor T1 , and a gate electrode of the seventh transistor T7 may be connected to the second node N2 .

[0084] A first electrode of the eighth transistor T8 may be connected to the first power line VSS1 , a second electrode of the eighth transistor T8 may be connected to the first electrode of the third transistor T3 , and a gate electrode of the eighth transistor T8 may be connected to the second node N2 .

[0085] A first electrode of the ninth transistor T9 may be connected to the first power line VSS1 , a second electrode of the ninth transistor T9 may be connected to the first electrode of the second transistor T2 , and a gate electrode of the ninth transistor T9 may be connected to the first node N1 .

[0086] A first electrode of the tenth transistor T10 may be connected to the first power line VSS1 , a second electrode of the tenth transistor T10 may be connected to the first electrode of the fourth transistor T4 , and a gate electrode of the tenth transistor T10 may be connected to the first node N1 .

[0087] A first electrode of the eleventh transistor T11 may be connected to the first power line VSS1 , a second electrode of the eleventh transistor T11 may be connected to the first electrode of the second transistor T2 , and a gate electrode of the eleventh transistor T11 may be connected to the second node N2 .

[0088] A first electrode of the twelfth transistor T12 may be connected to the first power line VSS1 , a second electrode of the twelfth transistor T12 may be connected to the first electrode of the fourth transistor T4 , and a gate electrode of the twelfth transistor T12 may be connected to the second node N2 .

[0089] A first electrode of the thirteenth transistor T13 may be connected to the carry line CR(2n-1), a second electrode of the thirteenth transistor T13 may be connected to the carry clock line CRCK5, and a gate electrode of the thirteenth transistor T13 may be connected to the third node N3.

[0090] A first electrode of the fourteenth transistor T14 may be connected to the second power line VSS2 , a second electrode of the fourteenth transistor T14 may be connected to the first electrode of the thirteenth transistor T13 , and a gate electrode of the fourteenth transistor T14 may be connected to the first node N1 .

[0091] A first electrode of the fifteenth transistor T15 may be connected to the second power line VSS2 , a second electrode of the fifteenth transistor T15 may be connected to the first electrode of the thirteenth transistor T13 , and a gate electrode of the fifteenth transistor T15 may be connected to the second node N2 .

[0092] A first electrode of the sixteenth transistor T16 may be connected to the carry line CR2n, a second electrode of the sixteenth transistor T16 may be connected to the carry clock line CRCK6, and a gate electrode of the sixteenth transistor T16 may be connected to the fourth node N4.

[0093] A first electrode of the seventeenth transistor T17 may be connected to the second power line VSS2 , a second electrode of the seventeenth transistor T17 may be connected to the first electrode of the sixteenth transistor T16 , and a gate electrode of the seventeenth transistor T17 may be connected to the first node N1 .

[0094] A first electrode of the eighteenth transistor T18 may be connected to the second power line VSS2 , a second electrode of the eighteenth transistor T18 may be connected to the first electrode of the sixteenth transistor T16 , and a gate electrode of the eighteenth transistor T18 may be connected to the second node N2 .

[0095] A first electrode of the nineteenth transistor may be connected to the second power supply line VSS2, a second electrode of the nineteenth transistor may be connected to the third node N3, and a gate electrode of the nineteenth transistor may be connected to the first node N1. In some exemplary embodiments, the nineteenth transistor may include a plurality of sub-transistors T19a and T19b connected in series. An appropriate intermediate voltage is applied to the fifth node N5 so that the nineteenth transistor can prevent degradation caused by an excessive voltage difference between the drain electrode and the source electrode.

[0096] The first electrode of the twentieth transistor may be connected to the second power line VSS2, the second electrode of the twentieth transistor may be connected to the fourth node N4, and the gate electrode of the twentieth transistor may be connected to the first node N1. In some exemplary embodiments, the twentieth transistor may include a plurality of sub-transistors T20a and T20b connected in series. An appropriate intermediate voltage is applied to the sixth node N6 so that the twentieth transistor can prevent degradation caused by an excessive voltage difference between the drain electrode and the source electrode.

[0097] A first electrode of the 21st transistor T21 may be connected to the first node N1, a second electrode of the 21st transistor T21 may be connected to the second power supply line VSS2, and a gate electrode of the 21st transistor T21 may be connected to the carry line CR(2n-4). In some exemplary embodiments, the gate electrode of the 21st transistor T21 may be connected to another carry line.

[0098] The first electrode of the 22nd transistor T22 may be connected to the second node N2, the second electrode of the 22nd transistor T22 may be connected to the second power supply line VSS2, and the gate electrode of the 22nd transistor T22 may be connected to the carry line CR(2n-3). In some exemplary embodiments, the gate electrode of the 22nd transistor T22 may be connected to another carry line.

[0099] A first electrode of the 23rd transistor may be connected to the second power line VSS2, a second electrode of the 23rd transistor may be connected to the third node N3, and a gate electrode of the 23rd transistor may be connected to the second node N2. In some exemplary embodiments, the 23rd transistor may include a plurality of sub-transistors T23a and T23b ​​connected in series. An appropriate intermediate voltage is applied to the fifth node N5 so that the 23rd transistor can prevent degradation caused by an excessive voltage difference between the drain electrode and the source electrode.

[0100] The first electrode of the 24th transistor may be connected to the second power line VSS2, the second electrode of the 24th transistor may be connected to the fourth node N4, and the gate electrode of the 24th transistor may be connected to the second node N2. In some exemplary embodiments, the 24th transistor may include a plurality of sub-transistors T24a and T24b connected in series. An appropriate intermediate voltage is applied to the sixth node N6 so that the 24th transistor can prevent degradation caused by an excessive voltage difference between the drain electrode and the source electrode.

[0101] A first electrode of the twenty-fifth transistor T25 may be connected to the first node N1 , a second electrode of the twenty-fifth transistor T25 may be connected to the second power line VSS2 , and a gate electrode of the twenty-fifth transistor T25 may be connected to the third node N3 .

[0102] A first electrode of the twenty-sixth transistor T26 may be connected to the second node N2 , a second electrode of the twenty-sixth transistor T26 may be connected to the second power line VSS2 , and a gate electrode of the twenty-sixth transistor T26 may be connected to the fourth node N4 .

[0103] A first electrode of the 27th transistor T27 may be connected to the third power line VSS3 , a second electrode of the 27th transistor T27 may be connected to the gate electrode of the 31st transistor T31 , and a gate electrode of the 27th transistor T27 may be connected to the fourth node N4 .

[0104] A first electrode of the 28th transistor T28 may be connected to the third power line VSS3 , a second electrode of the 28th transistor T28 may be connected to the gate electrode of the 32nd transistor T32 , and a gate electrode of the 28th transistor T28 may be connected to the fourth node N4 .

[0105] A first electrode of the twenty-ninth transistor T29 may be connected to the third power line VSS3 , a second electrode of the twenty-ninth transistor T29 may be connected to the gate electrode of the thirty-first transistor T31 , and a gate electrode of the twenty-ninth transistor T29 may be connected to the third node N3 .

[0106] A first electrode of the thirtieth transistor T30 may be connected to the third power line VSS3 , a second electrode of the thirtieth transistor T30 may be connected to the gate electrode of the thirty-second transistor T32 , and a gate electrode of the thirtieth transistor T30 may be connected to the third node N3 .

[0107] A first electrode of the thirty-first transistor T31 may be connected to the first node N1, a second electrode of the thirty-first transistor T31 may be connected to the fifth control line CS5, and the thirty-first transistor T31 may include a gate electrode.

[0108] A first electrode of the thirty-second transistor T32 may be connected to the second node N2 , a second electrode of the thirty-second transistor T32 may be connected to the sixth control line CS6 , and the thirty-second transistor T32 may include a gate electrode.

[0109] The first electrode of the 33rd transistor may be connected to the second power supply line VSS2, the second electrode of the 33rd transistor may be connected to the third node N3, and the gate electrode of the 33rd transistor may be connected to the carry line CR(2n+3). In some exemplary embodiments, the 33rd transistor may include a plurality of sub-transistors T33a and T33b connected in series. An appropriate intermediate voltage is applied to the fifth node N5 so that the 33rd transistor can prevent degradation caused by an excessive voltage difference between the drain electrode and the source electrode. In some exemplary embodiments, the gate electrode of the 33rd transistor may be connected to another carry line.

[0110] The first electrode of the 34th transistor may be connected to the second power supply line VSS2, the second electrode of the 34th transistor may be connected to the fourth node N4, and the gate electrode of the 34th transistor may be connected to the carry line CR (2n + 3). In some exemplary embodiments, the 34th transistor may include a plurality of sub-transistors T34a and T34b connected in series. An appropriate intermediate voltage is applied to the sixth node N6 so that the 34th transistor can prevent degradation caused by an excessive voltage difference between the drain electrode and the source electrode. In some exemplary embodiments, the gate electrode of the 34th transistor may be connected to another carry line.

[0111] The first electrode of the 35th transistor may be connected to the second power supply line VSS2, the second electrode of the 35th transistor may be connected to the third node N3, and the gate electrode of the 35th transistor may be connected to the fourth control line CS4. In some exemplary embodiments, the 35th transistor may include a plurality of sub-transistors T35a and T35b connected in series. An appropriate intermediate voltage is applied to the fifth node N5 so that the 35th transistor can prevent degradation caused by an excessive voltage difference between the drain electrode and the source electrode.

[0112] A first electrode of the thirty-sixth transistor may be connected to the second power supply line VSS2, a second electrode of the thirty-sixth transistor may be connected to the fourth node N4, and a gate electrode of the thirty-sixth transistor may be connected to the fourth control line CS4. In some exemplary embodiments, the thirty-sixth transistor may include a plurality of sub-transistors T36a and T36b connected in series. An appropriate intermediate voltage is applied to the sixth node N6 so that the thirty-sixth transistor can prevent degradation caused by an excessive voltage difference between the drain electrode and the source electrode.

[0113] A first electrode of the thirty-seventh transistor T37 may be connected to the gate electrode of the thirty-first transistor T31 , and a second electrode and the gate electrode of the thirty-seventh transistor T37 may be connected to the fifth control line CS5 .

[0114] A first electrode of the thirty-eighth transistor T38 may be connected to the gate electrode of the thirty-second transistor T32 , and a second electrode and the gate electrode of the thirty-eighth transistor T38 may be connected to the sixth control line CS6 .

[0115] The first electrode of the 39th transistor may be connected to the third node N3, and the second electrode and the gate electrode of the 39th transistor may be connected to the carry line CR (2n-4). In some exemplary embodiments, the 39th transistor may include a plurality of sub-transistors T39a and T39b connected in series. An appropriate intermediate voltage is applied to the fifth node N5 so that the 39th transistor can prevent degradation caused by an excessive voltage difference between the drain electrode and the source electrode. In some exemplary embodiments, the gate electrode of the 39th transistor may be connected to another carry line.

[0116] The first electrode of the 40th transistor may be connected to the fourth node N4, and the second electrode and the gate electrode of the 40th transistor may be connected to the carry line CR (2n-3). In some exemplary embodiments, the 40th transistor may include a plurality of sub-transistors T40a and T40b connected in series. An appropriate intermediate voltage is applied to the sixth node N6 so that the 40th transistor can prevent degradation caused by an excessive voltage difference between the drain electrode and the source electrode. In some exemplary embodiments, the gate electrode of the 40th transistor may be connected to another carry line.

[0117] A first electrode of the forty-first transistor T41 may be connected to the fifth node N5 , a second electrode of the forty-first transistor T41 may be connected to the second control line CS2 , and a gate electrode of the forty-first transistor T41 may be connected to the third node N3 .

[0118] A first electrode of the 42nd transistor T42 may be connected to the sixth node N6 , a second electrode of the 42nd transistor T42 may be connected to the second control line CS2 , and a gate electrode of the 42nd transistor T42 may be connected to the fourth node N4 .

[0119] A first electrode of the forty-third transistor T43 may be connected to the first node N1, a second electrode of the forty-third transistor T43 may be connected to the first electrode of the forty-fifth transistor T45, and a gate electrode of the forty-third transistor T43 may be connected to the third control line CS3.

[0120] A first electrode of the forty-fourth transistor T44 may be connected to the second node N2 , a second electrode of the forty-fourth transistor T44 may be connected to the first electrode of the forty-sixth transistor T46 , and a gate electrode of the forty-fourth transistor T44 may be connected to the third control line CS3 .

[0121] A first electrode of the forty-fifth transistor T45 may be connected to the second electrode of the forty-third transistor T43 , a second electrode of the forty-fifth transistor T45 may be connected to the second power line VSS2 , and a gate electrode of the forty-fifth transistor T45 may be connected to the first electrode of the fifty-first transistor.

[0122] A first electrode of the forty-sixth transistor T46 may be connected to the second electrode of the forty-fourth transistor T44 , a second electrode of the forty-sixth transistor T46 may be connected to the second power line VSS2 , and a gate electrode of the forty-sixth transistor T46 may be connected to the first electrode of the fifty-second transistor.

[0123] A first electrode of the forty-seventh transistor T47 may be connected to the second electrode of the forty-eighth transistor T48, a second electrode of the forty-seventh transistor T47 may be connected to the second control line CS2, and a gate electrode of the forty-seventh transistor T47 may be connected to the first electrode of the fifty-first transistor.

[0124] A first electrode of the forty-eighth transistor T48 may be connected to the third node N3, a second electrode of the forty-eighth transistor T48 may be connected to the first electrode of the forty-seventh transistor T47, and a gate electrode of the forty-eighth transistor T48 may be connected to the third control line CS3.

[0125] A first electrode of the forty-ninth transistor T49 may be connected to the fourth node N4, a second electrode of the forty-ninth transistor T49 may be connected to the first electrode of the fiftieth transistor T50, and a gate electrode of the forty-ninth transistor T49 may be connected to the third control line CS3.

[0126] A first electrode of the 50th transistor T50 may be connected to the second electrode of the 49th transistor T49 , a second electrode of the 50th transistor T50 may be connected to the second control line CS2 , and a gate electrode of the 50th transistor T50 may be connected to the first electrode of the 52nd transistor.

[0127] The fifty-first transistor may include a first electrode, a second electrode of the fifty-first transistor may be connected to a carry line CR(2n-3), and a gate electrode of the fifty-first transistor may be connected to a first control line CS1. The fifty-first transistor may include a plurality of sub-transistors T51a and T51b connected in series. In some exemplary embodiments, the gate electrode of the fifty-first transistor may be connected to another carry line.

[0128] The 52nd transistor may include a first electrode, a second electrode of the 52nd transistor may be connected to the carry line CR(2n-3), and a gate electrode of the 52nd transistor may be connected to the first control line CS1. The 52nd transistor may include a plurality of sub-transistors T52a and T52b connected in series. In some exemplary embodiments, the gate electrode of the 52nd transistor may be connected to another carry line.

[0129] A first electrode of the fifty-third transistor T53 may be connected to the second control line CS2 , a second electrode of the fifty-third transistor T53 may be connected to the second electrode of the sub-transistor T51 b , and a gate electrode of the fifty-third transistor T53 may be connected to the first electrode of the sub-transistor T51 b .

[0130] A first electrode of the fifty-fourth transistor T54 may be connected to the second control line CS2 , a second electrode of the fifty-fourth transistor T54 may be connected to the second electrode of the sub-transistor T52 b , and a gate electrode of the fifty-fourth transistor T54 may be connected to the first electrode of the sub-transistor T52 b .

[0131] A first electrode of the first capacitor C1 may be connected to the first electrode of the first transistor T1 , and a second electrode of the first capacitor C1 may be connected to the gate electrode of the first transistor T1 .

[0132] A first electrode of the second capacitor C2 may be connected to the first electrode of the second transistor T2 , and a second electrode of the second capacitor C2 may be connected to the gate electrode of the second transistor T2 .

[0133] A first electrode of the third capacitor C3 may be connected to the first electrode of the third transistor T3 , and a second electrode of the third capacitor C3 may be connected to the gate electrode of the third transistor T3 .

[0134] A first electrode of the fourth capacitor C4 may be connected to the first electrode of the fourth transistor T4 , and a second electrode of the fourth capacitor C4 may be connected to the gate electrode of the fourth transistor T4 .

[0135] A first electrode of the fifth capacitor C5 may be connected to the gate electrode of the forty-seventh transistor T47 , and a second electrode of the fifth capacitor C5 may be connected to the second electrode of the forty-seventh transistor T47 .

[0136] A first electrode of the sixth capacitor C6 may be connected to the gate electrode of the 50th transistor T50 , and a second electrode of the sixth capacitor C6 may be connected to the second electrode of the 50th transistor T50 .

[0137] Figure 5 and Figure 6 2 is a timing chart showing an exemplary driving method of the scan driver 13 in the display period.

[0138] Reference Figure 5, shows signals applied to the first control line CS1, the fourth control line CS4, multiple scan clock lines SCCK1 to SCCK6, multiple sense clock lines SSCK1 to SSCK6, multiple carry clock lines CRCK1 to CRCK6, the first scan carry line CR(2n-4), the first sense carry line CR(2n-3), the first scan line SC(2n-1), the second scan line SC2n, the first sense line SS(2n-1), the second sense line SS2n, the first carry line CR(2n-1) and the second carry line CR2n.

[0139] In the display period, the scan clock signal, the sense clock signal, and the carry clock signal respectively applied to the scan clock line, the sense clock line, and the carry clock line connected to the same scan stage may have the same phase. Figure 5 In the figure, signals of multiple first clock lines SCCK1, SSCK1 and CRCK1 are collectively shown, signals of multiple second clock lines SCCK2, SSCK2 and CRCK2 are collectively shown, signals of multiple third clock lines SCCK3, SSCK3 and CRCK3 are collectively shown, signals of multiple fourth clock lines SCCK4, SSCK4 and CRCK4 are collectively shown, signals of multiple fifth clock lines SCCK5, SSCK5 and CRCK5 are collectively shown, and signals of multiple sixth clock lines SCCK6, SSCK6 and CRCK6 are collectively shown.

[0140] However, referring to Figure 6 , the scan clock signal, the sense clock signal, and the carry clock signal respectively applied to the scan clock line, the sense clock line, and the carry clock line connected to the same scan stage may have different magnitudes. In an exemplary embodiment, for example, the low level of the scan clock signal and the sense clock signal may correspond to the magnitude of the voltage applied to the first power line VSS1, and the high level of the scan clock signal and the sense clock signal may correspond to the magnitude of the gate-on voltage VON. In addition, the low level of the carry clock signal may correspond to the magnitude of the voltage applied to the second power line VSS2 or the third power line VSS3, and the high level of the carry clock signal may correspond to the magnitude of the gate-on voltage VON. In an exemplary embodiment, for example, the voltage applied to the first power line VSS1 may be higher than the voltage applied to the second power line VSS2 or the third power line VSS3.

[0141] The magnitude of the gate-on voltage VON may be a magnitude sufficient to turn on the transistor, and the magnitude of each of the plurality of voltages applied to the first power line VSS1, the second power line VSS2, and the third power line VSS3 may have a magnitude sufficient to turn off the transistor. Hereinafter, a voltage level corresponding to the magnitude of the gate-on voltage VON (or a voltage having a turn-on level) may be represented as a high level, and a voltage level corresponding to the magnitude of each of the plurality of voltages applied to the first power line VSS1, the second power line VSS2, and the third power line VSS3 (or a voltage having a turn-off level) may be represented as a low level.

[0142] Refer again Figure 5 , the high level pulses of the plurality of second clock lines SCCK2, SSCK2 and CRCK2 have a phase delayed than the phases of the plurality of first clock lines SCCK1, SSCK1 and CRCK1, and the high level pulses of the plurality of second clock lines SCCK2, SSCK2 and CRCK2 and the high level pulses of the plurality of first clock lines SCCK1, SSCK1 and CRCK1 may partially overlap each other in time. In an exemplary embodiment, for example, the high level pulse may have a length of two horizontal periods, and the overlapping length may correspond to one horizontal period. Here, the horizontal period may be defined by a driving frame (frame rate) of the display device 10. When the display device 10 is driven at 120 Hz (Hz), the horizontal period may be about 3.8 microseconds (μs). Hereinafter, although the length of the period is described by using, for example, a case where the display device 10 is driven at 120 Hz, the driving frequency of the display device 10 is not limited thereto.

[0143] Similarly, the high level pulses of the plurality of third clock lines SCCK3, SSCK3 and CRCK3 have a phase delayed than the phase of the high level pulses of the plurality of second clock lines SCCK2, SSCK2 and CRCK2, and the high level pulses of the plurality of third clock lines SCCK3, SSCK3 and CRCK3 and the high level pulses of the plurality of second clock lines SCCK2, SSCK2 and CRCK2 may partially overlap each other in time. The high level pulses of the plurality of fourth clock lines SCCK4, SSCK4 and CRCK4 have a phase delayed than the phase of the high level pulses of the plurality of third clock lines SCCK3, SSCK3 and CRCK3, and the high level pulses of the plurality of fourth clock lines SCCK4, SSCK4 and CRCK4 and the high level pulses of the plurality of third clock lines SCCK3, SSCK3 and CRCK3 may partially overlap each other in time. The high level pulses of the plurality of fifth clock lines SCCK5, SSCK5 and CRCK5 have a phase delayed than the phase of the high level pulses of the plurality of fourth clock lines SCCK4, SSCK4 and CRCK4, and the high level pulses of the plurality of fifth clock lines SCCK5, SSCK5 and CRCK5 and the high level pulses of the plurality of fourth clock lines SCCK4, SSCK4 and CRCK4 may partially overlap with each other in time. The high level pulses of the plurality of sixth clock lines SCCK6, SSCK6 and CRCK6 have a phase delayed than the phase of the plurality of fifth clock lines SCCK5, SSCK5 and CRCK5, and the high level pulses of the plurality of sixth clock lines SCCK6, SSCK6 and CRCK6 and the high level pulses of the plurality of fifth clock lines SCCK5, SSCK5 and CRCK5 may partially overlap with each other in time. In addition, iteratively, the high level pulses of the multiple first clock lines SCCK1, SSCK1 and CRCK1 have a phase delayed than the phase of the high level pulses of the multiple sixth clock lines SCCK6, SSCK6 and CRCK6, and the high level pulses of the multiple first clock lines SCCK1, SSCK1 and CRCK1 and the high level pulses of the multiple sixth clock lines SCCK6, SSCK6 and CRCK6 may partially overlap with each other in time.

[0144] Hereinafter, the operation of the first stage ST(2n-1) in the display period will be described. The operations of the other stages are similar to those of the first stage ST(2n-1), and therefore, repeated description will be omitted.

[0145] First, a high level pulse may be applied to the fourth control line CS4. Therefore, the thirty-fifth transistor may be turned on, and the voltage of the third node N3 may be discharged to a low level.

[0146] After the predetermined time has passed, at time t1, a high level pulse may be generated in the carry line CR(2n-4). Accordingly, the thirty-ninth transistor is turned on, and the third node N3 is charged to a high level. The forty-first transistor T41 may be turned on, and the fifth node N5 may be charged to a high level voltage applied to the second control line CS2.

[0147] Next, at time t2, a high level pulse is generated in the first control line CS1, and thus, the fifty-first transistor may be turned on. Since a high level pulse is generated in the carry line CR(2n-3), a high level voltage may be charged in the first electrode of the fifth capacitor C5 through the fifty-first transistor.

[0148] Then, at time t3, a high level pulse is generated in the plurality of fifth clock lines SCCK5, SSCK5, and CRCK5. Therefore, the voltage of the third node N3 can be boosted to a higher level through the plurality of capacitors C1 and C2, and the high level pulse can be output to the scan line SC (2n-1), the sense line SS (2n-2), and the carry line CR (2n-1).

[0149] Although the third node N3 is boosted, since a high level voltage is applied to the fifth node N5, a voltage difference between the drain electrode and the source electrode of the plurality of sub-transistors T19a, T19b, T23a, T23b, T33a, T33b, T35a, T35b, T39a, and T39b is relatively small. Therefore, the plurality of sub-transistors T19a, T19b, T23a, T23b, T33a, T33b, T35a, T35b, T39a, and T39b can be prevented from being degraded.

[0150] In a similar manner, when a high level pulse is generated in the plurality of sixth clock lines SCCK6, SSCK6, and CRCK6, a high level pulse may be output from the scan line SC2n, the sense line SS2n, and the carry line CR2n of the second stage ST2n.

[0151] Although not shown in the drawing, when a high level pulse is applied through the carry line CR(2n+3), the third node N3 is connected to the second power line VSS2 through the thirty-third transistor, and thus, the voltage of the third node N3 may be discharged to a low level.

[0152] In addition, although not shown in the figure, the high-level control signal may be alternately applied to the fifth control line CS5 and the sixth control line CS6 in units of a predetermined period of time, which may correspond to, for example, a plurality of frames.

[0153] In an exemplary embodiment, for example, during the first period, a high level control signal may be applied to the fifth control line CS5, and a low level control signal may be applied to the sixth control line CS6. A plurality of transistors T31 and T37 may be turned on so that the first node N1 is charged to a high level. Therefore, the nineteenth transistor may be turned on to discharge the third node N3 to a low level, the fourteenth transistor T14 may be turned on to discharge the carry line CR (2n-1) to a low level, the ninth transistor T9 may be turned on to discharge the sense line SS (2n-1) to a low level, and the fifth transistor T5 may be turned on to discharge the scan line SC (2n-1) to a low level.

[0154] In addition, during the second period after the first period, a low level control signal may be applied to the fifth control line CS5, and a high level control signal may be applied to the sixth control line CS6. A plurality of transistors T32 and T38 may be turned on so that the second node N2 is charged to a high level. Therefore, the twenty-third transistor may be turned on to discharge the third node N3 to a low level, the fifteenth transistor T15 may be turned on to discharge the carry line CR (2n-2) to a low level, the eleventh transistor T11 may be turned on to discharge the sense line SS (2n-1) to a low level, and the seventh transistor T7 may be turned on to discharge the scan line SC (2n-1) to a low level.

[0155] Regarding the first period and the second period, different transistors can be used for the discharge of the third node N3, the carry line CR (2n-1), the sense line SS (2n-1) and the scan line SC (2n-1). Accordingly, the period during which the conduction bias is applied to the corresponding transistor is shortened, thereby preventing the degradation of the corresponding transistor.

[0156] Figure 7 is an equivalent circuit diagram showing an exemplary embodiment of a pixel PXij according to the present invention.

[0157] Reference Figure 7 , the pixel PXij in the exemplary embodiment of the present invention may include a plurality of transistors M1, M2 and M3, a storage capacitor Cst and a light emitting device LD. The plurality of transistors M1, M2 and M3 are shown as N-type transistors. However, in some exemplary embodiments, at least some of the plurality of transistors M1, M2 and M3 may be implemented with P-type transistors.

[0158] A gate electrode of the transistor M1 may be connected to the node Na, a first electrode of the transistor M1 may be connected to the power line ELVDD, and a second electrode of the transistor M1 may be connected to the node Nb. The transistor M1 may also be referred to as a driving transistor.

[0159] A gate electrode of transistor M2 may be connected to scan line SCi, a first electrode of transistor M2 may be connected to data line Dj, and a second electrode of transistor M2 may be connected to node Na. Transistor M2 may also be referred to as a switching transistor, a scan transistor, or the like.

[0160] A gate electrode of transistor M3 may be connected to a sensing line SSi, a first electrode of transistor M3 may be connected to a receiving line Rj, and a second electrode of transistor M3 may be connected to a node Nb. Transistor M3 may also be referred to as an initialization transistor, a sensing transistor, or the like.

[0161] A first electrode of the storage capacitor Cst may be connected to the node Na, and a second electrode of the storage capacitor Cst may be connected to the node Nb.

[0162] An anode of the light emitting device LD may be connected to the node Nb, and a cathode of the light emitting device LD may be connected to the power line ELVSS. The light emitting device LD may be configured as an organic light emitting diode, an inorganic light emitting diode, a quantum dot (QD) light emitting diode, or the like.

[0163] Reference Figure 5 As described in the description shown in , during the display period of one frame, a high level pulse may be applied to the scan line SCi and the sensing line SSi at least once. The corresponding data voltage may be applied to the data line Dj, and the first reference voltage may be applied to the receiving line Rj. Therefore, when the plurality of transistors M2 and M3 are in an on state, the storage capacitor Cst may store a voltage corresponding to the difference between the data voltage and the first reference voltage. Subsequently, although the plurality of transistors M2 and M3 are turned off, the voltage stored in the storage capacitor Cst may be maintained. The amount of driving current flowing through the transistor M1 is determined according to the voltage stored in the storage capacitor Cst, and the light emitting device LD emits light having a brightness corresponding to the amount of driving current.

[0164] Figure 8 2 is a timing chart showing an exemplary driving method of the scan driver 13 in the sensing period.

[0165] Reference Figure 8 , shows signals applied to the third control line CS3, the scan clock line SCCK5, the sense clock line SSCK5, other clock lines Other CKs, multiple scan lines SC(2n-1) and SC(2n+1), multiple sense lines SS(2n-1) and SS(2n+1), and multiple carry lines CR(2n-1) and CR(2n+1). In addition, Figure 2 The first stage ST(2n-1) shown in φ corresponds to the second to last stage with respect to the first stage ST(2n+1). Figure 3The input terminals and output terminals shown in can be applied to the input terminals and output terminals of each of the plurality of stages ST(2n-1) and ST(2n+1).

[0166] At time t4, a high level pulse may be generated in the third control line CS3. Accordingly, the 48th transistor T48 may be turned on. Since the fifth capacitor C5 is in a state where the voltage is charged in the fifth capacitor C5 during the above period from time t2 to time t3, the 47th transistor T47 may be in a turned-on state. Accordingly, the high level voltage applied to the second control line CS2 may be applied to the third node N3 through the plurality of transistors T47 and T48.

[0167] In the other first stages except the first stage ST(2n-1), the forty-seventh transistor T47 is in a turned-off state, and thus, the third node N3 may maintain a low level.

[0168] Next, at time t5, a high level signal may be applied to the scan clock line SCCK5, the sense clock line SSCK5, and the carry clock line CRCK5. Therefore, the voltage of the third node N3 may be boosted by the plurality of capacitors C1 and C2, and the high level signal may be output to the scan line SC(2n-1), the sense line SS(2n-1), and the carry line CR(2n-1).

[0169] Accordingly, a plurality of transistors M2 and M3 of the pixel connected to the scan line SC(2n-1) and the sensing line SS(2n-1) may be turned on. A second reference voltage may be applied to the data line. The sensor 14 may measure degradation information or characteristic information of the pixel according to the current value or voltage value received through the plurality of receiving lines R1, R2, R3, ..., Rj, ... and Rq.

[0170] Moreover, at time t5, the high level signal applied to the carry clock line CRCK5 can be maintained, and the output of the high level signal to the carry line CR (2n-1) can be maintained. The high level signal output to the carry line CR (2n-1) can mainly charge the fifty-second transistor connected to the input terminal of the next level (e.g., ST (2n + 1) or ST (2n + 2)). The carry clock line CRCK5 can be maintained at a high level during the period from time t5 to time t8. During the period from time t5 to time t8, the high level signal output to the carry line CR (2n-1) can be maintained.

[0171] In other first stages except the first stage ST(2n-1), since the voltage of the third node N3 has a low level, although a high level pulse is applied to the scan clock line SCCK5 and the sensing clock line SSCK5, a low level signal can also be output to the corresponding scan line and the corresponding sensing line.

[0172] Since the fifty-second transistor of the second stage ST2n is connected to the same carry line CR(2n-3) as the first stage ST(2n-1), the sixth capacitor C6 may be in a state where the same voltage as the fifth capacitor C5 is charged in the sixth capacitor C6. However, during the sensing period, a low level voltage is maintained in the scan clock line SCCK6 and the sense clock line SSCK6 connected to the second stage ST2n, so that the voltages of the scan line SC(2n+1) and the sense line SS(2n+1) may be maintained at a low level.

[0173] At time t6, a high level signal may be applied to the scan clock line SCCK5 and the sense clock line SSCK5. The just previous data voltage may be applied to the data line again. Therefore, the pixel connected to the scan line SC(2n-1) and the sense line SS(2n-1) may emit light having a grayscale based on the just previous data voltage again.

[0174] According to the present exemplary embodiment, the pixels connected to the scan line SC(2n-1) and the sensing line SS(2n-1) do not emit light having a grayscale based on the data voltage during the period from time t5 to time t6, but may emit light having a grayscale based on the data voltage again after time t6. In addition, the pixels connected to other scan lines and other sensing lines continuously emit light having a grayscale based on the data voltage during the sensing period, and therefore there is no problem when a viewer recognizes a frame.

[0175] At time t7, a low level signal may be applied to the scan clock line SCCK5 and the sense clock line SSCK5. The period from time t7 to time t8 may be a delay period after time t7 until the sensing period of the stages arranged adjacent to each other begins. That is, the sensing period may include a delay period (e.g., a period from time t7 to time t8) until the sensing period of the stages arranged adjacent to each other begins after the process of inputting a black data voltage to each pixel, initializing the pixel, sensing the pixel, and then inputting the black data voltage to the pixel again during the period from time t5 to time t7. In an exemplary embodiment, for example, the stage ST (2n-1) and the stage ST2n correspond to the stages arranged adjacent to each other, and the stage ST2n and the stage ST (2n+1) correspond to the stages arranged adjacent to each other.

[0176] In an exemplary embodiment, for example, the period from time t7 to time t8 is a delay period, and may have a length of six horizontal periods or longer. In an exemplary embodiment, for example, the period from time t7 to time t8 may be about 20 μs or longer.

[0177] In an exemplary embodiment, just before the period from time t7 to time t8 ends, a high level signal may be applied to the scan clock line SCCK5 and the sense clock line SSCK5. In an exemplary embodiment, for example, just before the period from time t7 to time t8 ends, a period during which a high level signal is applied to the scan clock line SCCK5 and the sense clock line SSCK5 may be six horizontal periods, or equal to or less than 20 μs or less.

[0178] Therefore, a high-level signal can be output to the scan line SC (2n-1) and the sensing line SS (2n-1). For example, the period during which the high-level signal is applied to the scan clock line SCCK5 and the sensing clock line SSCK5 may be equal to or less than six horizontal periods, or equal to or less than about 20 μs or less.

[0179] Since the output of the high-level signal to the carry line CR(2n-1) is maintained, the high-level signal output to the carry line CR(2n-1) can recharge the fifty-second transistor connected to the input terminal of the next level (for example, ST(2n+1) or ST(2n+2)).

[0180] Although the scan driver 13 is arranged (e.g., installed) as an OSG driver circuit, a high-level signal is output to the scan line SC (2n-1) and the sensing line SS (2n-1) at least once during the delay period while the high-level signal is output to the carry line CR (2n-1). Therefore, the next stage can be driven normally. Accordingly, sensing reliability can be improved.

[0181] In an exemplary embodiment, the time t8 at which the high-level signal output to the scan line SC(2n-1) and the sensing line SS(2n-1) is changed to a low-level signal may coincide with the time at which the low-level signal output to the scan line SC(2n+1) and the sensing line SS(2n+1) is changed to a high-level signal.

[0182] Fig. 9 1 is a schematic cross-sectional view showing an exemplary embodiment of a pixel unit 15 according to the present invention. In this exemplary embodiment, a pixel unit 15 in which an organic light emitting diode is applied to the above-mentioned light emitting device LD will be described as an example.

[0183] Reference Fig. 9 The pixel unit 15 may include a display substrate 101 , a plurality of transistors TR1 , TR2 , and TR3 arranged on the display substrate 101 , a plurality of organic light emitting diodes 310 arranged on the plurality of transistors TR1 , TR2 , and TR3 , and a first encapsulation layer 400 arranged on the plurality of organic light emitting diodes 310 .

[0184] The display substrate 101 may be a rigid substrate or a flexible substrate. When the display substrate 101 is a rigid substrate, the display substrate 101 may be one of a glass substrate, a quartz substrate, a glass ceramic substrate, and a crystallized glass substrate. When the display substrate 101 is a flexible substrate, the display substrate 101 may be one of a film substrate including a polymer organic material and a plastic substrate. Moreover, the display substrate 101 may include fiber glass reinforced plastic (FRP). The display substrate 101 may be the lower substrate of the pixel unit 15. In an exemplary embodiment, the display substrate 101 may be an opaque substrate.

[0185] A first buffer layer 201 is disposed on the display substrate 101. The first buffer layer 201 flattens the surface of the display substrate 101 and prevents penetration of moisture or external air. The first buffer layer 201 may be an inorganic layer. The first buffer layer 201 may be a single layer or a multilayer.

[0186] A plurality of transistors TR1, TR2, and TR3 are arranged on the first buffer layer 201. Each of the plurality of transistors TR1, TR2, and TR3 may be a thin film transistor. Each of the plurality of transistors TR1, TR2, and TR3 shown in the figure may be a driving transistor (eg, Figure 6 M1 shown in ).

[0187] The plurality of transistors TR1, TR2, and TR3 may include a first transistor TR1, a second transistor TR2, and a third transistor TR3. One or more of the plurality of transistors TR1, TR2, and TR3 may be provided for each pixel. In an exemplary embodiment, for example, the first transistor TR1 may be provided in a red pixel, the second transistor TR2 may be provided in a green pixel, and the third transistor TR3 may be provided in a blue pixel.

[0188] The plurality of transistors TR1, TR2 and TR3 may include a plurality of semiconductor layers A1, A2 and A3, a plurality of gate electrodes G1, G2 and G3, a plurality of source electrodes S1, S2 and S3, and a plurality of drain electrodes D1, D2 and D3, respectively. Specifically, the plurality of semiconductor layers A1, A2 and A3 are arranged on the first buffer layer 201. The plurality of semiconductor layers A1, A2 and A3 may include amorphous silicon, polycrystalline silicon, low temperature polycrystalline silicon and an organic semiconductor. In another exemplary embodiment, each of the plurality of semiconductor layers A1, A2 and A3 may be an oxide semiconductor. Although not clearly shown in the drawings, each of the plurality of semiconductor layers A1, A2 and A3 may include a channel region and a source region and a drain region arranged at both sides of the channel region and doped with impurities.

[0189] A gate insulating layer 211 is disposed above the plurality of semiconductor layers A1, A2, and A3. The gate insulating layer 211 may be an inorganic layer. The gate insulating layer 211 may be a single layer or multiple layers.

[0190] A plurality of gate electrodes G1, G2, and G3 are arranged on the gate insulating layer 211. The plurality of gate electrodes G1, G2, and G3 may include a metal material having conductivity. In an exemplary embodiment, for example, the plurality of gate electrodes G1, G2, and G3 may include molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti). Each of the plurality of gate electrodes G1, G2, and G3 may be a single layer or a multilayer.

[0191] An intermediate insulating layer 212 is disposed above the plurality of gate electrodes G1, G2, and G3. The intermediate insulating layer 212 may be an inorganic layer. The intermediate insulating layer 212 may be a single layer or multiple layers.

[0192] A plurality of source electrodes S1, S2, and S3 and a plurality of drain electrodes D1, D2, and D3 are arranged on the intermediate insulating layer 212. The plurality of source electrodes S1, S2, and S3 and the plurality of drain electrodes D1, D2, and D3 include a metal material having conductivity. In an exemplary embodiment, for example, the plurality of source electrodes S1, S2, and S3 and the plurality of drain electrodes D1, D2, and D3 may include aluminum (Al), copper (Cu), titanium (Ti), and molybdenum (Mo).

[0193] The plurality of source electrodes S1 , S2 , and S3 and the plurality of drain electrodes D1 , D2 , and D3 may be electrically connected to source and drain regions of the plurality of semiconductor layers A1 , A2 , and A3 through contact holes penetrating the intermediate insulating layer 212 and the gate insulating layer 211 , respectively.

[0194] Although not separately shown in the drawings, the display device 10 may further include a storage capacitor and a switching transistor on the display substrate 101 .

[0195] A protective layer 220 is disposed on the plurality of source electrodes S1, S2, and S3, the plurality of drain electrodes D1, D2, and D3, and the intermediate insulating layer 212. The protective layer 220 covers the circuit including the plurality of transistors TR1, TR2, and TR3. The protective layer 220 may be a passivation layer or a planarization layer. The passivation layer may include SiO 2 、SiN x The protective layer 220 may include a passivation layer and a planarization layer. The passivation layer may be disposed on the plurality of source electrodes S1, S2, and S3, the plurality of drain electrodes D1, D2, and D3, and the intermediate insulating layer 212, and the planarization layer may be disposed on the passivation layer. The upper surface of the protective layer 220 may be planarized.

[0196] A plurality of organic light emitting diodes 310 may be arranged on the protective layer 220. As described above, the organic light emitting diodes 310 may be arranged in corresponding pixels.

[0197] A plurality of first pixel electrodes 311 are disposed on the protective layer 220 . The first pixel electrodes 311 may be pixel electrodes disposed in corresponding pixels. Also, each of the plurality of first pixel electrodes 311 may be an anode of the organic light emitting diode 310 .

[0198] The plurality of first pixel electrodes 311 may be electrically connected to the plurality of drain electrodes D1 , D2 , and D3 (or the plurality of source electrodes S1 , S2 , and S3 ) disposed on the display substrate 101 through via holes penetrating the protective layer 220 , respectively.

[0199] The plurality of first pixel electrodes 311 may include a material having a high work function. The plurality of first pixel electrodes 311 may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ) and the like.

[0200] In an exemplary embodiment, in each pixel, the area occupied by the first pixel electrode 311 in a plan view may be the same, but the present invention is not limited thereto.

[0201] A pixel defining layer 330 is disposed on the plurality of first pixel electrodes 311. An opening exposing at least a portion of each of the plurality of first pixel electrodes 311 may be defined in the pixel defining layer 330. In an exemplary embodiment, the opening may have a different width in each pixel. In an exemplary embodiment, for example, the widths of the opening of the red pixel, the opening of the green pixel, and the opening of the blue pixel may be sequentially narrowed.

[0202] The pixel defining layer 330 may include an organic material or an inorganic material. In an exemplary embodiment, the pixel defining layer 330 may include a material such as a photoresist, a polyimide-based resin, an acrylic resin, a silicon compound, and a polyacrylic resin.

[0203] An organic light emitting layer 320 may be disposed on each of the plurality of first pixel electrodes 311 exposed by the pixel defining layer 330. In an exemplary embodiment, for example, the organic light emitting layer 320 may be provided in a form in which a first hole transport layer (not shown), a light emitting layer (not shown), and a first electron transport layer (not shown) are sequentially disposed. In an exemplary embodiment, the organic light emitting layer 320 of each pixel is a blue organic light emitting layer 320, but the present invention is not limited thereto.

[0204] A second pixel electrode 312 is disposed on the organic light emitting layer 320 . The second pixel electrode 312 may be a common electrode disposed on the entire display substrate 101 without distinguishing pixels. Also, the second pixel electrode 312 may be a cathode of the organic light emitting diode 310 .

[0205] The second pixel electrode 312 may include a material having a low work function. In an exemplary embodiment, for example, the second pixel electrode 312 may include Li, Ca, LiF / Ca, LiF / Al, Al, Mg, Ag, Pt, Pd, Ni, Au, Nd, Ir, Cr, BaF 2 , Ba or a compound or composition thereof (e.g., a composition of Ag and Mg). The second pixel electrode 312 may further include an auxiliary electrode. In an exemplary embodiment, the auxiliary electrode may include a layer provided by depositing a material and a transparent metal oxide located on the layer, such as ITO, IZO, zinc oxide (ZnO), indium tin zinc oxide (ITZO), etc.

[0206] In an exemplary embodiment, when the display device 10 is a top emission type display device, the conductive layer having a low work function used as the second pixel electrode 312 may be provided as a thin film, and a transparent conductive layer (e.g., an ITO layer, an IZO layer, a zinc oxide (ZnO) layer, an indium oxide (In 2 O 3 ) layer or the like) may be stacked on top of the conductive layer.

[0207] In each pixel, the first pixel electrode 311 , the organic light emitting layer 320 and the second pixel electrode 312 may constitute an organic light emitting diode 310 .

[0208] The element types and stacking sequence of the organic light emitting diode 310 are not limited to those shown in the figure.

[0209] The first encapsulation layer 400 includes an inorganic layer and / or an organic layer. The first encapsulation layer 400 may include a plurality of stacked layers. The first encapsulation layer 400 may be provided as a plurality of layers including a first inorganic layer 410, an organic layer 420, and a second inorganic layer 430 sequentially stacked on the second pixel electrode 312.

[0210] In an exemplary embodiment, for example, the first inorganic layer 410 and the second inorganic layer 430 may include silicon oxide (SiO x ), Silicon Nitride (SiN x ) and silicon oxynitride (SiON x ) at least one of ).

[0211] In exemplary embodiments, for example, the organic layer 420 may include at least one of epoxy, acrylate, and urethane acrylate.

[0212] The display device 10 may include a second buffer layer 501, a black matrix 521, a first color conversion filter, a first cover layer 511, a second color conversion filter, a second cover layer 512, an upper coating layer 513, a passivation layer 514, and a cover layer 550 sequentially stacked on the first encapsulation layer 400. The display device 10 may include a second buffer layer 501, a passivation layer 514, an upper coating layer 513, a second cover layer 512, a second color conversion filter, a first cover layer 511, a first color conversion filter, and a black matrix 521 sequentially stacked on the first encapsulation layer 400.

[0213] The second buffer layer 501 is disposed on the first encapsulation layer 400. The second buffer layer 501 flattens the surface of the first encapsulation layer 400 and prevents moisture or external air from penetrating into the first encapsulation layer 400. The second buffer layer 501 may be an inorganic layer. The second buffer layer 501 may be a single layer or a multilayer. In another exemplary embodiment, the second buffer layer 501 may be omitted.

[0214] In another exemplary embodiment, a separate filling material may be disposed between the first encapsulation layer 400 and the second buffer layer 501. In yet another exemplary embodiment, an upper surface of the first encapsulation layer 400 and a lower surface of the first color conversion filter, which will be described later, may directly contact each other.

[0215] The black matrix 521 is arranged on the upper substrate 560. The black matrix 521 may be arranged along the boundary of the pixel and block the transmission of light. The black matrix 521 may overlap with the pixel defining layer 330. An opening in which each pixel may be defined may be defined in the black matrix 521.

[0216] The material of the black matrix 521 is not particularly limited as long as the material can block light. In an exemplary embodiment, the black matrix 521 may include a photosensitive composition, an organic material, a metal material, or the like. In an exemplary embodiment, the photosensitive composition may include a binder resin, a polymer monomer, a polymer oligomer, a pigment, a dispersant, etc. The metal material may include chromium, etc.

[0217] The first color conversion filter is disposed on the upper substrate 560 and the black matrix 521. The first color conversion filter may overlap with the opening of the black matrix 521.

[0218] In an exemplary embodiment, the first color conversion filter may be a color filter 540. The color filter 540 allows light of a specific color to be selectively transmitted therethrough, and may block the travel of light of another color by absorbing the light. The light passing through the color filter 540 may display one of the primary colors of red, green, and blue. However, the color displayed by the light passing through the color filter 540 is not limited to the primary color, and the light may display any one of cyan, magenta, yellow, and white.

[0219] In the present exemplary embodiment, a case where the first color conversion filter includes a red first color filter 541 , a green second color filter 542 , and a blue third color filter 543 will be described as an example.

[0220] The first color filter 541 may be arranged in a red pixel. The first color filter 541 allows light of a first color to be transmitted therethrough, and may absorb and block light of a second color and light of a third color. The first color may be red, the second color may be green, and the third color may be blue. That is, the first color filter 541 may be a red color filter and include a red colorant. The red color filter allows red light to be transmitted therethrough, and may absorb and block green light and blue light.

[0221] The second color filter 542 may be arranged in the green pixel. The second color filter 542 allows the light of the second color to be transmitted therethrough, and may absorb and block the light of the first color and the light of the third color. That is, the second color filter 542 may be a green color filter and include a green colorant. The green color filter allows green light to be transmitted therethrough, and may absorb and block red light and blue light.

[0222] The third color filter 543 may be arranged in the blue pixel. The third color filter 543 allows the light of the third color to be transmitted therethrough, and may absorb and block the light of the first color and the light of the second color. That is, the third color filter 543 may be a blue color filter and include a blue colorant. The blue color filter allows the blue light to be transmitted therethrough, and may absorb and block the red light and the green light.

[0223] Since the color filter absorbs external light to a considerable extent, the color filter can reduce reflection of the external light even when a polarizing plate or the like is additionally arranged.

[0224] In an exemplary embodiment, a boundary portion between the color filters may be disposed in the non-emission region. That is, the boundary portion between the color filters may overlap with the black matrix 521.

[0225] The first cover layer 511 is arranged above the first color conversion filter. The first cover layer 511 prevents the first color conversion filter or the like from being damaged by penetration of moisture, air, or the like from the outside. Also, the first cover layer 511 prevents the colorant included in each color filter from diffusing into another component.

[0226] In some exemplary embodiments, the first capping layer 511 may include an inorganic material. In exemplary embodiments, for example, the first capping layer 511 may include at least one of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, cerium oxide, silicon oxynitride, and the like.

[0227] The second color conversion filter and the light-transmitting pattern 533 are disposed on the first cover layer 511. In an exemplary embodiment, for example, the thickness of the second color conversion filter and the light-transmitting pattern 533 is in a range of about 2 μs to about 20 μs.

[0228] The second color conversion filter may be a wavelength conversion pattern 530. The wavelength conversion pattern 530 may convert incident light having a peak wavelength into light having a specific peak wavelength and emit the converted light. Light passing through the wavelength conversion pattern 530 may display one of three primary colors such as red, green, and blue. However, the color displayed by the light passing through the wavelength conversion pattern 530 is not limited to the primary colors, and the light passing through the wavelength conversion pattern 530 may display any one of cyan, magenta, yellow, and white series colors.

[0229] In the present exemplary embodiment, a case where the wavelength conversion pattern 530 includes a first wavelength conversion pattern 531 and a second wavelength conversion pattern 532 that are different from each other will be described as an example.

[0230] The first wavelength conversion pattern 531 may be disposed in a red pixel. In an exemplary embodiment, for example, the first wavelength conversion pattern 531 may convert blue light into red light having a wavelength in a range of about 610 nanometers (nm) to about 650 nm and emit red light. The first wavelength conversion pattern 531 may not be disposed in a green pixel and a blue pixel.

[0231] The first wavelength conversion pattern 531 may include a first base resin 5311 and a first wavelength conversion material 5313 dispersed in the first base resin 5311 , and may further include a first scattering material 5315 dispersed in the first base resin 5311 .

[0232] The first base resin 5311 is not particularly limited as long as it is a material having high light transmittance and excellent dispersion characteristics with respect to the first wavelength conversion material 5313 and the first scattering material 5315. In an exemplary embodiment, for example, the first base resin 5311 may include an organic material such as an epoxy-based resin, an acryl-based resin, a cardo-based resin, or an imide-based resin.

[0233] The first wavelength conversion material 5313 may convert incident light having a peak wavelength into light having a specific peak wavelength. Examples of the first wavelength conversion material 5313 may be QDs, quantum rods, fluorescent substances, and the like.

[0234] QDs can be semiconductor nanocrystal materials. QDs have specific band gaps according to their composition and size, and can emit light with an inherent frequency band after absorbing light. Examples of semiconductor nanocrystals of QDs can include nanocrystals based on IV groups, compound nanocrystals based on II-VI groups, compound nanocrystals based on III-V groups, nanocrystals based on IV-VI groups, or combinations thereof.

[0235] In an exemplary embodiment, for example, the Group IV-based nanocrystals may include binary compounds such as silicon (Si), germanium (Ge), silicon carbide (SiC), and silicon germanium (SiGe). However, the present invention is not limited thereto.

[0236] In addition, II-VI compound nanocrystals may include binary compounds such as CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnO, HgS, HgSe, HgTe, MgSe, MgS, combinations thereof, and / or the like, such as CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZnTe, Cd Ternary compounds of HgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, MgZnSe, MgZnS, combinations thereof, and / or the like, and quaternary compounds such as HgZnTeS, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, HgZnSTe, combinations thereof, and / or the like. However, the present invention is not limited thereto.

[0237] In addition, the III-V compound nanocrystals may include binary compounds such as GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, InSb, combinations thereof, and / or the like, ternary compounds such as GaNP, GaNAs, GaNSb, GaPAs, GaPSb, AlNP, AlNAs, AlNSb, AlPAs, AlPSb, InNP, InNAs, InNSb, InPAs, InPSb, combinations thereof, and / or the like, and quaternary compounds such as GaAlNAs, GaAlNSb, GaAlPAs, GaAlPSb, GaInNP, GaInNAs, GaInNSb, GaInPAs, GaInPSb, InAlNP, InAlNAs, InAlNSb, InAlPAs, InAlPSb, GaAlNP, combinations thereof, and / or the like. However, the present invention is not limited thereto.

[0238] IV-VI group nanocrystals may include binary compounds such as SnS, SnSe, SnTe, PbS, PbSe, PbTe, combinations thereof and / or the like, ternary compounds such as SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbSTe, SnPbS, SnPbSe, SnPbTe, combinations thereof and / or the like, and quaternary compounds such as SnPbSSe, SnPbSeTe, SnPbSTe, combinations thereof and / or the like. However, the present invention is not limited thereto.

[0239] QD may have a core-shell structure including a core having the above-mentioned nanocrystals and a shell surrounding the core. The shell of QD may be used as a protective layer for preventing or reducing the chemical denaturation of the core to maintain semiconductor properties and / or as a charging layer for imparting electrophoretic properties to QD. The shell may be a single layer or multilayer structure. As an example, metal or non-metal oxides, semiconductor compounds, compositions thereof and / or the like may be adopted as the shell of QD.

[0240] In an exemplary embodiment, the metal or non-metal oxide may be SiO 2 、Al 2 O 3 、TiO 2 、ZnO、MnO、Mn 2 O 3 , Mn 3 O 4 , CuO, FeO, Fe 2 O 3 , Fe 3 O 4 , CoO, Co 3 O4 , NiO and / or similar binary compounds, or MgAl 2 O 4 、CoFe 2 O 4 、NiFe 2 O 4 、CoMn 2 O 4 And / or the like ternary compounds. However, the present invention is not limited thereto.

[0241] In addition, in an exemplary embodiment, for example, the semiconductor compound may include CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, GaAs, GaP, GaSb, HgS, HgSe, HgTe, InAs, InP, InSb, AlAs, AlP, AlSb, and / or the like. However, the present invention is not limited thereto.

[0242] In an exemplary embodiment, for example, the light emitted by the first wavelength conversion material 5313 may have a full width at half maximum (FWHM) of the emission wavelength spectrum of about 45 nm or less, about 40 nm or less, or about 30 nm or less, thereby further improving color purity and color reproducibility. In addition, the light emitted by the first wavelength conversion material 5313 may be emitted in various directions regardless of the incident angle of the incident light. Accordingly, the side visibility of the display device may be improved.

[0243] A portion of the light L emitted from the organic light emitting diode 310 is not converted into red light by the first wavelength conversion material 5313, but may be emitted by passing through the first wavelength conversion pattern 531. A component that is not converted by the first wavelength conversion pattern 531 but is incident into the first color filter 541 may be blocked by the first color filter 541. The red light converted by the first wavelength conversion pattern 531 may be emitted to the outside by passing through the first color filter 541. Accordingly, the first emission light L1 emitted to the outside in the red pixel may be red light.

[0244] The first scattering material 5315 may have a refractive index different from that of the first base resin 5311, and may form an optical interface with the first base resin 5311. In an exemplary embodiment, for example, the first scattering material 5315 may be light scattering particles. The first scattering material 5315 is not particularly limited because it includes a material capable of scattering at least some of the transmitted light. In an exemplary embodiment, for example, the first scattering material 5315 may include metal oxide particles or organic particles. Examples of metal oxides may include titanium oxide (TiO 2 )、ZrO 2 ), aluminum oxide (Al2 O 3 ), indium oxide (In 2 O 3 )、ZnO、SnO 2 ) and the like. Examples of the organic material may include acryl-based resins, polyurethane-based resins, and the like. The first scattering material 5315 may scatter light in multiple directions regardless of the incident direction of the incident light without substantially converting the wavelength of light transmitted through the first wavelength conversion pattern 531. Accordingly, the path length of light transmitted through the first wavelength conversion pattern 531 may be increased, and the color conversion efficiency caused by the first wavelength conversion material 5313 may be improved.

[0245] In some exemplary embodiments, the first wavelength conversion pattern 531 may have a thickness of 3 micrometers (μm) to 15 μm. For example, the first wavelength conversion material 5313 included in the first wavelength conversion pattern 531 may have a content of 10 percent (%) to 60%. In addition, the first scattering material 5315 included in the first wavelength conversion pattern 531 may have a content of 2% to 15%.

[0246] The second wavelength conversion pattern 532 may be disposed in the green pixel. In an exemplary embodiment, the second wavelength conversion pattern 532 may convert blue light into green light having a wavelength in the range of about 510 nm to about 550 nm and emit green light. The second wavelength conversion pattern 532 may not be disposed in the red pixel and the green pixel.

[0247] The second wavelength conversion pattern 532 may include a second base resin 5321 and a second wavelength conversion material 5323 dispersed in the second base resin 5321 , and may further include a second scattering material 5325 dispersed in the second base resin 5321 .

[0248] The second base resin 5321 is not particularly limited as long as it is a material having high light transmittance and excellent dispersion characteristics with respect to the second wavelength conversion material 5323 and the second scattering material 5325. In an exemplary embodiment, the second base resin 5321 may include an organic material such as an epoxy-based resin, an acryl-based resin, a cardo-based resin, or an imide-based resin.

[0249] Examples of the second wavelength conversion material 5323 may be QDs, quantum rods, fluorescent substances, and the like. In addition, the detailed description of the second wavelength conversion material 5323 is substantially the same or similar to that of the first wavelength conversion material 5313, and therefore, repeated description will be omitted.

[0250] The first wavelength conversion material 5313 and the second wavelength conversion material 5323 may both be constructed of QDs. The diameter of the QDs constituting the first wavelength conversion material 5313 may be greater than the diameter of the QDs constituting the second wavelength conversion material 5323. In an exemplary embodiment, for example, the QDs of the first wavelength conversion material 5313 may have a diameter of about 55 angstroms. to about In addition, in an exemplary embodiment, for example, the QD of the second wavelength conversion material 5323 may have a size of about To date size.

[0251] Light transmitted through the first wavelength conversion pattern 531 and the second wavelength conversion pattern 532 may be in a non-polarized state in which polarization is resolved. Non-polarized light means light that is not composed of polarization components only in a specific direction, that is, light that is not polarized only in a specific direction, that is, light composed of random polarization components. An example of non-polarized light may be natural light.

[0252] The second scattering material 5325 may have a refractive index different from that of the second base resin 5321 and may form an optical interface with the second base resin 5321. In addition, the detailed description of the second scattering material 5325 is substantially the same as or similar to that of the first scattering material 5315, and thus, a repeated description will be omitted.

[0253] The second wavelength conversion material 5323 included in the second wavelength conversion pattern 532 may have a content of 10% to 60%. In addition, in an exemplary embodiment, for example, the second scattering material 5325 included in the second wavelength conversion pattern 532 may have a content of 2% to 15%.

[0254] A portion of the light L emitted from the organic light emitting diode 310 is not converted into green light by the second wavelength conversion material 5323, but may be emitted by passing through the second wavelength conversion pattern 532. A component that is not converted by the second wavelength conversion pattern 532 but is incident into the second color filter 542 may be blocked by the second color filter 542. The green light converted by the second wavelength conversion pattern 532 may be emitted to the outside by passing through the second color filter 542. Accordingly, the second emission light L2 emitted to the outside in the green pixel may be green light.

[0255] The light-transmitting pattern 533 is disposed in the blue pixel, and may not be disposed in the red pixel and the green pixel. The light-transmitting pattern 533 may allow incident light to be substantially transmitted therethrough.

[0256] The light-transmitting pattern 533 may further include a third base resin 5331 and a third scattering material 5335 dispersed in the third base resin 5331 .

[0257] The third base resin 5331 may include an organic material having high light transmittance. The third base resin 5331 may include the same material as the first base resin 5311, or may include at least one of the materials constituting the first base resin 5311, for example.

[0258] The third scattering material 5335 may have a refractive index different from that of the third base resin 5331, and may form an optical interface with the third base resin 5331. In an exemplary embodiment, for example, the third scattering material 5335 may be light scattering particles. The third scattering material 5335 is not particularly limited because it includes a material capable of scattering at least some of the transmitted light. In an exemplary embodiment, for example, the third scattering material 5335 may be metal oxide particles or organic particles. Examples of metal oxides may be titanium oxide (TiO 2 )、ZrO 2 ), aluminum oxide (Al 2 O 3 ), indium oxide (In 2 O 3 )、ZnO、SnO 2 ) and the like. Examples of the organic material may be acryl-based resins, polyurethane-based resins, and the like. The third scattering material 5335 may scatter light in multiple directions regardless of the incident direction of the incident light without substantially converting the wavelength of light transmitted through the light-transmitting pattern 533. Accordingly, the lateral visibility of the light transmitted through the light-transmitting pattern 533 may be improved.

[0259] The light L emitted from the organic light emitting diode 310 is emitted to the outside by passing through the light-transmitting pattern 533 and the third color filter 543. That is, the third emission light L3 emitted from the blue pixel may have the same wavelength as the blue light emitted from the organic light emitting diode 310.

[0260] The first wavelength conversion pattern 531, the second wavelength conversion pattern 532, and the light-transmitting pattern 533 may be spaced apart from each other in a plan view. Therefore, materials respectively included in the first wavelength conversion pattern 531, the second wavelength conversion pattern 532, and the light-transmitting pattern 533 may not be mixed together. A separation space may be defined between the first wavelength conversion pattern 531, the second wavelength conversion pattern 532, and the light-transmitting pattern 533 that are spaced apart from each other.

[0261] The second cover layer 512 may be disposed over the first wavelength conversion pattern 531, the second wavelength conversion pattern 532, and the light-transmitting pattern 533. The second cover layer 512 may cover the first wavelength conversion pattern 531, the second wavelength conversion pattern 532, and the light-transmitting pattern 533. The second cover layer 512 may be disposed in a separation space between the first wavelength conversion pattern 531, the second wavelength conversion pattern 532, and the light-transmitting pattern 533. In the separation space, the second cover layer 512 may directly contact the first cover layer 511.

[0262] The second cover layer 512 may seal the first wavelength conversion pattern 531, the second wavelength conversion pattern 532, and the light-transmitting pattern 533 together with the first cover layer 511, and accordingly, may prevent the first wavelength conversion pattern 531, the second wavelength conversion pattern 532, and the light-transmitting pattern 533 from being damaged or contaminated due to penetration of impurities such as moisture or air from the outside. The second cover layer 512 may correspond to a top layer which will be described later.

[0263] The second capping layer 512 may include an inorganic material. The second capping layer 512 may include the same material as the first capping layer 511 , or include at least one of the materials mentioned in the description of the first capping layer 511 .

[0264] In an exemplary embodiment, for example, the second cover layer 512 may have a thickness of about to about In some exemplary embodiments, for example, the second cover layer 512 may have a thickness of about The second covering layer 512 may be provided as a single layer, but the present invention is not limited thereto.

[0265] The upper coating layer 513 is disposed on the second cover layer 512. The upper coating layer 513 may play a role of protecting the plurality of wavelength conversion patterns and the light-transmitting patterns while planarizing the second cover layer 512. Generally, an acrylic epoxy material is used for the upper coating layer 513, but the present invention is not limited thereto.

[0266] The passivation layer 514 is disposed on the upper coating layer 513. The emission region may be covered by the passivation layer 514. In an exemplary embodiment, the passivation layer 514 may include an inorganic insulating material, for example, silicon oxide (SiO x ), Silicon Nitride (SiN x ), Silicon Oxynitride (SiON x )wait.

[0267] In an exemplary embodiment, an upper substrate 560 may be disposed on the passivation layer 514. The upper substrate 560 may include a material having light transmittance. The upper substrate 560 may be a rigid substrate or a flexible substrate. In an exemplary embodiment, the upper substrate 560 may be a window member or a packaging substrate.

[0268] When the upper substrate 560 is a rigid substrate, the upper substrate 560 may be one of a glass substrate, a quartz substrate, a glass ceramic substrate, and a crystallized glass substrate. When the upper substrate 560 is a flexible substrate, the upper substrate 560 may be one of a film substrate including a polymer organic material and a plastic substrate. Moreover, the upper substrate 560 may include FRP.

[0269] Next, a display device in another exemplary embodiment of the present invention will be described. Figures 1 to 9 The same components as those shown in FIG. 1 are designated by the same reference numerals, and their repeated description will be omitted.

[0270] Fig.10 is a timing diagram illustrating an exemplary driving method of a scan driver in a sensing period of a display device in another exemplary embodiment of the present invention.

[0271] Reference Fig.10 , in the period from time t6 to time t8, a high-level signal may be maintained in the scan clock line SCCK5 and the sense clock line SSCK5. Therefore, in the period from time t6 to time t8, the output of the high-level signal to the scan line SC(2n-1) and the sense line SS(2n-1) may be maintained. For example, that is, the period in which the high-level signal is maintained in the scan clock line SCCK5, the sense clock line SSCK5, the scan line SC(2n-1), and the sense line SS(2n-1) may be equal to or greater than six horizontal periods or equal to or greater than about 20 μs.

[0272] In an exemplary embodiment, the period of maintaining the output of the high-level signal to the carry line CR (2n-1) and the sensing line SS (2n-1) may be not less than the period of maintaining the output of the high-level signal to the scan line SC (2n-1). The time when the output signals of the carry line CR (2n-1) and the sensing line SS (2n-1) change from the high level to the low level in the sensing period may be the same. That is, the high-level signal may be output to the carry line CR (2n-1) and the sensing line SS (2n-1) in the same manner in the sensing period.

[0273] Since the output of the high-level signal to the carry line CR(2n-1) is maintained, the high-level signal output to the carry line CR(2n-1) can charge the fifty-second transistor connected to the input terminal of the next level (for example, ST(2n+1) or ST(2n+2)).

[0274] Fig.11 is a diagram schematically showing another exemplary embodiment of a terminal connected to one stage of a display device according to the present invention.

[0275] Reference Fig.11, the Nth stage ST(N) according to the present exemplary embodiment is different from the above-described embodiments in that the Nth stage ST(N) is connected to the carry line CR(N-6) of the N-6th stage.

[0276] In an exemplary embodiment, the carry signal of the N-6th stage may be transmitted to the Nth stage ST(N) which is the next stage.

[0277] This exemplary embodiment and Figures 1 to 9 The exemplary embodiment shown in FIG. 1 differs from the exemplary embodiment shown in FIG. 1 in the order in which the carry signal of each stage is transmitted, and Figure 5 , Figure 6 and Figure 8 The exemplary embodiment shown in FIG. 1 can be applied to a driving method in a sensing period and a display period for each stage. Therefore, a repeated description will be omitted.

[0278] In the scan driver and the display device including the scan driver according to the present invention, discharge does not occur during a sensing period, and thus the sensing sensitivity can be improved.

[0279] Exemplary embodiments have been disclosed herein, and although specific terms are employed, they are used and interpreted in a general and descriptive sense only, and not for purposes of limitation. In some cases, as will be apparent to those of ordinary skill in the art with the filing of this application, unless otherwise expressly indicated, the features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with the features, characteristics, and / or elements described in conjunction with other exemplary embodiments. Accordingly, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention.

Claims

1. A display device, the display device being driven for at least one frame including a display period and a sensing period, the display device comprising: A pixel unit, wherein the pixel unit includes a plurality of pixels; as well as A scan driver, the scan driver comprising a plurality of stages, each of the plurality of stages being connected to each of the plurality of pixels, the scan line and the sensing line, the scan driver comprising: a first stage including a first output terminal connected to a first carry line, a second output terminal connected to a first scan line, and a third output terminal connected to a first sense line; and a second stage including a first input terminal connected to the first carry line, a fourth output terminal connected to a second scan line, and a fifth output terminal connected to a second sense line, wherein, in the sensing period, during a predetermined delay period before signals having a conduction level are respectively output from the fourth output terminal and the fifth output terminal, signals having a conduction level are respectively output from the first output terminal, the second output terminal, and the third output terminal, and Here, the signal having the on-level output from the first output terminal of the first stage is provided to the first input terminal of the second stage.

2. The display device according to claim 1, wherein: The display period is a period for reproducing an input image on a screen by supplying a data voltage to each of the plurality of pixels, and The sensing period is a period for performing a process of inputting a black data voltage to each of the plurality of pixels, initializing the plurality of pixels, and inputting the black data voltage to the plurality of pixels again after sensing the plurality of pixels.

3. The display device according to claim 2, wherein: The predetermined delay period is a period until a sensing period of stages arranged adjacent to each other starts after the process of inputting the black data voltage again, and is equal to or greater than six horizontal periods, Wherein, one of the horizontal periods is defined by one frame among the at least one frame.

4. The display device according to claim 1, wherein: In the sensing period, the time when the signals having the conduction level are respectively output from the first, second and third output terminals is 20 microseconds before the time when the signals having the conduction level are respectively output from the fourth and fifth output terminals.

5. The display device according to claim 1, wherein: the second output terminal outputting the signal having the on-level in response to a signal supplied from a first scanning clock line connected to the input terminal of the first stage, the third output terminal outputting the signal having the on-level in response to a signal provided from a first sensing clock line connected to the input terminal of the first stage, the fourth output terminal outputs the signal having the on-level in response to a signal supplied from a second scanning clock line connected to the input terminal of the second stage, and The fifth output terminal outputs the signal having the on-level in response to a signal provided from a second sensing clock line connected to the input terminal of the second stage.

6. The display device according to claim 1, wherein: In the sensing period, the second output terminal outputs the signal having the conduction level at least three times before the signals having the conduction level are output from the fourth output terminal and the fifth output terminal, respectively.

7. The display device according to claim 6, wherein: In the sensing period, the conduction level of the signal from the third output terminal is maintained during a period from the time when the second output terminal starts to provide the signal with the conduction level for the first time to the time when the second output terminal ends to provide the signal with the conduction level for the second time.

8. The display device according to claim 1, wherein: In the sensing period, the on-level of the signal from the second output terminal is maintained for six horizontal periods or more or 20 microseconds or more before the signals having the on-level are output from the fourth output terminal and the fifth output terminal, respectively.

9. The display device according to claim 8, wherein: In the sensing period, the first output terminal and the second output terminal respectively output the signal having the conduction level for the same duration.

10. The display device according to claim 1, further comprising: A sensor is connected to each of the plurality of pixels through a receiving line, and measures degradation information of the plurality of pixels according to a received current or voltage.

11. The display device according to claim 10, wherein: The degradation information includes mobility information of the driving transistor, threshold voltage information of the driving transistor, and degradation information of the light emitting device.

12. The display device according to claim 10, wherein: Each of the plurality of pixels comprises: a first transistor including a first gate electrode connected to a first node, a first electrode connected to a first power line, and a second electrode connected to a second node; a second transistor including a second gate electrode connected to the scan line, a third electrode connected to the data line, and a fourth electrode connected to the first node; a third transistor including a third gate electrode connected to the sensing line, a fifth electrode connected to the receiving line, and a sixth electrode connected to the second node; and A light emitting device includes an anode connected to the second node and a cathode connected to a second power line.

13. The display device according to claim 1, wherein: The pixel unit comprises: Display substrate; a plurality of transistors, wherein the plurality of transistors are arranged on the display substrate; a plurality of organic light emitting diodes, the plurality of organic light emitting diodes being arranged on the plurality of transistors; a wavelength conversion pattern, the wavelength conversion pattern being arranged on the plurality of organic light emitting diodes; and A color filter is disposed on the wavelength conversion pattern.

14. The display device according to claim 13, wherein: The wavelength conversion pattern includes quantum dots.

15. The display device according to claim 1, wherein: The scan driver is arranged as an oxide semiconductor thin film transistor gate driver circuit at one side of the pixel unit.

16. The display device according to claim 1, wherein: During the sensing period, the time when the off-level of the signal output from the fourth output terminal and the fifth output terminal respectively changes to the on-level coincides with the time when the on-level of the signal output from the first output terminal, the second output terminal and the third output terminal respectively changes to the off-level.

17. The display device according to claim 1, wherein: The first stage is arranged on the Nth row, and the second stage is arranged on the N+2th row.

18. The display device according to claim 1, wherein: Each of the first stage and the second stage includes an input terminal connected to a first power line, a second power line, and a third power line.

19. The display device according to claim 1, wherein: Each of the first stage and the second stage includes a P-type transistor.

20. A scanning driver, wherein: The scan driver drives at least one frame including a display period and a sensing period, and the scan driver includes: a first stage including a first output terminal connected to a first carry line, a second output terminal connected to a first scan line, and a third output terminal connected to a first sense line; and a second stage including a first input terminal connected to the first carry line, a fourth output terminal connected to a second scan line, and a fifth output terminal connected to a second sense line, wherein, in the sensing period, during a predetermined delay period before signals having a conduction level are respectively output from the fourth output terminal and the fifth output terminal, signals having a conduction level are respectively output from the first output terminal, the second output terminal, and the third output terminal, wherein the predetermined delay period is equal to or less than 20 microseconds, and Here, the signal having the on-level output from the first output terminal of the first stage is provided to the first input terminal of the second stage.

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