Stacked interposer structure and related microelectronic device assembly, method and electronic system

Abstract

The present application relates to stacked interposer structures and related microelectronic device assemblies, methods, and electronic systems. An interposer comprises semiconductor material and includes a cache memory below a location on the interposer for a host device. Memory interface circuitry may also be located below one or more locations on the interposer for a memory device. Microelectronic device assemblies incorporating such an interposer and including a host device and a plurality of memory devices and methods of making such microelectronic device assemblies are also disclosed.

Description

[0001] Priority claim

[0002] This application claims the benefit of the filing date of U.S. patent application serial number 16 / 715,242 filed on December 16, 2019 for "Stacked Interposer Structures, Microelectronic Device Assemblies Including Same, and Methods of Fabrication, and Related Electronic Systems." Technical Field

[0003] Embodiments disclosed herein relate to stacked interposer structures and microelectronic device assemblies including such stacked interposer structures and methods of manufacturing such structures and assemblies. More particularly, embodiments disclosed herein relate to assemblies including stacked interposer structures, each interposer including semiconductor material and incorporating interface functionality for mutual high-bandwidth communication between microelectronic devices operably coupled to the stacked interposer structures, to assemblies of such microelectronic devices incorporating stacked interposer structures, to methods of manufacturing such structures and assemblies, and to related electronic systems. Background Art

[0004] Many forms of microelectronic devices, such as IC (integrated circuit) assemblies, include multiple semiconductor dies (also referred to herein as "dies") or an assembly of such dies that are physically and electrically connected to each other through an interposer. In some cases, such an assembly on an interposer may be referred to as a "multi-chip package" or "MCP". In some embodiments, the interposer may include a redistribution structure (sometimes referred to in the art as a "redistribution layer" or "RDL", as discussed further below) configured to establish interconnections between two or more of the multiple dies within the assembly, and also facilitate electrical and mechanical attachment to other devices (e.g., a printed circuit board such as a motherboard or other higher-level packaging).

[0005] Such an RDL may include one or more dielectric layers, each dielectric layer supporting levels of conductive material that define conductive traces and vias that extend through respective dielectric layers to connect directly or indirectly with respective contacts on one or more semiconductor dies and / or to connect with vias in other layers of the RDL to reroute the die contacts to other locations on or within the interposer.

[0006] The interposer may be constructed with a core structure comprising a non-organic material, such as a semiconductor material, such as silicon (commonly referred to as a "silicon interposer"), or any one (or more) organic materials (commonly referred to as an "organic interposer"). The term "semiconductor interposer" is used herein to identify an interposer that includes (e.g., has a core formed therefrom) a semiconductor material, which may be an elemental material (e.g., silicon, germanium, selenium, etc., as known to those skilled in the art), a compound semiconductor material (e.g., gallium arsenide, indium gallium arsenide, also as known to those skilled in the art). The term "non-organic interposer" is used to identify a core formed of a non-organic material, which may be, for example, a semiconductor material, a glass material, and / or a ceramic material. For the purpose of providing examples herein, embodiments of the disclosed semiconductor interposer will be described in the form of a silicon interposer.

[0007] Under conventional processing, organic interposers tend to be more resilient and therefore more resistant to cracking or other damage caused by physical or thermal stresses. However, resistance to physical or thermal stresses is offset to some extent by the organic interposer, which typically has a coefficient of thermal expansion ("CTE") significantly different from that of the semiconductor die or die assembly attached to the interposer and is therefore susceptible to physical stress at the die attachment. In addition, commercially viable techniques for forming organic interposers encounter difficulties in providing line spacings less than about 10 / 10 μLS. This current practical limit leaves a significant size gap relative to the feature spacing achievable in conventional silicon processing employed in the manufacture of state-of-the-art semiconductor dies. Therefore, current commercially viable processes for forming organic interposers are unable to match the minimum contact spacing of the semiconductor die that is expected to be attached to the interposer, thereby imposing undesirable constraints on the substrate area required for the microelectronic device assembly and requiring undesirably long signal paths.

[0008] In addition, interposer performance characteristics are becoming increasingly important for implementing some high-bandwidth applications. One example of a microelectronic assembly disclosed herein includes high-bandwidth communications between one or more high-bandwidth memory (HBM) devices and a processor. Although each memory device may be an individual semiconductor die, it is becoming increasingly common for each memory device to include a vertical stack of multiple (e.g., four, eight, twelve, sixteen, etc.) memory dies interconnected by through-silicon vias (TSVs) and inter-die conductive elements (e.g., copper pillars operably coupled to the TSVs). In some cases, the stack further includes an operably coupled logic die, which may also be characterized as a controller or interface die. To obtain the full performance benefits of such multi-chip memory devices, the associated processor must be able to access multiple portions of the interconnected memory dies in parallel through high-speed parallel communication channels between the processor and the multi-die memory devices for data, command, and control signals.

[0009] To meet the design criteria for such high-speed parallel communications, which include, but are not limited to, minimizing conductive trace resistance and inter-trace capacitance, it is expected that the interposer will require a tighter line spacing ("L / S") of less than 5 / 5 μLS and preferably about 2 / 2 μLS or less. A semiconductor interposer, such as a silicon interposer, can be configured to provide this L / S capability because it can be manufactured using conventional semiconductor die manufacturing methods.

[0010] Although the use of semiconductor material-based interposers solves the above problems, as described above, in the implementation of HBM devices, the conventional practice is to use a discrete interface die between the stack of memory dies and the interposer of each HBM device. This approach increases manufacturing and assembly costs, lengthens signal paths, and increases the height of the HBM device assembly.

[0011] In addition to the above-mentioned considerations regarding the desirability of using semiconductor (e.g., silicon) materials to implement the interposer, utilizing semiconductor materials may also facilitate the reduction of cost and size of certain processor classes, such as graphics processing units (GPUs). It has been proposed that GPU designs monolithically integrate cache memory in the form of static random access memory (SRAM). Unfortunately, this approach would suffer from the requirement to incorporate TSVs in the GPU, but the manufacture of SRAM cache memory requires a significantly different process sequence than that employed in GPU manufacture. In addition, due to the memory component structure of SRAM, it may consume an undesirable amount of space in the GPU. Other processors such as central processing units (CPUs), controllers, and so-called systems on a chip (SoCs), as well as other host devices, may also suffer from a somewhat awkward integration of cache memory circuitry with processor circuitry manufacturing techniques. Summary of the invention

[0012] In an embodiment, a stacked interposer structure includes a first interposer including: a first core including semiconductor material; a first redistribution structure including a plurality of redistribution layers (RDLs) over a side of the first core; and a first set of through-silicon vias (TSVs) extending from the first redistribution structure through the first core to an opposite side of the first core; and a second interposer including: a second core including semiconductor material; a second redistribution structure including a plurality of redistribution layers (RDLs) over a side of the second core; and a second set of through-silicon vias (TSVs) extending from the second redistribution structure through the second core to an opposite side of the second core. The first redistribution structure and the second redistribution structure are operably coupled by at least one of the first set of TSVs and the second set of TSVs.

[0013] In an embodiment, a microelectronic device assembly includes a stacked interposer structure, which includes a plurality of interconnected interposers, each interposer having a semiconductor core and a redistribution structure on one side thereof; at least one host device and at least one memory device, which are mounted on and operably coupled to the redistribution structure of one of the plurality of interconnected interposers; and a circuit system of the stacked interposer structure, which is operably coupled to the at least one host device and the at least one memory device and extends to a side of the stacked interposer structure opposite to the at least one host device and the at least one memory device for connection to a higher level package.

[0014] In an embodiment, an interposer includes a silicon core comprising; at least one of an active circuit system and a passive circuit system above an active surface of the silicon core; a redistribution structure including at least four redistribution layers (RDLs) located above the active circuit system and the passive circuit system; and a through-silicon via (TSV) operably coupled to at least the redistribution structure and extending through the silicon core to a side thereof opposite the redistribution structure.

[0015] In an embodiment, a stacked interposer structure includes two interposers, one interposer is stacked on top of the other interposer and each has a redistribution structure including a plurality of redistribution layers (RDLs) operably coupled via TSVs extending through a semiconductor core of at least one of the two interposers; the redistribution structure of one of the two interposers, which is configured for operably coupling to a host device and a memory device; and the redistribution structure of each of the two interposers, which includes different conductive paths, which are configured to be operably coupled in combination to cooperatively act as a single redistribution structure including a combined number of multiple redistribution layers of the two interposers.

[0016] In an embodiment, an electronic system includes an input device, an output device, and the electronic system further includes: a processor device and at least one memory device, which are operably coupled to a redistribution structure of an interposer including a semiconductor core, the redistribution structure of the interposer is operably coupled to another redistribution structure of another interposer at least through a through-silicon via (TSV) extending from the redistribution structure of the interposer through the semiconductor core to a side thereof opposite to the redistribution structure, and the input device and the output device are operably coupled to the processor through a conductive path of the other interposer.

[0017] In an embodiment, a method includes providing two interposers, each having a redistribution structure including a plurality of redistribution layers (RDLs) above a semiconductor core, conductive paths of the plurality of redistribution layers (RDLs) of the redistribution structure being cooperatively configured to act as a single redistribution layer consisting of a total number of redistribution layers (RDLs) of the two interposers; and electrically connecting the conductive paths of the redistribution layers (RDLs) of the two interposers via TSVs extending through at least one of the semiconductor cores. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1A is a schematic perspective view of a microelectronic assembly including a host device in the form of a processor and a plurality of memory devices mounted to a stacked interposer structure in accordance with an embodiment of the invention;

[0019] Figure 1B A system comprising a plurality of memory devices and a processor supported on and operably coupled to a stacked interposer structure Figure 1A A schematic top view of a microelectronic device assembly;

[0020] Figure 1C According to an embodiment of the present invention Figure 1A and Figure 1B Schematic side view of a microelectronic device assembly depicting a stacked interposer structure mounted to a laminate substrate having conductive elements on opposite sides thereof for connection to a higher level package Figure 1A and 1B Components;

[0021] Figure 1D According to an embodiment of the present invention Figure 1A and Figure 1B Schematic side view of a microelectronic device assembly depicting a stacked interposer structure having no laminate substrate, a conductive element on its side opposite the microelectronic device for connecting to a higher level package Figure 1A and Figure 1B Components;

[0022] Figure 1E The HBM is a HBM cube that contains multiple memory dies stacked on an interface circuitry section integrated in an interposer. Figure 1A A schematic perspective view of a memory device;

[0023] Figure 2 is a schematic side cross-sectional view of an interposer including a semiconductor core according to an embodiment of the present invention;

[0024] Figures 3A to 3Care schematic side views of two cooperatively configured interposers having semiconductor cores, the two interposers are stacked together to form a stacked interposer structure, and a microelectronic device assembly includes a memory device and a host device according to an embodiment of the present invention;

[0025] Figures 3D to 3F are schematic side views of two cooperatively configured interposers having semiconductor cores, the two interposers are stacked together to form a stacked interposer structure, and a microelectronic device assembly includes a memory device and a host device according to an embodiment of the present invention;

[0026] Figure 4 is a schematic diagram of an embodiment of a microelectronic device assembly incorporating a stacked interposer structure according to an embodiment of the present invention;

[0027] Figure 5 is a simplified cross-sectional representation of an example cross-section of an embodiment of an interposer having a semiconductor core and incorporating logic structures according to an embodiment of the present invention; and

[0028] Figure 6 Block diagram of an electronic system incorporating a microelectronic device assembly according to an embodiment of the invention. DETAILED DESCRIPTION

[0029] Embodiments of the present invention encompass stacked interposer structures whose interposers can be cooperatively configured for effectively providing such high bandwidth communications in combination while reducing manufacturing and assembly costs and reducing component and assembly size. Microelectronic device assemblies incorporating such stacked interposer structures and methods for manufacturing such assemblies can provide advantages in terms of reduced cost, improved yield, and enhanced performance.

[0030] One example of a microelectronic device assembly proposed to address the above-mentioned problems would include a host device (e.g., a GPU) and a memory device, such as a high bandwidth memory device, including multiple stacked memory dies, all mounted to an interposer including a semiconductor material (e.g., silicon), which may be characterized as a "core". The interposer would in turn be mounted and operably coupled to a laminated (e.g., organic) substrate for connecting the microelectronic device assembly to a higher level package through discrete conductive elements, such as in the form of balls, bumps, or pillars composed of metallic materials. The GPU would have an integrated SRAM cache, which, as noted above, presents manufacturing issues and necessitates the use of TSVs in the GPU. The microelectronic device assembly would have the memory device located above and operably coupled to an interface die, which is operably coupled to circuitry carried by the interposer, through which the circuitry memory die of the memory device would communicate with the host device. The TSVs extending through the interposer will in turn communicate with the laminate substrate, which may include multiple levels of circuitry separated by dielectric materials, and which will be operably coupled to discrete conductive elements on its side opposite the interposer for connection to external circuitry.

[0031] Another example of a microelectronic device assembly proposed to address the above-mentioned problems would employ an interposer comprising a core of semiconductor material (e.g., silicon) with RDLs located on opposite sides of the interposer, each RDL having multiple (e.g., four or more) conductive trace layers to meet the high-speed, high-capacity signal requirements of HBM designs, and more particularly HBMx (also referred to as HBM2, HBM2e, HBM3, and HBM4) designs, incorporating a stack of memory (i.e., DRAM die) and a host in the form of a graphics processor unit (GPU) or a central processor unit (CPU). Applications for such proposed designs would include graphics, client, server, networking, and high-performance computing. However, the fabrication of silicon interposers carrying back-to-back RDLs presents issues in terms of process cost, complexity, and quality control.

[0032] Semiconductor (eg, silicon) interposer structures comprising a plurality of stacked interposers, as well as microelectronic device assemblies including such interposer structures, and methods of making such assemblies are disclosed.

[0033] The following description provides specific details, such as size, shape, material composition, and orientation, in order to provide a thorough description of embodiments of the present invention. However, those skilled in the art will understand that embodiments of the present invention may be practiced without necessarily adopting these specific details. Embodiments of the present invention may be practiced in conjunction with conventional manufacturing techniques used in the industry. In addition, the description provided below does not form a complete process flow for manufacturing HBM devices, silicon interposer structures, GPUs, CPUs, or other processors, or microelectronic device assemblies including HBM devices, GPUs, CPUs, or other processors and silicon interposer structures. Only those process actions and structures necessary for understanding embodiments of the present invention are described in detail below. Additional actions to form complete HBM devices, silicon interposer structures, GPUs, CPUs, or other processors, or microelectronic device assemblies including the above may be performed by conventional manufacturing processes known to those skilled in the semiconductor and electronics industries.

[0034] The drawings presented herein are for illustrative purposes only and are not intended to be actual views of any particular material, component, structure, device, or system. Variations in the shapes depicted in the drawings due to, for example, manufacturing techniques and / or tolerances may be expected. Therefore, the embodiments described herein should not be interpreted as being limited to the specific shapes or regions described, but rather include shape deviations, such as those caused by manufacturing. For example, a region described or described as a box shape may have rough and / or nonlinear features, and a region described or described as a circle may include some rough and / or linear features. In addition, the sharp angles between the surfaces described may be rounded, and vice versa. Therefore, the regions described in the drawings are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions, and do not limit the scope of the claims. The drawings are not necessarily drawn to scale.

[0035] As used herein, the terms "comprising," "including," "containing," "characterized by," and their grammatical equivalents are inclusive or open-ended terms that do not exclude additional, unrecited elements or methodological actions, but also encompass the more restrictive terms "consisting of," and "consisting essentially of," and their grammatical equivalents. As used herein, the term "may," with respect to a material, structure, feature, or methodological action, indicates that it is contemplated for use in practicing an embodiment of the invention, and this term is used in preference to the more restrictive term "are" in order to avoid any suggestion that other, compatible materials, structures, features, and methods that may be used in combination therewith should or must be excluded.

[0036] As used herein, the terms "longitudinal", "vertical", "lateral", and "horizontal" refer to a major plane of a substrate (e.g., a base material, a base structure, a base construction, etc.) in or on which one or more structures and / or features are formed, and are not necessarily defined by the Earth's gravitational field. A "lateral" or "horizontal" direction is a direction substantially parallel to the major plane of the substrate, while a "longitudinal" or "vertical" direction is a direction substantially perpendicular to the major plane of the substrate. The major plane of a substrate is defined by a surface of the substrate having a relatively large area compared to other surfaces of the substrate.

[0037] As used herein, for ease of description, spatially relative terms such as "below", "under", "lower", "bottom", "above", "over", "upper", "top", "front", "back", "left", "right", and the like may be used to describe the relationship of one element or feature to another element or feature as illustrated in the drawings. Unless otherwise stated, spatially relative terms are intended to encompass different orientations of material other than the orientation depicted in the drawings. For example, if the material in the drawings is inverted, an element described as being "above" or "over" or "on" or "on top" of other elements or features would be oriented as being "below" or "below" or "below" or "on bottom" of the other elements or features. Thus, the term "above" may encompass both the above and below orientations, depending on the context in which the term is used, as will be apparent to one of ordinary skill in the art. The material may be otherwise oriented (e.g., rotated 90 degrees, inverted, flipped), and the spatially relative descriptors used herein interpreted accordingly.

[0038] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0039] As used herein, the terms "configured" and "configuration" refer to the size, shape, material composition, orientation, and arrangement of one or more of at least one structure and at least one device to facilitate operation of one or more of the structures and devices in a predetermined manner.

[0040] As used herein, the term "substantially" with reference to a given parameter, property, or condition means and encompasses, to the extent that one of ordinary skill in the art would understand, that the given parameter, property, or condition is met with a certain degree of variance, such as being met within an acceptable tolerance. By way of example, depending on the particular parameter, property, or condition that is substantially met, the parameter, property, or condition may be at least 90.0% met, at least 95.0% met, at least 99.0% met, or even 100.0% met.

[0041] As used herein, "about" or "approximately" with reference to a numerical value of a particular parameter includes the numerical value and the degree of deviation from the numerical value that would be understood by one of ordinary skill in the art to be within an acceptable tolerance for the particular parameter. For example, "about" or "approximately" with reference to a numerical value may include additional numerical values ​​within the range from 90.0% to 110.0% of the numerical value, such as within the range from 95.0% to 105.0% of the numerical value, within the range from 97.5% to 102.5% of the numerical value, within the range from 99.0% to 101.0% of the numerical value, within the range from 99.5% to 100.5% of the numerical value, or within the range from 99.9% to 100.1% of the numerical value.

[0042] As used herein, the terms "layer" and "film" mean and include a layer, sheet or coating of material residing on a structure, which layer or coating may be continuous or discontinuous between portions of the material and which may be conformal or non-conformal, unless otherwise indicated.

[0043] As used herein, the term "substrate" means and includes a base material or structure on which additional materials are formed. The substrate may be a semiconductor substrate, a base semiconductor layer on a support structure, a metal electrode, or a semiconductor substrate on which one or more materials, layers, structures, or regions are formed. The materials on the semiconductor substrate may include, but are not limited to, semiconductor materials, insulating materials, conductive materials, etc. The substrate may be a conventional silicon substrate or other bulk substrate including a semiconductor material layer. As used herein, the term "bulk substrate" means and includes not only silicon wafers, but also silicon-on-insulator ("SOI") substrates, such as silicon-on-sapphire ("SOS") substrates and silicon-on-glass ("SOG") substrates, epitaxial layers of silicon on a base semiconductor foundation, and other semiconductor or optoelectronic materials, such as silicon germanium, germanium, gallium arsenide, gallium nitride, and indium phosphide. The substrate may be doped or undoped.

[0044] As used herein, the terms "comprising," "including," "containing," "characterized by," and their grammatical equivalents are inclusive or open terms that do not exclude additional, unrecited elements or method steps, and also encompass the more restrictive terms "consisting of," and "consisting essentially of," and their grammatical equivalents.

[0045] As used herein, the term "may" with respect to a material, structure, feature, or method act indicates that it is intended to be used to implement an embodiment of the invention, and this term is used in preference to the more restrictive term "is" so as to avoid any suggestion that other, compatible materials, structures, features, and methods that may be used in combination therewith should or must be excluded.

[0046] The following description and drawings sufficiently illustrate specific embodiments to enable those skilled in the art to practice them. Other embodiments may incorporate structural, logical, electrical, process and other changes. Portions and features of some embodiments may be included in or replace portions and features of other embodiments. The embodiments set forth in the claims encompass all available equivalents of the claims.

[0047] As described in more detail below, the specification describes various embodiments of a stacked interposer structure including a plurality of vertically stacked interposers. Embodiments include various configurations of stacked interposers, each interposer of the stack including a semiconductor core, such as a silicon core, and carrying a redistribution structure on one side thereof. In embodiments, the redistribution structure includes a plurality of individual redistribution layers. In some embodiments, the plurality of individual redistribution layers may be implemented to provide high bandwidth communication capabilities between microelectronic devices connected through the interposers.

[0048] Additionally, the specification describes the incorporation of circuit elements, including active and passive circuit elements, that may be formed in an interposer. In some embodiments, the active and passive circuit elements will be at least partially formed in a semiconductor core. In some examples, the circuit elements may have one or more bodies formed within the semiconductor core and one or more bodies formed in a material structure formed above the semiconductor core.

[0049] Reference will now be made in more detail to the drawings and in particular to Figures 1A to 1E . Figure 1A A simplified representation of an embodiment of a microelectronic device assembly 100 is depicted that includes a processor 102 and a plurality of memory devices 104A, 104B, 104C, 104D connected to an assembly of stacked interposers 106A and 106B, each interposer 106A and 106B including semiconductor material (e.g., silicon) according to one or more of the configurations described herein.

[0050] As will be apparent to one skilled in the art, processor 102 may be any of a number of configurations of a processor (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a controller), a system on a chip (SoC), or some other form of host device. Memory devices 104A, 104B, 104C, 104D may be of the same or different forms; and any of the memory devices may be a single die or a stack of interconnected memory dies, as described with reference to FIG. Figure 1E Discuss in more detail. Figure 1A104A, 104B, 104C, 104D as a stack of multiple memory dies 108A-108H. In some embodiments, the memory devices 104A-104D coupled to the stacked interposers 106A and 106B may all have a considerable height. Non-limiting examples of existing memory devices 104A-104D include JEDEC standard HBM memory devices and hybrid memory cube (HMC) memory devices, both of which include multiple vertically stacked DRAM dies. However, HMC memory devices employ TSV-equipped logic dies, while HBM memory devices do not employ such logic dies.

[0051] Processor 102 may exchange information with one or more of memory devices 104A, 104B, 104C, 104D using signals communicated through signal paths at least partially formed within and between interposers 106A and 106B. Such signal paths include paths that messages or transmissions may take when communicating from a transmitting component to a receiving component. In some cases, a signal path may be a conductor coupled to at least two components, wherein the conductor allows electrons to flow between at least two components. In some cases, a signal path may be at least partially formed in a wireless medium, such as in the case of wireless communications (e.g., radio frequency (RF) or optical). In some examples, stacked interposers 106A and 106B will be coupled to an external structure (e.g., a package substrate, a motherboard, etc.) to form part of a larger system.

[0052] In some applications, the microelectronic device assembly 100 may benefit from a high-speed connection between the processor 102 and one or more of the memory devices 104A, 104B, 104C, 104D. Thus, in some examples, one or more of the memory devices 104A, 104B, 104C, 104D will support applications, processes, or processors with bandwidth requirements of several terabytes per second (TB / s). Such applications may include a serializer / deserializer ("SerDes") between memory and a processor or other logic device that requires high bandwidth. Meeting this bandwidth constraint within an acceptable energy budget may present challenges in certain contexts.

[0053] The memory devices 104A, 104B, 104C, 104D and interposers 106A and 106B may be configured so that the signal paths between the memory cells in the memory devices 104A, 104B, 104C, 104D and the processor 102 are as short as the material properties, operating environment, component layout, and application allow. For example, the memory devices 104A, 104B, 104C, 104D may be unbuffered memory devices with point-to-point connections between the host device and the memory array. In other examples, the data channels coupling the memory devices 104A, 104B, 104C, 104D and the processor 102 may include a point-to-many configuration in which one pin of the processor 102 is coupled to corresponding pins of at least two memory arrays (which may be located in the same or different memory dies 108A-108H and / or memory devices 104A-104D).

[0054] Many interposers may be formed to have layers configured to interface with multiple devices (e.g., Figure 1A 104A-104D). For purposes of this description, each of the depicted devices is coupled to an interposer 106A at a respective mounting site; and at each mounting site the interposer 106A includes one or more contact arrays arranged and configured to engage complementary contact arrays on each of the processor 102 and the memory devices 104A-104D. A second interposer 106B is stacked below the interposer 106A and, in cooperation with the interposer 106A, serves as a unit for signal communication between the processor 102, the memory devices 104A-104D, and higher-level packages.

[0055] Figure 1B Depiction Figure 1A A top view of one embodiment of a microelectronic device assembly 100 of FIG. Figure 1C A schematic side view is depicted. As shown, memory devices 104A-104D are located at peripheral sites on interposer 106A on laterally opposite sides of processor 102, which in this example includes, for example, a GPU. Optionally, and as shown in Figure 1B As shown in the dashed lines in FIG. 1 , within the boundaries of processor 102, a cache memory in the form of SRAM 140 has been fabricated above the active surface of the silicon of interposer 106A to reside beneath processor 102, and is supported by back-end of line (BEOL) structures B ( Figure 1C) circuit traces operably couple processor 102 to memory devices 104A-104D, through interposer 106B cooperatively configured and operably coupled to memory devices 104A-104D and to circuitry external to microelectronic device assembly 100. However, such a memory configuration is not essential to implementation of embodiments of the present invention, and as described above, cache memory may be incorporated into or reside below the GPU. BEOL structure B includes multiple layers, each of which includes a level of dielectric material and conductive traces, the various conductive levels being vertically interconnected, as is known to those of ordinary skill in the art, and may serve as a redistribution structure, as further described below. Similarly, as Figure 1B , in dashed lines adjacent the boundaries of each memory device 104A-104D, interface circuitry sections 120A-120D have been fabricated above the active surface of the silicon of interposer 106A to reside directly beneath the location of each of the memory devices 104A-104D, respectively, and operably couple the memory devices 104A-104D to the processor 102 through conductive traces of BEOL structure B. The circuitry of interposer 106A is operably coupled to the circuitry of interposer 106B, which in turn may optionally be coupled to the circuitry of laminate substrate 106L through TSVs extending through interposers 106A and 106B, the circuitry of laminate substrate 106L being operably coupled to discrete conductive elements 110 for connection to higher level packaging. Interposer 106B includes a redistribution structure fabricated by BEOL processing and comprising a plurality of redistribution layers (RDLs), each RDL comprising a level of dielectric material and conductive traces operably coupled to conductive paths of BEOL structure B via TSVs.

[0056] Figure 1D Depiction Figure 1A A side view of another embodiment of a microelectronic device assembly 100 is shown. Figure 1D , the laminate substrate is omitted from the assembly, and instead, the interposer 106B is operatively coupled to the discrete conductive elements 110 for connection to a higher level package. Each interposer 106A, 106B includes a redistribution structure RS including a plurality of redistribution layers (RDL), each RDL including a layer of dielectric material and conductive traces. In one embodiment (not shown), Figure 1D ), the redistribution structure RS of the interposer 106B faces away from the interposer 106A and carries the discrete conductive elements 110 on the under bump metallization (UBM), as known to those skilled in the art. Figure 1DAs shown in , the redistribution structure RS of interposer 106B faces interposer 106A, and discrete conductive elements 110 for connecting to a higher level package are operably coupled to TSVs extending from the redistribution structure RS through the core of the semiconductor material of interposer 106B for connecting to the higher level package.

[0057] exist Figures 1A to 1D In an embodiment of the present invention, it will be apparent to a person of ordinary skill in the art that a cache memory in the form of SRAM is optionally placed in close proximity to and directly beneath the GPU to reduce signal lengths and latency, while relieving the GPU of the SRAM burden that would otherwise consume valuable real estate and simplifying the processor design.

[0058] Figure 1E Depicts a device suitable for use as memory devices 104A to 104D for Figure 1A 1. An example memory device 118 in a microelectronic device assembly 100 of FIG. 1. As an example, the memory device 118 includes eight individual memory dies 108A-108H that are vertically stacked and interconnected. As previously described, the memory device 118 may include only a single memory chip, or any other number of stacked memory dies, such as two memory dies, four memory chips, and / or more than eight memory dies, such as twelve, sixteen, thirty-two, or sixty-four memory dies.

[0059] One example structure for forming vertical interconnects includes a plurality of through-silicon vias ("TSVs"). Although the term "through-silicon via" ("TSV") is taken to literally imply a via extending through a silicon body, the term is conventionally used in the art to refer to vertical interconnects that extend through not only silicon and not only semiconductors, but also to vertical interconnects that extend through other materials. The term is used herein in a broader sense, and as used herein does not imply that the vias described may extend only through a silicon body.

[0060] Each memory die 108A-108H includes a plurality of memory cells that can be programmed to store different logic states. For example, each memory cell can be programmed to store one or more logic states (e.g., logic '0', logic '1', logic '00', logic '01', logic '10', logic '11'). The memory die can store data using one or more different memory technologies, including DRAM, SRAM, ferroelectric RAM (FeRAM), resistive RAM (RRam or ReRAM), phase change memory (PCM), 3D XPoint TM memory, NAND flash memory, NOR flash memory, or other memory technologies known to those skilled in the art, and / or combinations thereof.

[0061] In a memory device such as 118, all stacked memory dies may implement a first memory technology (e.g., DRAM); or alternatively, one or more of the stacked memory dies may include memory cells of a different memory technology than the first memory technology. Alternatively, any of the above types of memory devices may be stacked in combination within memory device 118.

[0062] Additionally, memory device 118 depicts a configuration in which stacked memory dies are stacked on top of interface circuitry sections 120A-120D of interposer 106A. Interface circuitry sections 120 may be any of a number of different configurations, and when present, may implement logic functions related to the operation or management of memory dies of memory devices 104A-104D stacked on associated interface circuitry sections 120A-D. Interface circuitry sections 120A-120D interface with other circuitry of interposer 106A and interposer 106B, as well as through BEOL structure B ( Figure 1C ) to interface with processor 102. In some embodiments, lowermost memory die 108A will include contacts 126, which may include, for example, conductive pillars or microbumps, for interfacing with associated interface circuitry sections 120A-120D. In many examples, contacts 126 will be arranged in one or more arrays configured to engage respective device mounting sites of contacts 128 of interface circuitry sections 120A-120D including interposer 106A.

[0063] In some examples, the vertically interconnected memory dies 108A to 108H may be interconnected by an array of TSVs that extend substantially linearly and vertically through the stacked memory dies 108 to 108H (although not necessarily through the topmost stacked memory die 108H), as depicted at 122A, 122B, 122C, 122D, 122E. In one of many alternative configurations, some TSVs through individual dies may be cross-connected to interleave the vertical connections through the stacked memory dies. For example, in one such embodiment, as depicted, the conductive paths may alternate between TSV paths in alternating dies within the stack, as schematically depicted at 124 in conductive paths 122F to 122G. Other more complex interleaved conductive paths may also be implemented. In some examples, one or more of the conductive paths will be connected to each of the stacked memory dies, while in other examples, the vertical conductive paths may only be electrically connected to communicate with other circuit systems in a subset of the stacked memory dies. For example, in the context of memory device 118, some TSVs may extend directly through the bottommost memory die 108A-108D without connecting to other circuitry, and only make electrical interconnections with circuitry in the upper half of stacked memory die 108E-108H. In other examples, TSVs may only make electrical connections with alternating die within a stack of memory dies.

[0064] In addition, individual memory dies 108A to 108H or a portion thereof may each contain multiple partitions (as indicated at 130A to 130H on memory die 108H). Some or all of memory dies 108A to 108H may be similarly partitioned. These partitions (or some subset thereof) may be vertically interconnected with corresponding partitions of other memory devices in the stack through the vertical connections discussed above, thereby forming independently operable memory units. In some examples, a storage unit may include two or more vertically aligned partitions; and in some examples, may include vertically aligned partitions from all memory dies in the stack. As indicated in partition 130A, each partition may be further subdivided into multiple memory banks or other subdivisions, such as individual memory channels. As an example, four memory banks (as indicated at 132A to 132D, defining four memory banks) are formed within partition 130A, wherein each memory bank includes additional subdivision units, such as representing individual memory channels (generally indicated at 134). In some examples, these further subdivisions will be interconnected vertically in the same manner as described for partitioning to include portions of memory in multiple or all memory dies in the stack, which can then be operated as a group.

[0065] Reference now Figure 2, the figure depicts a simplified cross-sectional representation of an embodiment of an interposer 200 suitable for implementing an embodiment of the present invention of an assembly including a memory and a host device (e.g., a processor). The interposer 200 includes a semiconductor core, which for the purposes of this example is described as a silicon core 202 having a plurality of TSVs 204 extending through the silicon core 202. As known to those skilled in the art, the TSVs 204 each include a conductive structure, typically a metal, extending within an insulator that isolates the conductive structure from the surrounding silicon. By utilizing the silicon core 202, the TSVs can be arranged at tighter spacings than can be achieved with current organic interposer technology. In some examples, for example, the TSVs can be arranged at a pitch of 40 μm or less, such as a pitch of approximately 20 μm. In many examples, the pitch of at least some portions of the TSVs will be sized to match the contact pitch of a semiconductor die or other device coupled to the interposer 200. In such examples, the contact pitch of the TSVs can correspond to the contact pitch of the die or other device coupled to the interposer 200. In the depicted example, a conductive level (designated M1) extends "above" the side of the core 202, with the conductive level M1 being electrically insulated from the core 202 by a corresponding dielectric level 208A (which may include one or more dielectric materials). The term "above" is used in this specification for clarity, and refers to a material or level being relatively outward from the core 202. As one skilled in the art will recognize, materials and structures to one side of the core will typically be formed at different times during which the corresponding side of the core over which the material is formed will be oriented upward. Similarly, the term "below" is used herein to indicate that a structure is closer to the core.

[0066] In many instances, the conductive level M1 will be patterned to define conductive traces 210, at least some of which will be interconnected to respective TSVs 204, as depicted. Some conductive traces 210 may not be connected to respective TSVs, and may simply provide interconnections for conductive traces formed above the conductive level M1. The term "redistribution layer" or "RDL" is sometimes used in the industry to refer to a single level of a multi-level structure, and sometimes to the multi-level structure itself, in a variety of contexts. Herein, for clarity, the term "redistribution layer" or "RDL" is used to refer to respective dielectric layers that support respective metal layers (as discussed below); and the term "redistribution structure" will be used to refer to a plurality of superimposed individual RDLs as a group. The redistribution structure as described herein may be manufactured using BEOL techniques known to those of ordinary skill in the art, and may correspond in structure and function to the multi-level structure described previously herein. Figures 1B to 1D Described BEOL structure B.

[0067] A first redistribution structure 214 may be formed over the first side of the core 202. The redistribution structure 214 includes a plurality of respective redistribution layers (RDLs). Each of the plurality of RDLs, in the example, the redistribution structure 214 includes four RDLs, although the number of RDLs is not limited thereto, and it is conceivable that a greater number of RDLs (e.g., six RDLs) may be employed in the redistribution structure to accommodate power and bias (e.g., grounding) as well as signal transmission. In the redistribution structure 214, RDLs 218, 220, 222, 224 extend over the first side of the core 202 and the metal layer M1 formed thereon. Each RDL includes a respective dielectric level 226, 228, 230, 232, each dielectric level 226, 228, 230, 232 supporting a respective metal (or other conductive material) level M2, M3, M4, M5. Each metal level M1-M5 will preferably be patterned to collectively form conductive traces to redistribute contacts of a semiconductor die or other microelectronic device or structure mounted to interposer 200 to desired locations within interposer 200. Of course, as described above, the redistribution layers in the form of four RDLs are merely examples, and a different number of RDLs may be employed.

[0068] In some examples, all metal levels M1 to M5 may be formed of the same metal. However, in other examples, the outermost metal level M5 will typically form a surface for connecting (directly or through an interconnect structure) with a complementary contact structure of another device. In the case of the outermost metal level M5, the level will form a surface suitable for connecting with contacts of a semiconductor die or other microelectronic device. Due to the different functions of these metal layers and the potential exposure of the metals to a potential oxidizing environment after formation, in some examples, one or both of the outermost metal levels may be formed of another conductive material that oxidizes much slower than the metals used for the other levels. For example, for an example in which the metal levels M1 to M4 are formed of copper, the outermost metal level M5 may be formed of aluminum. As will be apparent to those skilled in the art having the benefit of the present invention, other conductive materials and / or other metals may be used for one or more of the conductive levels corresponding to the metal levels M1 to M5.

[0069] In many instances, the dielectric levels of the RDL will primarily or mostly comprise polyimide compounds. In general, polyimide compounds are more resilient and less susceptible to cracking than other dielectric materials used elsewhere in semiconductor manufacturing (e.g., silicon oxide (in various forms), silicon nitride, etc.). Additionally, polyimide materials may be formed at lower temperatures than other materials used in build-up applications, thereby minimizing stress on the core 202 during fabrication of the interposer 200.

[0070] Interposer 200 may further include circuitry 280 formed within the dimensions of core 202. In some embodiments, circuitry 280 may include passive components (e.g., resistors, inductors, capacitors) that may be formed at least partially in the bulk semiconductor (silicon) of core 202. In other examples, the components may be formed at least partially of materials deposited in recesses formed in core 202. In some examples, the passive components may be formed entirely within the dimensions of the core. In such examples, individual circuit elements may connect the exterior of the core through interconnects to one or more microvias 282 extending through core 202, or through one or more TSVs formed as part of M1 formed above the upper surface of core 202, and extending through dielectric level 208A above the first surface of core 202. In some cases, multiple passive components may be connected to each other. For example, resistors and capacitors may be coupled together to form a resistor / capacitor circuit. As one example, such a resistor / capacitor circuit or inductor may be coupled and adapted to condition a signal on a conductive trace extending through one or more of the RDL layers of the redistribution structure 214 .

[0071] In embodiments of the invention, active circuit components may be located within the dimensions of core 202. Many forms of circuitry including active components will advantageously be formed from one or more bodies within the bulk silicon of core 202, with one or more additional bodies formed in material extending above core 202. In many forms of such devices, regions of silicon core 202 may be isolated from one another by shallow trench isolation in silicon core 202; and the isolated regions of silicon core 202 may be doped relative to the remaining silicon of silicon core 202. Specifically, and as described above, interface circuitry sections 120A-120D may be formed within or above core 202. Additionally, as described with respect to Figures 1A to 1D As described above, a cache memory in the form of SRAM may be formed at least partially within or above core 202 beneath the footprint of processor 102 .

[0072] Continue to refer Figure 2 , TSVs 204 extend from metal layer M1 through core 202 of interposer 200 for connecting individual circuit elements external to core 202, and also for connecting metal layers M2 through M5, and thus data, power, and bias (e.g., ground) signals to and from a microelectronic device, such as mounted to interposer 200 and connected via contacts 126 ( Figure 1E ) is connected to the metal level M5 memory and processor. TSV 204 extends from metal level M1 through core 202 and through dielectric layer 208B to another metal level M6 opposite to M1, and metal level M6 includes conductive pad 216.

[0073] By way of example only, the semiconductor material core 202 of the interposer 200 may have a thickness of about 50 μm or less, such as about 30 μm. The TSVs 204 may have a diameter of about 5 μm. The fabrication of the active and passive circuitry 280 may be accomplished by techniques known to one of ordinary skill in the art of semiconductor device fabrication, such as memory device fabrication. The redistribution structure 214, including the plurality of RDLs 218, 220, 222, and 224, may be fabricated by BEOL techniques known to one of ordinary skill in the art of semiconductor device fabrication. Similarly, the TSVs 204 may be fabricated initially in the form of blind vias, such as having a depth of about 65 μm in a semiconductor core of greater thickness, such as a partially thinned wafer of about 100 μm thickness, with the blind ends exposed by thinning of the core, and the backside pads (i.e., conductive pads 216) formed on the exposed ends by blanket conductive material deposition and patterning, all as known to one of ordinary skill in the art of semiconductor device fabrication. Such dimensions and processing techniques apply equally to all interposer embodiments of the present invention.

[0074] Notably, another interposer 200 may be fabricated to be stacked and connected with the interposer 200 described above to be connected to the interposer 200 in the same or "reverse" orientation, and having different patterns of metal layers M1-M5 and conductive pads 216 to be stacked with the other interposer 200 to provide a redistribution layer including eight (8) metal levels, and additional passive and active circuitry as described above, which may be the same or different than that employed in the first interposer, with the stacked interposers 200 connected by conductive elements extending before the conductive pads 216. If a second interposer 200 is fabricated to be connected to the first interposer 200 in a similar orientation (i.e., the redistribution structures face the same direction), then the conductive pads 216 of the second interposer 200 may be used to connect the assembly to a higher level package, such as a motherboard. When the interposer is configured for use in an inverted orientation, unlike an interposer 200 configured for direct connection to a microelectronic device, the metal level M5 of the redistribution structure of the inverted interposer can be configured with conductive pads for connection to a higher level package, such as a motherboard, while the metal level M6 is used to connect to the first interposer 200. In either embodiment, the pattern of TSVs through the core 202 of the respective first and second interposers 200 can also be the same or different, provided that, for example, the conductive pads 216 can be used together with circuit traces to reroute signals between the first and second interposers having mutually offset TSVs.

[0075] By further elaboration, and reference Figures 3A to 3C , a first embodiment of a stacked interposer 200 having redistribution structures 214 facing the same direction and a microelectronic device assembly 300 incorporated therein will be described. Figure 2 The described elements are identified with the same or similar reference numerals.

[0076] refer to Figure 3A , a first interposer 200D1 including a first redistribution structure configuration of four RDLs 218, 220, 222, 224 and optionally a first passive and active circuit system configuration is depicted over a second interposer 200D2 having a second redistribution structure including four RDLs 218, 220, 222, and 224 and optionally a second passive and active circuit system configuration. For clarity, the first metal level M1 has been omitted in the two illustrated interposers (see Figure 2 ). Upper interposer 200D1 includes a semiconductor (e.g., silicon) core 202 on which a redistribution structure 214 including four RDLs 218, 220, 222, 224 has been fabricated. Circuitry 280 including passive circuitry, active circuitry, or both may optionally be located within core 202 below redistribution structure 214. TSVs 204 extend from redistribution structure 214 through core 202 and through dielectric level 208B to conductive pads 216.

[0077] Still reference Figure 3A , the lower interposer 200D1 includes a semiconductor (e.g., silicon) core 202, above which a redistribution structure 214 including four RDLs 218, 220, 222, 224 has been fabricated on its upper side, with the redistribution structures 214 of both the upper interposer 200D1 and the lower interposer 200D2 facing the same direction. The conductive paths of the RDLs 218, 220, 222, 224 of the redistribution structure 214 of the lower interposer 200D2 are different from the conductive paths of the redistribution structure 214 of the upper interposer 200D1, and are cooperatively configured for signal and optionally power and ground transmission. A circuit system 280 including passive circuit systems, active circuit systems, or both may optionally be located within the core 202 below the redistribution structure 214. TSVs 204 extend from the redistribution structure 214 through the core 202 and through the dielectric layer 208B to the conductive pad 216.

[0078] refer to Figure 3B, interposer 200D1 is stacked above interposer 200D2 and physically and electrically connected to interposer 200D2 via conductive elements 230 bonded to conductive pads 216 of interposer 200D1 and conductive pads of metal level M5 of interposer 200D2 to form stacked interposer structure 200S. Conductive elements 230 may include, for example, solder-covered copper pillars bonded to conductive pads in a reflow process, copper pillars bonded to copper pads in a diffusion bonding process, reflowed solder balls, gold stud bumps, oxide bonding (also known as hybrid bonding), covalent bonding involving Cu-Cu diffusion bonding and oxide passivation materials in bond wires, or other suitable direct chip attach techniques. It is contemplated that conductive elements 230 may be used with non-conductive film (NCF) 240 interposed between interposer 200D1 and interposer 200D2, or alternatively wafer level underfill (WLUF).

[0079] Figure 3C A microelectronic device assembly 300 is depicted that includes a stacked interposer structure 200S and has a microelectronic device mounted thereto and configured for connection to a higher level package. By way of example only, the microelectronic device includes a memory stack 302 of DRAM dies mounted on the interposer 200D1 of the microelectronic device assembly 300 and operably coupled to its high bandwidth configuration. As previously described, any suitable number of DRAM dies may be incorporated into the memory stack 302, such as four, eight, twelve, sixteen, thirty-two, or sixty-four DRAM dies. Figures 1A to 1D , more than one stacked memory die and more than one type of memory die may be mounted to the microelectronic device assembly 300. A processor 304 may also be mounted on and connected to the interposer 200D1 of the microelectronic device assembly 300. The processor 304 may include, for example, a graphics processing unit (GPU), a central processing unit (CPU), a controller, or a system on a chip (SoC). The memory stack 302 and the processor 304 may each be physically and electrically connected to the conductive pads 250 of the metal level M5 of the interposer 200D1 by, for example, solder-covered copper pillars, diffusion-bonded conductive pillars, solder bumps, microbumps, or any other suitable conductive elements 306. Conductive elements 260 in the form of, for example, solder balls residing on the conductive pads 216 of the interposer 200D2 may be used to connect the microelectronic device assembly 300 to a higher level package. Prior to application and formation of the conductive elements 260 , the assembly 300 may be encapsulated with a dielectric molding compound, as known to one of ordinary skill in the art.

[0080] As further elaboration, and with reference to Figures 3D to 3F, a second embodiment of a stacked interposer 200 having a redistribution structure facing in opposite directions and a microelectronic device assembly incorporating the same will be described. Figure 2 The described elements are identified with the same or similar reference numerals.

[0081] refer to Figure 3D , a first interposer 200D1′ including a first redistribution structure configuration including four RDLs 218, 220, 222, 224 and optionally a first passive and active circuitry configuration is depicted above a second interposer 200D2′ having a second redistribution structure including four RDLs 218, 220, 222, and 224 and optionally a second passive and active circuitry configuration. Upper interposer 200D1′ includes a semiconductor (e.g., silicon) core 202 on which a redistribution structure 214 including four RDLs 218, 220, 222, 224 has been fabricated. Circuitry 280 including passive circuitry, active circuitry, or both may optionally be located within core 202 below redistribution structure 214. TSVs 204 extend from redistribution structure 214 through core 202 and through dielectric layer 208B to conductive pads 216.

[0082] Still reference Figure 3D , a lower interposer 200D2′ includes a semiconductor (e.g., silicon) core 202, above which a redistribution structure 214 including four RDLs 218, 220, 222, 224 has been fabricated on its underside such that the redistribution structures 214 of the interposers 200D1′ and 200D2′ face opposite directions. The conductive paths of the RDLs 218, 220, 222, 224 of the redistribution structure 214 of the lower interposer 200D2 are different from the conductive paths of the redistribution structure 214 of the upper interposer 200D1, and are cooperatively configured for signal, and optionally power and ground transmission. A circuit system 280 including passive circuit systems, active circuit systems, or both may optionally be located within the core 202 above the redistribution structure 214. The TSVs 204 extend from the redistribution structure 214 through the core 202 and through the dielectric layer 208B to the conductive pad 216.

[0083] refer to Figure 3E, interposer 200D1′ is stacked above interposer 200D2′ and is physically and electrically connected to interposer 200D2 via conductive elements 230 bonded to conductive pads 216 of interposer 200D1′ and conductive pads 216 of interposer 200D2′ to form a stacked interposer structure 200S′. Conductive elements 230 may include, for example, solder-covered copper pillars bonded to conductive pads in a reflow process, copper pillars bonded to copper pads in a diffusion bonding process, reflowed solder balls, gold stud bumps, oxide bonding (also known as hybrid bonding), covalent bonding involving Cu-Cu diffusion bonding and oxide passivation materials in bond wires, or other suitable direct chip attach techniques. It is contemplated that conductive elements 230 may be used with a non-conductive film (NCF) 240 interposed between interposer 200D1′ and interposer 200D2′ or alternatively a wafer level underfill (WLUF). It is worth noting that the conductive paths in the redistribution structures 214 of the interposers 200D1′ and 200D2′ (and thus the stacked interposer structure 200S′) may be different from those in the redistribution structures 214 of the interposers 200D1 and 200D2 (and thus the stacked interposer structure 200S), and one or more of the number, spacing, and pattern of the TSVs 204 connecting the stacked interposers 200 will also be different. Similarly, the type, number, and location of the passive and active circuitry may differ between the stacked interposer structures 200S and 200S′.

[0084] Figure 3F A microelectronic device assembly 300′ is depicted stacking and interconnecting interposers 200D1′ and 200D2′, having microelectronic devices mounted thereto and configured for connection to a higher level package. By way of example only, the microelectronic device includes a memory stack 302 of high bandwidth configured DRAM dies mounted on and operably coupled to interposer 200D1′ of assembly 300′. As previously described, any suitable number of DRAM dies may be incorporated into memory stack 302, such as four, eight, twelve, sixteen, thirty-two, or sixty-four DRAM dies. Figures 1A to 1D, more than one stacked memory die and more than one type of memory die may be mounted to the microelectronic device assembly 300. A processor 304 may also be mounted on and connected to the interposer 200D1′ of the assembly 300. The processor 304 may include, for example, a graphics processing unit (GPU), a central processing unit (CPU), a controller, or a system on a chip (SoC). The memory die 302 and the processor 304 may each be physically and electrically connected to the conductive pad 250 of the metal level M5 of the interposer 200D1′ by, for example, a solder-covered copper pillar, a diffusion-bonded conductive pillar, a solder bump, or any other suitable conductive element 306. Conductive elements 260 in the form of, for example, solder balls residing on the conductive pad 270 of the metal level M5 of the interposer 200D2′ may be used to connect the microelectronic device assembly 300′ to a higher level package. Prior to application and formation of the conductive elements 260, the assembly 300' may be encapsulated with a dielectric molding compound, as known to one of ordinary skill in the art.

[0085] In respectively about Figures 3A to 3C and Figures 3D to 3F In the embodiments depicted and described in each of the foregoing, the traces, vias, and active circuitry (if present) and passive circuitry (if present) included in each cooperative combination of two stacked interposers including stacked interposer structures 200S and 200S′ are designed to function as a single interposer, such as a single interposer having a core with redistribution structures on opposite sides of the core and operably coupled by conductive vias extending through the core and between the redistribution structures. However, embodiments of the stacked interposer design of the present invention employ techniques already used to manufacture active and passive circuitry within and on semiconductor wafers, as well as redistribution structures in the form of multiple RDLs on the active surface of the wafer, and are easier and less costly to manufacture. Additionally, utilizing embodiments of the present invention can improve production yields while increasing throughput.

[0086] For some instances, it will be desirable to form stacked interposers 200 having the same number of multiple RDLs in the redistribution structure 214. As discussed later herein, in some instances, a symmetrical structure may also be beneficial for transmitting signals in multiple conductive channels (e.g., in some instances where a first conductive channel is at least partially implemented by metal levels M2 through M5 in a first redistribution structure 214, and a second conductive channel is at least partially implemented by metal levels M2 through M5 in a second redistribution structure 214). In addition, there may be an unequal number of RDLs on each interposer 200, and individual RDLs may have vertical dimensions that differ from other RDLs. Furthermore, it is contemplated that in examples where height constraints of an assembly incorporating stacked interposers are not an issue, more than two interposers 200 may be stacked in various collaborative configurations and orientations. Additionally, it is contemplated that the RDLs of the respective interposers may be engineered to minimize warping of the interposers, and Figures 3A to 3C Embodiments of the invention may cause any warping of the stacked interposers to be mirrored (ie, warping in the same direction) to minimize stress within the interposer core.

[0087] Reference now Figure 4 , depicts a block diagram representation of an example configuration of a stacked interposer structure 400 including example optional circuit element portions that may be formed according to the description herein. The stacked interposer structure 400 is similar to Figure 1A The interposers 106A and 106 of the stack, wherein the upper surface of the stacked upper interposer defines metallization, the metallization being configured to form processor interfaces 402A, 402B, 402C, 402D for four memory devices as part of a processor interface operably coupled to an SRAM 410 located below the footprint of the processor 404 and additionally configured for external communication with other devices. Each processor interface 402A, 402B, 402C, 402D can communicate data, commands, and control signals between the memory devices and the processor through a cache memory in the form of the SRAM 410, to and through extensions corresponding to the processor interfaces 402A, 402B, 402C, 402D as described above. Figures 1A to 1E The interface circuitry sections 120A, 120B, 120C, 120D are depicted with respective communication channels 406A, 406B, 406C, 406D for the four memory interfaces 408A, 408B, 408C, 408D. The specific configuration of metallization used for each processor interface 402A, 402B, 402C, 402D and the contacts of the memory interfaces 408A, 408B, 408C, 408D may be adapted to the desired configuration, such as may be indicated by standardized ports.

[0088] The ability to configure the interposer to include active and / or passive circuit components facilitates forming logic structures such as interface circuitry sections 120A-120D and / or additional structures within the interposer, such as cache memory in the form of SRAM 410, to simplify incorporating such circuit components into a microelectronic device assembly to be formed using the interposer of stacked interposer structure 400. In addition to cache memory such as SRAM 410, another form of memory 412 may be formed within or above core 202, such as, by way of example only, DRAM, ferroelectric random access memory (FeRAM), phase change memory (PCM), 3D XPoint TM Memory, NAND flash memory, NOR flash memory, resistive random access memory (ReRAM or RRAM), or other memory types known to those skilled in the art, and / or combinations thereof.

[0089] Additionally, logic structures other than those of the interface circuitry sections 120A-120D may be formed in the interposers of the stacked interposer structure 400. Such logic structures may take the form of a field programmable gate array (FPGA) 414 or other type of logic 416. Additionally, configuration circuitry, such as that which may be used to tune or trim circuits or enable or disable circuit components, such as fuses or antifuses, may be formed in the interposers of the stacked interposer structure 400. Furthermore, as previously discussed, passive circuit components 420, such as, for example, components used to condition signals traversing the interposers of the stacked interposer structure 400, may also be formed.

[0090] For clarity of block diagram representation, various circuit components are depicted surrounding but offset from processor 404. However, the ability to incorporate such circuit components into the interposers of stacked interposer structure 400 facilitates placement of circuit components in desired locations within stacked interposer structure 400, such as placing cache memory in the form of 410 below the footprint of processor 404 and interface circuitry sections 120A-120D, as in Figure 1B , 1C Any of the above memory, logic or configuration circuitry may communicate via TSVs connected to opposite sides of the upper interposer of the stacked interposer structure 400 and applicable to the lower interposer thereof.

[0091] Thus, the stacked interposer structure 400 depicts in schematic form various features that may be incorporated into a combination of stacked interposers, such as stacked interposers 200D1 and D2 and stacked interposers 200D1′ and 200D2′, respectively. Figure 4Various circuit components on a single level in the stacked interposer structure 200S, 200S′ may be distributed among the two cooperating redistribution structures 214 of each of the two interposer stacked interposer structures 200S, 200S′, and active and passive circuit systems may be fabricated on one or both cores 202 of the stacked interposer structures 200S, 200S′ to operate in combination with the circuit systems of the redistribution structures 214 and with the TSVs 204 extending through the corresponding cores 202.

[0092] Previously identified are structures that incorporate logic gates and memory into the described interposer. As described, for many such structures, particularly those that include active components, it may be desirable to form one or more bodies of the components in the silicon of the interposer core, where the one or more bodies of the components are formed in material formed over the core. Reference will be made to Figure 5 Example ways of incorporating such active components and related structures into the structure of an interposer core are discussed.

[0093] Figure 5 A portion of an example interposer 500 is depicted that includes circuit elements as previously described with reference to Figure 2 The interposer 200 is discussed with respect to the logic gate. Figure 5Logic structure 502 is depicted formed over silicon core 522. The levels of the redistribution structure of metal levels M2 through M5, including RDL layers 532, 534, 536, and 538, have been enlarged for clarity, as have logic structure 502 and its components. In the depicted example, logic structure 502 includes coupled transistors 504, 506. Each transistor 504, 506 includes source / drain regions 508, 510, 512 formed by doping selected regions of silicon core 522. In some examples where such transistor gates are to be formed, it may be desirable to remove at least a portion of dielectric level 520 formed over silicon core 522 in order to form another dielectric material indicated at 514 that is optimized to form a gate oxide for the transistor. In regions outside of the logic gates, dielectric level 520 may remain intact. In some examples, it is advantageous to isolate portions of silicon core 522 adjacent to one or more circuit components, such as by forming shallow trench isolation, as indicated at 516 within silicon core 522. Formation of transistors 504, 506 may include forming one or more conductive gate materials 524, 526 (such as, for example, doped polysilicon) over gate oxide 514; and isolating the sidewalls of the gates with spacers, as depicted. In addition, as previously discussed, electrical connections between circuit systems may be made using one or more conductive levels, such as one or more logic metal (LM) materials within the logic region. To provide a planar surface on which to form the previously described RDL, where, as in the example, circuit components extend over the surface of silicon core 522, an insulating material 530 (such as TEOS) may be formed over the logic circuit system and planarized. On the opposite side of core 522, conductive pads 542 are connected to the circuit system described above by TSVs 540.

[0094] The microelectronic device assembly 300, 300' incorporating the stacked interposer structure according to embodiments of the present invention may be used in embodiments of the electronic system of the present invention. For example, Figure 66 is a block diagram of an illustrative electronic system 600 according to an embodiment of the present invention. The electronic system 600 includes at least one electronic device manufactured according to an embodiment of the present invention. The electronic device may include, for example, a memory device 602, which includes one or more embodiments of the microelectronic device assemblies 300, 300' previously described herein, such as a stacked HBM assembly including DRAM dies. The electronic system 600 may further include a host device in the form of a processor device 604, such as, for example, a GPU, CPU, controller, FPGA, or SoC incorporated into the microelectronic device assembly 300, 300'. The electronic system 600 may further include one or more input devices 606 for inputting information into the electronic system 600 by a user, such as, for example, a mouse or other pointing device, a keyboard, a touchpad, a button, or a control panel. The electronic system 600 may further include one or more output devices 608 for outputting information (e.g., visual or audio output) to the user, such as, for example, a monitor, a display, a printer, an audio output jack, a speaker, etc. In some embodiments, the input device 606 and the output device 608 may include a single touch screen device that can be used to input information to the electronic system 600 and to output visual information to the user. The input device 606 and the output device 608 may be in electrical communication with one or both of the processor device 604 and the memory device 602 in the microelectronic device assembly 300, 300'.

[0095] The electronic system 600 may be a computer, a server, a laptop computer, a notebook computer, a tablet computer with Wi-Fi or cellular functions, such as or Tablet computers, mobile phones, wearable electronic devices, personal electronic devices, digital cameras, portable media (e.g., music, video) players, navigation devices, or the like. Similarly, electronic system 600 may be a part or subcomponent of such a device. In some examples, electronic system 600 is an aspect of a computer with high reliability, mission critical, or low latency constraints or parameters, such as a vehicle (e.g., an autonomous car, airplane, spacecraft, or the like). Electronic system 600 may be or include logic for artificial intelligence (AI), augmented reality (AR), or virtual reality (VR) applications.

[0096] In an embodiment, a stacked interposer structure includes a first interposer including: a first core including semiconductor material; a first redistribution structure including a plurality of redistribution layers (RDLs) over a side of the first core; and a first set of through-silicon vias (TSVs) extending from the first redistribution structure through the first core to an opposite side of the first core; and a second interposer including: a second core including semiconductor material; a second redistribution structure including a plurality of redistribution layers (RDLs) over a side of the second core; and a second set of through-silicon vias (TSVs) extending from the second redistribution structure through the second core to an opposite side of the second core. The first redistribution structure and the second redistribution structure are operably coupled by at least one of the first set of TSVs and the second set of TSVs.

[0097] In an embodiment, a microelectronic device assembly includes a stacked interposer structure, which includes a plurality of interconnected interposers, each interposer having a semiconductor core and a redistribution structure on one side thereof; at least one host device and at least one memory device, which are mounted on and operably coupled to the redistribution structure of one of the plurality of interconnected interposers; and a circuit system of the stacked interposer structure, which is operably coupled to the at least one host device and the at least one memory device and extends to a side of the stacked interposer structure opposite to the at least one host device and the at least one memory device for connection to a higher level package.

[0098] In an embodiment, an interposer includes a silicon core comprising; at least one of an active circuit system and a passive circuit system above an active surface of the silicon core; a redistribution structure including at least four redistribution layers (RDLs) located above the active circuit system and the passive circuit system; and a through-silicon via (TSV) operably coupled to at least the redistribution structure and extending through the silicon core to a side thereof opposite the redistribution structure.

[0099] In an embodiment, a stacked interposer structure includes two interposers, one interposer is stacked on top of the other interposer and each has a redistribution structure including a plurality of redistribution layers (RDLs) operably coupled via TSVs extending through a semiconductor core of at least one of the two interposers; the redistribution structure of one of the two interposers, which is configured for operably coupling to a host device and a memory device; and the redistribution structure of each of the two interposers, which includes different conductive paths, which are configured to be operably coupled in combination to cooperatively act as a single redistribution structure including a combined number of multiple redistribution layers of the two interposers.

[0100] In an embodiment, an electronic system includes an input device, an output device, and the electronic system further includes: a processor device and at least one memory device, which are operably coupled to a redistribution structure of an interposer including a semiconductor core, the redistribution structure of the interposer is operably coupled to another redistribution structure of another interposer at least through a through-silicon via (TSV) extending from the redistribution structure of the interposer through the semiconductor core to a side thereof opposite to the redistribution structure, and the input device and the output device are operably coupled to the processor through a conductive path of the other interposer.

[0101] In an embodiment, a method includes providing two interposers, each having a redistribution structure including a plurality of redistribution layers (RDLs) above a semiconductor core, conductive paths of the plurality of redistribution layers (RDLs) of the redistribution structure being cooperatively configured to act as a single redistribution layer consisting of a total number of redistribution layers (RDLs) of the two interposers; and electrically connecting the conductive paths of the redistribution layers (RDLs) of the two interposers via TSVs extending through at least one of the semiconductor cores.

[0102] Although certain illustrative embodiments have been described in conjunction with the drawings, those of ordinary skill in the art will recognize and appreciate that the embodiments encompassed by the present invention are not limited to those embodiments explicitly shown and described herein. Rather, many additions, deletions, and modifications may be made to the embodiments described herein without departing from the scope of the embodiments encompassed by the present invention, such as those claimed below, including legal equivalents. Additionally, features from one disclosed embodiment may be combined with features of another disclosed embodiment while still being encompassed within the scope of the present invention.

Claims

1. A stacked interposer structure, comprising: The first intermediary layer comprises: a first core comprising a semiconductor material; a first redistribution structure including a plurality of redistribution layers (RDLs) over a side of the first core, the first redistribution structure being configured to be operably coupled to one or more memory device stacking locations and processor device locations on a surface of the first redistribution structure; a cache memory located at least partially within the first core, adjacent to the first redistribution structure, below the first redistribution structure and operatively coupled to the processor device location through the first redistribution structure; and A first set of through silicon vias (TSVs) extending from the first redistribution structure through the first core to the the opposite side of the first core; and The second intermediary layer includes: a second core comprising a semiconductor material; a second redistribution structure comprising a plurality of redistribution layers (RDL) over a side of the second core; a second set of through silicon vias (TSVs) extending from the second redistribution structure through the second core to an opposite side of the second core; and The first redistribution structure and the second redistribution structure are operably coupled through both the first set of TSVs and the second set of TSVs. 2 . The stacked interposer structure of claim 1 , wherein the first interposer and the second interposer are oriented such that the first redistribution structure and the second redistribution structure face a common direction. 3 . The stacked interposer structure of claim 1 , wherein the first interposer and the second interposer are oriented such that the first redistribution structure and the second redistribution structure face opposite directions.

4. A stacked interposer structure according to any one of claims 1 to 3, wherein the first redistribution structure and the second redistribution structure are cooperatively configured to operably couple the one or more memory device stacking positions and the processor position to each other in combination, and to operably couple the one or more memory device stacking positions to a higher level package through the second interposer. 5 . The stacked interposer structure according to claim 1 , wherein the second interposer is configured with conductive elements on a surface thereof facing away from the first interposer for operably coupling the stacked interposer structure to a higher-level package. 6 . The stacked interposer structure of claim 1 , wherein the TSVs of the first interposer and the TSVs of the second interposer are aligned with each other and operably coupled with discrete conductive elements.

7. The stacked interposer structure of any one of claims 1 to 3, wherein at least one of the first interposer and the second interposer comprises a passive circuit system comprising at least one of a capacitor, a resistor, or an inductor above its core, within its core, or both above its core and within its core.

8. The stacked interposer structure of claim 1 , wherein at least one of the first interposer and the second interposer comprises an active circuit system comprising at least one of a memory other than a cache memory, logic, a fuse, an antifuse, or a field programmable gate array.

9. The stacked interposer structure of any one of claims 1 to 3, wherein the first redistribution structure and the second redistribution structure include a same number of RDLs.

10. A microelectronic device assembly comprising: A stacked interposer structure comprising two interposers stacked in a direct interconnect, each interposer having a semiconductor core and a redistribution structure on one side thereof; at least one host device and at least one memory device mounted on and operably coupled to a redistribution structure of one of the two interconnected interposers, the at least one host device being operably coupled to a cache memory through the redistribution structure of the one interposer, the cache memory being at least partially located within the semiconductor core of the one interposer below the location of the at least one host device; and The circuitry of the stacked interposer structure operably couples the at least one host device and the at least one memory device and extends to a side of the stacked interposer structure opposite the at least one host device and the at least one memory device for connection to a higher level package.

11. The microelectronic device assembly according to claim 10, wherein the at least one host device comprises a graphics processor unit (GPU), a central processing unit (CPU), a controller, or a system on a chip (SoC), and the at least one memory device comprises a DRAM, a SRAM, a ferroelectric RAM (FeRAM), a resistive RAM (RRAM or ReRAM), a phase change memory (PCM), a 3D XPoint TM At least one of a memory, a NAND flash memory, or a NOR flash memory.

12. The microelectronic device assembly of claim 10, wherein the at least one host device comprises a graphics processor unit (GPU), and the at least one memory device comprises a high-bandwidth memory device configured as a stack of high-bandwidth DRAM dies.

13. The microelectronic device assembly of claim 12, wherein a core of one of the two interconnected interposers of the stacked interposer structure includes logic circuitry for interfacing with the high bandwidth memory device.

14. The microelectronic device assembly of claim 10, wherein the two interconnect interposers are interconnected by TSVs extending through the semiconductor core of at least one of the two interconnect interposers.

15. The microelectronic device assembly of any one of claims 10 to 14, wherein at least one of the two interconnect interposers includes at least one of passive circuitry other than cache memory and active circuitry on its semiconductor core.

16. A microelectronic device assembly as claimed in claim 15, wherein the passive circuitry includes at least one of a capacitor, a resistor or an inductor, and the active circuitry includes at least one of a memory other than a cache, logic, a fuse, an antifuse, or a field programmable gate array.

17. The microelectronic device assembly according to any one of claims 10 to 14, wherein the redistribution structure of each of the two interconnected interposers comprises a plurality of redistribution layers (RDLs). 18 . The microelectronic device assembly according to claim 17 , wherein each redistribution structure comprises a same number of redistribution layers (RDL).

19. A stacked interposer structure comprising: two interposers, one interposer stacked on top of the other interposer and each having a redistribution structure including a plurality of redistribution layers (RDLs) operably coupled via TSVs extending through semiconductor cores of both of the two interposers; the redistribution structure of one of the two interposers configured for operative coupling to a host device and a cache memory at least partially located in the semiconductor core of at least one of the two interposers; and The redistribution structure of each of the two interposers includes distinct conductive paths configured to be operably coupled in combination to cooperatively function as a single redistribution structure including a combined number of the two interposers.

20. An electronic system comprising: input device and output device, the electronic system further comprising: a processor device and at least one memory device operably coupled to a redistribution structure of an interposer including a semiconductor core, the semiconductor core including cache memory circuitry positioned below the processor device and operably coupled to the processor device through the redistribution structure of the interposer, the redistribution structure of the interposer operably coupled to another redistribution structure of another interposer at least through silicon vias (TSVs) extending from the redistribution structure of the interposer through the semiconductor core to a side opposite the redistribution structure thereof; and The input device and the output device are operably coupled to the processor through conductive paths of the further interposer.

21. The electronic system of claim 20, wherein the at least one memory device comprises at least one stack of a plurality of high bandwidth memory dies.

22. A method for connecting an interposer, comprising: providing two interposers, each having a redistribution structure including a plurality of redistribution layers (RDLs) above a semiconductor core, the conductive paths of the plurality of redistribution layers (RDLs) of the redistribution structure being cooperatively configured to function as a single redistribution layer consisting of a total number of the redistribution layers (RDLs) of the two interposers, the redistribution structure of at least one of the two interposers being configured to be operably coupled to a host device and a cache memory, the cache memory being at least partially located within the semiconductor core of the at least one of the two interposers; and The conductive paths of the redistribution layers (RDL) of the two interposers are electrically connected through TSVs extending through both of the semiconductor cores.

23. The method of claim 22, further comprising orienting the two interposers with the redistribution structures facing in a common direction.

24. The method of claim 22, further comprising orienting the two interposers with redistribution structures facing in opposite directions.

25. The method of claim 24, further comprising electrically connecting the conductive paths of the plurality of RDLs of the two interposers via TSVs extending from a respective redistribution layer of each interposer through the semiconductor core thereof to discrete conductive elements.

26. The method of claim 22, further comprising operatively coupling the host device with the cache memory, the cache memory being located at least partially within the semiconductor core of the at least one of the two interposers.

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