Semiconductor device and method for forming the same

Abstract

The present disclosure relates to semiconductor devices and methods for forming the same. A semiconductor device includes: a first dielectric layer disposed over a substrate and a conductive feature; a doped dielectric layer disposed over the first dielectric layer; a first metal portion disposed in the first dielectric layer and in contact with the conductive feature; and a doped metal portion disposed over the first metal portion. The first metal portion and the doped metal portion include the same noble metal material. The doped dielectric layer and the doped metal portion include the same dopant. The dopant is bonded to the noble metal material.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and more particularly, to semiconductor devices and methods for forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry is evolving rapidly. Technological advances in IC materials and design have resulted in successive generations of improved ICs. Each generation has smaller and more complex circuits than the previous one. However, these advances have increased the complexity of processing and manufacturing ICs.

[0003] Over the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs.

[0004] However, as feature sizes continue to decrease, manufacturing processes continue to become more difficult to perform. As a result, it has become a challenge to form reliable semiconductor devices with increasingly smaller dimensions. Summary of the invention

[0005] According to one embodiment of the present disclosure, a semiconductor device is provided, comprising: a first dielectric layer, disposed above a substrate and a conductive feature; a doped dielectric layer, disposed above the first dielectric layer; a first metal portion, disposed in the first dielectric layer and in contact with the conductive feature; and a doped metal portion, disposed above the first metal portion, wherein the first metal portion and the doped metal portion comprise the same precious metal material, and the doped dielectric layer and the doped metal portion comprise the same dopant, wherein the dopant is bonded to the precious metal material in the doped metal portion.

[0006] According to another embodiment of the present disclosure, a method for forming a semiconductor device is provided, comprising: forming a dielectric structure over a conductive feature, wherein the dielectric structure comprises an opening exposing a portion of the conductive feature; filling the opening with a metal layer comprising a noble metal material; forming a doped metal portion in the metal layer, wherein the doped metal portion comprises a dopant bonded to the metal material; and removing a portion of the metal layer to expose a top surface of the dielectric structure and form a connection structure.

[0007] According to another embodiment of the present disclosure, a method for forming a semiconductor device is provided, the method comprising: forming a dielectric structure over a conductive feature, wherein the dielectric structure comprises an opening, the opening exposing a portion of the conductive feature; filling the opening with a metal layer, wherein the metal layer covers a top surface of the dielectric structure; removing a portion of the metal layer to expose the top surface of the dielectric structure; and after removing the portion of the metal layer, forming a doped metal portion in the metal layer and a doped dielectric layer in the dielectric structure, wherein the metal layer and the doped metal portion comprise the same metal material, the doped metal portion and the doped dielectric layer comprise the same dopant, and the dopant is bonded to the metal material in the doped metal portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Various aspects of the present disclosure may be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0009] Figure 1 is a fragmentary cross-sectional view of a semiconductor structure.

[0010] Figure 2 is a flow chart of a method for forming a semiconductor device according to various aspects of the present disclosure.

[0011] FIG. 3A to FIG. 3F is a schematic diagram illustrating various stages in a method for forming a semiconductor device according to aspects of one or more embodiments of the present disclosure.

[0012] FIG. 4A to FIG. 4E is a schematic diagram illustrating various stages in a method for forming a semiconductor device according to aspects of one or more embodiments of the present disclosure.

[0013] Figure 5 is a diagram illustrating a semiconductor device according to aspects of one or more embodiments of the present disclosure.

[0014] FIG. 6A to FIG. 6D is a schematic diagram illustrating various stages in a method for forming a semiconductor device according to aspects of one or more embodiments of the present disclosure.

[0015] Figure 7 is a schematic diagram illustrating a semiconductor device according to various aspects of the present disclosure.

[0016] Figure 8 is a flow chart of a method for forming a semiconductor device according to various aspects of the present disclosure.

[0017] 9A to 9F is a schematic diagram illustrating various stages in a method for forming a semiconductor device according to aspects of one or more embodiments of the present disclosure.

[0018] FIG. 10A to FIG. 10C is a schematic diagram illustrating various stages in a method for forming a semiconductor device according to aspects of one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0019] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0020] Additionally, spatially relative terms (e.g., "below," "beneath," "lower," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element(s) or feature(s). These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0021] As used herein, terms such as "first", "second", and "third" describe various elements, components, regions, layers, and / or parts, but these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms can only be used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Terms such as "first", "second", and "third" used in this article do not mean a sequence or order unless the context clearly indicates.

[0022] The IC manufacturing process flow can generally be divided into three categories: front-end-of-line (FEOL), middle-end-of-line (MEOL), and back-end-of-line (BEOL). FEOL generally includes processes related to the manufacture of IC devices (e.g., transistors). For example, the FEOL process may include forming an isolation structure for isolating IC devices, forming a gate structure of a transistor, and a source and drain structure (also referred to as a source / drain structure). MEOL generally includes processes related to the manufacture of a connection structure (also referred to as a contact or plug) connected to a conductive feature (or conductive region) of an IC device. For example, the MEOL process may include forming a connection structure connected to a gate structure and a connection structure connected to a source / drain structure. BEOL generally includes processes related to the manufacture of multi-layer interconnect (MLI) structures that electrically connect the IC devices and connection structures manufactured by the FEOL and MEOL. Therefore, the operation of the IC device can be enabled. As described above, the scaled-down process increases the complexity of processing and manufacturing ICs. For example, in some comparative methods, ruthenium (Ru) with a lower resistivity is used to form a connection structure formed by MEOL to reduce the resistance of the plug contact. However, as the IC feature size continues to shrink, the connection structure becomes more and more compact, and the Ru-containing connection structure poses challenges to production yield and cost.

[0023] Embodiments such as those discussed herein provide semiconductor devices including connection structures and methods for forming semiconductor devices for mitigating bottom metal loss problems that may occur during annealing due to metal diffusion from a lower metal layer. In some embodiments, implantation is performed after processing the metal layer to form a barrier layer within the conductive material. In some embodiments, ions implanted into the conductive material bond with the conductive material to form a diffusion barrier layer so that metal diffusion can be blocked or reduced by the diffusion barrier layer. Thus, the bottom metal loss problem caused by metal diffusion can be mitigated or reduced.

[0024] Figure 1is a fragmentary cross-sectional view of part or all of a semiconductor structure 100 according to various aspects of some embodiments of the present disclosure. The semiconductor structure 100 may be included in a microprocessor, a memory, and / or another IC device. In some embodiments, the semiconductor structure 100 is part of an IC chip, a system on a chip (SoC), or a portion thereof, and the semiconductor structure 100 includes various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, p-type field effect transistors (PFETs), n-type field effect transistors (NFETs), metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, other suitable components, or combinations of the foregoing. The transistor may be a planar transistor or a multi-gate transistor, such as a fin FET (FinFET). In order to more clearly illustrate the inventive concept of the present invention, Figure 1 Additional features may be added to the semiconductor structure 100 , and some of the features described below may be replaced, modified, or eliminated in other embodiments of the semiconductor structure 100 .

[0025] In some embodiments, the semiconductor structure 100 includes a substrate (wafer) 102. In some embodiments, the substrate 102 includes silicon. Alternatively or additionally, the substrate 102 includes: another basic semiconductor, such as germanium; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor, such as silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or a combination of the foregoing. In some embodiments, the substrate 102 includes one or more III-V materials, one or more II-IV materials, or a combination thereof. In some embodiments, the substrate 102 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The semiconductor-on-insulator substrate can be manufactured using separation by oxygen implantation (SIMOX), wafer bonding, and / or other suitable methods. The substrate 102 may include various doped regions (not shown) configured according to the design requirements of the device, such as a p-type doped region, an n-type doped region, or a combination thereof. The p-type doped region (e.g., a p-type well) includes a p-type dopant, such as boron, indium, other p-type dopants, or a combination thereof. The n-type doped region (e.g., an n-type well) includes an n-type dopant, such as phosphorus, arsenic, other n-type dopants, or a combination thereof. In some implementations, the substrate 102 includes a doped region formed using a combination of a p-type dopant and an n-type dopant. Various doped regions may be formed directly on and / or in the substrate 102, for example, providing a p-well structure, an n-well structure, a double-well structure, a raised structure, or a combination of the foregoing. An ion implantation process, a diffusion process, and / or another suitable doping process may be performed to form the various doped regions.

[0026] Isolations (not shown) may be formed on and / or in the substrate 102 to electrically isolate various regions of the semiconductor structure 100, such as various device regions. For example, the isolations may define active device regions and / or passive device regions and electrically isolate them from each other. The isolations may include silicon oxide, silicon nitride, silicon oxynitride, another suitable isolation material, or a combination of the foregoing. The isolation features may include different structures, such as a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure, and / or a local oxidation of silicon (LOCOS) structure.

[0027] Various gate structures, such as gate structures 110, 112, and 114, may be disposed on the substrate 102. In some embodiments, one or more gate structures 110, 112, and 114 may be inserted between the source region and the drain region, wherein the channel region is defined between the source region and the drain region. In some embodiments, the gate structures 110, 112, and 114 are formed on the fin structure. In some embodiments, the gate structures 110, 112, and 114 include a metal gate structure. In some embodiments, the metal gate structure includes a gate dielectric layer and a gate electrode. The gate dielectric layer may be disposed on the substrate 102, and the gate electrode is disposed on the gate dielectric layer. The gate dielectric layer includes a dielectric material, such as silicon oxide, a high-k dielectric material, another suitable dielectric material, or a combination thereof. A high-k dielectric material generally refers to a dielectric material having a high dielectric constant (e.g., a dielectric constant greater than the dielectric constant of silicon oxide (k≈3.9)). Exemplary high-k dielectric materials include hafnium, aluminum, zirconium, lanthanum, tantalum, titanium, yttrium, oxygen, nitrogen, another suitable component, or a combination of the foregoing. In some embodiments, the gate dielectric layer includes a multilayer structure, such as an interfacial layer (IL), which includes, for example, silicon oxide; and a high-k dielectric layer, including, for example, HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, HfO2-Al2O3, TiO2, Ta2O5, La2O3, Y2O3, another suitable high-k dielectric material, or a combination of the foregoing.

[0028] The gate electrode includes a conductive material. In some embodiments, the gate electrode includes multiple layers, such as one or more work function metal layers and a gap filling metal layer. The work function metal layer includes a conductive material adjusted to have a desired work function (e.g., n-type work function or p-type work function), such as an n-type work function material and / or a p-type work function material. The p-type work function material includes TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, another P-type work function material, or a combination of the foregoing. The N-type work function material includes Ti, Al, Ag, Mn, Zr, TiAl, TiAlC, TaC, TaCN, TaSiN, TaAl, TaAlC, TiAlN, another n-type work function material, or a combination of the foregoing. The gap filling metal layer may include a suitable conductive material, such as Al, W and / or Cu.

[0029] The gate structures 110, 112, and 114 may also include a spacer 116, which is disposed adjacent to the gate structures 110, 112, and 114 (e.g., along the sidewalls of the gate structures 110, 112, and 114). The spacer 116 may be formed by any suitable process and include a dielectric material. The dielectric material may include silicon, oxygen, carbon, nitrogen, another suitable material, or a combination of the foregoing (e.g., silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide). In some embodiments, the spacer 116 may include a multilayer structure, such as a first dielectric layer including silicon nitride and a second dielectric layer including silicon oxide. In some embodiments, more than one set of spacers (e.g., sealing spacers, offset spacers, sacrificial spacers, dummy spacers, and / or main spacers) are formed adjacent to the gate structures 110, 112, and 114.

[0030] Before and / or after forming the spacers 116 , implantation, diffusion, and / or annealing processes may be performed to form lightly doped source and drain (LDD) features and / or heavily doped source and drain (HDD) features in the substrate 102 .

[0031] In some embodiments, the source / drain region S / D of the device may include an epitaxial structure 118. For example, a semiconductor material is epitaxially grown on the substrate 102, thereby forming an epitaxial source / drain structure 118 above the source region and the drain region of the substrate 102. Accordingly, the gate structure 110, the epitaxial source / drain structure 118, and the channel region defined between the epitaxial source / drain structure 118 form a device such as a transistor. In some embodiments, the epitaxial source / drain structure 180 may surround the source / drain region of the fin structure. In some embodiments, the epitaxial source / drain structure 180 may replace some portions of the fin structure. The epitaxial source / drain structure 180 is doped with n-type dopants and / or p-type dopants. In some embodiments, where the transistor is configured as an n-type device (e.g., having an n-channel), the epitaxial source / drain structure 180 may include a silicon-containing epitaxial layer or a silicon-carbon-containing epitaxial layer doped with phosphorus, another n-type dopant, or a combination thereof (e.g., forming a Si:P epitaxial layer or a Si:C:P epitaxial layer). In alternative embodiments, where the transistor is configured as a p-type device (e.g., having a p-channel), the epitaxial source / drain structure 180 may include an epitaxial layer containing silicon and germanium doped with boron, another p-type dopant, or a combination thereof (e.g., forming a Si:Ge:B epitaxial layer). In some embodiments, the epitaxial source / drain structure 180 includes materials and / or dopants that achieve a desired tensile stress and / or compressive stress in the channel region.

[0032] like Figure 1As shown, a plurality of dielectric layers 120, 122, and 124 may be disposed over the substrate 102. The dielectric layers 120, 122, and 124 may include a dielectric material including, for example, silicon oxide, silicon nitride, silicon oxynitride, an oxide formed from TEOS, PSG, BPSG, a low-k dielectric material, another suitable dielectric material, or a combination of the foregoing. Exemplary low-k dielectric materials include FSG, carbon-doped silicon oxide, Black (Applied Materials, Inc., Santa Clara, Calif.), xerogel, aerogel, amorphous fluorinated carbon, parylene, BCB, SILK (Dow Chemical, Midland, Mich.), polyimide, another low-k dielectric material, or a combination of the foregoing. Figure 1 As shown, dielectric layer 120 may cover source / drain regions S / D, spacers 116, and gate structures 110, 112, and 114. In some embodiments, dielectric layer 120 may be referred to as an interlayer dielectric (ILD) layer. In some embodiments, dielectric layers 122 and 124 may be referred to as interlayer dielectric (ILD) layers or intermetallic dielectric (IMD) layers.

[0033] In some embodiments, one or more connection structures 130, 132 may be formed over the source / drain regions S / D and the gate structure 110, such as Figure 1 As shown. The connection structure 130 is disposed on the gate structure 110 so that the gate structure 110 can be connected to a back-end-of-line (BEOL) interconnect (not shown) through the connection structure 130. The connection structure 132 may be referred to as a metal-to-device (MD) or metal-to-drain (MD) contact, which generally refers to a contact to a source / drain region S / D. Figure 1 As shown, a plurality of connection structures 132 may be respectively disposed on a plurality of epitaxial source / drain structures 118, such that the epitaxial source / drain structures 118 may be connected to the BEOL interconnection through the connection structures 132. Therefore, the FEOL structure may be electrically connected to the BEOL interconnection through the connection structures 130, 132, which may also be referred to as MEOL interconnection structures.

[0034] Still reference Figure 1, connection structures 140, 142 may be formed on connection structures 130, 132, and conductive features 150 may be formed on connection structures 140, 142. Connection structures 140, 142 electrically connect connection structures 130, 132 to conductive features 150. In some embodiments, in BEOL interconnects, connection structures 140, 142 are referred to as vias (V), and conductive features 150 are referred to as metal lines (M). In some embodiments, BEOL interconnects include dielectric layer stack 122, and vias and metal lines are formed in the dielectric layer stack.

[0035] Figure 2 1 is a flow chart representing a method 10 for forming a semiconductor device according to various aspects of the present disclosure. In some embodiments, the method 10 for forming a semiconductor device includes several operations (11, 12, 13, and 14). The method 10 for forming a semiconductor device will be further described according to one or more embodiments. It should be noted that the operations of the method 10 for forming a semiconductor device can be rearranged or otherwise modified within the scope of various aspects. It should be further noted that additional processes can be provided before, during, and after the method 10, and some other processes may only be briefly described herein. In some embodiments, the method 10 for forming a semiconductor device can be used to form connection structures 130, 132 in a MEOL structure. In other embodiments, the method 10 for forming a semiconductor device can be used to form connection structures 140, 142 in a BEOL interconnect.

[0036] FIG. 3A to FIG. 3F 1 is a schematic diagram showing various stages in a method 10 for forming a semiconductor device according to aspects of one or more embodiments of the present disclosure. In some embodiments, a substrate 200 may be received. The substrate 200 may be Figure 1 The substrate 102 is shown, but the present disclosure is not limited thereto. In some embodiments, the substrate 200 may include a semiconductor device, such as Figure 1 The transistor shown in FIG. 1 is a transistor, but the present disclosure is not limited thereto. Figure 3A As shown, substrate 200 may include conductive features 202 disposed therein. In some embodiments, conductive features 202 may be similar to Figure 1 The conductive features 202 may be FEOL features of the metal gate 110 or source / drain regions S / D shown. In some embodiments, the conductive features 202 may be MEOL features, such as those similar to Figure 1 Cobalt-containing device-level contacts of the connection structures 130, 132 are shown. In addition, the substrate 200 may include one or more dielectric layers. For example, in some embodiments, the conductive feature 202 may be a BEOL feature, such as Figure 1 Metal line (M) feature 150 is shown as a cobalt-containing line.

[0037] In operation 11, a dielectric structure 210 is formed over substrate 200 and conductive features 202. In some embodiments, dielectric structure 210 may include a single layer. In some embodiments, dielectric structure 210 may include a multi-layer structure. For example, Figure 3A As shown, the dielectric structure 210 may include at least a first dielectric layer 212 and a second dielectric layer 214, which are sequentially stacked on the substrate 200 and the conductive feature 202. The first dielectric layer 212 and the second dielectric layer 214 may include different dielectric materials. For example, the first dielectric layer 212 may be a contact etch stop layer (CESL), and the second dielectric layer may be an ILD layer or an IMD layer. In some embodiments, the CESL may include silicon nitride, silicon oxynitride, etc. The ILD layer or the IMD layer may include the materials described above.

[0038] Still reference Figure 3A In operation 11, an opening 215 may be formed in the dielectric structure 210. In some embodiments, the opening 215 passes through the dielectric structure 210 from the top surface 210t to the bottom of the dielectric structure 210. Therefore, a portion of the conductive feature 202 is exposed through the opening 215. The opening 215 may be formed using a photolithography operation with a masking technique and using an anisotropic etching operation (e.g., plasma etching or reactive ion etching), but the present disclosure is not limited thereto.

[0039] refer to Figure 3B In operation 12, a metal layer 220 such as a noble metal layer may be formed to fill the opening 215, but the present disclosure is not limited thereto. The noble metal layer may include rhenium (Re), rhodium (Rh), and ruthenium (Ru). The metal layer 220 extends from the top surface 210t of the dielectric structure 210 to the bottom of the dielectric structure 210. The metal layer 220 passes through the second dielectric layer 214 and the first dielectric layer 212 to contact the exposed portion of the conductive feature 202. In addition, the metal layer 220 covers the top surface 210t of the dielectric structure 210. In some embodiments, the thickness of the metal layer 220 overlying the top surface 210t of the dielectric structure 210 may be between about 1 nanometer and about 50 nanometers, but the present disclosure is not limited thereto.

[0040] It should be noted that in some embodiments, metal layer 220 may be formed without a liner, barrier, seed layer, or any intermediate layer. Thus, in such embodiments, metal layer 220 may contact dielectric structure 210, but the disclosure is not limited thereto.

[0041] refer to Figure 3CIn operation 13, a doped metal portion 222 is formed in the metal layer 220. In some embodiments, the doped metal portion 222 includes phosphorus (P), boron (B), arsenic (As), gallium (Ga), or indium (In), but the present disclosure is not limited thereto. The formation of the doped metal portion 222 includes ion implantation. In some embodiments, the dose of the ion implantation may be about 1E13 cm -2 to about 1E16 cm -2 The angle of the ion implantation may be between about 0 degrees and about 60 degrees, and the temperature of the ion implantation may be between about -100°C and about 500°C. It should be noted that the formed position or depth of the doped metal portion 222 may be determined by the implantation energy of the ion implantation. For example, when the implantation energy of the ion implantation is between about 500eV and about 50KeV, the doped metal portion 222 may be formed in the upper portion of the metal layer 220. In some embodiments, as shown in FIG. Figure 3C As shown, the doped metal portion 222 is formed to cover the top surface 210t of the dielectric structure 210. The distribution of the dopant in the doped metal portion 222 is depicted as Figure 3C In some embodiments, the peak of the distribution curve may be near the middle of the doped metal portion 222 covering the second dielectric layer 214, but the disclosure is not limited thereto. In some embodiments, the thickness of the doped metal portion 222 may be between about 1 nanometer and about 50 nanometers, but the disclosure is not limited thereto.

[0042] refer to Figure 3D In some embodiments, annealing is performed to improve gap filling results, reduce plug resistance, and fix the interface between the dielectric structure 210 and the metal layer 220. In some embodiments, the temperature for annealing can be in the range of about 100°C to about 500°C, but the present disclosure is not limited thereto. The pressure for annealing can be in the range of about 100mTorr to about 760mTorr, but the present disclosure is not limited thereto. The process duration of annealing can be in the range of about 10 minutes to about 120 minutes, but the present disclosure is not limited thereto. In addition, gases such as nitrogen (N2), hydrogen (H2), helium (He), and / or argon (Ar) can be used in the annealing. During annealing, metal diffusion may occur, and metal ions may move from the conductive feature 202 to the upper portion of the metal layer 220 along the interface between the dielectric structure 210 and the metal layer 220 or within the metal layer 220. It should be noted that the doped metal portion 222 acts as a barrier layer that helps to block or reduce metal diffusion, such as Figure 3E Therefore, the metal loss problem can be alleviated or reduced.

[0043] refer to Figure 3EIn operation 14, a portion of the metal layer 220 is removed to expose the top surface 210t of the dielectric structure 210 and form a connection structure 240. In some embodiments, in operation 14, the doped metal portion 222 may be removed and a portion of the dielectric structure 210 (e.g., a portion of the second dielectric layer 214) may be removed. In some embodiments, the removal of a portion of the metal layer 220, the doped metal portion 222, and a portion of the dielectric structure 210 may be performed using a chemical mechanical polishing (CMP) operation.

[0044] refer to Figure 3F In some embodiments, another dielectric structure 250 may be formed over the dielectric structure 210 and the connection structure 240. Another conductive feature 260 may be formed in the dielectric structure 250. The conductive feature 260 may be coupled to the connection structure 240. In some embodiments, the conductive feature 260 may refer to Figure 1 In some embodiments, the conductive feature 260 may refer to the connection structure 140, 142. Figure 1 The metal wire 150 in.

[0045] According to the method 10 for forming a semiconductor device, a doped metal portion 222 can be formed before removing a portion of the metal layer 220 and a portion of the dielectric structure 210. The doped metal portion 222 includes ions that can be bonded to Ru. Therefore, the doped metal portion 222 may include ruthenium phosphide, ruthenium boride, and ruthenium arsenide, and the doped metal portion 222 acts as a diffusion barrier. Therefore, the diffusion barrier can block metal diffusion, and the metal loss problem can be alleviated. As described above, the thickness of the doped metal portion 222 can be between about 1 nanometer and about 50 nanometers. When the thickness of the doped metal portion 222 is less than about 1 nanometer, the doped metal portion 222 may be too thin to block metal diffusion. In some alternative methods, when the thickness of the doped metal portion 222 is greater than about 50 nanometers, such a thickness may result in a higher cost for removing the doped metal portion 222.

[0046] FIG. 4A to FIG. 4E , Figure 5 and FIG. 6A to FIG. 6D 1 is a schematic diagram showing various stages in a method 10 for forming a semiconductor device according to aspects of different embodiments of the present disclosure. It should be understood that FIG. 3A to FIG. 3F and FIG. 4A to FIG. 4E Like elements in the drawings are depicted by like numerals, and repeated details may be omitted for the sake of brevity.

[0047] In some embodiments, a substrate 200 may be received. Figure 4AAs shown, substrate 200 may include conductive features 202 disposed therein. In operation 11, dielectric structure 210 is formed over substrate 200 and conductive features 202, and an opening may be formed in dielectric structure 210. In operation 12, a metal layer 220 such as a noble metal layer may be formed to fill opening 215. Figure 4A As shown, the metal layer 220 extends from the top surface 210t of the dielectric structure 210 to the bottom of the dielectric structure 210. The metal layer 220 passes through the second dielectric layer 214 and the first dielectric layer 212 to contact the exposed portion of the conductive feature 202. In addition, the metal layer 220 covers the top surface 210t of the dielectric structure 210. As described above, in some embodiments, the metal layer 220 can be formed without a liner, a barrier, a seed layer, or any intermediate layer. Therefore, in such an embodiment, the metal layer 220 can be in contact with the dielectric structure 210, but the present disclosure is not limited thereto.

[0048] refer to Figure 4B , in operation 13, a doped metal portion 222 is formed in the metal layer 220. In some embodiments, the doped metal portion 222 includes phosphorus (P), boron (B), arsenic (As), gallium (Ga), or indium (In), but the present disclosure is not limited thereto. In some embodiments, the formation of the doped metal portion 222 includes ion implantation. The dose, angle, and temperature used in the ion implantation may be similar to the dose, angle, and temperature described above; therefore, the details are omitted for the sake of brevity. It should be noted that the formed position or depth of the doped metal portion 222 may be determined by the implantation energy of the ion implantation. For example, when the implantation energy of the ion implantation is greater than 50 KeV, the doped metal portion 222 may be formed in the lower portion of the metal layer 220, such as Figure 4B As shown. However, it should be noted that by controlling or adjusting the implantation energy of the ion implantation, the doped metal portion 222 can be separated from the conductive feature 202. When the doped metal portion 222 contacts the conductive feature 202, the resistance of the conductive feature 202 may be negatively affected. In some embodiments, the doped dielectric layer 224 can be formed in the dielectric structure 210 simultaneously with the formation of the doped metal portion 222. In addition, the doped dielectric layer 224 and the doped metal portion 222 are substantially aligned with each other, as shown in FIG. Figure 4B As shown. Thus, the doped metal portion 222 is spaced apart from the top surface of the metal layer 220, and the doped dielectric layer 224 is spaced apart from the top surface 210t of the dielectric structure 210. The distribution of dopants in the doped metal portion 222 and the doped dielectric layer 224 is depicted as Figure 4BIn some embodiments, the peak of the distribution curve may be near the middle of the doped metal portion 222, but the disclosure is not limited thereto. In some embodiments, the thickness of the doped metal portion 222 and the thickness of the doped dielectric layer 224 may be between about 1 nanometer and about 50 nanometers, but the disclosure is not limited thereto.

[0049] In some embodiments, the doped dielectric layer 224 is formed in the second dielectric layer 214 so that the top and bottom surfaces of the doped dielectric layer 224 are in contact with the second dielectric layer 214. Figure 4B In some embodiments, by adjusting the implantation energy, the doped dielectric layer 224 can be formed in the second dielectric layer 214 and the first dielectric layer 212. Therefore, the top surface of the doped dielectric layer 224 contacts the second dielectric layer 214, and the bottom surface of the doped dielectric layer 224 contacts the first dielectric layer 212, as shown in FIG. Fig. 6A shown.

[0050] refer to Figure 4C and Figure 6B In some embodiments, annealing is performed to improve gap filling results, reduce plug resistance, and fix the interface between dielectric structure 210 and metal layer 220. During annealing, metal diffusion may occur, and metal ions may move from conductive feature 202 to an upper portion of metal layer 220 along the interface between dielectric structure 210 and metal layer 220 or within metal layer 220. It should be noted that doped metal portion 222 and doped dielectric layer 224 act as barrier layers that help block or reduce metal diffusion, such as Figure 4C and Figure 6B Therefore, the metal loss problem can be alleviated or reduced.

[0051] refer to Figure 4D and Figure 6C In operation 14, a portion of the metal layer 220 is removed to expose the top surface 210t of the dielectric structure 210 and form a connection structure 240. In some embodiments, in operation 14, a portion of the dielectric structure 210 may be removed, such as a portion of the second dielectric layer 214. In some embodiments, the removal of a portion of the metal layer 220, the doped metal portion 222, and a portion of the dielectric structure 210 may be performed using a CMP operation.

[0052] Thus, a connection structure 240 is obtained. Figure 4DAs shown, the connection structure 240 includes a dielectric structure 210, which includes: a first dielectric layer 212 and a second dielectric layer 214 located above the substrate 200 and the conductive feature 202; a metal layer 220 disposed in the dielectric structure 210; a doped metal portion 222; and a doped dielectric layer 224 disposed above the first dielectric layer 212. As described above, the first dielectric layer 212 and the second dielectric layer 214 may include different dielectric materials. In some embodiments, the metal layer may be divided into two parts by the doped metal portion 222. For example, the metal layer 220 includes a first metal portion 220-1 in contact with the conductive feature 202 and a second metal portion 220-2 disposed above the first metal portion 220-1. In addition, the doped metal portion 222 is disposed between the first metal portion 220-1 and the second metal portion 220-2. As described above, the first metal portion 220-1, the second metal portion 220-2, and the doped metal portion 222 include the same precious metal material. The doped dielectric layer 224 and the second dielectric layer 214 include the same dielectric material. In addition, the doped dielectric layer 224 and the doped metal portion 222 include the same dopant.

[0053] As described above, doped dielectric layer 224 and doped metal portion 222 are substantially aligned with each other. In some embodiments, the thickness of doped dielectric layer 224 may be similar to the thickness of doped metal portion 222, but the present invention is not limited thereto. Figure 4D As shown, the thickness of the first metal portion 220-1 may be greater than the thickness of the first dielectric layer 212, but the present disclosure is not limited thereto. In some embodiments, the top surface of the doped metal portion 222 contacts the second metal portion 220-2, and the bottom surface of the doped metal portion 222 contacts the first metal portion 220-1. In some embodiments, both the top and bottom surfaces of the doped dielectric layer 224 contact the second dielectric layer 214. In other words, a portion of the second dielectric layer 214 is disposed between the doped dielectric layer 224 and the first dielectric layer 212. Figure 4D As shown, the top surface of the doped dielectric layer 224 is spaced apart from the top surface 210 t of the dielectric structure 210 .

[0054] In some embodiments, by removing a portion of the metal layer 220 and a portion of the second dielectric layer 214 in operation 14, the top surface of the doped metal portion 222 and the top surface of the doped dielectric layer 224 may be exposed, as shown in FIG. Figure 5In such an embodiment, the connection structure 240 may include a doped metal portion 222 disposed on the first metal portion 220-1, and a doped dielectric layer 224 disposed on the second dielectric layer 214 and the first dielectric layer 212. In some embodiments, the peak of the profile of the dopant in the doped metal portion 222 may be observed below the top surface of the doped metal portion 222, as shown in FIG. Figure 5 For example, in some embodiments, a peak of the distribution curve of the dopant in the doped metal portion 222 may be observed at the top surface of the doped metal portion 222 .

[0055] refer to Figure 6C In some embodiments, a connection structure 240 may be obtained in operation 14. In these embodiments, a doped dielectric layer 224 is disposed between the first dielectric layer 212 and the second dielectric layer 214. The top surface of the doped dielectric layer 224 contacts the second dielectric layer 214, and the bottom surface of the doped dielectric layer 224 contacts the first dielectric layer 212. Figure 6C As shown, the top surface of the doped dielectric layer 224 is spaced apart from the top surface 210t of the dielectric structure 210. In addition, the thickness of the first metal portion 220-1 can be substantially the same as the thickness of the first dielectric layer 212, which is located below the doped dielectric layer 224, as shown in FIG. Figure 6C shown.

[0056] In some embodiments, by removing a portion of the metal layer 220 and a portion of the second dielectric layer 214 in operation 14, the top surface of the doped metal portion 222 and the top surface of the doped dielectric layer 224 may be exposed, as shown in FIG. Figure 7 In such an embodiment, the connection structure 240 may include a doped metal portion 222 disposed on the first metal portion 220-1 and a doped dielectric layer 224 disposed on the first dielectric layer 212. In some embodiments, the peak of the profile of the dopant in the doped metal portion 222 may be observed below the top surface of the doped metal portion 222, as shown in FIG. Figure 7 For example, in some embodiments, a peak of the profile of the dopant in the doped metal portion 222 may be observed at the top surface of the doped metal portion 222 .

[0057] refer to Figure 4E , Figure 5 , Fig.6D and Figure 7In some embodiments, another dielectric structure 250 may be formed over the dielectric structure 210 and the connection structure 240. Another conductive feature 260 may be formed in the dielectric structure 250. The conductive feature 260 may be coupled to the connection structure 240. In some embodiments, the conductive feature 260 may refer to Figure 1 In some embodiments, the conductive feature 260 may refer to the connection structure 140, 142. Figure 1 The metal wire 150 in.

[0058] According to the method 10 for forming a semiconductor device, the doped metal portion 222 is formed before removing a portion of the metal layer 220 and a portion of the dielectric structure 210. The doped metal portion 222 including the dopant bonded to the metal material acts as a diffusion barrier so that metal diffusion can be blocked or reduced, and the metal loss problem can be alleviated or reduced. In some embodiments, as Figure 4E , Figure 5 , Fig.6D and Figure 7 As shown, the doped dielectric layer 224 can be formed to act as a diffusion barrier for alleviating metal loss issues. As described above, the thickness of the doped metal portion 222 and the doped dielectric layer 224 can be between about 1 nanometer and about 50 nanometers. When the thickness of the doped metal portion 222 and the thickness of the doped dielectric layer 224 are less than about 1 nanometer, the diffusion barrier may be too thin to block metal diffusion. In some alternative methods, when the thickness of the doped metal portion 222 and the thickness of the doped dielectric layer 224 are greater than about 50 nanometers, such thickness may result in higher costs for removing the doped metal portion 222 and the doped dielectric layer 224.

[0059] Figure 8 30 is a flow chart representing a method 30 for forming a semiconductor device according to aspects of the present disclosure. In some embodiments, the method 30 for forming a semiconductor device includes a plurality of operations (31, 32, 33, and 34). The method 30 for forming a semiconductor device will be further described according to one or more embodiments. It should be noted that the operations of the method 30 for forming a semiconductor device may be rearranged or otherwise modified within the scope of various aspects. It should also be noted that additional processes may be provided before, during, and after the method 30, and some other processes may only be briefly described herein.

[0060] 9A to 9F is a schematic diagram showing various stages in a method 30 for forming a semiconductor device according to aspects of one or more embodiments of the present disclosure. It should be noted that FIG. 3A to FIG. 3F and 9A to 9FThe same materials may be included, and repeated details may be omitted for brevity. In some embodiments, a substrate 400 may be received. The substrate 400 may be Figure 1 The substrate 102 is shown, but the present disclosure is not limited thereto. In some embodiments, the substrate 400 may include a semiconductor device, such as Figure 1 The transistor shown in FIG. 1 is a transistor, but the present disclosure is not limited thereto. Fig. 9A As shown, substrate 400 may include conductive features 402 disposed therein. In some embodiments, conductive features 402 may be similar to Figure 1 1 or the FEOL features of the metal gate 110 or source / drain regions S / D shown in FIG. In some embodiments, the conductive features 402 may be MEOL features, such as those similar to Figure 1 , 132. In other embodiments, the conductive feature 402 may be a BEOL feature, such as Figure 1 The metal line (M) feature 150 shown in FIG.

[0061] In operation 31, a dielectric structure 410 is formed over substrate 400 and conductive features 402. In some embodiments, dielectric structure 410 may include a single layer. In some embodiments, dielectric structure 410 may include a multi-layer structure. For example, Fig. 9A As shown, dielectric structure 410 may include at least first dielectric layer 412 and second dielectric layer 414, which are sequentially stacked on substrate 400 and conductive feature 402. First dielectric layer 412 and second dielectric layer 414 may include different dielectric materials.

[0062] Still reference Fig. 9A In operation 31, an opening 415 may be formed in the dielectric structure 410. In some embodiments, the opening 415 passes through the dielectric structure 410 from the top surface 410t to the bottom of the dielectric structure 410. Thus, a portion of the conductive feature 402 is exposed through the opening 415.

[0063] refer to Fig. 9B, in operation 32, a metal layer 420 such as a noble metal layer may be formed to fill the opening 415. The metal layer 420 extends from the top surface 410t of the dielectric structure 410 to the bottom of the dielectric structure 410. The metal layer 420 passes through the second dielectric layer 414 and the first dielectric layer 412 to contact the exposed portion of the conductive feature 402. In addition, the metal layer 420 covers the top surface 410t of the dielectric structure 410. It should be noted that in some embodiments, the metal layer 420 may be formed without a liner, a barrier, a seed layer, or any intermediate layer. Therefore, in such an embodiment, the metal layer 420 may be in contact with the dielectric structure 410, but the present disclosure is not limited thereto.

[0064] refer to Fig. 9C In operation 33, a portion of the metal layer 420 is removed to expose the top surface 410t of the dielectric structure 410 and form a connection structure 440. In some embodiments, in operation 33, a portion of the dielectric structure 410 may be removed, for example, a portion of the second dielectric layer 414. In some embodiments, the removal of a portion of the metal layer 420 and a portion of the dielectric structure 410 may be performed using a CMP process.

[0065] refer to Fig.9D In operation 34, a doped metal portion 422 is formed in the metal layer 420, and a doped dielectric layer 424 is formed in the second dielectric layer 414 of the dielectric structure 410. In some embodiments, the doped metal portion 422 and the doped dielectric layer 424 are aligned with each other, but the present disclosure is not limited thereto. In some embodiments, the doped metal portion 422 and the doped dielectric layer 424 include phosphorus (P), boron (B), arsenic (As), gallium (Ga), or indium (In), but the present disclosure is not limited thereto. In some embodiments, the formation of the doped metal portion 422 and the doped dielectric layer 424 includes ion implantation. The dose of the ion implantation may be about 1E13 cm -2 to about 1E16 cm -2 The angle of the ion implantation may be between about 0 degrees and about 60 degrees. In some embodiments, the temperature of the ion implantation may be between about -100°C and about 500°C. It should be noted that the formed position or depth of the doped metal portion 422 may be determined by the implantation energy of the ion implantation. For example, when the implantation energy of the ion implantation is between about 500 eV and about 50 KeV, the doped metal portion 422 may be formed on the upper portion of the metal layer 420, and the doped dielectric layer 424 may be formed on the upper portion of the second dielectric layer 414. In some embodiments, as Fig.9D As shown, the top surface of the doped metal portion 422 and the top surface of the doped dielectric layer 424 are exposed. The distribution of the dopant in the doped metal portion 422 in the doped dielectric layer 424 is depicted as Fig.9DIn some embodiments, the peak of the distribution curve may be near the middle of the doped metal portion 422 and the middle of the doped dielectric layer 424, but the disclosure is not limited thereto. In some embodiments, the thickness of the doped metal portion 422 may be between about 1 nanometer and about 30 nanometers, but the disclosure is not limited thereto. In addition, the thickness of the doped dielectric layer 424 may be between about 1 nanometer and about 50 nanometers, but the disclosure is not limited thereto.

[0066] refer to Fig.9E In some embodiments, annealing is performed to improve gap filling results, reduce plug resistance, and fix the interface between dielectric structure 410 and metal layer 420. During annealing, metal diffusion may occur, and metal ions may move from conductive feature 402 to the upper portion of metal layer 420 along the interface between dielectric structure 410 and metal layer 420 or within metal layer 420. It should be noted that doped metal portion 422, together with doped dielectric layer 424, acts as a barrier layer that helps to block or reduce metal diffusion, such as Fig.9E Therefore, the metal loss problem can be alleviated or reduced.

[0067] According to the method 30 for forming a semiconductor device, the doped metal portion 422 and the doped dielectric layer 424 can be formed after removing a portion of the metal layer 420 and a portion of the second dielectric layer 414. The doped metal portion 422 includes ions that can be bonded to the metal layer, such as Ru. Therefore, the doped metal portion 422 can include ruthenium phosphide, ruthenium boride, and ruthenium arsenide, and act as a diffusion barrier. Therefore, the diffusion barrier can prevent metal diffusion, and the metal loss problem can be alleviated. As described above, the thickness of the doped metal portion 422 and the thickness of the doped dielectric layer 424 can be between about 1 nanometer and about 30 nanometers. When the thickness of the doped metal portion 422 and the thickness of the doped dielectric layer 424 are less than about 1 nanometer, the diffusion barrier may be too thin to block metal diffusion. In some alternative methods, when the thickness of the doped metal portion 422 and the thickness of the doped dielectric layer 424 are greater than about 50 nanometers, the thickness can have a negative impact on the resistance of the conductive feature 402.

[0068] FIG. 10A to FIG. 10C 3 is a schematic diagram showing various stages in a method 30 for forming a semiconductor device according to aspects of one or more embodiments of the present disclosure. 9A to 9C The associated steps are then executed as follows FIG. 10A to FIG. 10C It should be understood that 9A to 9F and FIG. 10A to FIG. 10C Depicted by the same numerals, and repeated details may be omitted for the sake of brevity.

[0069] In some embodiments, a substrate 400 may be received. Fig. 10A As shown, substrate 400 may include conductive features 402 disposed therein. In operation 31, a dielectric structure 410 is formed over substrate 400 and conductive features 402, and an opening may be formed in dielectric structure 410. In operation 32, a metal layer 420 such as a noble metal layer may be formed to fill the opening. As described above, in some embodiments, metal layer 420 may be formed without a liner, barrier, seed layer, or any intermediate layer. Therefore, in such an embodiment, metal layer 420 may be in contact with dielectric structure 410, but the present disclosure is not limited thereto.

[0070] refer to Fig. 10A In operation 33, a portion of the metal layer 420 is removed to expose the top surface 410t of the dielectric structure 410 and form a connection structure 440. In some embodiments, in operation 33, a portion of the dielectric structure 410 may be removed, for example, a portion of the second dielectric layer 414. In some embodiments, the removal of a portion of the metal layer 420 and a portion of the dielectric structure 410 may be performed using a CMP process.

[0071] In operation 34, a doped metal portion 422 is formed in the metal layer 420, and a doped dielectric layer 424 is formed in the dielectric structure 410. In some embodiments, the formation of the doped metal portion includes ion implantation. The dose, angle, and temperature used in the ion implantation can be similar to those described above; therefore, the details are omitted for the sake of brevity. It should be noted that the depth or position of the doped metal portion 422 and the doped dielectric layer 424 can be determined by the implantation energy of the ion implantation. For example, by adjusting the implantation energy, the doped metal portion 422 and the doped dielectric layer 424 can be formed away from the top surface 410t of the dielectric structure 410 or formed at the lower portion of the second dielectric layer 414. In some embodiments, by adjusting the implantation energy, the doped dielectric layer 424 can be formed in both the first dielectric layer 412 and the second dielectric layer 414, such as Fig. 10A However, it should be noted that by controlling or adjusting the implantation energy of the ion implantation, the doped metal portion 422 and the doped dielectric layer 424 are separated from the conductive feature 402. In some comparative methods, when the doped metal portion 422 contacts the conductive feature 402, the resistance of the conductive feature 402 may be negatively affected.

[0072] refer to Fig. 10BIn some embodiments, annealing is performed to improve gap filling results, reduce plug resistance, and fix the interface between dielectric structure 410 and metal layer 420. During annealing, metal diffusion may occur, and metal ions may move from conductive feature 402 to the upper portion of metal layer 420 along the interface between dielectric structure 410 and metal layer 420 or within metal layer 420. It should be noted that Fig. 10B As shown, doped metal portion 422 and doped dielectric layer 424 act as barrier layers that help block or reduce metal diffusion. Thus, metal loss issues can be mitigated or reduced.

[0073] refer to Fig.9F and Fig. 10C In some embodiments, another dielectric structure 450 may be formed over the dielectric structure 410 and the connection structure 440. Another conductive feature 460 may be formed in the dielectric structure 450. The conductive feature 460 may be coupled to the connection structure 440. In some embodiments, the conductive feature 460 may refer to Figure 1 In some embodiments, the conductive feature 460 may refer to the connection structure 140, 142. Figure 1 The metal wire 150 in.

[0074] Accordingly, a connection structure 440 is obtained, such as Fig.9E or Fig. 10B As shown. The connection structure 440 includes a dielectric structure 410, which includes: a first dielectric layer 412 and a second dielectric layer 414 located above the substrate 400 and the conductive feature 402; a metal layer 420 disposed in the dielectric structure 410; a doped metal portion 422; and a doped dielectric layer 424. In some embodiments, the top surface of the doped metal portion 422 and the top surface of the doped dielectric layer 424 form the top surface of the connection structure 440, as shown in FIG. Fig.9E In such an embodiment, the second dielectric layer 414 can be disposed between the doped dielectric layer 424 and the first dielectric layer 412. Thus, the bottom surface of the doped dielectric layer 424 is in contact with the second dielectric layer 414. In addition, the doped metal portion 422 is separated from the conductive feature 402 by the metal layer 420.

[0075] In other embodiments, as described above, metal layer 420 may be divided into two portions by doped metal portion 422. For example, the metal layer includes a first metal portion 420-1 in contact with conductive feature 402 and a second metal portion 420-2 disposed on first metal portion 420-1. In addition, doped metal portion 422 including a dopant bonded to a metal material is disposed between first metal portion 420-1 and second metal portion 420-2. In such an embodiment, doped dielectric layer 424 is disposed between first dielectric layer 412 and second dielectric layer 414. In some embodiments, the thickness of first metal portion 420-1 may be greater than the thickness of first dielectric layer 412, such as Fig.9E In other embodiments, the thickness of the first metal portion 420-1 may be substantially the same as the thickness of the first dielectric layer 412, which is located below the doped dielectric layer 424. Fig. 10B In some embodiments, the top surface of the doped metal portion 422 is separated from the top surface of the connection structure 440 by the second metal portion 420-2, and the top surface of the doped dielectric layer 424 is separated from the top surface 410t of the dielectric structure 410 and the top surface of the connection structure 440 by the second dielectric layer 414. In such an embodiment, the top surface of the doped metal portion 422 is in contact with the second metal portion 420-2, and the bottom surface of the doped metal portion 422 is in contact with the first metal portion 420-1. The top surface of the doped dielectric layer 424 is in contact with the second dielectric layer 414, and the bottom surface of the doped dielectric layer 424 is in contact with the first dielectric layer 412.

[0076] As described above, doped dielectric layer 424 and doped metal portion 422 are substantially aligned with each other. In some embodiments, the thickness of doped dielectric layer 424 can be similar to the thickness of doped metal portion 422, but the disclosure is not limited thereto.

[0077] According to the method 30 for forming a semiconductor device, the doped metal portion 422 and the doped dielectric layer 424 can be formed after removing a portion of the metal layer 420 and a portion of the second dielectric layer 414. The doped metal portion 422, which includes a dopant bonded to the metal material, acts as a diffusion barrier so that metal diffusion can be blocked and metal loss problems can be alleviated. As described above, the thickness of the doped metal portion 422 and the thickness of the doped dielectric layer 424 can be between about 1 nanometer and about 30 nanometers. When the thickness of the doped metal portion 422 and the thickness of the doped dielectric layer 424 are less than about 1 nanometer, the diffusion barrier may be too thin to block metal diffusion. In some alternative methods, when the thickness of the doped metal portion 422 and the thickness of the doped dielectric layer 424 are greater than about 50 nanometers, such thickness may have a negative impact on the resistance of the conductive feature 402.

[0078] In short, embodiments of the present disclosure provide semiconductor devices including connection structures and methods for forming semiconductor devices to mitigate bottom metal loss problems. In some embodiments, ion implantation is performed after processing a metal layer to form a barrier layer in a conductive material. The ion implantation may be performed before or after removing excess metal layers. In some embodiments, ions implanted into the conductive material are bonded to the conductive material to form a diffusion barrier layer so that metal diffusion can be blocked by the barrier layer. Therefore, the bottom metal loss problem caused by metal diffusion can be mitigated.

[0079] In some embodiments, a semiconductor device is provided. The semiconductor device includes a first dielectric layer disposed over a substrate and a conductive feature, a doped dielectric layer disposed over the first dielectric layer, a first metal portion disposed in the first dielectric layer and in contact with the conductive feature, and a doped metal portion disposed over the first metal portion. In some embodiments, the first metal portion and the doped metal portion include the same noble metal material. In some embodiments, the doped dielectric layer and the doped metal portion include the same dopant. In some embodiments, the dopant is bonded to the noble metal material in the doped metal portion.

[0080] In some embodiments, a method for forming a semiconductor device is provided. The method includes the following operations. A dielectric structure is formed over a conductive feature. The dielectric structure includes an opening that exposes a portion of the conductive feature. The opening is filled with a metal layer. A doped metal portion is formed in the metal layer. A portion of the metal layer is removed to expose a top surface of the dielectric structure and form a connection structure.

[0081] In some embodiments, a method for forming a semiconductor device is provided. The method includes the following operations. A dielectric structure is formed over a conductive feature. The dielectric structure includes an opening that exposes a portion of the conductive feature. The opening is filled with a metal layer. The metal layer covers a top surface of the dielectric structure. A portion of the metal layer is removed to expose the top surface of the dielectric structure. After removing the portion of the metal layer, a doped metal portion is formed in the metal layer, and a doped dielectric layer is formed in the dielectric structure. The metal layer and the doped metal portion include the same metal material. The doped metal portion and the doped dielectric layer include the same dopant. The dopant is bonded to the metal material in the doped metal portion.

[0082] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose of the embodiments introduced herein and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

[0083] Example 1. A semiconductor device comprising:

[0084] a first dielectric layer disposed over the substrate and the conductive features;

[0085] a doped dielectric layer, disposed on the first dielectric layer;

[0086] a first metal portion disposed in the first dielectric layer and contacting the conductive feature; and

[0087] A doped metal portion is disposed above the first metal portion, wherein the first metal portion and the doped metal portion include the same precious metal material, and the doped dielectric layer and the doped metal portion include the same dopant, wherein the dopant is bonded to the precious metal material in the doped metal portion.

[0088] Example 2. The semiconductor device of Example 1, wherein the doped dielectric layer and the doped metal portion are substantially aligned with each other.

[0089] Example 3. The semiconductor device of Example 1, wherein the doped dielectric layer contacts the first dielectric layer.

[0090] Example 4. The semiconductor device according to Example 1 further includes a second dielectric layer arranged above the substrate, wherein the first dielectric layer includes a first dielectric material, the second dielectric layer and the doped dielectric layer include a second dielectric material, and the first dielectric material and the second dielectric material are different.

[0091] Example 5. The semiconductor device of Example 4, wherein the second dielectric layer is disposed between the doped dielectric layer and the first dielectric layer.

[0092] Example 6. The semiconductor device of Example 4, wherein the doped dielectric layer is disposed between the second dielectric layer and the first dielectric layer.

[0093] Example 7. The semiconductor device of Example 1 further includes a second metal portion disposed above the substrate, wherein the second metal portion includes the same precious metal material as the first metal portion.

[0094] Example 8. The semiconductor device of Example 7, wherein the doped metal portion is disposed between the second metal portion and the first metal portion.

[0095] Example 9. The semiconductor device of Example 1, wherein the dopant comprises phosphorus (P), boron (B), arsenic (As), gallium (Ga), or indium (In).

[0096] Example 10. A method for forming a semiconductor device, comprising:

[0097] forming a dielectric structure over the conductive feature, wherein the dielectric structure includes an opening that exposes a portion of the conductive feature;

[0098] filling the opening with a metal layer comprising a noble metal material;

[0099] forming a doped metal portion in the metal layer, wherein the doped metal portion includes a dopant that bonds to the metal material; and

[0100] A portion of the metal layer is removed to expose a top surface of the dielectric structure and form a connection structure.

[0101] Example 11. The method according to Example 10, wherein the precious metal material includes rhenium (Re), rhodium (Rh) and ruthenium (Ru).

[0102] Example 12. The method of Example 11, wherein the dopant comprises phosphorus, boron, arsenic, or nitrogen.

[0103] Example 13. The method of Example 10, wherein the doped metal portion covers a top surface of the dielectric structure, and during the removal of the portion of the metal layer, the doped metal portion is removed to expose the top surface of the dielectric structure.

[0104] Example 14. The method of Example 13, wherein the forming of the doped metal portion comprises ion implantation, and an implantation energy of the ion implantation is between about 500 eV and about 50 KeV.

[0105] Example 15. The method of Example 10, further comprising forming a doped dielectric layer in the dielectric structure simultaneously with the forming of the doped metal portion, wherein the doped dielectric layer and the doped metal portion are substantially aligned with each other.

[0106] Example 16. The method of Example 15, wherein the forming of the doped metal portion and the forming of the doped dielectric layer include ion implantation using an implantation energy greater than about 50 KeV.

[0107] Example 17. The method of Example 15, wherein the doped metal portion is spaced apart from a top surface of the metal layer, and the doped dielectric layer is spaced apart from a top surface of the dielectric structure.

[0108] Example 18. A method for forming a semiconductor device, the method comprising:

[0109] forming a dielectric structure over the conductive feature, wherein the dielectric structure includes an opening that exposes a portion of the conductive feature;

[0110] filling the opening with a metal layer, wherein the metal layer covers a top surface of the dielectric structure;

[0111] removing a portion of the metal layer to expose a top surface of the dielectric structure; and

[0112] After removing the portion of the metal layer, a doped metal portion is formed in the metal layer and a doped dielectric layer is formed in the dielectric structure, wherein the metal layer and the doped metal portion include the same metal material, the doped metal portion and the doped dielectric layer include the same dopant, and the dopant is bonded to the metal material in the doped metal portion.

[0113] Example 19. The method according to Example 18, wherein the metal material comprises a precious metal material.

[0114] Example 20. The method of Example 18, wherein the dopant comprises phosphorus (P), boron (B), arsenic (As), gallium (Ga), or indium (In).

Claims

1. A semiconductor device, comprising: a first dielectric layer disposed over the substrate and the conductive features; a doped dielectric layer, disposed on the first dielectric layer; a first metal portion disposed in the first dielectric layer and in contact with the conductive feature; as well as A doped metal portion is arranged on the first metal portion, wherein the first metal portion and the doped metal portion include the same precious metal material, the doped dielectric layer and the doped metal portion include the same dopant, wherein the dopant is bonded to the precious metal material in the doped metal portion, and the peak of the distribution curve of the dopant in the doped metal portion is at a position close to the middle of the doped metal portion.

2. The semiconductor device according to claim 1, wherein The doped dielectric layer and the doped metal portion are substantially aligned with each other.

3. The semiconductor device according to claim 1, wherein The doped dielectric layer contacts the first dielectric layer.

4. The semiconductor device according to claim 1, further comprising a second dielectric layer disposed on the substrate, wherein The first dielectric layer includes a first dielectric material, the second dielectric layer and the doped dielectric layer include a second dielectric material, and the first dielectric material and the second dielectric material are different.

5. The semiconductor device according to claim 4, wherein: The second dielectric layer is disposed between the doped dielectric layer and the first dielectric layer.

6. The semiconductor device according to claim 4, wherein: The doped dielectric layer is disposed between the second dielectric layer and the first dielectric layer.

7. The semiconductor device according to claim 1, further comprising a second metal portion disposed on the substrate, wherein The second metal portion includes the same noble metal material as the first metal portion.

8. The semiconductor device according to claim 7, wherein: The doped metal portion is disposed between the second metal portion and the first metal portion.

9. The semiconductor device according to claim 1, wherein: The dopant includes phosphorus (P), boron (B), arsenic (As), gallium (Ga), or indium (In).

10. A method for forming a semiconductor device, comprising: forming a dielectric structure over the conductive feature, wherein the dielectric structure includes an opening that exposes a portion of the conductive feature; filling the opening with a metal layer comprising a noble metal material; forming a doped metal portion in the metal layer, wherein the doped metal portion includes a dopant that bonds to the metal material; and removing a portion of the metal layer to expose a top surface of the dielectric structure and form a connection structure, The peak of the distribution curve of the dopant in the doped metal portion is located close to the middle of the doped metal portion.

11. The method according to claim 10, wherein: The noble metal materials include rhenium (Re), rhodium (Rh) and ruthenium (Ru).

12. The method according to claim 11, wherein: The dopant includes phosphorus, boron, arsenic or nitrogen.

13. The method according to claim 10, wherein: The doped metal portion covers a top surface of the dielectric structure, and during the removal of the portion of the metal layer, the doped metal portion is removed to expose the top surface of the dielectric structure.

14. The method according to claim 13, wherein: The forming of the doped metal portion includes ion implantation, and the implantation energy of the ion implantation is between 500 eV and 50 KeV.

15. The method of claim 10, further comprising forming a doped dielectric layer in the dielectric structure simultaneously with the forming of the doped metal portion, wherein The doped dielectric layer and the doped metal portion are substantially aligned with each other.

16. The method according to claim 15, wherein: The forming of the doped metal portion and the forming of the doped dielectric layer include ion implantation using an implantation energy greater than 50 KeV.

17. The method according to claim 15, wherein: The doped metal portion is spaced apart from a top surface of the metal layer, and the doped dielectric layer is spaced apart from a top surface of the dielectric structure.

18. A method for forming a semiconductor device, the method comprising: forming a dielectric structure over the conductive feature, wherein the dielectric structure includes an opening that exposes a portion of the conductive feature; filling the opening with a metal layer, wherein the metal layer covers a top surface of the dielectric structure; removing a portion of the metal layer to expose a top surface of the dielectric structure; and After removing the portion of the metal layer, a doped metal portion is formed in the metal layer and a doped dielectric layer is formed in the dielectric structure, wherein the metal layer and the doped metal portion include the same metal material, the doped metal portion and the doped dielectric layer include the same dopant, and the dopant is bonded to the metal material in the doped metal portion.

19. The method according to claim 18, wherein: The metal material includes a noble metal material.

20. The method according to claim 18, wherein: The dopant includes phosphorus (P), boron (B), arsenic (As), gallium (Ga), or indium (In).

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