Semiconductor assembly including combined memory and method for manufacturing the same

Abstract

The present application relates to semiconductor assemblies including combined memories and methods of manufacturing the same. A semiconductor device including a vertically stacked combined memory device and associated systems and methods are disclosed herein. The vertically stacked combined memory device includes at least one volatile memory die and at least one non-volatile memory die stacked one on top of the other. The corresponding stack can be attached to a controller die configured to provide an interface to the attached volatile and non-volatile memory dies.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Application No. 62 / 958,159, filed on January 7, 2020; which is incorporated herein by reference in its entirety. Technical Field

[0003] The present technology relates to packaging semiconductor assemblies, such as memory and processors, and several embodiments relate to semiconductor assemblies including vertical integrated circuits. Background Art

[0004] The current trend in semiconductor manufacturing is to create smaller and faster devices and to provide higher density components for computers, cell phones, pagers, personal digital assistants, and many other products. Since semiconductor devices / components are typically arranged along a lateral plane (e.g., on a circuit board), increasing density becomes critical to providing increased capacity and / or functionality for the corresponding products (e.g., computers, cell phones, etc.). Summary of the invention

[0005] In one aspect, the present disclosure provides a semiconductor package comprising: a die stack, comprising a group of dies stacked vertically on top of each other, the group of dies comprising: at least one volatile memory die configured to store volatile data when power is available, at least one NV memory die configured to retain non-volatile (NV) data when power is not available; and a controller device directly attached to the die stack, the controller device configured to provide an interface to the die stack and control the operation of the die stack.

[0006] On the other hand, the present disclosure provides a semiconductor package comprising: a packaging substrate; a logic device attached to the packaging substrate; and a vertically stacked combination (VC) memory device attached to the packaging substrate, wherein the VC memory device is a die stack including: at least one dynamic random access memory (DRAM) die, at least one non-volatile (NV) memory die, and a controller die electrically coupled to the packaging substrate, the at least one DRAM die, and the at least one NV memory die, the controller die being configured to provide an external interface for the die stack and to control the operation of the die stack, wherein the die stack includes the at least one DRAM die, the at least one NV memory die, and the controller die attached to each other and vertically stacked one above the other.

[0007] On the other hand, the present disclosure provides a semiconductor assembly comprising: a vertically stacked combination (VC) memory device electrically coupled to an assembly substrate, wherein the VC memory device is a die stack including: at least one dynamic random access memory (DRAM) die, at least one non-volatile (NV) memory die, and a controller die electrically coupled to the assembly substrate, the at least one DRAM die, and the at least one NV memory die, the controller die being configured to provide an external interface for the die stack and to control the operation of the die stack, wherein the die stack includes the at least one DRAM die, the at least one NV memory die, and the controller die attached to each other and vertically stacked one above the other.

[0008] In another aspect, the present disclosure provides a method of manufacturing a semiconductor package, the method comprising: providing a controller die; attaching a first memory die over the controller die, wherein the first die includes either a volatile memory cell or a non-volatile (NV) memory cell and a through silicon via (TSV) electrically coupled to the controller die and extending away from the controller die; and attaching a second memory die over the first die and electrically coupling it to the TSV of the first die, wherein the second die includes the other of the volatile memory cell or the NV memory cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1A is a top view of a semiconductor device assembly according to an embodiment of the present technology.

[0010] Figure 1B According to an embodiment of the present invention Figure 1A Schematic cross-sectional view of a semiconductor device assembly taken along line 1B--1B.

[0011] Figure 2 is a schematic cross-sectional view of a vertically stacked combination memory device according to an embodiment of the present technology.

[0012] Figure 3 is a schematic cross-sectional view of a vertically stacked combination memory device according to an embodiment of the present technology.

[0013] Figure 4 is a schematic cross-sectional view of a vertically stacked combination memory device according to an embodiment of the present technology.

[0014] Figure 5 is a flow chart illustrating a method of manufacturing a semiconductor device assembly according to an embodiment of the present technology.

[0015] Figure 6is a schematic diagram of a system including a semiconductor assembly configured in accordance with an embodiment of the present technology. DETAILED DESCRIPTION

[0016] In the following description, many specific details are discussed in order to provide a full and illuminating description of the embodiments of the present invention. However, those skilled in the relevant art will recognize that the present disclosure can be practiced without one or more of the specific details. In other examples, well-known structures or operations typically associated with semiconductor devices are not shown or described in detail to avoid obscuring other aspects of the present invention. In general, it should be understood that various other devices, systems, and methods other than those specific embodiments disclosed herein may also be within the scope of the present invention.

[0017] Several embodiments of semiconductor devices, packages, and / or assemblies according to the present technology may include a vertically stacked combined memory device ("combined memory device"). The combined memory device includes at least one permanent memory die (e.g., one or more NAND dies) and at least one volatile memory die (e.g., one or more dynamic random access memory (DRAM) dies) stacked vertically on top of each other. For example, the combined memory device may include one or more NAND dies stacked on / above one or more DRAM dies. The die stack including NAND and DRAM dies may be attached to a controller (e.g., a logic die and / or a substrate). The NAND and / or DRAM dies may include and / or may be electrically coupled to through silicon vias (TSVs). TSVs may be used to transmit information (e.g., commands and / or data) between dies, such as between a controller, a NAND die, and / or a DRAM die. Thus, the TSVs may form vertical electrical connections extending between the controller and one or more of the DRAM dies, between the controller and one or more of the NAND dies, and / or between one or more of the DRAM dies and one or more of the NAND dies.

[0018] In some embodiments, one or more dimensions of the NAND die may match corresponding dimensions of the DRAM die. For example, a die stack including NAND and DRAM die may have a rectilinear three-dimensional shape. Additionally, one or more dimensions of the controller may match corresponding dimensions of the die stack. In other embodiments, the controller may extend laterally beyond one or more peripheral edges of the NAND die and / or the DRAM die. In one or more embodiments, the DRAM die may include a high bandwidth memory (HBM) device, which includes a three-dimensional (3D) stacked volatile memory device (e.g., a synchronous DRM (SDRAM) die).

[0019] The combined memory device can be used for various applications. For example, a semiconductor package / assembly may include a combined device and other logic devices (e.g., logic devices or processors, such as application processors) and / or other memory devices (e.g., HBM). In some embodiments, the combined device can be attached to one or more other devices on the package substrate in a lateral proximity. The height of the combined device can match the height of other devices on the package substrate. In some embodiments, the corresponding package can be attached to the assembly substrate or system substrate together with other devices or components. Details about the combined device and its application are described below.

[0020] Figure 1A is a top view of a semiconductor device assembly 100 (“assembly 100 ”), Figure 1B According to an embodiment of the present invention Figure 1A A schematic cross-sectional view of the assembly 100 taken along line 1B--1B. Figure 1A and Figure 1B , assembly 100 may include a semiconductor package 102 ("package 102") on an assembly substrate 104 (e.g., a printed circuit board (PCB) substrate). Package 102 may be attached to assembly substrate 104 via electrical and / or mechanical connectors such as solder, fused metal, adhesive, conductive wires (e.g., bonding wires), etc. Electrical connectors may also electrically couple package 102 to assembly substrate 104 and / or electrically couple other components to assembly substrate 104.

[0021] Package 102 may include one or more functional devices, such as one or more logic devices 122, one or more memory devices 124, and / or a vertically stacked combined memory device 130 ("VC memory device 130"). In some embodiments, for example, package 102 may include a package substrate 112 (e.g., a silicon interposer) and an application processor and / or HBM, and a VC memory device 130 on package substrate 112. The functional devices may be placed in close proximity to each other (e.g., laterally adjacent to each other) on package substrate 112. The functional devices may be attached and electrically coupled to package substrate 112 using solder, wires, fused metals, adhesives, and / or other connection mechanisms. Package 102 may be a chip-on-wafer (CoW) device and / or assembly 100 may be a chip-on-wafer-on-substrate (CoWoS) device. Based on the functional devices, package 102 may be configured to perform a set of functions to process information.

[0022] To process information, assembly 100 and / or package 102 may include a VC memory device 130 having non-volatile (NV) or permanent memory and volatile or non-permanent memory within or corresponding to one structural unit (e.g., a packaging structure, a housing, and / or a single or combined interface). As described in detail below, VC memory device 130 may include one or more NV memory dies and one or more DRAM dies stacked vertically on top of each other. VC memory device 130 may also include a controller die having vertically stacked NV memory and DRAM dies.

[0023] In some embodiments, package 102 may include an encapsulant (e.g., an epoxy or resin material) that directly contacts and encapsulates VC memory device 130, logic device 122, memory device 124, at least a portion of package substrate 112, or a combination thereof. In some embodiments, VC memory device 130 may include an encapsulant that encapsulates a group of vertically stacked semiconductor dies.

[0024] In some embodiments, the height 126 of the VC memory device 130 may match the height of other devices on the package substrate 112 and / or other structures on the assembly substrate 104. For example, the VC memory device 130 may be configured to have a height 126 that matches or corresponds to a common height of a group of adjacently located devices / components.

[0025] Figure 2 2 is a schematic cross-sectional view of a vertically stacked combined memory device 200 ("VC memory device 200") according to an embodiment of the present technology. VC memory device 200 may be Figure 1B An example of a VC memory device 130 .

[0026] The VC memory device 200 may include a controller die 202, an NV memory die 204, and a volatile memory die 206 within a single structure (e.g., a package). The NV memory die 204 may include an NV memory cell (e.g., a NAND-type floating gate memory cell that stores charge) configured to store / retain information (e.g., charge) across power reset / cycles. The volatile memory die 206 (e.g., a DRAM die) may include a memory cell including a capacitor and / or a transistor configured to store / retain charge when input power is provided or applied. The charge and corresponding information stored in the volatile memory die 206 may be removed or changed when the input power is removed. The controller die 202 may include circuits configured to control the operation of the NV memory die 204 and / or the volatile memory die 206. For example, the controller die 202 may be configured to control a read operation, a write operation, an erase operation, a refresh operation, etc. of a NAND memory and / or a DRAM memory. Also, the controller die 202 may be configured to transfer stored information from one die to another die. In some embodiments, the controller die 202 may be configured to facilitate the transfer of information stored in the volatile memory die 206 to the NV memory die 204 based on a triggering event (e.g., a power-off event). The controller die 202 may further restore previously stored information to the volatile memory die 206 based on a reload event (e.g., a power-on event), such as by loading the information stored in the NV memory die 204 to the volatile memory die 206.

[0027] In one or more embodiments, the volatile memory die 206 can be directly attached to and above the controller die 202 via an attachment mechanism 210 such as solder, bonding wire and / or adhesive. The volatile memory die 206 can be directly attached to the controller die 202 so that there is no intermediate die or circuit between the directly attached structures. Similarly, the NV memory die 204 can be directly attached to and above the volatile memory die 206. Therefore, the NV memory die 204 can be attached to the controller die 202, wherein there is a volatile memory die 206 between the two structures. Therefore, the controller die 202, the NV memory die 204 and / or the volatile memory die 206 can form a die stack. In other embodiments, the stacking order of the die can be different. For example, the volatile memory die 206 can be attached above the NV memory die 204. Also, the controller die 202 may be attached over the volatile memory die 206 and / or the NV memory die 204 .

[0028] To communicate signals (e.g., commands and / or data) between the vertically attached dies, the controller die 202, the volatile memory die 206, and / or the NV memory die 204 may include through silicon vias 208 ("TSVs 208"). The TSVs 208 may include metal structures (e.g., connection paths) that extend through the body / thickness of the corresponding die, such as from an active side of the die to an opposite side thereof. The TSVs 208 may be electrically connected (e.g., via traces, pads, solder, metal pillars, etc.) to provide direct die-to-die connections 212 between the attached dies. For example, the direct die-to-die connections 212 may allow the controller die 202 to communicate directly with the volatile memory die 206 and / or the NV memory die 204 (e.g., without routing the signal through active circuitry on an intermediate die).

[0029] In some embodiments, direct die-to-die connections 212 may allow external devices (e.g., Figure 1B The controller die 202 may communicate directly with the volatile memory die 206 and / or the NV memory die 204. Additionally or alternatively, the controller die 202 may be configured to provide external interfacing functionality for the volatile memory die 206 and / or the NV memory die 204. In other words, the controller die 202 may communicate with the logic device 122 to store information to the volatile memory die 206 and / or the NV memory die 204 and / or to access information stored therein.

[0030] for Figure 2 , the controller die 202 and the volatile memory die 206 include TSVs 208. The controller die 202 may be a flip chip with the active surface / circuitry facing down. The TSVs 208 may thus form direct inter-die connections 212 between the active side of the controller die 202 and the volatile memory die 206 and / or the NV memory die 204. In some embodiments, the TSVs 208 may provide a means of bypassing the active circuitry of the controller die 202 and passing through the Figure 1B The packaging substrate 112 electrically connects the volatile memory die 206 and / or the NV memory die 204 to the logic device 122 .

[0031] In some embodiments, the vertically stacked dies may be aligned and / or have one or more matching dimensions. For example, the stacked dies (e.g., volatile memory die 206, NV memory die 204, and / or controller die 202) may have the same lateral dimension 215 (e.g., length and / or width). The vertically stacked dies may be aligned so that their central portions coincide with the vertical alignment line. And, the vertically stacked dies may have peripheral edges that coincide with the vertical alignment plane 214. Thus, the die stack may have a rectangular box shape or a cubic shape (i.e., a three-dimensional linear shape). In one or more embodiments, one die (e.g., a bottom die, such as controller die 202) may have one or more dimensions that are greater than the lateral dimension 215 of the other stacked dies. Thus, the peripheral edge of the one die may laterally protrude beyond (e.g., positioned further away from its central portion) the corresponding peripheral edge of the stacked die (e.g., volatile memory die 206 and / or NV memory die 204) by a protrusion distance 216.

[0032] Although solder and / or other adhesive mechanisms physically attach the dies, the operation of the vertically stacked combination of volatile memory die 206 and NV memory die 204 can be implemented using direct die-to-die connections 212 and / or controller die 202. Data, commands, and / or other signals from an external device (e.g., a processor such as logic device 122) can be initially processed by controller die 202. Controller die 202 can use direct die-to-die connections 212 to directly control or operate each of volatile memory die 206 and NV memory die 204. For example, controller die 202 can identify and send critical data and / or corresponding commands directly to NV memory die 204 for storage. Also, controller die 202 can identify a power-off condition and, in response, obtain data stored in volatile memory die 206 through corresponding direct die-to-die connections 212. Using a separate set of direct die-to-die connections 212, controller die 202 can store the obtained data in NV memory die 204 for permanent storage. After recognizing that power is restored, controller die 202 may obtain the data stored in NV memory die 204 and restore it to volatile memory die 206 via corresponding direct inter-die connections 212 .

[0033] The VC memory device described above reduces the footprint and increases density by vertically stacking volatile and NV memory dies. Also, stacking volatile and NV memory dies reduces the connection distance compared to a lateral placement / coplanar arrangement of dies on a common substrate. Thus, propagation delays, power losses, and signal attenuation of corresponding signals can be reduced, thereby increasing processing speed and accuracy.

[0034] Furthermore, the package 102 including the VC memory device may allow the application (via the logic device 122) to store select / critical data in the NV memory. Furthermore, the package 102 may transfer data from the volatile memory to the NV memory after a power removal / failure, and restore the data to the volatile memory immediately after power is restored, thereby improving the data processing efficiency and robustness of the package 102.

[0035] Figure 3 is a schematic cross-sectional view of a vertically stacked combined memory device 300 ("VC memory device 300") according to an embodiment of the present technology. VC memory device 300 may be Figure 1B VC memory device 300 may be similar to Figure 2 VC memory device 200.

[0036] VC memory device 300 may include a controller die 302, an NV memory die 304, and a plurality of volatile memory dies 306 within a single structure (eg, package). NV memory die 304 may be similar to Figure 2 NV memory die 204 and contains NV memory cells configured to store / retain information across power reset / cycles. Each of the volatile memory die 306 may be similar to Figure 2 The controller die 302 may be similar to the volatile memory die 206 of FIG. 1 and may include non-permanent memory cells configured to store / retain charge when input power is provided or applied. Figure 2 The controller die 202 includes a controller die 202 configured to control the operation (e.g., read, write, memory transfer, etc.) of the NV memory die 304 and / or the volatile memory die 306. For example, the controller die 302 may be configured to facilitate / control the transfer of information stored in the volatile memory die 306 to the NV memory die 304 based on a triggering event (e.g., a power-off event). The controller die 302 may further restore previously stored information to the volatile memory die 306 based on a reload event (e.g., a power-on event), such as by loading information stored in the NV memory die 304 to the volatile memory die 306.

[0037] In one or more embodiments, the volatile memory die 306 can be directly attached to each other on and above via an attachment mechanism 310 such as solder, a connector, a bonding wire, and / or an adhesive. Similarly, the volatile memory die 306 (e.g., its bottom die) can be directly attached to the controller die 302 on and above. And, the NV memory die 304 can be directly attached to the volatile memory die 306 on and above. Therefore, the NV memory die 304 can be attached above the controller die 302, wherein there is a volatile memory die 306 between the two structures. Therefore, the controller die 302, the NV memory die 304, and / or the volatile memory die 306 can form a die stack. In other embodiments, the stacking order of the die can be different. For example, the volatile memory die 306 can be attached above the NV memory die 304. Also, the controller die 302 may be attached over the volatile memory die 306 and / or the NV memory die 304 .

[0038] Signals (e.g., commands and / or data) may be passed between vertically attached dies (e.g., controller die 302, volatile memory die 306, and / or NV memory die 304) through through silicon vias 308 ("TSVs 308"). TSVs 308 may be electrically connected (e.g., via traces, pads, solder, metal pillars, etc.) to provide direct inter-die connections 312 between attached dies. For example, similar to Figure 2 The direct die-to-die connection 312 of the direct die-to-die connection 212 may allow the controller die 302 to communicate directly with one or more of the volatile memory dies 306 and / or the NV memory die 304. Similar to the direct die-to-die connection 212, the direct die-to-die connection 312 may allow an external device (e.g., Figure 1B The controller die 302 may be configured to communicate directly with one or more of the volatile memory dies 306 and / or the NV memory die 304. Additionally or alternatively, the controller die 302 may be configured to provide external interfacing functionality for the volatile memory die 306 and / or the NV memory die 304.

[0039] Similar to VC memory device 200, VC memory device 300 may include vertically stacked dies that are aligned and / or have one or more matching dimensions. For example, volatile memory die 306, NV memory die 304, and / or controller die 202 may have one or more common lateral dimensions. Also, volatile memory die 306, NV memory die 304, and / or controller die 302 may be aligned so that their central portions coincide with a common centerline, and / or so that their peripheral edges coincide with a vertical plane. In one or more embodiments, one die (e.g., a bottom die, such as controller die 302) may have one or more dimensions that are larger than the dimensions of the other stacked dies, such that a peripheral portion of the one die protrudes laterally beyond a corresponding peripheral edge of the stacked die.

[0040] The plurality of volatile memory dies 306 provide increased storage capacity for the VC memory device 300. With an increased number of volatile memory dies 306, the VC memory device 300 can provide increased non-persistent storage capacity (e.g., DRAM capacity) without increasing the overall footprint. Furthermore, the vertically stacked NV memory dies 304 and controller die 302 can support combined operation of the VC memory device 300 similar to the VC memory device 200 described above.

[0041] Figure 4 4 is a schematic cross-sectional view of a vertically stacked combined memory device 400 ("VC memory device 400") according to an embodiment of the present technology. VC memory device 400 may be Figure 1B VC memory device 400 may be similar to Figure 2 The VC memory device 200 and / or Figure 3 VC memory device 300.

[0042] VC memory device 400 may include a controller die 402, a plurality of NV memory dies 404, and a plurality of volatile memory dies 406 within a single structure (eg, package). Each of NV memory dies 404 may be similar to Figure 2 NV memory die 204 and contains NV memory cells configured to store / retain information across power reset / cycles. Each of the volatile memory die 406 may be similar to Figure 2 The controller die 402 may be similar to the volatile memory die 206 of FIG. 4 and may include non-permanent memory cells configured to store / retain charge when input power is provided or applied. Figure 2The controller die 202 includes a controller die 202 configured to control the operation (e.g., read, write, memory transfer, etc.) of the NV memory die 404 and / or the volatile memory die 406. For example, the controller die 402 may be configured to facilitate / control the transfer of information stored in the volatile memory die 406 to the NV memory die 404 based on a triggering event (e.g., a power-off event). The controller die 402 may further restore previously stored information to the volatile memory die 406 based on a reload event (e.g., a power-on event), such as by loading information stored in the NV memory die 404 to the volatile memory die 406.

[0043] In one or more embodiments, the volatile memory die 406 can be directly attached to each other on and above via an attachment mechanism 410 such as solder, a connector, a bonding wire and / or an adhesive. Similarly, the NV memory die 404 can be directly attached to each other on and above. And, the volatile memory die 406 (e.g., its bottom die) can be directly attached to the controller die 402 on and above. And, the NV memory die 404 can be directly attached to the volatile memory die 406 on and above. Therefore, the NV memory die 404 can be attached above the controller die 402, wherein there is a volatile memory die 406 between the two structures. Therefore, the controller die 402, the NV memory die 404 and / or the volatile memory die 406 can form a die stack. In other embodiments, the stacking order of the die can be different. For example, the volatile memory die 406 can be attached above the NV memory die 404. Also, the controller die 402 may be attached over the volatile memory die 406 and / or the NV memory die 404 .

[0044] Signals (e.g., commands and / or data) may be transmitted between vertically attached dies (e.g., controller die 402, volatile memory die 406, and / or NV memory die 404) through through silicon vias 408 ("TSVs 408"). TSVs 408 may be electrically connected (e.g., via traces, pads, solder, metal pillars, etc.) to provide direct inter-die connections 412 between attached dies. For example, similar to Figure 2 The direct die-to-die connections 412 of the direct die-to-die connections 212 may allow the controller die 402 to communicate directly with one or more of the volatile memory dies 406 and / or one or more of the NV memory dies 404. Similar to the direct die-to-die connections 212, the direct die-to-die connections 412 may allow external devices (e.g., Figure 1BThe controller die 402 may be configured to communicate directly with one or more of the volatile memory dies 406 and / or one or more of the NV memory dies 404. Additionally or alternatively, the controller die 402 may be configured to provide external interfacing functionality for the volatile memory dies 406 and / or the NV memory dies 404.

[0045] Similar to VC memory device 200, VC memory device 400 may include vertically stacked dies that are aligned and / or have one or more matching dimensions. For example, volatile memory die 406, NV memory die 404, and / or controller die 402 may have one or more common lateral dimensions. Also, volatile memory die 406, NV memory die 404, and / or controller die 202 may be aligned so that their central portions coincide with a vertical line, and / or so that their peripheral edges coincide with a vertical plane. In one or more embodiments, one die (e.g., a bottom die, such as controller die 402) may have one or more dimensions that are larger than the dimensions of the other stacked dies, such that a peripheral portion of the one die protrudes laterally beyond a corresponding peripheral edge of the stacked die.

[0046] The plurality of volatile memory dies 406 and the plurality of NV memory dies 404 provide increased storage capacity for the VC memory device 400. With an increased number of both types of dies, the VC memory device 400 can provide increased permanent and non-permanent storage capacity without increasing the overall footprint. Furthermore, the vertically stacked NV memory dies 404 and controller die 402 can support combined operation of the VC memory device 400 similar to the VC memory device 200 described above.

[0047] Figure 5 is a diagram showing how to manufacture a semiconductor device (e.g., Figure 2 VC memory device 200, Figure 3 VC memory device 300, Figure 4 VC memory device 400, Figure 1A Package 102 and / or Figure 1A The method 500 may be used to fabricate a semiconductor device including a VC memory device including a die stack including at least one NV memory die and at least one volatile memory die.

[0048] At block 502, the method includes providing a VC memory device (e.g., VC memory device 200, VC memory device 300, and / or VC memory device 400). For example, a die stack including at least one volatile memory die (e.g., a DRAM die) and at least one NV memory die (e.g., a NAND die) physically and operatively coupled together in a vertical stack configuration may be provided.

[0049] In some embodiments, providing a VC memory device may include assembling or forming a VC memory device. At block 512, a die may be provided for assembly. For example, a die may be provided. Figure 2 The controller die 202, Figure 3 The controller die 302, Figure 4 The controller die 402, Figure 2 The volatile memory die 206, Figure 3 The volatile memory die 306, Figure 4 The volatile memory die 406, Figure 2 NV memory die 204, Figure 3 The NV memory die 304 and / or Figure 4 The provided die may include active circuitry (e.g., semiconductor devices on the active side) and / or connections between active circuitry. The provided die may also have inter-die connectors such as guide posts, pads, solder bumps, and / or TSVs (e.g., Figure 2 TSV 208, Figure 3 TSV 308 and / or Figure 4 TSV 408).

[0050] In one or more embodiments, providing the die may include forming or manufacturing the die. At block 514, the die may be formed. For example, the die may be formed via processes such as masking, doping, etching, deposition, thinning, bonding, etc. that form active circuitry and connections (e.g., traces) for each die. Also, forming the die may include processes of removing portions of the silicon substrate, depositing metal and / or dielectric material into the resulting recesses (e.g., vias), and / or connecting metal features in the recesses to other connections to form TSVs within the die.

[0051] At block 516, the provided dies may be vertically stacked to assemble or form a VC memory device. For example, a bottom die (e.g., a controller die) may be provided. A first group of dies (e.g., including at least one volatile memory die) may be attached above the bottom die. A second group of dies (e.g., including at least one NV memory die) may be attached above the bottom die and / or the first group of dies. Figure 2-4In the example shown in , the volatile memory die can be attached directly onto and above the controller die. Also, the NV memory die can be attached directly onto and above the volatile memory die, which can be the same as the die directly attached to the controller die or a different volatile memory die.

[0052] The die can be attached using electrical and / or mechanical mechanisms. For example, the die can be attached by reflowing and hardening solder, fusing metal structures (e.g., guide posts), connecting bonding wires, and / or connecting other electromechanical structures. Also, the die can be attached via an adhesive and / or encapsulant disposed between the attached die. When attaching the die, the die can be positioned so that the TSV is electrically coupled to one or more vertically adjacent die. For example, a TSV in one die can contact a vertical connector (e.g., pad, guide post, solder, etc.) on a die above and / or below the die or electrically connected to this die.

[0053] Vertically stacking the die may include aligning the center portions and / or peripheral portions of the die before attaching the die. For example, the controller die, the volatile memory die, and / or the NV memory die may be positioned so that their center portions are aligned with a common center line. In other words, the die may be placed at different heights with the center portions in the same lateral position so as to overlap each other. Also, the controller die, the volatile memory die, and / or the NV memory die may be positioned so that one or more peripheral edges thereof are aligned with corresponding vertically oriented planes. Thus, the die may be stacked to form a rectangular box or a cube shape.

[0054] At block 504, the method may include providing a package (eg, Figure 1A The provided package may include a VC memory device (e.g., VC memory device 200, VC memory device 300, and / or VC memory device 400). In some embodiments, providing the package may include assembling or forming the package. At block 522, the provided VC memory device may be attached to a package substrate (e.g., Figure 1B The VC memory device may be attached to a package substrate 112 such as a silicon interposer. The VC memory device may be attached in a manner similar to that described above for the die. For example, the bottom die (e.g., the controller die) in the VC memory device may be attached to the package substrate by solder, fused metal, adhesive, wire, etc.

[0055] At block 524, other devices may be attached to the package substrate. For example, Figure 1B The logic device 122 and / or Figure 1BThe memory device 124 is attached to the package substrate. Other devices may be attached to the common surface as the VC memory device such that the other devices and the VC memory device are laterally adjacent to each other.

[0056] In some embodiments, the VC memory device, other devices, and / or packaging substrate may be encapsulated to form a package. In some embodiments, the VC memory device may be encapsulated separately (eg, as part of forming a VC memory device).

[0057] At block 506, the method may include forming a semiconductor assembly (eg, assembly 100 of FIG. 1 ). For example, an assembly substrate (eg, Figure 1A At block 532, the provided package may be attached to the assembly substrate. At block 534, other components / devices may be attached to the assembly substrate to form a semiconductor assembly.

[0058] References Figure 1A-5 Any of the described semiconductor devices may be incorporated into any of a number of larger and / or more complex systems, a representative example of which is in Figure 6 690 is schematically shown in FIG. 690. System 690 may include a semiconductor device 600 ("device 600") (e.g., a semiconductor device, package, and / or assembly), a power supply 692, a driver 694, a processor 696, and / or other subsystems or components 698. Device 600 may include features generally similar to those described above. The resulting system 690 may perform any of a variety of functions, such as memory storage, data processing, and / or other suitable functions. Thus, representative systems 690 may include, but are not limited to, handheld devices (e.g., mobile phones, tablet computers, digital readers, and digital audio players), computers, and appliances. The components of system 690 may be housed in a single unit or distributed among multiple interconnected units (e.g., via a communication network). Components of system 690 may also include any of a remote device and a variety of computer-readable media.

[0059] The present disclosure is not intended to be exhaustive or to limit the present invention to the precise form disclosed herein. Those skilled in the relevant art will recognize that, although specific embodiments are disclosed herein for illustrative purposes, various equivalent modifications are possible without departing from the present invention. In some cases, well-known structures and functions are not shown or described in detail to avoid unnecessarily obscuring the description of the embodiments of the present invention. Although the steps of the method are presented in a particular order herein, alternative embodiments may perform the steps in a different order. Similarly, certain aspects of the present invention disclosed in the context of a particular embodiment may be combined or removed in other embodiments. In addition, although advantages associated with certain embodiments of the present invention may have been disclosed in the context of those embodiments, other embodiments may also exhibit such advantages, and not all embodiments must exhibit such advantages or other advantages disclosed herein to fall within the scope of the present invention. Therefore, the present disclosure and associated technology may cover other embodiments not explicitly shown or described herein, and the present invention is limited only by the appended claims.

[0060] Throughout this disclosure, unless the context clearly states otherwise, the singular terms "a / an" and "the" include multiple references. Similarly, unless the word "or" is explicitly limited to mean only a single item exclusive of other items in a list of reference two or more items, the use of "or" in this list can be understood to include: (a) any single item in the list, (b) all items in the list, or (c) any combination of items in the list. In addition, the terms "include", "comprise" and "have" are used throughout the text to mean at least one or more of the described features, so that any greater number of the same features and / or additional types of other features are not excluded. References to "one embodiment", "embodiment", "some embodiments" or similar forms herein mean that the specific features, structures, operations or characteristics described in conjunction with the embodiments may be included in at least one embodiment of the present invention. Therefore, the appearance of such phrases or expressions in this article may not necessarily refer to the same embodiment. In addition, in one or more embodiments, each specific feature, structure, operation or characteristic can be combined in any suitable manner.

Claims

1. A semiconductor package, comprising: A die stack, which includes a group of dies stacked vertically on top of each other, the group of dies including: at least one volatile memory die configured to store volatile data when power is available, at least one non-volatile NV memory die configured to retain NV data when power is unavailable; as well as A controller device is attached directly to the die stack, the controller device being configured to provide an interface to the die stack and control operation of the die stack.

2. The semiconductor package according to claim 1, wherein: The at least one volatile memory die includes a through silicon via (TSV) electrically coupled to the controller device; and The at least one NV memory die is attached to and over the volatile memory die, the at least one NV memory die being electrically coupled to the TSVs.

3. The semiconductor package according to claim 2, wherein: The controller device comprises a controller die; and The at least one volatile memory die is attached directly onto and over the controller die. 4 . The semiconductor package of claim 3 , wherein the TSVs comprise direct die-to-die connections between at least the controller die and the at least one NV die.

5. The semiconductor package according to claim 3, wherein: Center portions of the die stack and the controller die are aligned, the center portions coinciding with a vertical line; and The controller die protrudes beyond a peripheral edge of the die stack in a lateral direction.

6. The semiconductor package according to claim 3, wherein: The die stack has a common length between its peripheral edge and an opposing edge; The controller die has the common length between a peripheral edge and an opposing edge thereof; and Peripheral edges of the die stack and the controller die are aligned, the peripheral edges coinciding with a vertical plane.

7. The semiconductor package according to claim 1, wherein: The at least one volatile memory die and the at least one NV memory die each have a common length between a perimeter edge and an opposing edge; and Perimeter edges of the at least one volatile memory die and the at least one NV memory die are aligned, the peripheral edges coinciding with a vertical plane.

8. The semiconductor package of claim 1 , wherein the controller device is configured to transfer data initially stored in either the at least one volatile memory die or the at least one NV memory die and store the data in the other of the at least one volatile memory die or the at least one NV memory die.

9. The semiconductor package of claim 1, wherein the at least one volatile memory die comprises a high bandwidth memory (HBM) device comprising two or more dynamic random access memory (DRAM) dies.

10. The semiconductor package of claim 1, wherein the at least one NV memory die comprises at least one NAND memory die.

11. A semiconductor package, comprising: Package substrate; a logic device attached to the packaging substrate; as well as A vertically stacked combined VC memory device attached to the package substrate, wherein the VC memory device is a stack of dies comprising: at least one dynamic random access memory DRAM die, at least one non-volatile NV memory die, and a controller die electrically coupled to the package substrate, the at least one DRAM die, and the at least one NV memory die, the controller die configured to provide an external interface for the die stack and control operation of the die stack, Wherein the die stack includes the at least one DRAM die, the at least one NV memory die, and the controller die attached to each other and stacked vertically on top of each other.

12. The semiconductor package according to claim 11, wherein: The at least one DRAM die includes a high bandwidth memory (HBM) device comprising a plurality of DRAM dies attached to and over the controller die; and The at least one NV memory die includes at least one NAND memory die attached onto and over the HBM device.

13. The semiconductor package of claim 11, wherein the logic device is an application processor. 14 . The semiconductor package of claim 11 , wherein the semiconductor package comprises a chip-on-wafer (CoW) packaging device.

15. A semiconductor assembly comprising: A vertically stacked combined VC memory device electrically coupled to an assembly substrate, wherein the VC memory device is a stack of dies comprising: at least one dynamic random access memory DRAM die, at least one non-volatile NV memory die, and a controller die electrically coupled to the assembly substrate, the at least one DRAM die, and the at least one NV memory die, the controller die configured to provide an external interface for the die stack and to control operation of the die stack, Wherein the die stack includes the at least one DRAM die, the at least one NV memory die, and the controller die attached to each other and stacked vertically on top of each other.

16. The semiconductor assembly of claim 15, wherein the VC memory device comprises a semiconductor package directly attached to the assembly substrate, the semiconductor package comprising: a packaging substrate attached to the VC memory device; and A logic device is attached to the package substrate and electrically coupled to the VC memory device.

17. The semiconductor assembly of claim 16, wherein the semiconductor package comprises a chip-on-wafer (CoW) device.

18. The semiconductor assembly of claim 16, further comprising an assembly substrate attached to the semiconductor package.

19. The semiconductor assembly of claim 18, wherein: The packaging substrate is a silicon interposer; and The assembly substrate is a printed circuit board PCB.

20. The semiconductor assembly of claim 18, wherein the semiconductor assembly comprises a Wafer-on-Substrate (Chip-on-WoS) device.

21. A method for manufacturing a semiconductor package, the method comprising: Provide controller die; attaching a first memory die over the controller die, wherein the first memory die includes either volatile memory cells or non-volatile NV memory cells, and a through silicon via (TSV) electrically coupled to the controller die and extending away from the controller die; as well as A second memory die is attached over the first memory die and electrically coupled to the TSVs of the first memory die, wherein the second memory die includes the other of the volatile memory cells or the NV memory cells.

22. The method of claim 21, further comprising: attaching the controller die to a packaging substrate; as well as A logic device is attached to the packaging substrate, wherein the logic device is electrically coupled to the first memory die and the second memory die through the controller die.

23. The method of claim 22, further comprising attaching the packaging substrate to an assembly substrate.

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