DEVM compensation circuit for power amplifier, power amplifier

Abstract

The present invention provides a DEVM compensation circuit for a power amplifier and a power amplifier, wherein the DEVM compensation circuit includes a voltage control module and a radio frequency switch module, the input end of the voltage control module is connected to a control signal, and is used to generate a first voltage and a second voltage according to the control signal; the first output end of the voltage control module is electrically connected to the first control end of the radio frequency switch module, and the second output end of the voltage control module is electrically connected to the second control end of the radio frequency switch module, so as to feed back the first voltage and the second voltage to the radio frequency switch module, the input end of the radio frequency switch module is connected to the original input signal, and the output end of the radio frequency switch module is connected to the input end of the power amplifier, so that when the first voltage is greater than the second voltage, different gain compensation is performed on the original input signal within a target time period to obtain a compensated input signal, and the compensated input signal is transmitted to the power amplifier to solve the problem of large gain change after the power amplifier is turned on.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a DEVM compensation circuit for a power amplifier and a power amplifier. Background Art

[0002] The RF power amplifier (RF PA) is a key component of the transmission system and is primarily used in the pre-amplifier circuit of the transmitter. It amplifies the RF signal generated by the modulation circuit to obtain sufficient RF power, which is then fed to the antenna for radiation.

[0003] To reduce energy consumption, the RF power amplifier (RFPA) is enabled only when a signal is being transmitted, controlled by an enable signal, and is disabled when no signal is being transmitted. When the RF PA is initially turned on, the internal amplification circuitry has not yet reached a stable state. In particular, the temperature of the power transistors continues to rise, causing the RF PA's gain to vary over time for a long period after being turned on. When applied to communication systems using OFDM (Orthogonal Frequency Division Multiplexing) modulation (such as 802.11a / g / n / ac / ax), this can lead to a deterioration in the dynamic error vector magnitude (DEVM).

[0004] In the prior art, the problem of large gain variation after the RF power amplifier is turned on is generally improved by changing the bias current generated by the bias circuit in the RF power amplifier. However, this method has a complex circuit and low accuracy. Summary of the Invention

[0005] The present invention provides a DEVM compensation circuit for a power amplifier and a power amplifier, so as to solve the problem of large gain variation after the power amplifier is turned on.

[0006] A first aspect of the present invention provides a DEVM compensation circuit for a power amplifier, comprising: a voltage control module, a radio frequency switch module,

[0007] The input terminal of the voltage control module is connected to a control signal, and is used to: generate a first voltage and a second voltage according to the control signal, wherein the first voltage is generated based on the control signal, the second voltage is generated based on an inverted signal of the control signal, and the first voltage when the control signal is at a target level is lower than the second voltage when the control signal is at a non-target level;

[0008] The first output end of the voltage control module is electrically connected to the first control end of the RF switch module, and the second output end of the voltage control module is electrically connected to the second control end of the RF switch module, so as to feed back the first voltage and the second voltage to the RF switch module.

[0009] The input end of the RF switch module is connected to the original input signal, and the output end of the RF switch module is connected to the input end of the power amplifier, so that when the first voltage is greater than the second voltage, different gain compensation is performed on the original input signal within a target time period to obtain a compensated input signal, and the compensated input signal is transmitted to the power amplifier.

[0010] Optionally, the radio frequency switch module includes a first transistor, a second transistor, a first switch capacitor, a second switch capacitor, and a third switch capacitor.

[0011] The control electrode of the first transistor is electrically connected to the first output terminal of the voltage control module to receive the first voltage.

[0012] A first electrode of the first transistor is electrically connected to a first end of the first switch capacitor, and a second end of the first transistor is electrically connected to a first end of the second switch capacitor;

[0013] The second end of the first switch capacitor is connected to the original input signal, and the second end of the second switch capacitor is electrically connected to the input end of the power amplifier;

[0014] The control electrode of the second transistor is electrically connected to the second output terminal of the voltage control module to receive the second voltage;

[0015] A first electrode of the second transistor is electrically connected to a first end of the second switch capacitor, and a second electrode of the second transistor is electrically connected to a first end of the third switch capacitor;

[0016] A second terminal of the third switched capacitor is grounded.

[0017] Optionally, the RF switch module further includes a first switch resistor and a second switch resistor.

[0018] Two ends of the first switch resistor are electrically connected to the first electrode and the second electrode of the first transistor respectively;

[0019] Two ends of the second switch resistor are electrically connected to the first electrode and the second electrode of the second transistor respectively.

[0020] Optionally, the RF switch module further includes a third switch resistor and a fourth switch resistor;

[0021] A first end of the third switch resistor is electrically connected to the first output end of the voltage control module, and a second end of the third switch resistor is electrically connected to the control electrode of the first transistor;

[0022] A first end of the fourth switch resistor is electrically connected to the second output end of the voltage control module, and a second end of the fourth switch resistor is electrically connected to the control electrode of the second transistor.

[0023] Optionally, the voltage control module includes an inverter, a buffer, a first control resistor and a second control resistor;

[0024] The input end of the inverter is connected to the control signal, and the output end of the inverter is electrically connected to the control electrode of the second transistor, so as to generate the second voltage when the control signal is at a target level, and feed the second voltage back to the second transistor;

[0025] The input end of the buffer is connected to the control signal, the output end of the buffer is electrically connected to the first end of the first control resistor, the second end of the first control resistor is electrically connected to the first end of the second control resistor, and the second end of the second control resistor is grounded;

[0026] The second end of the first control resistor is electrically connected to the control electrode of the first transistor, so as to generate the first voltage when the control signal is at a target level, and feed the first voltage back to the first transistor.

[0027] Optionally, the first control resistor is a thermistor, and the resistance value of the first control resistor is adapted to the temperature of the power amplifier.

[0028] Optionally, the RF switch module further includes a first DC unit and a second DC unit.

[0029] The first end of the first DC unit is electrically connected to the second end of the first switching capacitor, and the second end of the first DC unit is grounded;

[0030] A first end of the second DC unit is electrically connected to a second end of the second switched capacitor, and a second end of the second DC unit is grounded.

[0031] Optionally, the first DC unit includes a first DC inductor, and the second DC unit includes a second DC inductor.

[0032] The first end of the first DC inductor is electrically connected to the second end of the first switched capacitor, and the second end of the first DC inductor is grounded;

[0033] A first end of the second DC inductor is electrically connected to a second end of the second switched capacitor, and a second end of the second DC inductor is grounded.

[0034] Optionally, the first DC unit includes a first DC resistor, and the second DC unit includes a second DC resistor.

[0035] The first end of the first DC resistor is electrically connected to the second end of the first switched capacitor, and the second end of the first DC resistor is grounded;

[0036] A first end of the second DC resistor is electrically connected to a second end of the second switched capacitor, and a second end of the second DC resistor is grounded.

[0037] Optionally, the first transistor and the second transistor are depletion-mode HEMTs.

[0038] According to a second aspect of the present invention, there is provided a power amplifier comprising an amplifying circuit, a bias circuit, and the DEVM compensation circuit for the power amplifier according to the first aspect of the present invention and its optional solutions;

[0039] The output end of the radio frequency switch module is electrically connected to the amplifier circuit to transmit the compensation input signal to the amplifier circuit;

[0040] The bias circuit is electrically connected to the amplifier circuit to generate a bias voltage and feed the bias voltage back to the amplifier circuit;

[0041] The amplifying circuit is directly or indirectly electrically connected to the antenna to amplify the compensated input signal based on the bias voltage and then transmit the amplified signal through the antenna.

[0042] Optionally, the amplifying circuit includes an output transistor,

[0043] The output end of the RF switch module and the bias circuit are electrically connected to the control electrode of the output transistor, the first electrode of the output transistor is electrically connected to a first power supply, and the second electrode of the output transistor is grounded; the first electrode of the output transistor is directly or indirectly electrically connected to the antenna;

[0044] The bias circuit is electrically connected to the first power supply.

[0045] Optionally, the bias circuit includes a first bias transistor, a second bias transistor and a reference current source,

[0046] A first terminal of the reference current source is electrically connected to a second power supply, and a second terminal of the reference current source is electrically connected to a control electrode of the first bias transistor and a first electrode of the second bias transistor;

[0047] A first electrode of the first bias transistor is electrically connected to the first power supply, and a second electrode of the first bias transistor is electrically connected to the control electrode of the output transistor;

[0048] A control electrode of the second bias transistor is electrically connected to a control electrode of the output transistor, and a second electrode of the second bias transistor is grounded.

[0049] Optionally, the power amplifier further includes an isolation capacitor, a first end of which is electrically connected between the output end of the RF switch module and the control electrode of the output transistor.

[0050] Optionally, the power amplifier further includes an output matching circuit, a first end of the output matching circuit is electrically connected to the first electrode of the output transistor, and a second end of the output matching circuit is electrically connected to the antenna.

[0051] According to a third aspect of the present invention, an electronic device is provided, comprising the DEVM compensation circuit for a power amplifier according to the first aspect of the present invention and its optional solutions, or the power amplifier according to the second aspect of the present invention and its optional solutions.

[0052] The present invention provides a DEVM compensation circuit and a power amplifier for a power amplifier, wherein a voltage control module in the DEVM compensation circuit generates a first voltage and a second voltage according to a control signal, and further controls the radio frequency switch module to generate different gain compensations for the original input signal according to the difference between the first voltage when the control signal PA_EN is a target level and the second voltage when the control signal is a non-target level. When the control signal converts the target level, the insertion loss of the DEVM compensation circuit gradually decreases with the passage of time, that is, the gain of the DEVM compensation circuit gradually increases, which complements the trend of the gain of the power amplifier without a DEVM compensation circuit gradually decreasing over time, thereby ensuring the stability of the gain of the power amplifier.

[0053] In an optional solution of the present invention, the first DC unit and the second DC unit are provided to shield the influence of external equipment at the access end of the original input signal on the DEVM compensation circuit and / or the power amplifier.

[0054] In an optional solution of the present invention, the resistance value of the first control resistor is adapted to the temperature of the output transistor of the power amplifier, so that the voltage control module can generate different first voltages and second voltages according to the different shutdown times of the power amplifier, and then the RF switch module performs different gain compensation on the original input signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0056] Figure 1 is a schematic structural diagram of a DEVM compensation circuit in one embodiment of the present invention;

[0057] Figure 2 Schematic diagram of a DEVM compensation circuit in one embodiment of the present invention Figure 1 ;

[0058] Figure 3 Schematic diagram of a DEVM compensation circuit in one embodiment of the present invention Figure 2 ;

[0059] Figure 4 1 is a schematic diagram of an equivalent circuit of a radio frequency switch module in one embodiment of the present invention;

[0060] Figure 5 Schematic diagram of a DEVM compensation circuit in one embodiment of the present invention Figure 3 ;

[0061] Figure 6 Schematic diagram of a DEVM compensation circuit in one embodiment of the present invention Figure 4 ;

[0062] Figure 7 This is a schematic diagram of the structure of a power amplifier in one embodiment of the present invention. Figure 1 ;

[0063] Figure 8 This is a schematic diagram of the structure of a power amplifier in one embodiment of the present invention. Figure 2 ;

[0064] Figure 9 is a schematic structural diagram of the first circuit board 21 in one embodiment of the present invention;

[0065] Figure 10 is a circuit diagram of a power amplifier according to an embodiment of the present invention;

[0066] Figure 11 1 is a waveform diagram of the gain of a power amplifier in an embodiment of the prior art;

[0067] Figure 12 is a waveform diagram of the gain of a power amplifier in one embodiment of the present invention;

[0068] Figure 13 is a waveform diagram of the gain of the DEVM compensation circuit in one embodiment of the present invention;

[0069] Figure 14 1 is a schematic diagram of the EVM waveform of a power amplifier in an embodiment of the prior art;

[0070] Figure 15FIG. 1 is a schematic diagram of an EVM waveform of a power amplifier according to an embodiment of the present invention.

[0071] Description of reference numerals:

[0072] 11-voltage control module; 12-RF switch module; 121-first DC unit; 122-second DC unit;

[0073] L121-first DC inductor; L122-second DC inductor; R125-first DC resistor; R126-second DC resistor;

[0074] H1 - first transistor; H2 - second transistor; C11 - first switch capacitor; C12 - second switch capacitor; C13 - third switch capacitor; R121 - first switch resistor; R122 - second switch resistor; R123 - third switch resistor; R124 - fourth switch resistor;

[0075] R111 - first control resistor; R112 - second control resistor; U1 - buffer; U2 - inverter; Vc1 - first voltage; Vc2 - second voltage;

[0076] 21-amplifier circuit; 22-bias circuit; 23-output matching circuit; Q1-output transistor; Q2-first bias transistor; Q3-second bias transistor; IREF-bias current source; L21-inductor; C23-matching capacitor; L23-matching inductor; C21-isolation capacitor;

[0077] Rfin-raw input signal; PA_EN-control signal; ANT-antenna;

[0078] VCC1 - first power supply; VCC2 - second power supply. DETAILED DESCRIPTION

[0079] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0080] The terms "first," "second," "third," "fourth," and the like (if any) in the description and claims of the present invention and in the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. In addition, the terms "including" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions, e.g., a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to these processes, methods, products, or apparatus.

[0081] The following specific embodiments are used to describe the technical solution of the present invention in detail. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0082] Please refer to Figure 1 In one embodiment of the present invention, a DEVM compensation circuit for a power amplifier includes: a voltage control module 11, a radio frequency switch module 12,

[0083] The input terminal of the voltage control module 11 is connected to the control signal PA_EN, and is used to: generate a first voltage Vc1 and a second voltage Vc2 according to the control signal PA_EN, wherein the first voltage is generated based on the control signal PA_EN, and the second voltage is generated based on the inverted signal of the control signal PA_EN, and the first voltage when the control signal PA_EN is at a target level is lower than the second voltage when the control signal PA_EN is at a non-target level;

[0084] The control signal PA_EN can be understood as an enable signal for controlling the power amplifier circuit to be turned on and off. For example, when the control signal PA_EN is at a high level, the power amplifier circuit is turned on, and when the control signal PA_EN is at a low level, the power amplifier circuit is turned off.

[0085] The target level can be high or low. When the target level is high, the corresponding non-target level is low. When the target level is low, the corresponding non-target level is high.

[0086] The first output end of the voltage control module 11 is electrically connected to the first control end of the RF switch module 12, and the second output end of the voltage control module 11 is electrically connected to the second control end of the RF switch module 12, so as to feed back the first voltage Vc1 and the second voltage Vc2 to the RF switch module 12.

[0087] The input of the RF switch module 12 is connected to the original input signal Rfin, and the output of the RF switch module 12 is connected to the input of the power amplifier. When the first voltage Vc1 is greater than the second voltage Vc2, the original input signal Rfin is compensated for different gains within a target period to obtain a compensated input signal, and the compensated input signal is transmitted to the power amplifier. The target period matches the time period from when the power amplifier is turned on and the gain changes until the region stabilizes when the DEVM compensation circuit is not configured.

[0088] Please refer to Figure 2 In one embodiment, the RF switch module 12 includes a first transistor H1, a second transistor H2, a first switch capacitor C11, a second switch capacitor C12, and a third switch capacitor C13.

[0089] The control electrode of the first transistor H1 is electrically connected to the first output terminal of the voltage control module 11 to receive the first voltage Vc1.

[0090] A first electrode of the first transistor H1 is electrically connected to a first end of the first switch capacitor C11, and a second end of the first transistor H1 is electrically connected to a first end of the second switch capacitor C12;

[0091] The second end of the first switch capacitor C11 is connected to the original input signal Rfin, and the second end of the second switch capacitor C12 is electrically connected to the input end of the power amplifier;

[0092] The control electrode of the second transistor H2 is electrically connected to the second output terminal of the voltage control module 11 to receive the second voltage Vc2;

[0093] A first electrode of the second transistor H2 is electrically connected to a first end of the second switch capacitor C12, and a second electrode of the second transistor H2 is electrically connected to a first end of the third switch capacitor C13;

[0094] A second terminal of the third switched capacitor is grounded.

[0095] The voltage control module in the DEVM compensation circuit in the above embodiment generates a first voltage and a second voltage when the control signal is at the target level, and controls the RF switch module to generate different gain compensations for the original input signal. As the control signal converts the target level, the insertion loss of the DEVM compensation circuit gradually decreases with the passage of time, that is, the gain of the DEVM compensation circuit gradually increases, which complements the trend of the power amplifier gain gradually decreasing over time without the DEVM compensation circuit, thereby ensuring the stability of the power amplifier gain.

[0096] In one embodiment, the first transistor H1 and the second transistor H2 are depletion-mode HEMTs (High Electron Mobility Transistor).

[0097] In one example, the longer the power amplifier is turned off, the lower the first voltage Vc1 will be when it is turned back on.

[0098] The first switch capacitor C11 and the second switch capacitor C12 are connected to the ground via a DC unit;

[0099] The working principle of the RF switch module 12 is as follows:

[0100] When the power amplifier is in the off state, the second voltage Vc2 is at a high level, and the first voltage Vc1 is at a low level. The voltage at node N0 is Vc2-Vth, where Vth is the threshold voltage of the second transistor H2. At this time, the voltages across the first, second, and third switched capacitors C11, C12, and C13 are also Vc2-Vth.

[0101] When the power amplifier is about to turn on, the first voltage Vc1 is at a high level and the second voltage Vc2 is at a low level. When the power amplifier is in a steady state, the voltage at node N0 is Vc1-Vth. Since the first voltage Vc1 at this time is lower than the second voltage Vc2 when the power amplifier is in the off state, after the first voltage Vc1 is pulled to a high level, the voltage at node N0 will change from high to low.

[0102] Part of the equivalent schematic diagram can be, for example, Figure 4 As shown, the first transistor and the second transistor can be regarded as diodes, and the voltage change time constant of the node N0 is determined by the capacitance value of the first switch capacitor C11, the second switch capacitor C12, and the third switch capacitor C13 in parallel and the reverse conduction resistance of the second transistor H2.

[0103] The voltage difference between the first voltage Vc1 and the node N0 directly determines the insertion loss of the RF switch module 12. When the first voltage Vc1 is just pulled to a high level, the voltage difference is the smallest, so the insertion loss is the largest at this time. Over time, the current I2 flows from the first switch capacitor C11, the second switch capacitor C12, and the third switch capacitor C13 to the second transistor H2, and the current I1 flows from the first transistor H1 to the second transistor H2 until the second switch transistor is reversely conducted. In this process, the voltage of the node N0 drops, the voltage difference increases, and the insertion loss is also reduced. Therefore, the RF switch module 12 compensates for the gain change of the power amplifier by changing the insertion loss.

[0104] In one embodiment, the RF switch module 12 further includes a first switch resistor R121 and a second switch resistor R122.

[0105] Two ends of the first switch resistor R121 are electrically connected to the first electrode and the second electrode of the first transistor H1 respectively;

[0106] Two ends of the second switch resistor R122 are electrically connected to the first electrode and the second electrode of the second transistor H2 respectively.

[0107] In one embodiment, the RF switch module 12 further includes a third switch resistor R123 and a fourth switch resistor R124;

[0108] A first end of the third switch resistor R123 is electrically connected to the first output end of the voltage control module 11, and a second end of the third switch resistor R123 is electrically connected to the control electrode of the first transistor H1;

[0109] A first end of the fourth switch resistor R124 is electrically connected to the second output end of the voltage control module 11 , and a second end of the fourth switch resistor R124 is electrically connected to the control electrode of the second transistor H2 .

[0110] In one embodiment, the voltage control module 11 includes an inverter U2, a buffer U1, a first control resistor R111 and a second control resistor R112;

[0111] The input end of the inverter U2 is connected to the control signal PA_EN, and the output end of the inverter U2 is electrically connected to the control electrode of the second transistor H2, so as to generate the second voltage Vc2 when the control signal PA_EN is at a target level, and feed the second voltage Vc2 back to the second transistor H2;

[0112] The input end of the buffer U1 is connected to the control signal PA_EN, the output end of the buffer U1 is electrically connected to the first end of the first control resistor R111, the second end of the first control resistor R111 is electrically connected to the first end of the second control resistor R112, and the second end of the second control resistor R112 is grounded;

[0113] A second end of the first control resistor R111 is electrically connected to the control electrode of the first transistor H1 , so as to generate the first voltage Vc1 when the control signal PA_EN is at a target level, and feed the first voltage Vc1 back to the first transistor H1 .

[0114] In one embodiment, the first control resistor R111 is a thermistor, and the resistance value of the first control resistor R111 is adapted to the temperature of the power amplifier. In a further optional solution, the resistance value of the first control resistor is adapted to the temperature of an output transistor in the power amplifier.

[0115] In the above embodiment, the resistance value of the first control resistor R111 is adapted to the temperature of the output transistor. This can be understood as thermally coupling the first control resistor R111 to the output transistor Q1 so that the resistance value of the first control resistor R111 changes with the temperature of the output transistor Q1.

[0116] The specific working mode of the voltage control module 11 is as follows:

[0117] The control signal PA_EN controls the inverter U2 and the buffer U1, and the high-level voltages at the output ends of the inverter U2 and the buffer U1 are the same;

[0118] The output of inverter U2 is directly used as the second voltage Vc2. The output voltage of buffer U1 is divided by first control resistor R111 and second control resistor R112 to form the first voltage Vc1. The resistance value of first control resistor R111 is small at high temperatures and large at low temperatures. The first control resistor R111 and output transistor Q1 are tightly thermally coupled. When the off-time is short, the temperature near output transistor Q1 is still relatively high, the first control resistor R111 and the first voltage Vc1 are high, and the resulting compensation gain variation is smaller. When the off-time is long, the temperature near output transistor Q1 has dropped, the resistance value of first control resistor R111 is high, the first voltage Vc1 is low, and the resulting compensation gain variation is larger.

[0119] In the above embodiment, the resistance value of the first control resistor is adapted to the temperature of the output transistor of the power amplifier, so that the voltage control module can generate different first voltages and second voltages according to the different shutdown times of the power amplifier, and then the RF switch module performs different gain compensation on the original input signal.

[0120] Please refer to Figure 3 In one embodiment, the RF switch module 12 further includes a first DC unit 121 and a second DC unit 122.

[0121] A first end of the first DC unit 121 is electrically connected to a second end of the first switching capacitor C11, and a second end of the first DC unit 121 is grounded;

[0122] A first end of the second DC unit 122 is electrically connected to a second end of the second switched capacitor C12 , and a second end of the second DC unit 122 is grounded.

[0123] In the above embodiment, the first DC unit 121 and the second DC unit 122 are provided to shield the influence of the external device at the access end of the original input signal on the DEVM compensation circuit and / or the power amplifier.

[0124] Please refer to Figure 5 In one embodiment, the first DC unit 121 includes a first DC inductor L121, and the second DC unit 122 includes a second DC inductor L122.

[0125] A first end of the first DC inductor L121 is electrically connected to a second end of the first switch capacitor C11, and a second end of the first DC inductor L121 is grounded;

[0126] A first end of the second DC inductor L122 is electrically connected to a second end of the second switched capacitor C12 , and a second end of the second DC inductor L122 is grounded.

[0127] Please refer to Figure 6 In one embodiment, the first DC unit 121 includes a first DC resistor R125, and the second DC unit 122 includes a second DC resistor R126.

[0128] A first end of the first DC resistor R125 is electrically connected to a second end of the first switch capacitor C11, and a second end of the first DC resistor R125 is grounded;

[0129] A first end of the second DC resistor R126 is electrically connected to a second end of the second switch capacitor C12 , and a second end of the second DC resistor R126 is grounded.

[0130] Please refer to Figure 7 In one embodiment of the present invention, a power amplifier is provided, comprising an amplifier circuit 21, a bias circuit 22, and the DEVM compensation circuit for a power amplifier according to the first aspect of the present invention and its optional solutions;

[0131] The input end of the RF switch module 12 is connected to the original input signal Rfin, the output end of the RF switch module 12 is electrically connected to the amplifier circuit 21, and the input end of the voltage control module 11 is connected to the control signal PA_EN, so that when the control signal PA_EN is at a target level, the original input signal Rfin is gain compensated to obtain a compensated input signal, and the compensated input signal is transmitted to the amplifier circuit 21;

[0132] The bias circuit 22 is electrically connected to the amplifier circuit 21 to generate a bias voltage and feed the bias voltage back to the amplifier circuit 21;

[0133] The amplifying circuit 21 is directly or indirectly electrically connected to the antenna ANT to amplify the compensated input signal based on the bias voltage and then transmit the amplified signal through the antenna ANT.

[0134] In one example, the amplifier circuit may be a single-stage amplifier circuit, that is, the amplifier circuit includes only one transistor or a transistor array, and performs one-stage amplification on the compensation input signal.

[0135] In another example, the amplifier circuit is a two-stage amplifier circuit, and the corresponding bias circuits are also two, that is, the amplifier circuit includes two transistors or two transistor arrays, and realizes double amplification of the compensation input signal.

[0136] In another example, the amplifier circuit is a three-stage amplifier circuit, and the corresponding bias circuits are also three, that is, the amplifier circuit includes three transistors or three transistor arrays, and realizes double amplification of the compensation input signal.

[0137] It can be seen that the number of amplifications of the amplifier circuit can be designed according to actual applications. No matter how many times the amplifier circuit achieves amplification, it is included in the protection scope of the present invention.

[0138] Please refer to Figure 8 In one embodiment, the amplifier circuit 21 includes an output transistor Q1.

[0139] The output end of the RF switch module 12 and the bias circuit 22 are electrically connected to the control electrode of the output transistor Q1, the first electrode of the output transistor Q1 is electrically connected to the first power supply VCC1, and the second electrode of the output transistor Q1 is grounded; the first electrode of the output transistor Q1 is directly or indirectly electrically connected to the antenna ANT;

[0140] The bias circuit 22 is electrically connected to the first power supply VCC1.

[0141] The output transistor Q1 may be a single GaAs HBT or an array of GaAs HBTs. The control electrode of the output transistor Q1 may be the base of the output transistor Q1 , the first electrode of the output transistor Q1 may be the collector of the output transistor Q1 , and the second electrode of the output transistor Q1 may be the emitter of the output transistor Q1 .

[0142] In one embodiment, the bias circuit 22 includes a first bias transistor Q2, a second bias transistor Q3 and a reference current source IREF.

[0143] A first end of the reference current source IREF is electrically connected to a second power supply VCC2, and a second end of the reference current source IREF is electrically connected to a control electrode of the first bias transistor Q2 and a first electrode of the second bias transistor Q3;

[0144] A first electrode of the first bias transistor Q2 is electrically connected to the first power supply VCC1, and a second electrode of the first bias transistor Q2 is electrically connected to the control electrode of the output transistor Q1;

[0145] A control electrode of the second bias transistor Q3 is electrically connected to a control electrode of the output transistor Q1 , and a second electrode of the second bias transistor Q3 is grounded.

[0146] Please refer to Figure 9 In one example, a power amplifier and a portion of the DEVM compensation circuit can be integrated on a circuit board 3, wherein the output transistor is a two-stage HBT array. That is, the compensated input signal received by the power amplifier is amplified by the two-stage HBT array and then transmitted through the antenna. The first control resistor R111 and a portion of the second bias transistor Q3 are disposed between the HBT arrays near the antenna, forming a tight thermal coupling to monitor the temperature of the output transistor and convert it into a corresponding resistance value or voltage value. The portion of the second bias transistor Q3 is disposed between the HBT arrays far from the antenna, forming a tight thermal coupling, thereby causing the gain of the power amplifier to decrease monotonically with the length of the power amplifier's on-time until it stabilizes. This is different from some solutions in which the second bias transistor Q3 is far from the output transistor Q1 and lacks a tight thermal coupling. As a result, the current of the output transistor Q1 first increases rapidly due to the self-heating effect, and then the heat is transferred to the second bias transistor Q3 after a period of time (approximately several hundred microseconds). The rising trend of the current in the output transistor Q1 then decreases until it stabilizes. The gain of the power amplifier will first increase and then decrease, increasing the difficulty of gain compensation.

[0147] In one embodiment, the power amplifier further includes an isolation capacitor C21 , and a first end of the isolation capacitor C21 is electrically connected between the output end of the RF switch module 12 and the control electrode of the output transistor Q1 .

[0148] By setting the isolation capacitor C21, the DEVM compensation circuit can be isolated from the amplifier circuit 21.

[0149] In one embodiment, the power amplifier further includes an output matching circuit 23 , wherein a first end of the output matching circuit 23 is electrically connected to a first electrode of the output transistor Q1 , and a second end of the output matching circuit 23 is electrically connected to the antenna ANT.

[0150] In one example, the output matching circuit 23 includes a matching capacitor C23 and a matching inductor L23, the first end of the matching capacitor C23 is electrically connected to the first electrode of the output transistor Q1, the second end of the matching capacitor C23 is electrically connected to the antenna ANT, the first end of the matching inductor L23 is electrically connected to the second end of the matching capacitor C23, and the second end of the matching inductor L23 is grounded.

[0151] In another example, the output matching circuit 23 can be a matching network composed of multiple matching units, each matching unit includes a matching capacitor and a matching inductor, the first end of each matching inductor is electrically connected to one end of a matching capacitor, and the second end of each matching inductor is grounded, and then multiple matching capacitors are connected in series to form a matching network.

[0152] The following will be combined Figures 10 to 15 , elaborating in detail the positive effects of an embodiment of the present invention:

[0153] Depend on Figure 11 It can be seen that when the power amplifier does not perform gain compensation (i.e., the DEVM compensation circuit is not set), the gain of the power amplifier drops sharply after the power amplifier is turned on, and after a period of time, the gain tends to be stable;

[0154] Depend on Figure 12 and Figure 13 It can be seen that when the power amplifier performs gain compensation (i.e., sets the DEVM compensation circuit), after the power amplifier is turned on, the gain of the DEVM compensation circuit will slowly increase over time until it stabilizes, while the gain of the power amplifier decreases to a certain extent over time, but it still tends to be stable overall.

[0155] Figure 14 and Figure 15 In the figure, the EVM change curves are shown when the DEVM compensation circuit is used or not. It can be seen that the EVM after the DEVM compensation circuit is added is almost stable after the power amplifier is turned on.

[0156] The present invention further provides an electronic device, comprising the DEVM compensation circuit for a power amplifier or the power amplifier mentioned above.

[0157] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A DEVM compensation circuit for a power amplifier, characterized in that: include: Voltage control module, RF switch module, The input terminal of the voltage control module is connected to a control signal, and is used to: generate a first voltage and a second voltage according to the control signal, wherein the first voltage is generated based on the control signal, the second voltage is generated based on an inverted signal of the control signal, and the first voltage when the control signal is at a target level is lower than the second voltage when the control signal is at a non-target level; The first output end of the voltage control module is electrically connected to the first control end of the RF switch module, and the second output end of the voltage control module is electrically connected to the second control end of the RF switch module, so as to feed back the first voltage and the second voltage to the RF switch module. The input end of the RF switch module is connected to the original input signal, and the output end of the RF switch module is connected to the input end of the power amplifier, so that when the first voltage is greater than the second voltage, different gain compensation is performed on the original input signal within a target time period to obtain a compensated input signal, and the compensated input signal is transmitted to the power amplifier; the RF switch module also includes a first DC unit and a second DC unit; Wherein, the target level is a high level or a low level, wherein when the target level is a high level, the corresponding non-target level is a low level; when the target level is a low level, the corresponding non-target level is a high level; The target period matches the time period from when the power amplifier is turned on and the gain changes until the region stabilizes when the DEVM compensation circuit is not set.

2. The DEVM compensation circuit for a power amplifier according to claim 1, wherein: The radio frequency switch module includes a first transistor, a second transistor, a first switch capacitor, a second switch capacitor, and a third switch capacitor. The control electrode of the first transistor is electrically connected to the first output terminal of the voltage control module to receive the first voltage. A first electrode of the first transistor is electrically connected to a first end of the first switch capacitor, and a second end of the first transistor is electrically connected to a first end of the second switch capacitor; The second end of the first switch capacitor is connected to the original input signal, and the second end of the second switch capacitor is electrically connected to the input end of the power amplifier; The control electrode of the second transistor is electrically connected to the second output terminal of the voltage control module to receive the second voltage; A first electrode of the second transistor is electrically connected to a first end of the second switch capacitor, and a second electrode of the second transistor is electrically connected to a first end of the third switch capacitor; A second terminal of the third switched capacitor is grounded.

3. The DEVM compensation circuit for a power amplifier according to claim 2, wherein: The radio frequency switch module further includes a first switch resistor and a second switch resistor. Two ends of the first switch resistor are electrically connected to the first electrode and the second electrode of the first transistor respectively; Two ends of the second switch resistor are electrically connected to the first electrode and the second electrode of the second transistor respectively.

4. The DEVM compensation circuit for a power amplifier according to claim 2, wherein: The radio frequency switch module further includes a third switch resistor and a fourth switch resistor; A first end of the third switch resistor is electrically connected to the first output end of the voltage control module, and a second end of the third switch resistor is electrically connected to the control electrode of the first transistor; A first end of the fourth switch resistor is electrically connected to the second output end of the voltage control module, and a second end of the fourth switch resistor is electrically connected to the control electrode of the second transistor.

5. The DEVM compensation circuit for a power amplifier according to claim 2, wherein: The voltage control module includes an inverter, a buffer, a first control resistor and a second control resistor; The input end of the inverter is connected to the control signal, and the output end of the inverter is electrically connected to the control electrode of the second transistor, so as to generate the second voltage when the control signal is at a high level, and feed the second voltage back to the second transistor; The input end of the buffer is connected to the control signal, the output end of the buffer is electrically connected to the first end of the first control resistor, the second end of the first control resistor is electrically connected to the first end of the second control resistor, and the second end of the second control resistor is grounded; The second end of the first control resistor is electrically connected to the control electrode of the first transistor, so as to generate the first voltage when the control signal is at a high level, and feed the first voltage back to the first transistor.

6. The DEVM compensation circuit for a power amplifier according to claim 5, wherein: The first control resistor is a thermistor, and the resistance value of the first control resistor is adapted to the temperature of the power amplifier.

7. The DEVM compensation circuit for a power amplifier according to any one of claims 2 to 6, characterized in that: The first transistor and the second transistor are depletion-mode HEMTs.

8. A power amplifier, characterized in that: A DEVM compensation circuit for a power amplifier comprising an amplifier circuit, a bias circuit, and the DEVM compensation circuit for a power amplifier according to any one of claims 1 to 7; The output end of the radio frequency switch module is electrically connected to the amplifier circuit to transmit the compensation input signal to the amplifier circuit; The bias circuit is electrically connected to the amplifier circuit to generate a bias voltage and feed the bias voltage back to the amplifier circuit; The amplifying circuit is directly or indirectly electrically connected to the antenna to amplify the compensated input signal based on the bias voltage and then transmit the amplified signal through the antenna.

9. The power amplifier according to claim 8, wherein: The amplifier circuit includes an output transistor, The output end of the RF switch module and the bias circuit are electrically connected to the control electrode of the output transistor, the first electrode of the output transistor is electrically connected to a first power supply, and the second electrode of the output transistor is grounded; the first electrode of the output transistor is directly or indirectly electrically connected to the antenna; The bias circuit is electrically connected to the first power supply.

10. The power amplifier according to claim 9, wherein: The bias circuit includes a first bias transistor, a second bias transistor and a reference current source, A first terminal of the reference current source is electrically connected to a second power supply, and a second terminal of the reference current source is electrically connected to a control electrode of the first bias transistor and a first electrode of the second bias transistor; A first electrode of the first bias transistor is electrically connected to the first power supply, and a second electrode of the first bias transistor is electrically connected to the control electrode of the output transistor; A control electrode of the second bias transistor is electrically connected to a control electrode of the output transistor, and a second electrode of the second bias transistor is grounded.

11. The power amplifier according to claim 9, wherein: It also includes an isolation capacitor, a first end of which is electrically connected between the output end of the RF switch module and the control electrode of the output transistor.

12. The power amplifier according to claim 9, wherein: An output matching circuit is also included, wherein a first end of the output matching circuit is electrically connected to the first electrode of the output transistor, and a second end of the output matching circuit is electrically connected to the antenna.

13. An electronic device, characterized in that: The DEVM compensation circuit for a power amplifier comprises any one of claims 1 to 7 or the power amplifier according to any one of claims 8 to 12.

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