A method for creating different designs by combining a set of predefined separate masks

Abstract

The present invention describes a method for achieving creation of multiple similar designs by utilizing a set of multiple separate manufacturing masks. A first set of device features may be formed from a material layer in a first portion of a die area of ​​a semiconductor substrate based on a first photolithographic exposure. A second set of device features may be formed from the material layer in a second portion of the die area of ​​the semiconductor substrate based on a second photolithographic exposure subsequent to the first photolithographic exposure. The first portion of the die area may not overlap with the second portion of the die area.

Description

[0001] Priority claim

[0002] This application claims priority to U.S. Provisional Patent Application No. 62 / 780,140, ​​filed on December 14, 2018, entitled "METHOD FORCREATION OF DIFFERENT DESIGNS BY COMBINING A SET OF PRE-DEFINED DISJOINTMASKS," and is incorporated by reference in its entirety. Background Art

[0003] The integrated circuit (IC) design and manufacturing process can be very long and arduous. Modern IC design and manufacturing processes can be highly customized, and the time required to go from design concept to working chip can be months or even years. Many techniques can be used to reduce the time to produce a working chip, some of which may incorporate design reuse.

[0004] Some techniques may involve using pre-silicon methods to reduce design time. These methods can be deployed at the architectural level as well as the circuit design level, which may ultimately lead to the creation of a set of customized masks for any single chip, even though they may be derivatives of previous designs. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The embodiments of the present disclosure will be more fully understood from the detailed description given below and from the drawings of various embodiments of the present disclosure. However, while the drawings aid in explanation and understanding, they are merely an aid and should not be considered to limit the present disclosure to the specific embodiments depicted therein.

[0006] Figure 1 A first photolithography mask, a second photolithography mask, and an integrated circuit (IC) die manufactured using the first photolithography mask and the second photolithography mask according to some embodiments of the present disclosure are described.

[0007] Figures 2A to 2F A manufacturing process involving a semiconductor substrate, a first photolithography mask, and a second photolithography mask according to some embodiments of the present disclosure is described.

[0008] Figures 3A to 3E Another manufacturing process involving a semiconductor substrate, a first photolithography mask, and a second photolithography mask according to some embodiments of the present disclosure is described.

[0009] Figure 4 A first photolithography mask, a second photolithography mask, and an IC die manufactured using the first photolithography mask and the second photolithography mask according to some embodiments of the present disclosure are described.

[0010] Figure 5 An IC die having multiple die area portions is described according to some embodiments of the present disclosure.

[0011] Figure 6 Methods of enabling creation of multiple similar designs by utilizing multiple separate fabrication masks according to some embodiments of the present disclosure are described.

[0012] Figure 7 Methods of enabling creation of multiple similar designs by utilizing multiple separate fabrication masks according to some embodiments of the present disclosure are described.

[0013] Figure 8 Methods of enabling creation of multiple similar designs by utilizing multiple separate fabrication masks according to some embodiments of the present disclosure are described. DETAILED DESCRIPTION

[0014] In the following description, many details are discussed to provide a more thorough explanation of the embodiments of the present disclosure. However, it is apparent to those skilled in the art that the embodiments of the present disclosure can be implemented without these specific details. In other examples, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring the embodiments of the present disclosure.

[0015] Throughout the specification and in the claims, the term "connected" means a direct electrical, mechanical, or magnetic connection between the things that are connected, without any intermediate devices. The term "coupled" means a direct electrical, mechanical, or magnetic connection between the things that are connected, or an indirect connection through one or more passive or active intermediate devices. The term "circuit" or "module" may refer to one or more passive and / or active components that are arranged to cooperate with each other to provide the desired functionality. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data / clock signal. The meaning of "a", "an", and "said" includes plural meanings. The meaning of "in..." includes "in..." and "on..."

[0016] The terms "substantially," "close," "approximately," "near," and "about" generally refer to within + / - 10% of a target value. Unless otherwise specified, the use of ordinal adjectives "first," "second," and "third," etc. to describe a common object merely indicates that different instances of similar objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, whether in time, space, ranking, or in any other manner.

[0017] It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than illustrated or otherwise described herein.

[0018] The terms "left", "right", "front", "back", "top", "bottom", "upper", "lower" and the like in the description and claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions.

[0019] For purposes of this disclosure, the phrases "A and / or B" and "A or B" mean (A), (B), or (A and B). For purposes of this disclosure, the phrases "A, B, and / or C" mean (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0020] Additionally, the various elements of combinatorial and sequential logic discussed in this disclosure may both relate to physical structures (e.g., AND gates, OR gates, or XOR gates), or a synthetic or otherwise optimized collection of devices that implement logic structures that are Boolean equivalents of the logic in question.

[0021] Disclosed herein is a method for enabling the creation of multiple similar designs by utilizing a set of multiple separate manufacturing masks, which can advantageously significantly reduce design time and cost. In various embodiments, an integrated circuit (IC) die may have a modular design in which multiple intellectual property cores (IPs) may be used as modules. The methods discussed herein may include reusing and / or combining created separate masks from previous designs to support new designs. In some embodiments, the various modules of the modular design may be associated with system capacities or capabilities (e.g., processors, memory, radio circuits, etc.).

[0022] Figure 1 A first photolithography mask, a second photolithography mask, and an IC die are illustrated according to some embodiments of the present disclosure: The first mask 110 may include a set of first mask features 111 , and the second mask 120 may include a set of second mask features 121 .

[0023] As discussed in further detail below, the IC die 130 may be fabricated using the first mask 110 and the second mask 120. The first portion 131 of the IC die 130 may include a set of first device features 151 formed using the first mask 110 and its first mask features 111. Similarly, the second portion 132 of the IC die 130 may include a set of second device features 152 formed using the second mask 120 and its second mask features 121. In various embodiments, the first portion 131 may be separated from the second portion 132, and the first device features 151 may be separated from the second device features 152.

[0024] Device feature 151 may correspond to a first module and / or a first IP for the overall design of IC die 130, and device feature 152 may correspond to a second module and / or a second IP for the overall design. If one or more dedicated masks are created for first portion 131, and if one or more dedicated masks are created for second portion 132, the overall design or final design of IC die 130 may be created by using the dedicated masks for first portion 131 and the dedicated masks for second portion 132. As a result, in some embodiments, the final design of IC die 130 may include first device feature 151 and second device feature 152.

[0025] However, in other embodiments, the final design may alternatively include first device features 151 having another separate set of device features corresponding to another module and / or IP. Similarly, in other embodiments, the final design may include second device features 152 having yet another separate set of device features corresponding to yet another module and / or IP. Thus, the methods discussed herein may advantageously support the use of first mask 110 and second mask 120 for a variety of different IC die designs.

[0026] For example, the first mask 110 and / or the second mask 120 (in some embodiments, along with one or more other masks) may be used to form device features in one or more upper layers of the IC die design where global routing may be performed. In some embodiments, the one or more upper layers may include a metal layer, or a layer that primarily includes metal. In some embodiments, the one or more upper layers may include a redistribution layer. In some embodiments, features in a redistribution layer (e.g., interconnects or other wiring) may have one or more cross-sectional dimensions that, on average, are larger than cross-sectional dimensions of other layers (e.g., other metal layers for a redistribution layer that primarily includes metal). Thus, features of a redistribution layer may have a larger cross-sectional height or cross-sectional width than features of another layer (e.g., interconnects).

[0027] Following various design rules during the design process of global routing can accommodate decisions about which set of masks (e.g., which set of masks for global routing device features) can be used to meet a given design requirement or design standard. For example, the various design rules can support decisions to use masks corresponding to various design features that may support different capacities or capabilities (as further discussed herein). Therefore, the methods discussed herein can advantageously facilitate and / or enable rapid prototyping of IC dies having a modular design by accommodating different masks corresponding to different IPs.

[0028] Figures 2A to 2FA manufacturing process involving a semiconductor substrate, a first photolithography mask, and a second photolithography mask according to some embodiments of the present disclosure is described. The semiconductor substrate may include a silicon wafer, such as a silicon wafer in a photolithography IC manufacturing process. In various embodiments, the semiconductor substrate may be covered or coated with a photoresist layer.

[0029] like Figure 2A As depicted, a die area 230 of a semiconductor substrate may have a first portion 231 and a second portion 232. The first portion 231 and the second portion 232 may be separated and / or spaced apart from each other on the semiconductor substrate. A first mask 210 may be placed in a first alignment with at least the first portion 231 of the die area 230. The first mask 210 may include a set of first mask features 211. The first alignment may place the first mask features 211 in a position corresponding to the first portion 231 of the die area 230.

[0030] exist Figure 2B , a first photolithographic exposure may be performed on die area 230 through first mask 210. The exposure light may pass through first mask features 211 and may interact with first photoresist region 241 of first portion 231 (and may not interact with photoresist of second portion 232).

[0031] After the first photolithographic exposure, the first photoresist region 241 may be weakened. The first photoresist region 241 may then be dissolved and removed by subsequent processing, leaving trenches that expose the remaining portion of the semiconductor substrate below the photoresist. A material (e.g., a metal material or a material including a metal) may then be deposited on the die region 230 and may fill the trenches exposed by removing the first photoresist region 241.

[0032] exist Figure 2C In the embodiment of the present invention, the remaining portion of the photoresist outside the first photoresist region 241 can be removed to form a first device feature 251 in the first portion 231. Therefore, the first device feature 251 of the die area 230 can be formed by a material (e.g., a metal material) that has filled the trench exposed by removing the first photoresist region 241, which is then exposed based on the first photolithography. Various embodiments may use a positive photoresist and / or a lift-off process.

[0033] Figures 2D to 2F The processing can be Figures 2A to 2C The processing is substantially similar, but with respect to the second portion 232 instead of the first portion 231. In various embodiments, the semiconductor substrate may be covered or coated with another photoresist layer (which may be substantially similar to the photoresist layer that may be used for Figure 2A The type of photoresist layer is set).

[0034] exist Figure 2D In the second embodiment, the second mask 220 may be placed in a second alignment with at least a second portion 232 of the die area 230. The second mask 220 may include a set of second mask features 221. The second alignment may place the second mask features 221 in a position corresponding to the second portion 232 of the die area 230.

[0035] exist Figure 2E In the embodiment of the present invention, a second photolithographic exposure may be performed on the die area 230 through the second mask 220. The exposure light may pass through the second mask features 221 and may interact with the second photoresist region 242 of the second portion 232 (and may not interact with the photoresist of the first portion 231).

[0036] After the second photolithographic exposure, the second photoresist region 242 may be weakened. The second photoresist region 242 may then be dissolved and removed by subsequent processing, leaving trenches that expose the remaining portion of the semiconductor substrate beneath the photoresist. A material (e.g., a metal material or a material including a metal) may then be deposited on the die region 230 and may fill the trenches exposed by removing the second photoresist region 242.

[0037] exist Figure 2F In the embodiment of the present invention, the remaining portion of the photoresist outside the second photoresist region 242 can be removed to form a second device feature 252 in the second portion 232. Therefore, the second device feature 252 of the die region 230 can be formed by the material (e.g., metal material) that has filled the trench exposed by removing the second photoresist region 242, which is then exposed based on the second photolithography.

[0038] After these processing steps, die area 230 may include first device feature 251 in first portion 231 and second device feature 252 in second portion 232. In various embodiments, first portion 231 may be spaced apart from second portion 232, and / or first portion 231 may be separated from second portion 232, and / or first portion 231 may not overlap second portion 232. For various embodiments, the metal material of first device feature 251 and / or second device feature 252 may include portions of a metal layer of a semiconductor substrate.

[0039] For some embodiments, portions of the semiconductor substrate below the first device feature 251 and / or portions of the semiconductor substrate below the second device feature 252 may include analog signaling regions and / or wiring operable to route analog signals. Thus, some portions of the die area 230 may have wiring for digital signals, while other portions of the die area 230 (including portions of the die area 230 formed by the first mask 210 and / or the second mask 220) may have wiring more suitable for analog signals.

[0040] Figures 3A to 3E Another manufacturing process involving a semiconductor substrate, a first photolithography mask, and a second photolithography mask according to some embodiments of the present disclosure is described. Figure 3A and 3B A die area 330 having a first portion 331 and a second portion 332 , and a first mask 310 having a set of first mask features 311 may be involved.

[0041] Figure 3A and 3B The process can be basically similar to Figure 2A and 2B After the first photolithography exposure is performed through the first mask feature 311, the first photoresist region 341 may be weakened. However, instead of dissolving and removing the photoresist in the first photoresist region 341, depositing material to fill the trench exposed by the first photoresist region 341, removing the remaining portion of the photoresist, and covering or coating the semiconductor substrate with another photoresist layer, a second photolithography exposure may be performed on the same photoresist layer.

[0042] Therefore, in Figure 3C In the second embodiment, the second mask 320 can be placed in a second alignment with at least a second portion 332 of the die area 330. The second mask 320 can include a set of second mask features 321. The second alignment can place the second mask features 321 in a position corresponding to 332 of the die area 330.

[0043] exist Figure 3D , a second photolithographic exposure may be performed on die area 330 through second mask 310. The exposure light may pass through second mask features 321 and may interact with second photoresist region 342 of second portion 332 (and may not interact with regions of first portion 331).

[0044] Thus, after the second photolithography exposure, both the first photoresist region 341 and the second photoresist region 342 may be weakened. Then, both the first photoresist region 341 and the second photoresist region 341 may be dissolved and removed by subsequent processing, leaving trenches that expose the remaining portion of the semiconductor substrate below the photoresist. A material (e.g., a metal material or a material including a metal) may then be deposited on the die region 330 and may fill the trenches exposed by removing the first photoresist region 341 and the second photoresist region 342.

[0045] As a result, in some embodiments, after one photolithographic exposure, dissolution and removal of various photoresist regions may be postponed until another photolithographic exposure has been performed.

[0046] The photoresist layers discussed above are depicted as positive photoresist layers (i.e., photoresist materials whose structural integrity is degraded by exposure to light). However, some embodiments may utilize negative photoresist layers (i.e., photoresist materials whose structural integrity is enhanced by exposure to light). Figure 4 A first photolithography mask, a second photolithography mask, and an IC die manufactured using the first photolithography mask and the second photolithography mask according to some embodiments of the present disclosure are illustrated. The first mask 410 may include a set of first mask features 411 , and the second mask 420 may include a set of second mask features 421 .

[0047] Compared to the first mask 110, the first mask 410 can be designed so that the areas of the photoresist layer exposed to light outside the first mask features 411 can become enhanced. The remaining photoresist areas (i.e., the photoresist areas corresponding to the first mask features 411) can then be dissolved and removed by subsequent processing, leaving the channels that expose the areas of the photoresist layer to the light outside the first mask features 411. A material (e.g., a metal material or a material including a metal) can then be deposited on the die area 430 and can fill the channels exposed by removing the unexposed photoresist. Various embodiments can use a negative photoresist and / or etching process (e.g., for depositing a layer of material, such as a metal material, then depositing a layer of photoresist, and then etching away the metal not covered by the patterned photoresist).

[0048] An IC die created according to the methods discussed herein may be advantageously designed to implement a programmable semiconductor interposer to which a chiplet may be mounted. A programmable semiconductor interposer may be or may include an IC. Such an interposer may provide a substrate to electrically connect with and / or between one or more chiplets. In turn, a chiplet may be or may include a semiconductor die, an IC, and / or a semiconductor chip. A chiplet may have a smaller footprint (e.g., a smaller x-dimension and y-dimension) than an interposer, and in various embodiments, multiple chiplets may fit within the footprint of an interposer.

[0049] Incorporating components with different capacities and capabilities into an IC die via chiplets mounted on an interconnect substrate can advantageously support rapid prototyping. At the same time, some chiplets that provide capacities and capabilities such as radio circuits or other wireless communication circuits can benefit from including routing for analog signaling on the interposer. Thus, the methods discussed herein can advantageously support the use of programmable semiconductor interconnects and one or more chiplets by allowing a user to defer certain fabrication and / or manufacturing process steps, thereby providing flexibility with respect to modules or IP to be incorporated into an IC design.

[0050] For example, Figure 5 An IC die having multiple die area portions according to some embodiments of the present disclosure is illustrated. IC die 530 may include a programmable semiconductor interposer portion 535. A first chiplet 561 may be mounted to IC die 530 in an area including a set of first device features, and a second chiplet 562 may be mounted to IC die 530 in an area including a set of second device features.

[0051] The methods discussed herein can advantageously accommodate placement of chiplets with associated global wiring onto a programmable semiconductor interposer. Such mounted chiplets can advantageously tolerate relatively minor imperfections of the type in the alignment between device features created by a first mask and device features created by a second mask, because mounting or placing the chiplets onto a programmable semiconductor interposer can tolerate alignment imperfections. In contrast, previous design methods have not been able to tolerate alignment imperfections, and thus a multiple mask approach of the type disclosed herein would be undesirable for such designs.

[0052] Figure 6 A method of achieving creation of multiple similar designs by utilizing multiple separate manufacturing masks according to some embodiments of the present disclosure is illustrated. Method 600 may include forming 610 and forming 615. In some embodiments, method 600 may also include mounting 620 and / or mounting 625.

[0053] In forming 610, a first set of device features (e.g., first device features 251) may be formed from a material layer in a first portion of a die area of ​​a semiconductor substrate (e.g., first portion 231 of die area 230) based on a first photolithography exposure. In forming 615, a second set of device features (e.g., second device features 252) may be formed from a material layer in a second portion of a die area of ​​a semiconductor substrate (e.g., second portion 232 of die area 230) based on a second photolithography exposure subsequent to the first photolithography exposure. The first portion of the die area may not overlap with the second portion of the die area.

[0054] In some embodiments, a first set of device features may be formed using a first photolithographic mask, and / or a second set of device features may be formed using a second photolithographic mask. For some embodiments, at least one of the first set of device features and the second set of device features is formed using a positive photoresist.

[0055] In some embodiments, the material layer may include a metal layer. For some embodiments, the material layer may include a redistribution layer.

[0056] In some embodiments, a portion of the semiconductor substrate below at least one of the first set of device features and the second set of device features includes an analog signaling region (e.g., a region having design features supporting global routing for analog signaling). For various embodiments, the semiconductor substrate may include a silicon wafer. In some embodiments, the die region may include features for a programmable semiconductor interposer (e.g., programmable semiconductor interposer portion 535).

[0057] For some embodiments, in mounting 620, a first chiplet (e.g., first chiplet 561) can be mounted in a first portion of the die area. For some embodiments, in mounting 625, a second chiplet (e.g., second chiplet 562) can be mounted in a second portion of the die area.

[0058] Figure 7 A method of enabling creation of multiple similar designs by utilizing multiple separate manufacturing masks according to some embodiments of the present disclosure is illustrated. Method 700 may include application 710, application 715, and process 720. In some embodiments, method 700 may include installation 730 and / or installation 735.

[0059] In application 710, a first photolithography pattern (e.g., a pattern of first mask features 211) may be applied to a first portion of a single die region of a semiconductor wafer (e.g., a first portion 231 of a die region 230) using a first photolithography mask (e.g., a first mask 210). In application 715, a second photolithography pattern (e.g., a pattern of second mask features 221) may be applied to a second portion of a single die region of a semiconductor wafer (e.g., a second portion 232 of a die region 230) using a second photolithography mask (e.g., a second mask 220). The second portion of the single die region may be separated from the first portion of the single die region. In process 720, the semiconductor wafer may be processed to form at least one of a first set of device features (e.g., first device features 251) in the first portion of the single die region and a second set of device features (e.g., second device features 252) in the second portion of the single die region.

[0060] In some embodiments, at least a portion of the first set of device features and at least a portion of the second set of device features may be formed in a metal layer and / or a redistribution layer. For some embodiments, at least one of the first photolithography pattern and the second photolithography pattern may be applied to a positive photoresist. In some embodiments, a portion of the semiconductor wafer below the first set of device features and / or the second set of device features may include an analog signaling region.

[0061] In some embodiments, a single die area may include features for a programmable semiconductor interposer (e.g., programmable semiconductor interposer portion 535). For some embodiments, in mounting 730, a first chiplet may be mounted in a first portion of the die area. For some embodiments, in mounting 735, a second chiplet may be mounted in a second portion of the die area.

[0062] Figure 8 The method 800 may include placing 810, performing 815, placing 820, and performing 825. The method 800 may also include processing 830, installing 840, and / or installing 845.

[0063] In placement 810, a first photolithography mask (e.g., first mask 210) may be placed to be first aligned with respect to a first portion of a single die region of a semiconductor wafer (e.g., first portion 231 of die region 230). In execution 815, a first photolithography exposure of the semiconductor wafer through the first photolithography mask may be performed. In placement 820, a second photolithography mask (e.g., second mask 220) may be placed to be second aligned with respect to a second portion of a single die region of a semiconductor wafer (e.g., second portion 232 of die region 230). In execution 825, a second photolithography exposure of the semiconductor wafer through the second photolithography mask may be performed. The first portion of the single die region may be separated from the second portion of the single die region.

[0064] In some embodiments, in process 830, the semiconductor wafer may be processed to form at least one of a first set of device features (e.g., first device features 251) in a first portion of the single die area and a second set of device features (e.g., second device features 252) in a second portion of the single die area.

[0065] For some embodiments, a portion of the semiconductor wafer below at least one of the first set of device features and the second set of device features may include an analog signaling area. In some embodiments, a single die area may include features for a programmable semiconductor interposer (e.g., programmable semiconductor interposer portion 535). For some embodiments, in mounting 240, a first chiplet (e.g., first chiplet 561) may be mounted in a first portion of the die area. For some embodiments, in mounting 245, a second chiplet (e.g., second chiplet 562) may be mounted in a second portion of the die area.

[0066] Although reference Figures 6 to 8 The actions in the flowcharts of are shown in a particular order, but the order of the actions may be modified. Thus, the illustrated embodiments may be performed in a different order, and some actions may be performed in parallel. According to some embodiments, Figures 6 to 8 Some of the actions and / or operations listed in the description are optional. The numbering of the actions presented is for clarity and is not intended to dictate the order in which the various actions must occur. In addition, the operations from the various flows may be utilized in various combinations.

[0067] In some embodiments, the apparatus may include a device for performing Figures 6 to 8 Methods of various actions and / or operations on components.

[0068] Furthermore, in some embodiments, a machine-readable storage medium may have executable instructions that, when executed, cause one or more processors to perform operations including method 600, method 700, or method 800. Such machine-readable storage media may include any of a variety of storage media, such as magnetic storage media (e.g., magnetic tapes or magnetic disks), optical storage media (e.g., optical disks), electronic storage media (e.g., conventional hard drives, solid-state disk drives, or flash memory-based storage media), or any other tangible storage media or non-transitory storage media.

[0069] References in the specification to "one embodiment," "an embodiment," "some embodiments," or "other embodiments" mean that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in at least some embodiments, but not necessarily in all embodiments. The various appearances of "one embodiment," "an embodiment," or "some embodiments" do not necessarily all refer to the same embodiment. If the specification states that a component, feature, structure, or characteristic "may," "might," or "could" be included, then inclusion of a particular component, feature, structure, or characteristic is not required. If the specification or claims refer to "a or an" element, then this does not mean that there is only one element. If the specification or claims refer to "an additional" element, then the presence of more than one additional element is not excluded.

[0070] In addition, in one or more embodiments, specific features, structures, functions or characteristics may be combined in any suitable manner. For example, the first embodiment may be combined with the second embodiment as long as the specific features, structures, functions or characteristics associated with the two embodiments are not mutually exclusive.

[0071] Although the present disclosure has been described in conjunction with specific embodiments of the present disclosure, many alternatives, modifications, and variations of these embodiments will be apparent to those of ordinary skill in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the embodiments discussed. The embodiments of the present disclosure are intended to encompass all such alternatives, modifications, and variations to fall within the broad scope of the appended claims.

[0072] In addition, for simplicity of illustration and discussion, and in order not to confuse the present disclosure, well-known power / ground connections to IC chips and other components may or may not be shown in the presented figures. Further, the arrangement may be shown in block diagram form to avoid confusing the present disclosure, and also taking into account the fact that the details of the implementation of such block diagram arrangements are highly dependent on the platform in which the present disclosure will be implemented (i.e., such details should be fully within the capabilities of those skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the present disclosure, it should be apparent to those skilled in the art that the present disclosure may be implemented without or by variations of these specific details. Therefore, the description should be considered illustrative and not restrictive.

[0073] An abstract is provided that will allow the reader to ascertain the nature and gist of the technical disclosure. The abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.

Claims

1. A method of achieving the creation of multiple similar designs by utilizing multiple separate manufacturing masks, wherein include: forming a first set of device features from a material layer in a first portion of a die region of a semiconductor substrate based on a first lithographic exposure; and forming a second set of device features from the material layer in a second portion of the die area of ​​the semiconductor substrate based on a second lithographic exposure subsequent to the first lithographic exposure; wherein the first portion of the die area does not overlap with the second portion of the die area, wherein a portion of the semiconductor substrate beneath at least one of the first set of device features and the second set of device features comprises an analog signaling region, wherein the die region includes features for a programmable semiconductor interposer; mounting a first chiplet in the first portion of the die area including a first set of device features; and mounting a second chiplet in the second portion of the die area including a second set of device features, The first chiplet and the second chiplet are mounted to the programmable semiconductor interposer, which provides a substrate for making electrical connections with and / or between one or more chiplets.

2. The method according to claim 1, wherein the first set of device features are formed using a first photolithographic mask, and Wherein the second set of device features are formed using a second photolithography mask.

3. The method according to claim 1, Wherein at least one of the first set of device features and the second set of device features is formed using a positive photoresist.

4. The method according to claim 1, The material layer includes a metal layer.

5. The method according to claim 1, The material layer comprises a redistribution layer.

6. The method according to claim 1, The semiconductor substrate comprises a silicon wafer.

7. A method of achieving the creation of multiple similar designs by utilizing multiple separate manufacturing masks, wherein include: applying a first lithographic pattern to a first portion of a single die region of a semiconductor wafer using a first lithographic mask; applying a second photolithographic pattern to a second portion of the single die area of ​​the semiconductor wafer using a second photolithographic mask, the second portion of the single die area being spaced apart from the first portion of the single die area; and processing the semiconductor wafer to form at least one of a first set of device features in the first portion of the single die area and a second set of device features in the second portion of the single die area, wherein a portion of the semiconductor wafer underlying at least one of the first set of device features and the second set of device features comprises an analog signaling region; wherein the single die region includes features for a programmable semiconductor interposer; mounting a first chiplet in said first portion of said die area; and mounting a second chiplet in the second portion of the die area, The first chiplet and the second chiplet are mounted to the programmable semiconductor interposer, which provides a substrate for making electrical connections with and / or between one or more chiplets.

8. The method according to claim 7, Wherein at least a portion of the first set of device features and at least a portion of the second set of device features are formed in at least one of a metal layer and a redistribution layer.

9. The method according to claim 7, At least one of the first photolithography pattern and the second photolithography pattern is applied to a positive photoresist.

10. A method of achieving the creation of multiple similar designs by utilizing multiple separate manufacturing masks, wherein include: placing a first photolithography mask in a first alignment relative to a first portion of a single die area of ​​a semiconductor wafer; performing a first photolithography exposure of the semiconductor wafer through the first photolithography mask; placing a second photolithography mask in a second alignment relative to a second portion of the single die region of the semiconductor wafer; and performing a second photolithography exposure of the semiconductor wafer through the second photolithography mask, wherein the first portion of the single die area is separated from the second portion of the single die area, processing the semiconductor wafer to form at least one of a first set of device features in the first portion of the single die area and a second set of device features in the second portion of the single die area, wherein a portion of the semiconductor wafer underlying at least one of the first set of device features and the second set of device features comprises an analog signaling region; wherein the single die region includes features for a programmable semiconductor interposer; mounting a first chiplet in said first portion of said die area; and mounting a second chiplet in the second portion of the die area, The first chiplet and the second chiplet are mounted to the programmable semiconductor interposer, which provides a substrate for making electrical connections with and / or between one or more chiplets.

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