Network processor and packet processing method

Abstract

The embodiment of the present application discloses a network processor, relates to the computer field, and solves the problems of how to reduce the long time length of the network processor for processing a message and the volume, power consumption and cost of the network processor. The network processor comprises N processors, an instruction memory and an instruction branch lookup engine, each processor in the N processors is connected with the instruction memory and the instruction branch lookup engine, and N is an integer greater than or equal to 2. The processor is used for determining a query condition according to a forwarding processing operation on the message; the instruction branch lookup engine is used for obtaining an associated data index according to the query condition, the associated data index is used for indicating a storage address of a forwarding processing instruction corresponding to the forwarding processing operation; the processor is further used for obtaining the forwarding processing instruction from the instruction memory according to the associated data index; and the processor is further used for performing the forwarding processing operation on the message according to the forwarding processing instruction. The embodiment of the present application is used in the process of message forwarding.

Description

Technical Field

[0001] This application relates to the field of computers, and more particularly to a network processor and a message processing method. Background Technology

[0002] In the Internet, network devices (e.g., switches or routers) preprocess and forward received packets to facilitate transmission from the source to the destination. Typically, a network processor (NP) within the network device performs this forwarding process. In existing technology, a network processor comprises multiple processors, each connected to an instruction memory. Each instruction memory stores all forwarding instructions related to the forwarding process. When any processor performs a first forwarding operation on a preprocessed packet, it retrieves a first forwarding instruction from the instruction memory connected to that processor. This first forwarding instruction is the one related to the first forwarding operation. Then, the processor performs the first forwarding operation on the packet according to this instruction. In this network processor architecture, the long processing time leads to significant forwarding latency. Furthermore, the large size of the network processor results in higher power consumption and cost. Therefore, reducing the time it takes for network processors to process packets, as well as the size, power consumption, and cost of network processors, is an urgent problem to be solved. Summary of the Invention

[0003] This application provides a network processor and a packet processing method, which solves the problems of how to reduce the processing time of network processors, as well as the size, power consumption and cost of network processors.

[0004] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0005] In a first aspect, embodiments of this application provide a network processor comprising: N processors, an instruction memory, and an instruction branch lookup engine. Each of the N processors is connected to both the instruction memory and the instruction branch lookup engine, where N is an integer greater than or equal to 2. The processors are configured to determine query conditions based on packet forwarding operations; the instruction branch lookup engine is configured to obtain an associated data index based on the query conditions, the associated data index indicating the storage address of the forwarding processing instruction corresponding to the forwarding operation; the processors are further configured to retrieve the forwarding processing instruction from the instruction memory based on the associated data index; and the processors are further configured to perform forwarding processing operations on the packet based on the forwarding processing instruction. The network processor provided in this application, by determining the storage address of the forwarding processing instruction based on the query conditions and the correspondence between the query conditions, the associated data index, and the storage address of the forwarding processing instruction, and retrieving the forwarding processing instruction required for packet processing, can effectively reduce the processing time of the network processor when processing packets and the latency of forwarding packets, avoiding the problem of long packet forwarding latency caused by searching and retrieving the forwarding processing instruction from the instruction memory based on the starting address of the forwarding processing instruction. In addition, by reducing the number of instruction memories and instruction branch lookup engines included in the network processor, the size, power consumption, and cost of the network processor can be reduced.

[0006] In conjunction with the first aspect, in one possible implementation, the instruction memory includes N instruction buffer storage modules and one instruction storage module. Each of the N instruction buffer storage modules is connected to a processor, and the N instruction buffer storage modules are respectively connected to the instruction storage module. Therefore, by adding instruction buffer storage modules to the instruction memory to store frequently used forwarding instructions of the processor, the processing time of the network processor when processing packets and the latency of forwarding packets can be further reduced.

[0007] In another possible implementation, combining the above possible methods, the processor includes a controller. The controller determines the storage address of the forwarding processing instruction in the instruction buffer storage module based on the associated data index. The controller also retrieves the forwarding processing instruction from the instruction buffer storage module based on the storage address of the forwarding processing instruction. Thus, by querying the correspondence between the conditions, the associated data index, and the storage address of the forwarding processing instruction, the forwarding processing instruction required for processing the packet can be obtained. This effectively reduces the processing time of the network processor when processing packets and the latency of forwarding packets, avoiding the problem of long forwarding latency caused by searching and retrieving the forwarding processing instruction from the instruction storage module based on its starting address.

[0008] Specifically, the storage space corresponding to the storage address of the forwarding processing instruction can be the storage space corresponding to a buffered instruction line in the instruction buffer storage module. Alternatively, the storage space corresponding to the storage address of the forwarding processing instruction can be the storage space required to store the forwarding processing instruction. This effectively improves the utilization rate of storage space in the instruction buffer storage module.

[0009] In conjunction with the first aspect, in another possible implementation, the processor includes a controller. If the processor fails to retrieve the forwarding instruction from the instruction buffer storage module based on the storage address of the forwarding instruction, the controller retrieves the forwarding instruction from the instruction storage module based on the starting address of the forwarding instruction. The starting address of the forwarding instruction is obtained by the processor from the instruction branch lookup engine based on query conditions. The instruction buffer storage module is also used to store the forwarding instruction based on its storage address, which is the address in the instruction buffer storage module corresponding to the associated data index.

[0010] Secondly, embodiments of this application provide a message processing method applicable to a network processor. The network processor includes N processors, an instruction memory, and an instruction branch lookup engine. Each of the N processors is connected to both the instruction memory and the instruction branch lookup engine, where N is an integer greater than or equal to 2. The method includes: the processor determining query conditions based on the message forwarding operation; the instruction branch lookup engine obtaining an associated data index based on the query conditions, the associated data index indicating the storage address of the forwarding processing instruction corresponding to the forwarding operation; the processor retrieving the forwarding processing instruction from the instruction memory based on the associated data index; and the processor performing forwarding processing on the message according to the forwarding processing instruction. The network processor provided in this application, by determining the storage address of the forwarding processing instruction based on the query conditions and the correspondence between the query conditions, the associated data index, and the storage address of the forwarding processing instruction, and retrieving the forwarding processing instruction required for message processing, can effectively reduce the processing time of the network processor when processing messages and the latency of forwarding messages, avoiding the problem of long forwarding latency caused by searching and retrieving the forwarding processing instruction from the instruction memory based on the starting address of the forwarding processing instruction. In addition, by reducing the number of instruction memories and instruction branch lookup engines included in the network processor, the size, power consumption, and cost of the network processor can be reduced.

[0011] In conjunction with the second aspect, in one possible implementation, the instruction memory includes N instruction buffer storage modules and one instruction storage module. Each of the N instruction buffer storage modules is connected to a processor, and each of the N instruction buffer storage modules is connected to the instruction storage module. The processor includes a controller. The processor retrieves forwarding processing instructions from the instruction memory according to an associated data index, including: the controller determining the storage address of the forwarding processing instruction in the instruction buffer storage module based on the associated data index; and the controller retrieving the forwarding processing instruction from the instruction buffer storage module based on the storage address of the forwarding processing instruction. Therefore, by adding instruction buffer storage modules to the instruction memory to store frequently used forwarding processing instructions, the processing time of the network processor when processing packets and the latency of forwarding packets can be further reduced.

[0012] Specifically, the storage space corresponding to the storage address of the forwarding processing instruction can be the storage space corresponding to a buffered instruction line in the instruction buffer storage module. Alternatively, the storage space corresponding to the storage address of the forwarding processing instruction can be the storage space required to store the forwarding processing instruction. This effectively improves the utilization rate of storage space in the instruction buffer storage module.

[0013] In conjunction with the second aspect, in another possible implementation, the instruction memory includes N instruction buffer memory modules and one instruction storage module. Each of the N instruction buffer memory modules is connected to a processor, and the N instruction buffer memory modules are respectively connected to the instruction storage module. The processor includes a controller. If the processor fails to retrieve the forwarding instruction from the instruction buffer memory module based on the storage address of the forwarding instruction, the method further includes: the controller retrieving the forwarding instruction from the instruction storage module based on the starting address of the forwarding instruction, where the starting address of the forwarding instruction is obtained by the processor from the instruction branch lookup engine based on query conditions; and the instruction buffer memory modules storing the forwarding instruction based on the storage address of the forwarding instruction in the instruction buffer memory module corresponding to the associated data index.

[0014] Optionally, the network processor provided by any of the above aspects can adopt a multi-processor parallel (pipeline) architecture. Therefore, in the embodiments of this application, the network processor can use multiple processors to forward the same packet, with each processor performing different forwarding operations. Thus, the processor used to process packets in the network processor can be at least one processor, thereby further reducing the time for the network processor to process packets and the latency of forwarding packets.

[0015] Thirdly, embodiments of this application also provide a computer-readable storage medium, including: computer software instructions; when the computer software instructions are executed in a network processor, they cause the network processor to perform the method described in the second aspect above.

[0016] Fourthly, embodiments of this application also provide a computer program product containing instructions that, when run in a network processor, cause the network processor to execute the method described in the second aspect above.

[0017] Fifthly, embodiments of this application provide a chip system including a processor and potentially a memory, for implementing the functions of the network processor described above. This chip system can be composed of chips or may include chips and other discrete devices.

[0018] Furthermore, the technical effects brought about by any of the above design methods can be found in the technical effects brought about by different design methods in the first and second aspects, and will not be repeated here.

[0019] In this embodiment, the name of the network processing device is not limiting to the device itself; in actual implementation, these devices may appear under other names. As long as the function of each device is similar to that of the embodiment in this application, it falls within the scope of the claims of this application and its equivalents. Attached Figure Description

[0020] Figure 1 An example diagram illustrating the composition of a network processor provided for the prior art;

[0021] Figure 2 An example diagram illustrating the composition of a network processor provided in an embodiment of this application;

[0022] Figure 3 An example diagram illustrating the composition of another network processor provided in an embodiment of this application;

[0023] Figure 4 An example diagram illustrating the correspondence between a tag and an instruction line address, provided for an embodiment of this application;

[0024] Figure 5 An example diagram illustrating the correspondence between tags and storage space provided in an embodiment of this application;

[0025] Figure 6 This is a flowchart of a message processing method provided in an embodiment of this application. Detailed Implementation

[0026] The terms "first," "second," and "third," etc., used in this application specification and claims are used to distinguish different objects, not to define a specific order.

[0027] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0028] To ensure clarity and conciseness in the description of the following embodiments, a brief introduction to the related technologies is given first:

[0029] According to the definition of the Network Processors Conference, a network processor is a programmable device used to perform various specific tasks in the field of communications. Examples include packet processing, protocol analysis, route lookup, voice / data aggregation, firewalls, and Quality of Service (QoS).

[0030] In existing technologies, to ensure the hit rate of the network processor in acquiring forwarding processing instructions, all forwarding processing instructions related to the forwarding processing operation are stored in multiple independent instruction memories associated with the network processor. Each instruction memory stores the same forwarding processing instructions. Each processor is connected to one instruction memory. Understandably, one processor can be connected to one instruction memory, or two processors can be connected to the same instruction memory. For example, with Atom processors, every two Atom processors can be connected to the same instruction memory, and every two Atom processors use the same instruction memory to store all forwarding processing instructions related to forwarding processing.

[0031] Example, Figure 1 An example diagram illustrating the composition of a network processor provided for the prior art. For example... Figure 1 As shown, the network processor includes N processors 101, N instruction memories 102, and N instruction branch lookup engines 103. Each processor 101 is connected to one instruction memory 102 and one instruction branch lookup engine 103. Each instruction memory 102 stores all forwarding processing instructions related to forwarding processing. N is an integer greater than or equal to 2.

[0032] Processor 101 is the control center of the network processor. It can be a single processor or a collective term for multiple processing elements. For example, processor 101 can be a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of this application, such as one or more digital signal processors (DSPs), or one or more field-programmable gate arrays (FPGAs).

[0033] The processor 101 can perform various functions of the network processor by running or executing software programs stored in memory 104 and calling forwarding processing instructions stored in instruction memory 102.

[0034] In a specific implementation, as one example, the processor 101 may include one or more CPUs, for example... Figure 1 CPU0 and CPU1 are shown in the diagram.

[0035] In a practical implementation, each of these processors can be a single-core processor (SCPU) or a multi-core processor (Multi-CPU). Here, "processor" can refer to one or more devices, circuits, and / or processing cores used to process data (e.g., computer program instructions).

[0036] Instruction memory 102 may be read-only memory (ROM) or other types of static storage devices capable of storing static information and instructions. Memory 104 may be other memory included in the network processor that differs from instruction memory 102. For example, it may be cache, random access memory (RAM), or other types of dynamic storage devices capable of storing information and instructions. Of course, the aforementioned memories may also be electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed discs, laser discs, optical discs, digital universal discs, Blu-ray discs, etc.), magnetic disk storage media, or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures that can be accessed by a computer, but is not limited thereto.

[0037] Instruction memory 102 and memory 104 can exist independently and are connected to processor 101 via communication bus 105. Alternatively, instruction memory 102 and memory 104 can be integrated with processor 101. Communication bus 105 can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. This bus can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 1 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0038] The branch engine ternary content addressable memory (BETCAM) 103 stores the mapping between query conditions and the starting addresses of the corresponding forwarding instructions. One query condition corresponds to one forwarding operation. BETCAM is a tri-state content addressable memory primarily used for fast lookup of Access Control Lists (ACLs), routing table entries, etc. The branch engine 103 can also be connected to the processor 101 via the communication bus 105.

[0039] Optionally, the network processor may also include a communication interface 106, such as an input / output interface, for communicating with other chips in the network device where the network processor resides.

[0040] Figure 1 The network processor architecture shown does not constitute a limitation on the network processor. In practical applications, it may include more or fewer components than shown, or combine certain components, or arrange the components differently. For example, an arithmetic and logic unit (ALU). An arithmetic logic unit is a combinational logic circuit that can implement multiple sets of arithmetic and logical operations.

[0041] In summary, each instruction memory and each instruction branch lookup engine are essentially independent entities. Each processor, along with its associated instruction memory and instruction branch lookup engine, can independently process a single packet. Because network processors may need to perform multiple forwarding operations on a packet during forwarding, and these operations are processed serially by a single processor, and the processor needs to retrieve the forwarding instructions from the instruction memory based on the start instruction, the processing time for network processors is relatively long, resulting in significant forwarding latency. Furthermore, the large size of network processors leads to higher power consumption and cost. Therefore, reducing the packet processing time, size, power consumption, and cost of network processors is a pressing issue that needs to be addressed.

[0042] To address the aforementioned problems, this application provides a network processor comprising N processors, an instruction memory, and an instruction branch lookup engine. Each of the N processors is connected to both the instruction memory and the instruction branch lookup engine, where N is an integer greater than or equal to 2. The processors determine query conditions based on packet forwarding operations; the instruction branch lookup engine retrieves an associated data index based on the query conditions; the processors also retrieve forwarding instructions from the instruction memory based on the associated data index; and the processors further perform forwarding operations on packets based on the forwarding instructions. The associated data index indicates the storage address of the forwarding instructions corresponding to the forwarding operations. The network processor provided in this application determines the storage address of the forwarding instructions based on the query conditions and the correspondence between the query conditions, the associated data index, and the storage address of the forwarding instructions, and retrieves the forwarding instructions required for packet processing. This effectively reduces the processing time of the network processor when processing packets and the latency of forwarding packets, avoiding the problem of long forwarding latency caused by searching and retrieving forwarding instructions from the instruction memory based on their starting address. In addition, by reducing the number of instruction memories and instruction branch lookup engines included in the network processor, the size, power consumption, and cost of the network processor can be reduced.

[0043] It should be noted that in this application, the packets processed by the network processor are preprocessed packets. The preprocessing may include parsing the packet header, extracting packet type, priority, and other information, and then transmitting the preprocessed packet to the network processor. For convenience, the packets mentioned below refer to preprocessed packets. Furthermore, the forwarding processing operations described in the embodiments of this application may refer to packet processing, protocol analysis, route lookup, voice / data aggregation, firewall, quality of service, etc.

[0044] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0045] Figure 2 This is an example diagram illustrating the composition of a network processor provided in an embodiment of this application. For example... Figure 2 As shown, the network processor includes N processors 201, an instruction memory 202, and an instruction branch lookup engine 203. Each of the N processors 201 is connected to both the instruction memory 202 and the instruction branch lookup engine 203. N is an integer greater than or equal to 2. The N processors 201 can be numbered from 0 to n-1. Therefore, by reducing the number of instruction memories and instruction branch lookup engines included in the network processor, the N processors can share one instruction memory and one instruction branch lookup engine, effectively reducing the size, power consumption, and cost of the network processor.

[0046] Typically, a network processor can execute multiple forwarding operations when forwarding packets. In this embodiment, the network processor can adopt a multi-processor pipeline architecture, where multiple forwarding operations for a single packet can be completed by multiple processors within the network processor. For example, five forwarding operations for a single packet can be completed by five processors within the network processor, with one processor handling one forwarding operation. This effectively reduces packet forwarding latency. For applications with low to medium traffic volumes and where low-cost chips are a requirement, the network processor provided in this embodiment can be used.

[0047] It should be noted that the process of fetching forwarding instructions from the instruction memory is the same for each processor; only the specific forwarding instructions fetched differ. The following explanation uses the first forwarding operation as an example to illustrate the specific roles of the processor, instruction memory, and instruction branch lookup engine.

[0048] Processor 201 determines a first query condition based on a first forwarding processing operation on a packet. For example, before the network processor operates, the correspondence between forwarding processing operations and query conditions can be pre-stored in the processor's memory. After acquiring a packet, the processor can determine the first query condition corresponding to the first forwarding processing operation based on the first forwarding processing operation and the stored correspondence between forwarding processing operations and query conditions. For example, the first forwarding processing operation is a route lookup, and the first query condition is the query condition corresponding to the route lookup. After acquiring the first query condition, the processor can transmit the first query condition to the instruction branch lookup engine.

[0049] The instruction branch lookup engine 203 is used to obtain a first associated data index based on a first query condition. The first associated data index indicates the storage address of a first forwarding processing instruction corresponding to a first forwarding processing operation. In the following text, the first forwarding processing instruction may refer to the forwarding processing instruction corresponding to the first forwarding processing operation. For example, before the network processor operates, the instruction branch lookup engine may store the correspondence between query conditions and associated data indexes. After obtaining the first query condition, the instruction branch lookup engine can obtain the first associated data index based on the first query condition and the correspondence between the query condition and the associated data index. After obtaining the first associated data index, the instruction branch lookup engine can transmit the first associated data index to the processor.

[0050] Processor 201 is also configured to retrieve a first forwarding processing instruction from instruction memory 202 based on a first associated data index.

[0051] In one possible implementation, such as Figure 3As shown, the instruction memory 202 includes N instruction buffer memory modules 2021 and one instruction storage module 2022. Each of the N instruction buffer memory modules 2021 is connected to a processor 201, and each of the N instruction buffer memory modules 2021 is connected to the instruction storage module 2022. The N instruction buffer memory modules 2021 can be numbered from 0 to n-1. The instruction buffer memory modules can be dynamic storage devices, such as RAM. The instruction storage modules can also be static storage devices, such as ROM. The instruction buffer memory modules are used to store frequently used forwarding instructions. The instruction storage module is used to store all forwarding instructions related to forwarding processing.

[0052] Specifically, the processor may include a controller, which is configured to determine the storage address of a first forwarding processing instruction in the instruction buffer memory module based on a first associated data index. The controller is also configured to retrieve the first forwarding processing instruction from the instruction buffer memory module based on the storage address of the first forwarding processing instruction.

[0053] For example, a tag table and a cached instruction storage table can be pre-stored. The tag table is used to store tags. The tag table can include X*Y tag storage units. One tag storage unit stores one tag. Tags can be managed based on an associated data index. The cached instruction storage table is used to cache forwarding processing instructions related to forwarding processing operations. The tag table and the cached instruction storage table can be associated with each other through tags. Therefore, tags can be determined based on the associated data index, and then forwarding processing instructions related to forwarding processing operations can be retrieved based on the tags. The tags indicate the storage address of the forwarding processing instructions.

[0054] In Option 1, a tag can correspond to an instruction line address in the cached instruction storage table. The storage space corresponding to this instruction line address is used to store the forwarding processing instruction corresponding to a forwarding processing operation. If the cached instruction storage table includes Z instruction line addresses, X*Y = Z, indicating that the number of tags in the tag table is the same as the number of instruction lines in the cached instruction storage table, and there is a one-to-one correspondence between tags and instruction line addresses.

[0055] It should be noted that the correspondence between the associated data index and the tag, as well as the correspondence between the tag and the instruction line address, can be pre-configured. Once the processor obtains the associated data index, it can determine the instruction line address based on the pre-set correspondence between the associated data index and the tag, and the correspondence between the tag and the instruction line address. For example, the processor can first determine the first tag based on the first associated data index, then use the correspondence between the tag and the instruction line address to determine the first instruction line address based on the first tag; and then retrieve the first forwarding processing instruction from the memory space corresponding to the first instruction line address.

[0056] Additionally, the X rows in the tag table can be understood as the depth of the buckets, with each depth represented by a bucket identifier (bucket_id). The Y column in the tag table can be understood as the number of tag storage units (ways or slots) corresponding to each depth. For example, ... Figure 4 As shown, assuming the depth of the bucket can be 32, the bucket identifier number can be from 0 to 31. The number of tag storage units corresponding to each depth can be 8, and the storage unit number can be from 0 to 7. The bucket identifier can be determined according to the 0th to 4th bits of the associated data index, that is, bucket_id = ad_index[4:0], and the tag can be determined according to the 5th to 10th bits of the associated data index, that is, tag = ad_index[10:5].

[0057] The network processor provided in this application determines the storage address of the forwarding processing instruction based on the query conditions and the correspondence between the query conditions, the associated data index and the storage address of the forwarding processing instruction, and obtains the forwarding processing instruction required for processing the packet. This can effectively reduce the time taken by the network processor to process the packet and the latency of forwarding the packet, and avoid the problem of long latency in forwarding the packet caused by searching and obtaining the forwarding processing instruction in the instruction memory based on the starting address of the forwarding processing instruction.

[0058] In Scheme 1, the storage space corresponding to the storage address of the forwarding processing instruction refers to the storage space corresponding to a buffered instruction line in the instruction buffer storage module. However, each storage unit may store a small number of forwarding processing instructions, leaving some capacity remaining. To improve storage space utilization, the storage space corresponding to the storage address of the forwarding processing instruction can refer to the storage space required to store the first forwarding processing instruction. Each instruction line in the cached instruction storage table can be divided into at least two storage units, each capable of storing the same number of forwarding processing instructions. For example... Figure 4 As shown. An instruction line consists of 4 storage units, each of which can store 4 forwarding instructions, and the 4 storage units can store 16 forwarding instructions.

[0059] Option 2: One tag can correspond to the storage space required for forwarding processing instructions stored in the cached instruction storage table. The storage space required for forwarding processing instructions can be a portion of the storage space of an instruction line, or it can be the entire storage space of an instruction line. Storage space is measured in units of storage units comprised of the instruction line. For example, ... Figure 5As shown, tag i can correspond to the first storage unit of the instruction line, and tag j can correspond to the first to third storage units of the instruction line. Other storage units can correspond to other tags. The number of tags that each instruction line can correspond to is the same as the number of storage units included in the instruction line. Thus, the utilization rate of storage space in the instruction buffer storage module can be effectively improved.

[0060] Optionally, if the processor fails to retrieve the forwarding instruction from the instruction buffer memory module based on the storage address of the forwarding instruction, the processor may retrieve the forwarding instruction from the instruction memory module.

[0061] For example, the controller retrieves the first forwarding instruction from all forwarding instructions related to forwarding processing stored in the instruction storage module, based on the starting address of the first forwarding instruction. The starting address of the first forwarding instruction is obtained by the processor from the instruction branch lookup engine based on a first query condition.

[0062] The instruction buffer storage module is also used to store the first forwarding processing instruction according to its storage address. The storage address of the first forwarding processing instruction is the address in the instruction buffer storage module determined according to the first associated data index. This allows the processor to directly retrieve the first forwarding processing instruction from the instruction buffer storage module when needed again, reducing the time the network processor takes to process packets and the latency of forwarding packets.

[0063] The processor is also used to perform forwarding operations on packets according to forwarding instructions.

[0064] In this embodiment, when each of the N processors forwards a packet, it can first retrieve the forwarding instruction from the instruction buffer storage module. If the forwarding instruction is not retrieved from the instruction buffer storage module, it then retrieves the forwarding instruction from the instruction storage module. For details, please refer to the above description; further elaboration is omitted here.

[0065] Figure 2 The network processor architecture shown does not constitute a limitation on the network processor. In practical applications, it may include more or fewer components than shown, or combine certain components, or arrange the components differently. For example, an arithmetic and logic unit (ALU). An arithmetic logic unit is a combinational logic circuit that can implement multiple sets of arithmetic and logical operations.

[0066] A network processor typically consists of several microcode processors and several hardware coprocessors. Multiple microcode processors process data in parallel within the network processor, with the processing flow controlled by pre-programmed microcode. For complex standard operations (such as memory operations, routing table lookup algorithms, QoS congestion control algorithms, and traffic scheduling algorithms), hardware coprocessors are used to further improve processing performance, thus achieving an organic combination of service flexibility and high performance.

[0067] Figure 6 This is a flowchart illustrating a message processing method provided in an embodiment of this application. This method can be applied to the above-mentioned... Figure 2 The network processor shown. The method may include the following steps.

[0068] S601, The processor determines the query conditions based on the message forwarding processing operation.

[0069] S602, The instruction branch search engine retrieves the related data index based on the query conditions.

[0070] S603: The processor retrieves the forwarding processing instruction from the instruction memory based on the associated data index.

[0071] like Figure 3 As shown, the instruction memory includes N instruction buffer memory modules and one instruction storage module. Each of the N instruction buffer memory modules is connected to a processor, and the N instruction buffer memory modules are respectively connected to the instruction storage module. The processor may include a controller. The processor retrieves forwarding processing instructions from the instruction memory according to the associated data index, specifically including:

[0072] The controller determines the storage address of the forwarding processing instruction in the instruction buffer storage module based on the associated data index; then, the controller retrieves the forwarding processing instruction from the instruction buffer storage module based on the storage address of the forwarding processing instruction.

[0073] The storage space corresponding to the storage address of the forwarding processing instruction can be the storage space corresponding to a buffered instruction line in the instruction buffer storage module. Alternatively, the storage space corresponding to the storage address of the forwarding processing instruction can be the storage space required to store the forwarding processing instruction.

[0074] S604. The processor performs forwarding processing operations on the message according to the forwarding processing instructions.

[0075] If the processor fails to retrieve the forwarding instruction from the instruction buffer memory module based on the memory address of the forwarding instruction, the method further includes:

[0076] The controller retrieves the forwarding instruction from the instruction storage module based on the starting address of the forwarding instruction. The starting address of the forwarding instruction is obtained by the processor from the instruction branch lookup engine based on the query conditions.

[0077] The instruction buffer storage module stores forwarding instructions according to the storage address of the forwarding instructions in the instruction buffer storage module corresponding to the associated data index.

[0078] For details, please refer to the description of the above embodiments; the embodiments of this application will not be repeated here.

[0079] The network processor provided in this application determines the storage address of the forwarding processing instruction based on query conditions and the correspondence between the query conditions, the associated data index, and the storage address of the forwarding processing instruction. It then retrieves the forwarding processing instruction required for processing the packet, effectively reducing the processing time and forwarding latency of the network processor. This avoids the problem of long forwarding latency caused by searching for and retrieving the forwarding processing instruction from the instruction memory based on its starting address. Furthermore, by reducing the number of instruction memories and instruction branch lookup engines included in the network processor, the size, power consumption, and cost of the network processor are reduced.

[0080] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A network processor, comprising: The method comprises the following steps: An N-processor, an instruction memory and an instruction branch lookup engine, each of the N processors is connected with the instruction memory and the instruction branch lookup engine respectively, N is an integer greater than or equal to 2, the instruction branch lookup engine stores the correspondence between the query condition and the associated data index, wherein, The processor is used for determining the query condition according to the forwarding processing operation of the packet, and the query condition is the query condition of the forwarding processing operation; The instruction branch lookup engine is used for obtaining the associated data index according to the query condition and the correspondence between the query condition and the associated data index, and the associated data index is used for indicating the storage address of the forwarding processing instruction corresponding to the forwarding processing operation; The processor is further used for obtaining the forwarding processing instruction from the instruction memory according to the associated data index; The processor is further used for performing the forwarding processing operation on the packet according to the forwarding processing instruction.

2. The network processor of claim 1, wherein, The instruction memory comprises N instruction buffer storage modules and an instruction storage module, each of the N instruction buffer storage modules is connected with a processor, and the N instruction buffer storage modules are connected with the instruction storage module respectively.

3. The network processor of claim 2 wherein, The processor comprises a controller, The controller is used for determining the storage address of the forwarding processing instruction in the instruction buffer storage module according to the associated data index; The controller is further used for obtaining the forwarding processing instruction from the instruction buffer storage module according to the storage address of the forwarding processing instruction.

4. The network processor of claim 3 wherein, The storage space corresponding to the storage address of the forwarding processing instruction is the storage space corresponding to one buffer instruction line in the instruction buffer storage module.

5. The network processor of claim 3 wherein, The storage space corresponding to the storage address of the forwarding processing instruction is the storage space required for storing the forwarding processing instruction.

6. The network processor of claim 2 wherein, In the case that the processor does not obtain the forwarding processing instruction from the instruction buffer storage module according to the storage address of the forwarding processing instruction, The controller is used for obtaining the forwarding processing instruction from the instruction storage module according to the starting address of the forwarding processing instruction, and the starting address of the forwarding processing instruction is obtained by the processor from the instruction branch lookup engine according to the query condition; The instruction buffer storage module is further used for storing the forwarding processing instruction according to the storage address of the forwarding processing instruction, and the storage address of the forwarding processing instruction is the address corresponding to the associated data index in the instruction buffer storage module.

7. A method of processing a packet, the method comprising: The method is applied to a network processor, the network processor comprises N processors, an instruction memory and an instruction branch lookup engine, each of the N processors is connected with the instruction memory and the instruction branch lookup engine respectively, N is an integer greater than or equal to 2, the instruction branch lookup engine stores the correspondence between the query condition and the associated data index, and the method comprises the following steps: The processor determines the query condition according to the forwarding processing operation of the packet, and the query condition is the query condition of the forwarding processing operation; The instruction branch lookup engine obtains the associated data index according to the query condition and a correspondence between the query condition and the associated data index, and the associated data index is used to indicate a storage address of a forwarding processing instruction corresponding to the forwarding processing operation; The processor obtains the forwarding processing instruction from the instruction memory according to the associated data index; The processor performs the forwarding processing operation on the packet according to the forwarding processing instruction.

8. The method of claim 7, wherein, The instruction memory comprises N instruction buffer storage modules and an instruction storage module, each of the N instruction buffer storage modules is connected with one of the processors, the N instruction buffer storage modules are respectively connected with the instruction storage module, the processor comprises a controller, and the processor obtains the forwarding processing instruction from the instruction memory according to the associated data index, which comprises: The controller determines the storage address of the forwarding processing instruction in the instruction buffer storage module according to the associated data index; The controller obtains the forwarding processing instruction from the instruction buffer storage module according to the storage address of the forwarding processing instruction.

9. The method of claim 8, wherein, The storage space corresponding to the storage address of the forwarding processing instruction is the storage space corresponding to one buffer instruction line in the instruction buffer storage module.

10. The method of claim 8, wherein, The storage space corresponding to the storage address of the forwarding processing instruction is the storage space required for storing the forwarding processing instruction.

11. The method of claim 8, wherein, The instruction memory comprises N instruction buffer storage modules and an instruction storage module, each of the N instruction buffer storage modules is connected with one of the processors, the N instruction buffer storage modules are respectively connected with the instruction storage module, the processor comprises a controller, and in the case that the processor does not obtain the forwarding processing instruction from the instruction buffer storage module according to the storage address of the forwarding processing instruction, the method further comprises: The controller obtains the forwarding processing instruction from the instruction storage module according to the start address of the forwarding processing instruction, and the start address of the forwarding processing instruction is obtained by the processor from the instruction branch lookup engine according to the query condition; The instruction buffer storage module stores the forwarding processing instruction according to the storage address of the forwarding processing instruction in the instruction buffer storage module corresponding to the associated data index.

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