Instruction processing method and device, electronic equipment, storage medium and chip

Abstract

The invention provides an instruction processing method and device, electronic equipment, a storage medium and a chip, and relates to the technical field of computers. The method comprises the following steps: acquiring execution time information of a plurality of to-be-processed instruction sequences and position information of the plurality of to-be-processed instruction sequences; according to the execution time information and the position information, determining an execution sequence of the plurality of to-be-processed instruction sequences; and executing the plurality of to-be-processed instruction sequences according to the execution sequence. The execution time information reflects the time characteristic, the position reflects the space characteristic, the time characteristic and the space characteristic are considered at the same time, instruction execution better meets the actual requirement, and the instruction execution efficiency is improved.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to an instruction processing method, apparatus, electronic device, storage medium, and chip. Background Technology

[0002] During operation, the terminal processing chip generates a large number of instructions. In order to ensure the normal operation of the chip, the instructions need to be processed.

[0003] In instruction processing technologies, instructions are typically executed based on their execution frequency. However, since instruction execution is affected by many factors, relying solely on execution frequency is too simplistic and leads to low execution efficiency. Summary of the Invention

[0004] This disclosure provides an instruction processing method, apparatus, electronic device, storage medium, and chip to solve problems in the related art.

[0005] A first aspect of this disclosure provides an instruction processing method, the method comprising: Obtain the execution time information and position information of multiple instruction sequences to be processed; The execution order of the plurality of instructions to be processed is determined based on the execution time information and the location information. The plurality of pending instruction sequences are executed in the order described.

[0006] In some embodiments, determining the execution order of the plurality of pending instruction sequences based on the execution time information and the location information includes: Based on the execution time information and the location information, determine the correlation strength between each pair of instruction sequences to be processed in the plurality of instruction sequences to be processed; The execution order is determined based on the association strength.

[0007] In some embodiments, determining the correlation strength between any two pairs of instruction sequences to be processed in the plurality of instruction sequences to be processed based on the execution time information and the location information includes: Based on the execution time information, determine the jump frequency between any two pairs of instruction sequences to be processed in the plurality of instruction sequences to be processed; Based on the location information, determine the location information difference between each pair of instruction sequences to be processed in the plurality of instruction sequences to be processed; The association strength is calculated based on the jump frequency and the difference in location information.

[0008] In some embodiments, calculating the association strength based on the jump frequency and the location information difference includes: Obtain the first weight of the jump frequency and the second weight of the position information difference; The association strength is calculated based on the first weight, the second weight, the jump frequency, and the difference in location information.

[0009] In some embodiments, the method further includes: Based on the execution time information, determine the type of the plurality of instruction sequences to be processed; The execution priority of the plurality of instruction sequences to be processed is determined according to their types. The plurality of pending instruction sequences are executed according to the execution priority.

[0010] In some embodiments, determining the type of the plurality of pending instruction sequences based on the execution time information includes: The type of the instruction sequence to be processed with an execution frequency greater than a preset first threshold in the execution time information is determined as the first type, and / or the instruction sequence to be processed with a jump frequency greater than a preset second threshold in the execution time information is determined as the first type; The type of the instruction sequence to be processed with an execution frequency less than or equal to the preset first threshold is determined as the second type, and / or the instruction sequence to be processed with a jump frequency less than or equal to the preset second threshold is determined as the second type.

[0011] In some embodiments, determining the execution priority of the plurality of instruction sequences to be processed based on their types includes: The first type is determined as the first execution priority; The second type is determined as the second execution priority; The execution priority includes a first execution priority and a second execution priority, wherein the first execution priority is greater than the second execution priority.

[0012] In some embodiments, determining the execution order based on the association strength includes: Based on the correlation strength, generate the correlation strength matrix of the plurality of instruction sequences to be processed; The execution order of the plurality of instruction sequences to be processed is determined based on the correlation strength matrix; the execution order is positively correlated with the correlation strength.

[0013] In some embodiments, executing the plurality of pending instruction sequences according to the execution order includes: Obtain the cache space of the target cache line corresponding to the plurality of instruction sequences to be processed, and obtain the data volume of the plurality of instruction sequences to be processed; The multiple sequences of instructions to be processed are cached in the target cache line and executed in descending order of the execution order, until the target cache line can no longer cache the next sequence of instructions to be processed; If the target cache line cannot cache the next instruction sequence to be processed, and there is remaining cache space in the target cache line, the remaining cache space is filled with an empty instruction sequence.

[0014] A second aspect of this disclosure provides an instruction processing apparatus, comprising: The acquisition unit is used to acquire the execution time information and the position information of the multiple instruction sequences to be processed; The determining unit is configured to determine the execution order of the plurality of instructions to be processed based on the execution time information and the position information; An execution unit is configured to execute the plurality of pending instruction sequences in the order of execution.

[0015] In some embodiments, the determining unit includes: The first determining module is used to determine the correlation strength between any two pairs of instruction sequences to be processed in the plurality of instruction sequences to be processed, based on the execution time information and the location information. The first determining module is further configured to determine the execution order based on the association strength.

[0016] In some embodiments, the first determining module is further configured to: Based on the execution time information, determine the jump frequency between any two pairs of instruction sequences to be processed in the plurality of instruction sequences to be processed; Based on the location information, determine the location information difference between each pair of instruction sequences to be processed in the plurality of instruction sequences to be processed; The association strength is calculated based on the jump frequency and the difference in location information.

[0017] In some embodiments, the first determining module is further configured to: Obtain the first weight of the jump frequency and the second weight of the position information difference; The association strength is calculated based on the first weight, the second weight, the jump frequency, and the difference in location information.

[0018] In some embodiments, the apparatus further includes: The determining unit is further configured to determine the type of the plurality of instruction sequences to be processed based on the execution time information; The determining unit is further configured to determine the execution priority of the plurality of instruction sequences to be processed based on their types; The execution unit is further configured to execute the plurality of pending instruction sequences according to the execution priority.

[0019] In some embodiments, the determining unit includes: The second determining module is used to determine the type of the instruction sequence to be processed with an execution frequency greater than a preset first threshold in the execution time information as a first type, and / or to determine the instruction sequence to be processed with a jump frequency greater than a preset second threshold in the execution time information as the first type; The second determining module is further configured to determine the type of the instruction sequence to be processed with an execution frequency less than or equal to the preset first threshold as a second type, and / or to determine the instruction sequence to be processed with a jump frequency less than or equal to the preset second threshold as the second type.

[0020] In some embodiments, the determining unit is further configured to: The first type is determined as the first execution priority; The second type is determined as the second execution priority; The execution priority includes a first execution priority and a second execution priority, wherein the first execution priority is greater than the second execution priority.

[0021] In some embodiments, the first determining module is further configured to: Based on the correlation strength, generate the correlation strength matrix of the plurality of instruction sequences to be processed; The execution order of the plurality of instruction sequences to be processed is determined based on the correlation strength matrix; the execution order is positively correlated with the correlation strength.

[0022] In some embodiments, the execution unit is further configured to: Obtain the cache space of the target cache line corresponding to the plurality of instruction sequences to be processed, and obtain the data volume of the plurality of instruction sequences to be processed; The multiple sequences of instructions to be processed are cached in the target cache line and executed in descending order of the execution order, until the target cache line can no longer cache the next sequence of instructions to be processed; If the target cache line cannot cache the next instruction sequence to be processed, and there is remaining cache space in the target cache line, the remaining cache space is filled with an empty instruction sequence.

[0023] A third aspect of this disclosure provides an electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the methods described in the first aspect of this disclosure.

[0024] A fourth aspect of this disclosure provides a non-transitory computer-readable storage medium that, when instructions in the storage medium are executed by a processor of a mobile terminal, enables the mobile terminal to perform the methods described in the first aspect of this disclosure.

[0025] According to a fifth aspect of this disclosure, a computer program product is provided, including a computer program that, when executed by a processor, implements the methods described in the embodiments of the first aspect of this disclosure.

[0026] In summary, the instruction processing method proposed in this disclosure includes obtaining execution time information and position information of multiple instruction sequences to be processed; determining the execution order of the multiple instruction sequences to be processed based on the execution time information and the position information; and executing the multiple instruction sequences to be processed according to the execution order. The execution time information reflects temporal characteristics, and the position reflects spatial characteristics. Considering both time and spatial characteristics makes instruction execution more aligned with actual needs, thus improving instruction execution efficiency.

[0027] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0028] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure, and are not intended to unduly limit this disclosure.

[0029] Figure 1 A flowchart of an instruction processing method provided in an embodiment of this disclosure; Figure 2 A flowchart illustrating another instruction processing method provided in an embodiment of this disclosure; Figure 3 A flowchart of an instruction processing method provided in an embodiment of this disclosure; Figure 4 This is a schematic diagram of the structure of an instruction processing device provided in an embodiment of the present disclosure; Figure 5 This is a schematic diagram of another instruction processing apparatus provided in an embodiment of the present disclosure; Figure 6This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present disclosure; Figure 7 This is a schematic diagram of the structure of a chip provided in an embodiment of the present disclosure. Detailed Implementation

[0030] Some embodiments of this disclosure will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. Various changes, modifications, and equivalents of the methods, apparatus, and / or systems described herein will become apparent upon understanding this disclosure. For example, the order of operations described herein is merely illustrative and is not limited to those orders set forth herein, but can be changed as will become apparent upon understanding this disclosure, except for operations that must be performed in a particular order. Furthermore, for clarity and brevity, descriptions of features known in the art may be omitted.

[0031] The embodiments described in the following examples of this disclosure are not representative of all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0032] During operation, the terminal processing chip generates a large number of instructions. In order to ensure the normal operation of the chip, the instructions need to be processed.

[0033] In instruction processing technologies, instructions are typically executed based on their execution frequency. However, since instruction execution is affected by many factors, relying solely on execution frequency is too simplistic and leads to low execution efficiency.

[0034] Therefore, to address the problems existing in related technologies, this disclosure proposes an instruction processing method. This method includes acquiring execution time information and position information of multiple instruction sequences to be processed; determining the execution order of the multiple instruction sequences to be processed based on the execution time information and the position information; and executing the multiple instruction sequences to be processed according to the execution order. The execution time information reflects temporal characteristics, and the position reflects spatial characteristics. Considering both time and spatial characteristics makes instruction execution more closely aligned with actual needs, thereby improving instruction execution efficiency.

[0035] This disclosure is not exhaustive, but merely illustrative of some embodiments, and is not intended to limit the scope of protection of this disclosure. Unless otherwise specified, each step in a particular embodiment can be implemented as an independent embodiment, and the steps can be arbitrarily combined. For example, a solution after removing some steps in a particular embodiment can also be implemented as an independent embodiment, and the order of the steps in a particular embodiment can be arbitrarily interchanged. Furthermore, the optional implementation methods in a particular embodiment can be arbitrarily combined; moreover, the embodiments can be arbitrarily combined, for example, some or all steps of different embodiments can be arbitrarily combined, and a particular embodiment can be arbitrarily combined with the optional implementation methods of other embodiments. In each of the disclosed embodiments, unless otherwise specified or in case of logical conflict, the terminology and / or descriptions of the embodiments are consistent and can be referenced by each other. Technical features in different embodiments can be combined to form new embodiments based on their inherent logical relationships. The terminology used in the embodiments of this disclosure is for the purpose of describing particular embodiments only and is not intended to limit the scope of this disclosure. In this disclosure, unless otherwise stated, elements expressed in the singular form, such as "a," "an," "the," "the," "the," "the," "the," "the," "this," etc., can mean "one and only one," or "one or more," "at least one," etc. For example, when using articles such as "a," "an," "the," etc. in translation, the noun following the article can be understood as either a singular or a plural expression. In some embodiments, the terms “in response to…”, “in response to determining…”, “in the case of…”, “when…”, “if…”, “if…”, etc., can be used interchangeably. In some embodiments, the terms “greater than,” “greater than or equal to,” “not less than,” “more than,” “more than or equal to,” “not less than,” “higher than,” “higher than or equal to,” “not lower than,” and “above” can be used interchangeably, as can the terms “less than,” “less than or equal to,” “not greater than,” “less than,” “less than or equal to,” “not more than,” “lower than,” “lower than or equal to,” “not higher than,” and “below”. The prefixes such as "first" and "second" in the embodiments of this disclosure are only for distinguishing different descriptive objects and do not constitute restrictions on the position, order, priority, number or content of the descriptive objects. For the description of the descriptive objects, please refer to the description in the claims or the context of the embodiments. The use of prefixes should not constitute unnecessary restrictions.

[0036] In the embodiments disclosed herein, "multiple" refers to two or more. In the embodiments disclosed herein, terms such as “import”, “input”, and “read in” can be used interchangeably.

[0037] Figure 1 This is a flowchart illustrating an instruction processing method provided in an embodiment of this disclosure. This method can be applied to application scenarios such as smart terminals, and can be executed by a terminal with integrated instruction processing capabilities or an instruction processor within a terminal, or by other devices suitable for instruction processing; this disclosure does not limit its application. Figure 1 As shown, the instruction processing method includes steps S101-S103.

[0038] Step S101: Obtain the execution time information and position information of the multiple instruction sequences to be processed.

[0039] In the embodiments of this disclosure, the sequence of instructions to be processed is explained. This sequence of instructions is executed via a terminal, which refers to an electronic device with data processing capabilities, including but not limited to smartphones, tablets, desktop computers, laptops, smartwatches, in-vehicle terminals, and servers. These devices run operating systems and various applications, generating a large number of instruction sequences. The sequence of instructions to be processed refers to a set of instructions that needs to be optimized, scheduled, or loaded. This sequence can be a basic block, a function, a method, a thread's code segment, or any logically related group of instructions.

[0040] In the embodiments of this disclosure, the execution time information is explained as follows: Execution time information refers to data reflecting the behavioral characteristics of the instruction sequence in the time dimension during its execution, including but not limited to: the execution frequency of the instruction sequence within a time window: the number of times the instruction sequence is called or executed within a specific time window; the jump frequency between pairs of instruction sequences within a time window: the number of times two instruction sequences jump to each other within a specific time window; the execution duration of the instruction sequence: the average or total time consumed by the instruction sequence in a single execution or multiple executions; and the timestamp information of the instruction sequence: the specific time point at which the instruction sequence is executed, used to analyze temporal locality.

[0041] In the embodiments of this disclosure, the location information is explained as the static or dynamic address information of the instruction sequence to be processed in the storage space (such as Dynamic Random Access Memory (DRAM) / cache, etc.), including but not limited to the instruction address: the start address and / or end address of the instruction sequence in physical memory or virtual memory; storage medium location: the segment of the instruction sequence in the binary file after compilation, such as the code segment, the specific function library, and the physical sector information on the storage device.

[0042] In the embodiments of this disclosure, obtaining the execution time information and location information of multiple pending instruction sequences can be achieved in the following way: When the application or system process is running, the generation and execution status of the instruction sequences are monitored in real time. When an instruction sequence enters the pending state (e.g., marked as pending execution by the system scheduler), an information (execution time information and location information) recording process is triggered; simultaneously, for previously executed instruction sequences, the instruction monitoring module periodically (e.g., every 30 seconds) extracts their historical execution data from the terminal's log system to ensure the integrity of the information.

[0043] In the embodiments of this disclosure, an example of obtaining the execution time information of a sequence of instructions to be processed is provided. The timestamp is obtained through the terminal's system clock: when the sequence of instructions to be processed is first generated, the time it enters the processing queue is recorded (as an initial timestamp); if the instruction sequence has historical execution records, the start and end times of each execution are read from the terminal's execution log, and the execution duration is calculated (e.g., an execution starts at 10:00:01 and ends at 10:00:03, with an execution duration of 2 seconds). For the execution frequency in the execution time information, the execution frequency is obtained by statistically analyzing the number of times the instruction sequence has been executed within a preset duration (e.g., 5 minutes) (executions 8 times), dividing the number of executions by the preset duration. For the jump time interval in the execution time information, the time difference between the end of one instruction sequence and the start of the next is recorded by tracking the execution connection relationship of different instruction sequences, and this time difference is determined as the jump time interval (e.g., if instruction sequence A ends at 10:00:05 and instruction sequence B starts at 10:00:06, the jump time interval between them is 1 second).

[0044] In an embodiment of this disclosure, an example is provided for obtaining the position information of the execution sequence to be processed. This is achieved by reading the physical address of the instruction sequence to be processed in the terminal storage medium and associating that address with the unique identifier of the instruction sequence. The sequence number of the instruction sequence in the queue to be processed (e.g., the queue contains 20 instruction sequences, and the current sequence is the 7th) is obtained as the position information of the instruction sequence to be processed.

[0045] In the embodiments of this disclosure, the storage of execution time information and location information of the execution sequence to be processed can be achieved in the following manner: the obtained execution time information and location information are associated with the unique identifier of the corresponding instruction sequence to be processed and stored in the terminal's temporary database. By verifying the completeness of the execution time information and location information (e.g., ensuring that each instruction sequence has corresponding execution time information and location information), if any is missing, a second retrieval is triggered (e.g., re-querying the log or storage management module) to avoid information omission.

[0046] The combination of execution time and location information provides detailed data for in-depth analysis of instruction scheduling characteristics, which helps to identify potential scheduling problems.

[0047] Step S102: Determine the execution order of the plurality of instruction sequences to be processed based on the execution time information and the location information.

[0048] In the embodiments of this disclosure, the execution order is explained, which refers to the order in which multiple sequences of instructions to be processed are executed.

[0049] In the embodiments of this disclosure, the execution order of the plurality of instruction sequences to be processed can be determined based on the execution time information and the location information in the following ways: Analyzing the jump frequency of each pair of instruction sequences to be processed: a higher jump frequency indicates a closer logical connection between the two instruction sequences (e.g., a higher probability of consecutive execution); analyzing the difference in location information between each pair of instruction sequences to be processed: a smaller difference in location information indicates a closer proximity in the storage locations of the two instruction sequences (e.g., consecutive or small intervals in storage unit numbers); combining the above two factors to determine the correlation strength: instruction sequences with high jump frequencies and close proximity have higher correlation strength; instruction sequences with low jump frequencies or distant locations have lower correlation strength. The pairwise correlation strength of all instruction sequences to be processed is organized into a correlation strength matrix (e.g., 5 instruction sequences correspond to a 5×5 matrix, where the matrix elements visually reflect the correlation degree between any two sequences); the execution order is determined based on the principle of positive correlation strength: instruction sequences with higher correlation strength are executed first; for a single instruction sequence, it is prioritized to be executed adjacent to other sequences with the highest correlation strength, forming a cluster-like execution order of highly correlated sequences.

[0050] At the same time, by combining execution time information (jump frequency) and location information (storage location relationship), the temporal and spatial correlation of the instruction sequence is comprehensively considered to avoid execution logic disorder caused by a single dimension judgment.

[0051] Step S103: Execute the multiple sequences of instructions to be processed according to the execution order.

[0052] In the embodiments of this disclosure, the execution of the plurality of pending instruction sequences according to the execution order can be achieved in the following manner: obtaining the total cache space of the target cache line; extracting the corresponding data volume from the metadata of each pending instruction sequence; storing the pending instruction sequences into the target cache line in descending order of execution (i.e., the earlier the execution order, the higher the priority); after storing each instruction sequence, calculating the used space of the target cache line in real time, and determining whether the data volume of the next pending instruction sequence is less than or equal to the remaining cache space: if it is satisfied, continuing to store; if it is not satisfied (i.e., the next sequence cannot be completely stored), stopping the storage of new instruction sequences. If the target cache line can no longer store the next pending instruction sequence, but there is still remaining cache space (i.e., used space + next sequence data volume > total cache space, but total cache space > used space); generating an empty instruction sequence and filling it into the remaining cache space until the cache space of the target cache line is completely occupied, and then executing the pending instruction sequences in the target cache line.

[0053] By strictly following the predetermined execution order of the instruction sequence, the overall execution efficiency of the system can be optimized, reducing unnecessary waiting and resource waste.

[0054] In summary, in the embodiments of this disclosure, the instruction processing method proposed in this disclosure includes obtaining execution time information and position information of a plurality of instruction sequences to be processed; determining the execution order of the plurality of instruction sequences to be processed based on the execution time information and the position information; and executing the plurality of instruction sequences to be processed according to the execution order. The execution time information reflects temporal characteristics, and the position reflects spatial characteristics. Considering both time and spatial characteristics makes instruction execution more closely aligned with actual needs, thereby improving instruction execution efficiency.

[0055] As a refinement of step S102, when performing the step of determining the execution order of the plurality of instruction sequences to be processed based on the execution time information and the position information, the following methods can be used, but are not limited to: determining the correlation strength between any two instruction sequences to be processed in the plurality of instruction sequences to be processed based on the execution time information and the position information; and determining the execution order based on the correlation strength.

[0056] In the embodiments of this disclosure, the correlation strength is explained as a numerical metric used to quantitatively evaluate the overall degree of correlation between any two sequences of instructions to be processed. A higher correlation strength indicates that the two instruction sequences are more tightly integrated in terms of logical execution flow and physical storage layout, and therefore should be scheduled for consecutive execution. Correlation strength is a composite metric that integrates temporal dynamic characteristics and spatial static characteristics.

[0057] In embodiments of this disclosure, the execution order can be determined as follows: For each pair of instruction sequences (e.g., sequence X and sequence Y), the jump frequency (i.e., the frequency of X jumping to Y or Y jumping to X) between each pair of instruction sequences is extracted from the execution time information. Simultaneously, the positional information difference (e.g., the absolute difference in memory addresses) between each pair of instruction sequences is calculated from the positional information. The extracted raw jump frequencies and positional differences are mapped to a uniform, comparable numerical range. For example, the highest jump frequency is normalized to a value of one, and others are calculated proportionally; the smallest address difference (representing proximity) is normalized to a value of one, with the value decreasing as the address difference increases. The normalized jump frequency value (reflecting temporal correlation) and the positional proximity value (reflecting spatial correlation) are then fused according to a preset importance ratio to generate the final "association strength" value. For example, if the execution jump behavior is considered more important than physical address proximity, a higher weight can be assigned to the temporal component.

[0058] In the embodiments of this disclosure, the execution order is determined based on the correlation strength in the following manner: All sequences of instructions to be processed are used as rows and columns of a matrix (the sequences in each row and column correspond one-to-one); the correlation strength of each pair of sequences is marked at the corresponding element positions in the matrix (e.g., "high," "medium," "low"), forming a complete correlation strength matrix that visually presents the correlation relationships between all sequences. The core principle is "positive correlation strength": sequences with higher correlation strength have higher execution priority; sequences with "high" correlation strength are prioritized to form "high correlation clusters," and then sorted according to the degree of mutual correlation within the cluster (e.g., sequences A and B have the highest correlation, and sequences B and C have the second highest correlation, so the order within the cluster is A→B→C); sequences with "medium" correlation strength are then sorted according to the same logic and placed after the "high correlation clusters"; finally, sequences with "low" correlation strength are arranged sequentially at the end, forming the overall execution order.

[0059] The correlation strength matrix visually presents the relationships between all sequences, ensuring that the execution order is highly matched with the actual coordination requirements of the sequences (highly correlated sequences are executed in clusters), and reducing frequent jumps between unrelated sequences.

[0060] Figure 2 A flowchart of an instruction processing method proposed in this disclosure is further shown. Based on Figure 1 The embodiments shown further explain the above embodiments. Figure 2 This may include the following steps: Step S201: Based on the execution time information, determine the jump frequency between any two pairs of instruction sequences to be processed in the plurality of instruction sequences to be processed.

[0061] In the embodiments of this disclosure, the jump frequency is explained as follows: the jump frequency is the number of times that one instruction sequence to be processed is executed and another instruction sequence to be processed is directly triggered to start execution within a unit of time. It is used to reflect the degree of linkage between the two instruction sequences in the time dimension.

[0062] In the embodiments of this disclosure, the jump frequency can be determined by iterating through the collected execution time information and judging jump events: if the execution end time of instruction sequence A is consecutive to the execution start time of instruction sequence B (without other instruction sequences being inserted for execution), then a "instruction sequence A → instruction sequence B" jump event is determined to have occurred. If the chip enters an idle state after an instruction sequence is completed (without subsequent instruction sequences being executed), or is triggered by a system interrupt instruction to execute other non-pending instruction sequences, then it is not included in the jump event statistics. For all "pairs of pending instruction sequences" combinations, the number of jump events occurring within a set statistical period is counted (for example, the "instruction sequence A → instruction sequence B" jump event occurs 12 times within the statistical period, and the "instruction sequence B → instruction sequence A" jump event occurs 8 times). A dedicated statistical entry is established for each pair of instruction sequence combinations, clearly marking the combination name (e.g., "sequence X - sequence Y") and the corresponding number of jumps. The jump frequency of each pair of instruction sequences is calculated by dividing the number of jumps in each pair by the set statistical period. This is the number of jumps per unit time. (For example, if the statistical period is 10 seconds and the jump count for "Instruction Sequence A → Instruction Sequence B" is 12, then the jump frequency is "1.2 jumps / second"). The jump frequency of all pair of instruction sequences is uniformly expressed as "number of jumps / statistical period unit" (e.g., jumps / second, jumps / minute) to ensure data comparability.

[0063] By analyzing the jump frequency of instruction sequences, the system can identify which instruction sequences cause execution delays due to high-frequency jumps, and then take corresponding optimization measures, such as reducing jumps and reordering instructions. The optimized instruction sequences can utilize processor resources more efficiently, thereby improving the overall system execution efficiency.

[0064] Step S202: Based on the location information, determine the position information difference between each pair of instruction sequences to be processed in the plurality of instruction sequences to be processed.

[0065] In the embodiments of this disclosure, the location information is explained as follows: the location information difference is an indicator of the physical distance between two instruction sequences to be processed in the chip storage medium. By comparing the storage location range of the two sequences, it is found that the smaller the location information difference, the closer the storage locations of the two sequences are, and the larger the location information difference, the more remote the storage locations are.

[0066] In the embodiments of this disclosure, the location information difference can be determined as follows: for any two instruction sequences, such as instruction sequence M and instruction sequence N, the system calculates based on the key positioning points of each pair of instruction sequences. The most direct and effective calculation method is to calculate the absolute value of the difference between their starting addresses. Let the starting address of instruction sequence M be Addr_M and the starting address of instruction sequence N be Addr_N. Then the location information difference Diff_MN can be calculated as |Addr_M - Addr_N|. The unit of the location information difference is bytes.

[0067] By calculating and optimizing the positional information difference of the instruction sequence, the system can rationally arrange the execution order of instructions, avoid excessive jumps and switches, reduce system scheduling overhead, and improve task execution efficiency.

[0068] Step S203: Calculate the association strength based on the jump frequency and the difference in location information.

[0069] In the embodiments of this disclosure, the correlation strength can be calculated as follows: the jump frequency and the difference in location information are normalized to eliminate dimensional differences and make their numerical ranges similar. The weights of jump frequency and distance are dynamically allocated according to system requirements; for example, the jump frequency weight is 70% and the distance weight is 30%. Based on the allocated weights, the normalized jump frequency and distance are weighted and calculated to generate the correlation strength.

[0070] By dynamically adjusting the weights, different task requirements can be met.

[0071] As a refinement of step S203, when performing the calculation of the association strength based on the jump frequency and the distance, it can be implemented in the following ways, but is not limited to: obtaining a first weight of the jump frequency and a second weight of the location information difference; calculating the association strength based on the first weight, the second weight, the jump frequency and the location information difference.

[0072] In the embodiments of this disclosure, the first weight and the second weight are explained. The first weight is a coefficient used to adjust the contribution of jump frequency in the association strength calculation. The first weight quantifies the importance the system attaches to the dynamic logical association between the sequences of instructions to be processed. The larger the first weight value, the more the system tends to classify sequences with frequent jumps as having high association when making decisions. The second weight is a coefficient used to adjust the contribution of position information difference in the association strength calculation. The second weight quantifies the system's sensitivity to the static space cost between the sequences of instructions to be processed.

[0073] In embodiments of this disclosure, the correlation strength can be calculated using the following formula:

[0074] in, For correlation strength, As the first weight, For time or space coefficients, The time window for the jump frequency. For time window ( The number of jumps from the i-th instruction sequence to the j-th instruction sequence within a given range. As the second weight, Let be the average jump time interval between the i-th instruction sequence to the j-th instruction sequence. The time decay factor, Let be the distance between the i-th instruction sequence and the j-th instruction sequence to be processed. This represents the position of the i-th instruction sequence to be processed. This represents the position of the j-th instruction sequence to be processed.

[0075] By assigning different weights to jump frequency and distance, the system can more accurately calculate the correlation between instructions or tasks, avoid oversimplifying task dependencies, and thus improve the accuracy of the calculation results.

[0076] In practical applications, there are different types of instructions to be processed. In order to facilitate the loading of different types of instruction sequences, the following methods can be used, but are not limited to: determining the type of the multiple instruction sequences to be processed based on the execution time information; determining the execution priority of the multiple instruction sequences to be processed based on the type of the multiple instruction sequences to be processed; and executing the multiple instruction sequences to be processed according to the execution priority.

[0077] In the embodiments of this disclosure, the types and execution priorities are explained. The type of the instruction sequence to be processed refers to a category based on execution time information, used to distinguish the sequence's requirements for storage performance and response speed, including: First type: Instruction sequences with high execution frequency or high jump frequency (such as interface refresh instructions frequently operated by users, and core data verification instructions in the execution chain), which have high requirements for response speed and storage access efficiency; Second type: Instruction sequences with low execution frequency and low jump frequency (such as log backup instructions that occasionally run in the background, and exception recovery instructions that are rarely triggered), which have lower requirements for storage performance and can tolerate a certain amount of access latency. Execution priority is a hierarchical classification that determines the order in which the instruction sequences to be processed are executed, including first execution priority and second execution priority. Sequences with higher priority are processed by the chip first.

[0078] In the embodiments of this disclosure, the execution of the instruction sequence to be processed can be achieved in the following way: if the execution frequency of an instruction sequence is greater than a preset first threshold, or the jump frequency is greater than a preset second threshold (either condition needs to be met), then the sequence type is determined to be the first type (representing a core sequence with high-frequency execution or high-frequency linkage); if the execution frequency of an instruction sequence is less than or equal to the preset first threshold, and the jump frequency is less than or equal to the preset second threshold (both must be met), then the sequence type is determined to be the second type (representing a normal sequence with low-frequency execution or low linkage); the first type instruction sequence is assigned to the first execution priority (high priority), indicating that this type of sequence is more critical to the chip function implementation and needs to be responded to first; the second type instruction sequence is assigned to the second execution priority (low priority), indicating that this type of sequence can be processed after the core sequence is executed; the first execution priority is always higher than the second execution priority, without exception, to ensure the uniformity of scheduling logic. All instruction sequences to be processed are sorted in order of first execution priority first and second execution priority last to form an overall execution queue; the chip first processes all instruction sequences of first execution priority (without waiting for low priority sequences, ensuring fast response of core functions); after all first execution priority sequences have been processed, the instruction sequences of second execution priority are processed in sequence.

[0079] By determining the type of instruction sequence based on execution time information, the system can allocate resources more rationally, enabling high-priority tasks to be executed in a timely manner and preventing low-priority tasks from being delayed due to resource contention, thereby improving the overall task processing efficiency.

[0080] As a refinement of the above embodiments, when performing the step of determining the type of the plurality of instruction sequences to be processed based on the execution time information, the following methods can be used, but are not limited to: determining the type of instruction sequences to be processed with an execution frequency greater than a preset first threshold in the execution time information as a first type, and / or determining the instruction sequences to be processed with a jump frequency greater than a preset second threshold in the execution time information as the first type; determining the type of instruction sequences to be processed with an execution frequency less than or equal to the preset first threshold as a second type, and / or determining the instruction sequences to be processed with a jump frequency less than or equal to the preset second threshold as the second type.

[0081] In the embodiments of this disclosure, the preset first threshold is explained. The preset first threshold refers to the execution frequency judgment standard preset by the terminal based on its own hardware performance and application scenario, used to distinguish between high-frequency active sequences and low-frequency inactive sequences. The threshold needs to be adapted to the terminal type. For example, for mobile terminals (phones, smartwatches): because they focus on real-time interaction, the preset first threshold is usually set to execute ≥3 times within 1 minute (such as the screen swiping to interface switching command of high frequency user operation needs to be responded to quickly); for servers / industrial terminals: because they process batch tasks, the preset first threshold is set to execute ≥100 times within 1 hour (such as the database query command in the data server needs to be processed frequently).

[0082] In the embodiments disclosed herein, the preset second threshold is explained. The preset second threshold refers to the terminal's preset jump frequency determination standard, used to distinguish between core sequences and independent non-core sequences. The threshold also adapts to different scenarios: for example, mobile terminals: the preset second threshold is set to a jump frequency ≥ 50% (i.e., after the sequence is executed, there is a greater than 50% probability of triggering other sequences, such as clicking an input box to bring up keyboard instructions); servers: the preset second threshold is set to a jump frequency ≥ 60% (because the server's execution link is more complex, and the core sequence requires higher jump drive, such as data reception to data verification instructions).

[0083] In embodiments of this disclosure, the type of instruction sequence to be processed can be implemented by comparing the execution frequency of each instruction sequence to be processed with a preset first threshold. If the execution frequency is greater than the first threshold, the instruction sequence is determined to be of the first type. Similarly, the system also compares the jump frequency of the instruction sequence with a preset second threshold. If the jump frequency is greater than the second threshold, the instruction sequence is also determined to be of the first type. If the execution frequency of the instruction sequence to be processed is less than or equal to the first threshold, and the jump frequency is less than or equal to the second threshold, the instruction sequence is determined to be of the second type. Instruction sequences of the second type are typically tasks with fewer executions and simpler control flows, which the system can process with lower priority.

[0084] By categorizing tasks based on execution and jump frequencies, the system can more accurately identify task characteristics. Frequently executed tasks or those involving complex jumps are prioritized to avoid system bottlenecks.

[0085] As a refinement of the above embodiments, when performing the step of determining the execution priority of the plurality of instruction sequences to be processed according to their types, the following methods may be used, but are not limited to: determining the first type as the first execution priority; determining the second type as the second execution priority; wherein the execution priority includes the first execution priority and the second execution priority, and the first execution priority is greater than the second execution priority.

[0086] In the embodiments disclosed herein, the first execution priority and the second execution priority are explained. The first execution priority refers to the high-level execution priority corresponding to the first type of instruction sequence, meaning that this type of sequence should be processed by the chip first to ensure rapid response of core functions. The second execution priority refers to the low-level execution priority corresponding to the second type of instruction sequence, meaning that this type of sequence can be executed after the high-priority sequence has been processed, avoiding the occupation of core resources.

[0087] In the embodiments of this disclosure, the execution priority of each type can be determined as follows: all instruction sequences marked as first type are directly associated with the first execution priority; all instruction sequences marked as second type are directly associated with the second execution priority. There is a one-to-one correspondence between type and priority, eliminating the need to refer to other parameters (such as sequence data volume or storage location), ensuring consistent and unambiguous rules. The first execution priority is higher than the second execution priority, and this relationship is irreversible (regardless of whether there are special circumstances, the second type sequence cannot be executed before the first type sequence). This priority relationship is preset in the chip's instruction scheduling module to ensure that the chip strictly follows this rule when executing instructions, avoiding resource allocation chaos. All instruction sequences are traversed, and their corresponding execution priorities are assigned one by one according to their type markings. The final execution list is then formed in the order of first execution priority first, followed by second execution priority. The list clearly records the identifier, type, and corresponding priority of each sequence, providing a direct basis for the chip's subsequent instruction execution.

[0088] The first execution priority is strictly higher than the second execution priority, ensuring that core sequences that execute frequently and are linked frequently have priority to obtain chip resources, and avoiding delays in core functions due to resource contention.

[0089] As a refinement of the above embodiments, when performing the step of determining the execution order based on the association strength, it can be implemented in the following ways, but is not limited to: generating an association strength matrix of the plurality of instruction sequences to be processed based on the association strength; determining the execution order of the plurality of instruction sequences to be processed based on the association strength matrix; the execution order being positively correlated with the association strength.

[0090] In the embodiments of this disclosure, the association strength is explained as follows: the association strength matrix is ​​a two-dimensional table with all the instruction sequences to be processed as rows and columns, and the cells filled with the association strength of the corresponding two sequences, used to intuitively present the association relationship between global sequences. For example, if there are 3 sequences A, B, and C, the matrix has a 3×3 structure, where the value of the cell in row A-column B is the association strength between A and B, and the value in row B-column C is the association strength between B and C, and the matrix has symmetry (the association value between A and B = the association value between B and A).

[0091] In the embodiments of this disclosure, the execution order can be determined as follows: All sequences of instructions to be processed are used as rows and columns of a matrix (rows and columns correspond one-to-one, forming a square matrix), with the number of rows and columns equal to the total number of sequences of instructions to be processed. All pairwise combinations of sequences of instructions to be processed are traversed, and the determined correlation strength level (strong, medium, weak) of each sequence is filled into the corresponding intersection cell of the row and column in the matrix; the correlation strength between the same sequence and itself does not need to be marked (indicated by -), ensuring the matrix is ​​clear and free of redundancy. It is confirmed that the correlation strength of all pairwise sequence combinations has been filled into the matrix without omissions or errors, ensuring that the matrix comprehensively reflects the correlation relationships between all sequences. Cells with strong correlation strength are selected from the matrix, and instruction sequences with strong correlations are integrated into high-correlation clusters (for example, if the cells for sequences A and B, and B and C are both strong, then A, B, and C constitute a high-correlation cluster). Within each high-correlation cluster, sequences are sorted according to the tightness of their correlation strength (sequences with strong correlation strengths are arranged adjacently to ensure minimal jump time during execution within the cluster). Sequences with medium association strength are extracted and integrated into medium-association clusters using the same logic. After sorting, these clusters are placed after the high-association clusters. Independent sequences with weak association strength (sequences with no obvious association) are arranged sequentially at the end. The final execution order is formed by combining the high-association clusters → medium-association clusters → weak-association independent sequences, ensuring that the overall execution order is positively correlated with the association strength (the higher the association strength, the earlier it is executed).

[0092] The association strength matrix organizes scattered paired association data into a global view, allowing the system to simultaneously evaluate the association relationships between all sequences.

[0093] As a refinement of the above embodiments, when executing the plurality of pending instruction sequences according to the execution order, it can be implemented in the following ways, but is not limited to: obtaining the cache space of the target cache line corresponding to the plurality of pending instruction sequences, and obtaining the data volume of the plurality of pending instruction sequences; caching the plurality of pending instruction sequences to the target cache line for execution in descending order of the execution order, until the target cache line can no longer cache the next pending instruction sequence; when the target cache line can no longer cache the next pending instruction sequence, and the target cache line has remaining cache space, filling the remaining cache space with an empty instruction sequence.

[0094] In the embodiments of this disclosure, the terms target cache line, cache space, data volume, and empty instruction sequence are explained. A target cache line refers to one or more contiguous memory units of fixed size selected in the processor instruction cache to store the current batch of instructions to be processed. Its size is determined by the hardware architecture and is the smallest unit of cache management. Cache space refers to the currently available, unoccupied byte capacity in the target cache line. Data volume refers to the total number of bytes occupied in memory by the machine code formed after each instruction sequence to be processed is compiled and assembled. An empty instruction sequence refers to a series of machine instructions that do not perform any actual operation but occupy a specific number of bytes. Its function is to physically occupy the remaining space in the cache line to ensure the integrity and alignment of the cache line structure.

[0095] In the embodiments of this disclosure, the execution of the instruction sequence to be processed can be achieved in the following manner: extract the total cache space of the target cache line (determining the maximum capacity available for storing instruction sequences); extract the corresponding data volume from the metadata of each instruction sequence to be processed (determining the storage size required for a single sequence); confirm the preset execution order (determined by the aforementioned association strength or type priority), and define the descending order sorting rule (the higher the priority, the earlier the sorting). In descending order of execution, select the instruction sequences to be processed sequentially and attempt to store them in the target cache line; after storing each instruction sequence, calculate the used space and remaining cache space of the target cache line in real time (remaining cache space = total cache space - used space); determine whether the data volume of the next instruction sequence to be processed is less than or equal to the remaining cache space: if so, continue to store the sequence in the target cache line and repeat the calculation of the remaining space; if not (i.e., the data volume of the next sequence > the remaining cache space), stop storing new instruction sequences to be processed. If the target cache line can no longer store the next instruction sequence to be processed, but there is still remaining cache space (total cache space > used space), an empty instruction sequence with the same size as the remaining cache space is generated; the empty instruction sequence is filled into the remaining space of the target cache line until the cache space of the target cache line is completely occupied; the chip executes continuously according to the storage order in the target cache line (instruction sequence to be processed + empty instruction sequence), and after the cache line is processed, the remaining uncached instruction sequence to be processed is processed according to the same logic.

[0096] The cache is sorted in descending order of execution to ensure that high-priority instruction sequences are stored and executed first, avoiding delays in core instructions due to disordered cache order.

[0097] In the embodiments of this disclosure, in order to facilitate a better understanding of the entire instruction processing process, such as Figure 3 As shown, Figure 3 This disclosure provides a flowchart of instruction processing. It utilizes an embedded trace macrocell (ETM) to collect real-time data such as instruction cache hit rate and branch jump paths during program execution. Combined with a binary optimization and layout tool (BOLT), it dynamically adjusts the code segment layout to reduce instruction cache miss rate, improve throughput, and solve the instruction cache contention and execution efficiency problems of Advanced RISC Machines (ARM) chips in mobile devices under high-load scenarios. Figure 3 These are typical application scenarios and scenario diagrams. Figure 3 By leveraging the real-time tracing capabilities of ARM ETM and combining them with microarchitecture-level caching optimization strategies, we can achieve precise breakthroughs in mobile device performance bottlenecks.

[0098] In the embodiments disclosed herein, Scenario 1: Mobile Game Performance Optimization: Scenario Description: When running high-quality mobile games, the graphics processing unit (GPU) rendering thread and the instruction stream calculated by the physics engine frequently compete for the L1 instruction cache (L1i), causing frame rate fluctuations. This solution improves the cache hit rate by dynamically reorganizing the basic block (i.e., the sequence of instructions to be processed) layout of key functions (key functions are functions in the program that affect the chip's running performance) by analyzing the instruction stream hotspots captured by ETM in real time. Scenario 2: Multi-task Fast Switching Optimization: Scenario Description: When multiple applications (social, navigation, video) run in parallel in the background, frequent switching causes frequent refresh of the instruction cache. By analyzing the spatial distribution characteristics of high-frequency code segments of each application through ETM, the cold and hot code separation layout is optimized.

[0099] In the embodiments disclosed herein, 1. ETM instruction stream capture and preprocessing: Hardware configuration: Enable ARM ETM's full trace mode (FULL_TRACE) to capture instruction addresses, branch targets, and cached events (L1i missing flags). Data filtering: Limit the monitoring area using an address range filter (ETM_FILTER.ADDR_RANGE) to reduce the amount of data. Key filtering operations: Remove low-relevance instructions (such as No Operation (NOP) instructions and non-branch instructions); Mark high-frequency jump paths: If a continuous jump sequence occurs more than a threshold number of times within a time window T, it is recorded as a hotspot path.

[0100] In the embodiments of this disclosure, the spatiotemporal joint affinity of basic blocks is dynamically calculated: Input: ETM instruction stream sequence S={(t1,addr1),(t2,addr2),...,(tn,addrn)}. Where t1 to tn are execution time information, and addr1 to addrn are positions. Define basic blocks: Divide continuous non-branch instructions into basic blocks B={b1,b2,...,bm}, where b1 to bm are the instruction sequence to be processed. Construct the affinity matrix (i.e., the association strength matrix): For each pair of basic blocks (bi,bj), calculate the spatiotemporal joint weight (i.e., the association strength):

[0101] in, For correlation strength, For time or space coefficients, The time window for the jump frequency. For time window ( The number of jumps from the i-th instruction sequence to the j-th instruction sequence within a given range. Let be the average jump time interval between the i-th instruction sequence to the j-th instruction sequence. The time decay factor is the jump time interval of the instruction sequence to be processed. This represents the position of the i-th instruction sequence to be processed. This represents the position of the j-th instruction sequence to be processed.

[0102] In the embodiments of this disclosure, the dynamic cache line alignment strategy includes: Hot block (i.e., a sequence of instructions of the first type) identification: Basic blocks whose execution frequency exceeds a threshold (i.e., a preset first threshold) are marked as hot blocks. Alignment rules: The starting address of a hot block is aligned to 64 bytes: Aligned address (aligned_addr) = (Original address (orig_addr) / / 64) * 64; If multiple hot blocks compete for the same cache line, they are sorted according to affinity weight (W_{i,j}), with higher weight blocks taking priority. Conflict resolution: For hot blocks that cannot be aligned, NOP instructions are inserted to fill the gaps, ensuring that subsequent hot blocks are aligned. BOLT integration optimization: Plugin development: A customized BOLT plugin parses the affinity matrix and generates a layout strategy file. BOLT rearranges code segments according to the strategy file to ensure that high-affinity basic blocks are continuously distributed in memory and that hot code is strictly aligned.

[0103] Corresponding to the instruction processing method described above, the present invention also proposes an instruction processing apparatus. Since the apparatus embodiments of the present invention correspond to the method embodiments described above, details not disclosed in the apparatus embodiments can be referred to in the method embodiments described above, and will not be repeated here.

[0104] Figure 4 This is a schematic diagram of the structure of an instruction processing device 400 provided in an embodiment of the present disclosure. The instruction processing device includes: The acquisition unit 41 is used to acquire the execution time information of multiple instruction sequences to be processed and the position information of the multiple instruction sequences to be processed; The determining unit 42 is used to determine the execution order of the plurality of instructions to be processed based on the execution time information and the position information; The execution unit 43 is used to execute the plurality of pending instruction sequences in the order of execution.

[0105] In summary, in the embodiments of this disclosure, the instruction processing apparatus proposed herein includes acquiring execution time information and position information of a plurality of instruction sequences to be processed; determining the execution order of the plurality of instruction sequences to be processed based on the execution time information and the position information; and executing the plurality of instruction sequences to be processed according to the execution order. The execution time information reflects temporal characteristics, and the position reflects spatial characteristics. Considering both time and spatial characteristics makes instruction execution more closely aligned with actual needs, thereby improving instruction execution efficiency.

[0106] Furthermore, in one possible implementation of the embodiments of this disclosure, such as Figure 5 As shown, the determining unit 42 includes: The first determining module 421 is used to determine the correlation strength between any two pairs of instruction sequences to be processed in the plurality of instruction sequences to be processed based on the execution time information and the location information. The first determining module 421 is further configured to determine the execution order based on the association strength.

[0107] Furthermore, in one possible implementation of the embodiments of this disclosure, such as Figure 5 As shown, the first determining module 421 is further configured to: Based on the execution time information, determine the jump frequency between any two pairs of instruction sequences to be processed in the plurality of instruction sequences to be processed; Based on the location information, determine the location information difference between each pair of instruction sequences to be processed in the plurality of instruction sequences to be processed; The association strength is calculated based on the jump frequency and the difference in location information.

[0108] Furthermore, in one possible implementation of the embodiments of this disclosure, such as Figure 5 As shown, the first determining module 421 is further configured to: Obtain the first weight of the jump frequency and the second weight of the position information difference; The association strength is calculated based on the first weight, the second weight, the jump frequency, and the difference in location information.

[0109] Furthermore, in one possible implementation of the embodiments of this disclosure, such as Figure 5 As shown, the device further includes: The determining unit 42 is further configured to determine the type of the plurality of instruction sequences to be processed based on the execution time information; The determining unit 42 is further configured to determine the execution priority of the plurality of instruction sequences to be processed based on the types of the plurality of instruction sequences to be processed; The execution unit 43 is further configured to execute the plurality of pending instruction sequences according to the execution priority.

[0110] Furthermore, in one possible implementation of the embodiments of this disclosure, such as Figure 5 As shown, the determining unit 42 includes: The second determining module 422 is used to determine the type of the instruction sequence to be processed with an execution frequency greater than a preset first threshold in the execution time information as a first type, and / or to determine the instruction sequence to be processed with a jump frequency greater than a preset second threshold in the execution time information as the first type; The second determining module 422 is further configured to determine the type of the instruction sequence to be processed with an execution frequency less than or equal to the preset first threshold as a second type, and / or to determine the instruction sequence to be processed with a jump frequency less than or equal to the preset second threshold as the second type.

[0111] Furthermore, in one possible implementation of the embodiments of this disclosure, such as Figure 5 As shown, the determining unit 42 is further configured to: The first type is determined as the first execution priority; The second type is determined as the second execution priority; The execution priority includes a first execution priority and a second execution priority, wherein the first execution priority is greater than the second execution priority.

[0112] Furthermore, in one possible implementation of the embodiments of this disclosure, such as Figure 5 As shown, the first determining module 421 is further configured to: Based on the correlation strength, generate the correlation strength matrix of the plurality of instruction sequences to be processed; The execution order of the plurality of instruction sequences to be processed is determined based on the correlation strength matrix; the execution order is positively correlated with the correlation strength.

[0113] Furthermore, in one possible implementation of the embodiments of this disclosure, such as Figure 5 As shown, the execution unit 43 is further configured to: Obtain the cache space of the target cache line corresponding to the plurality of instruction sequences to be processed, and obtain the data volume of the plurality of instruction sequences to be processed; The multiple sequences of instructions to be processed are cached in the target cache line and executed in descending order of the execution order, until the target cache line can no longer cache the next sequence of instructions to be processed; If the target cache line cannot cache the next instruction sequence to be processed, and there is remaining cache space in the target cache line, the remaining cache space is filled with an empty instruction sequence.

[0114] Since the apparatus provided in this embodiment corresponds to the methods provided in the above embodiments, the implementation of the methods is also applicable to the apparatus provided in this embodiment, and will not be described in detail in this embodiment.

[0115] The methods and apparatus provided in the embodiments of this application have been described above. To implement the functions of the methods provided in the embodiments of this application, the electronic device may include a hardware structure and software modules, and may implement the above functions in the form of a hardware structure, software modules, or a hardware structure plus software modules. One of the above functions may be executed in the form of a hardware structure, software modules, or a hardware structure plus software modules.

[0116] Figure 6 This is a block diagram illustrating an electronic device 500 for implementing the above-described instruction processing method according to an exemplary embodiment. For example, the electronic device 500 may be applied to servers, cloud environments, operational service platforms, various computer platforms, terminal systems, and web page systems.

[0117] Reference Figure 6 The electronic device 500 may include one or more of the following components: processing component 502, memory 504, power supply component 506, multimedia component 508, audio component 510, input / output (I / O) interface 512, sensor component 514, and communication component 516.

[0118] Processing component 502 typically controls the overall operation of electronic device 500, such as operations associated with display, telephone calls, data communication, camera operation, and recording. Processing component 502 may include one or more processors 520 to execute instructions to perform all or part of the steps of the methods described above. Furthermore, processing component 502 may include one or more modules to facilitate interaction between processing component 502 and other components. For example, processing component 502 may include a multimedia module to facilitate interaction between multimedia component 508 and processing component 502.

[0119] Memory 504 is configured to store various types of data to support the operation of electronic device 500. Examples of this data include instructions for any application or method operating on electronic device 500, contact data, phonebook data, messages, pictures, videos, etc. Memory 504 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0120] Power supply component 506 provides power to various components of electronic device 500. Power supply component 506 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to electronic device 500.

[0121] Multimedia component 508 includes a screen that provides an output interface between electronic device 500 and user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors may sense not only the boundaries of touch or swipe actions but also the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 508 includes a front-facing camera and / or a rear-facing camera. When electronic device 500 is in an operating mode, such as a shooting mode or video mode, the front-facing camera and / or rear-facing camera may receive external multimedia data. Each front-facing camera and rear-facing camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

[0122] Audio component 510 is configured to output and / or input audio signals. For example, audio component 510 includes a microphone (MIC) configured to receive external audio signals when electronic device 500 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 504 or transmitted via communication component 516. In some embodiments, audio component 510 also includes a speaker for outputting audio signals.

[0123] I / O interface 512 provides an interface between processing component 502 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, power buttons, and lock buttons.

[0124] Sensor assembly 514 includes one or more sensors for providing state assessments of various aspects of electronic device 500. For example, sensor assembly 514 may detect the on / off state of electronic device 500, the relative positioning of components such as the display and keypad of electronic device 500, changes in position of electronic device 500 or a component of electronic device 500, the presence or absence of user contact with electronic device 500, orientation or acceleration / deceleration of electronic device 500, and temperature changes of electronic device 500. Sensor assembly 514 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 514 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, sensor assembly 514 may also include an accelerometer, gyroscope, magnetometer, pressure sensor, or temperature sensor.

[0125] Communication component 516 is configured to facilitate wired or wireless communication between electronic device 500 and other devices. Electronic device 500 can access wireless networks based on communication standards, such as WiFi, 2G or 3G, 4G LTE, 5G NR (NewRadio), or combinations thereof. In one exemplary embodiment, communication component 516 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 516 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0126] In an exemplary embodiment, the electronic device 500 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the methods described above.

[0127] Embodiments of this disclosure also provide a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause a computer to perform the methods described in the above embodiments of this disclosure.

[0128] Embodiments of this disclosure also provide a computer program product comprising a computer program executable by a programmable device, the computer program having, when executed by the programmable device, the method described in the above embodiments of this disclosure.

[0129] For cases where electronic devices can be chips or chip systems, see [link to relevant documentation]. Figure 7 The diagram shows the structure of the chip. Figure 7 The chip shown includes a processor 601 and an interface 602. There can be one or more processors 601, and multiple interfaces 602.

[0130] Optionally, the chip also includes a memory 603 for storing necessary computer programs and data.

[0131] Those skilled in the art will also understand that the various illustrative logical blocks and steps listed in the embodiments of this application can be implemented by electronic hardware, computer software, or a combination of both. Whether such functionality is implemented through hardware or software depends on the specific application and the overall system design requirements. Those skilled in the art can implement the functionality using various methods for each specific application, but such implementation should not be construed as exceeding the scope of protection of the embodiments of this application.

[0132] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0133] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0134] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process, and the scope of the preferred embodiments of the invention includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as will be understood by those skilled in the art to which embodiments of the invention pertain.

[0135] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processing module, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (control method), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic device, and portable optical disc read-only memory (CDROM). Furthermore, computer-readable media can even be paper or other suitable media on which programs can be printed, because programs can be obtained electronically, for example, by optically scanning the paper or other media, followed by editing, interpreting, or otherwise processing as necessary, and then stored in computer memory.

[0136] It should be understood that various parts of the embodiments of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0137] Those skilled in the art will understand that all or part of the steps of the methods described in the above embodiments can be implemented by a program instructing related hardware, and the program can be stored in a computer-readable storage medium. When executed, the program includes one or a combination of the steps of the method embodiments.

[0138] Furthermore, the functional units in the various embodiments of the present invention can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. The storage medium mentioned above can be a read-only memory, a disk, or an optical disk, etc.

[0139] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. An instruction processing method, characterized in that, The method includes: Obtain the execution time information and position information of multiple instruction sequences to be processed; The execution order of the plurality of instructions to be processed is determined based on the execution time information and the location information. The plurality of pending instruction sequences are executed in the order described.

2. The method according to claim 1, characterized in that, Determining the execution order of the plurality of pending instruction sequences based on the execution time information and the location information includes: Based on the execution time information and the location information, determine the correlation strength between each pair of instruction sequences to be processed in the plurality of instruction sequences to be processed; The execution order is determined based on the association strength.

3. The method according to claim 2, characterized in that, The step of determining the correlation strength between any two pairs of instruction sequences to be processed in the plurality of instruction sequences to be processed based on the execution time information and the location information includes: Based on the execution time information, determine the jump frequency between any two pairs of instruction sequences to be processed in the plurality of instruction sequences to be processed; Based on the location information, determine the location information difference between each pair of instruction sequences to be processed in the plurality of instruction sequences to be processed; The association strength is calculated based on the jump frequency and the difference in location information.

4. The method according to claim 3, characterized in that, The step of calculating the association strength based on the jump frequency and the location information difference includes: Obtain the first weight of the jump frequency and the second weight of the position information difference; The association strength is calculated based on the first weight, the second weight, the jump frequency, and the difference in location information.

5. The method according to any one of claims 1-3, characterized in that, The method further includes: Based on the execution time information, determine the type of the plurality of instruction sequences to be processed; The execution priority of the plurality of instruction sequences to be processed is determined according to their types. The plurality of pending instruction sequences are executed according to the execution priority.

6. The method according to claim 5, characterized in that, Determining the type of the plurality of pending instruction sequences based on the execution time information includes: The type of the instruction sequence to be processed with an execution frequency greater than a preset first threshold in the execution time information is determined as the first type, and / or the instruction sequence to be processed with a jump frequency greater than a preset second threshold in the execution time information is determined as the first type; The type of the instruction sequence to be processed with an execution frequency less than or equal to the preset first threshold is determined as the second type, and / or the instruction sequence to be processed with a jump frequency less than or equal to the preset second threshold is determined as the second type.

7. The method according to claim 6, characterized in that, Determining the execution priority of the plurality of instruction sequences to be processed based on their types includes: The first type is determined as the first execution priority; The second type is determined as the second execution priority; The execution priority includes a first execution priority and a second execution priority, wherein the first execution priority is greater than the second execution priority.

8. The method according to claim 2, characterized in that, Determining the execution order based on the association strength includes: Based on the correlation strength, generate the correlation strength matrix of the plurality of instruction sequences to be processed; The execution order of the plurality of instruction sequences to be processed is determined based on the correlation strength matrix; the execution order is positively correlated with the correlation strength.

9. The method according to claim 1, characterized in that, The step of executing the plurality of pending instruction sequences according to the execution order includes: Obtain the cache space of the target cache line corresponding to the plurality of instruction sequences to be processed, and obtain the data volume of the plurality of instruction sequences to be processed; The multiple sequences of instructions to be processed are cached in the target cache line and executed in descending order of the execution order, until the target cache line can no longer cache the next sequence of instructions to be processed; If the target cache line cannot cache the next instruction sequence to be processed, and there is remaining cache space in the target cache line, the remaining cache space is filled with an empty instruction sequence.

10. An instruction processing apparatus, characterized in that, The device includes: The acquisition unit is used to acquire the execution time information and the position information of the multiple instruction sequences to be processed; The determining unit is configured to determine the execution order of the plurality of instructions to be processed based on the execution time information and the position information; An execution unit is configured to execute the plurality of pending instruction sequences in the order of execution.

11. The apparatus according to claim 10, characterized in that, The determining unit includes: The first determining module is used to determine the correlation strength between any two pairs of instruction sequences to be processed in the plurality of instruction sequences to be processed, based on the execution time information and the location information. The first determining module is further configured to determine the execution order based on the association strength.

12. The apparatus according to claim 11, characterized in that, The first determining module is further configured to: Based on the execution time information, determine the jump frequency between any two pairs of instruction sequences to be processed in the plurality of instruction sequences to be processed; Based on the location information, determine the location information difference between each pair of instruction sequences to be processed in the plurality of instruction sequences to be processed; The association strength is calculated based on the jump frequency and the difference in location information.

13. An electronic device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-9.

14. A computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to perform the method according to any one of claims 1-9.

15. A chip, characterized in that, The chip includes a processing circuit and an interface circuit; wherein the interface circuit is used to read instructions and send the instructions to the processing circuit so that the processing circuit executes the method as described in any one of claims 1-9.

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