Multimode qubit readout and qubit state allocation

Abstract

Systems, computer-implemented methods, and computer program products are provided for facilitating external port measurements of qubit port responses. According to one embodiment, the system may include a memory storing computer-executable components and a processor executing the computer-executable components stored in the memory. The computer-executable components may include an analysis component capable of analyzing the response of a multi-mode readout device coupled to the qubit. The computer-executable components may further include an allocation component capable of allocating a readout state of the qubit based on the response. In some embodiments, the multi-mode readout device may be electrically coupled to at least one of the qubit or a qubit environment based on a defined electrical coupling value.

Description

Technical Field

[0001] This invention relates to superconducting quantum circuits, and more specifically, to multi-mode qubit readout and qubit state allocation. Background Art

[0002] Quantum computing typically utilizes quantum mechanical phenomena to perform computational and information processing functions. It can be contrasted with classical computing, which typically uses transistors to operate on binary values. That is, classical computers operate on bit values ​​of 0 or 1, while quantum computers operate on qubits, which contain a superposition of 0s and 1s, and can entangle multiple qubits using interference.

[0003] Quantum computing hardware differs from classical computing hardware. In particular, superconducting quantum circuits typically rely on Josephson junctions, which can be fabricated on semiconductor substrates. Josephson junctions generally exhibit the Josephson effect of supercurrent, where current can flow through the junction indefinitely without the application of a voltage. One or more Josephson junctions can be embedded in a superconducting circuit to form qubits. Multiple such qubits can be arranged in a superconducting quantum circuit fabricated on a semiconductor substrate, which may further include microwave readout resonators coupled to the individual qubits to facilitate the reading of quantum information (also known as addressing or reading the quantum logic state of the qubits). Such superconducting quantum circuits and microwave readout resonators can be integrated onto a semiconductor substrate to form an integrated quantum processor capable of performing computational and information processing functions substantially more complex than those performed by classical computing devices (e.g., general-purpose computers, special-purpose computers, etc.).

[0004] While fast readout is generally preferred, the robustly coupled readout resonators to the environment result in low qubit coherence via the Purcell effect, causing the qubits to release their energy into the environment through the resonator. To mitigate this mechanism, some existing superconducting quantum systems employ various filters that allow photons at the resonator frequency to pass through the readout line while suppressing qubit relaxation. These filters can be bulky and often come with design and fabrication constraints that can limit the dynamic control of each readout resonator.

[0005] Furthermore, the high coupling between the readout resonator and the environment enables fast, high-fidelity qubit state allocation, making the system extremely sensitive to noise at the resonator frequency. This noise impairs the coherence of the qubits, thereby compromising their coherence time. Purcell filters only protect the qubits from attenuation, but not the resonator from phase-shift noise. Summary of the Invention

[0006] The following is an overview to provide a basic understanding of one or more embodiments of the invention. This overview is not intended to identify key or essential elements, nor is it intended to depict any scope of a particular embodiment or any scope of the claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that follows. In one or more embodiments described herein, devices, systems, computer-implemented methods, and / or computer program products that can facilitate multimode qubit readout and state allocation are described.

[0007] According to an embodiment, the system may include a memory storing computer-executable components and a processor executing the computer-executable components stored in the memory. The computer-executable components may include an analysis component that analyzes the response of a multi-mode readout device coupled to the qubits. The computer-executable components may further include an allocation component that allocates the readout state of the qubits based on the response. The advantage of such a system is that it can provide improved qubit readout fidelity without increasing qubit decay (e.g., due to the Purcell effect) and / or increasing phase shift, without employing a Purcell filter.

[0008] In some embodiments, the multimode readout device can be electrically coupled to at least one of a qubit or a qubit environment based on a defined electrical coupling value. The advantage of such a system is that the multimode readout device can be weakly coupled to the qubit and / or qubit environment, which can facilitate improved accuracy of the simulation results generated by the system, and can promote improved processing accuracy, improved processing efficiency, and / or improved processing performance of the processing units associated with the system.

[0009] According to one embodiment, a computer-implemented method may include: analyzing the response of a multi-mode readout device coupled to a qubit via a system operatively coupled to a processor. The computer-implemented method may further include assigning a readout state of the qubit by the system based on the response. An advantage of this computer-implemented method is that it can be used to provide improved qubit readout fidelity without inducing increased qubit decay (e.g., due to the Purcell effect) and / or increased phase shift, without the need for a Purcell filter.

[0010] In some embodiments, the analysis may include analyzing the response of a multimode readout device electrically coupled to at least one qubit or qubit environment by the system based on defined electrical coupling values. The advantage of this computer-implemented method is that it can be used to weakly couple a multimode readout device to a qubit and / or qubit environment, where such weak coupling can promote improved accuracy of simulation results generated by the system coupled to the multimode readout device, thereby promoting improved processing accuracy, improved processing efficiency, and / or improved processing performance of the processing units associated with the system.

[0011] According to another embodiment, a computer program product is provided that can facilitate the multimode qubit readout and state assignment process. The computer program product may include a computer-readable storage medium having program instructions embodied thereon, which can be executed by a processor to cause the processor to analyze the response of a multimode readout device coupled to the qubit. The program instructions can be further executed to cause the processor to assign the processor's readout state to the qubit based on the response. An advantage of this computer program product is that it can be used to provide improved qubit readout fidelity without causing increased qubit decay (e.g., due to the Purcell effect) and / or increased phase shift, without the need for a Purcell filter.

[0012] In some embodiments, the program instructions may also be executable to cause a processor to analyze the response of a multimode readout device electrically coupled to at least one of a qubit-based or qubit-based environment based on a defined electrical coupling value. The advantage of such a computer program product is that it can be used for weakly coupled multimode readout devices to qubit and / or qubit environments, where such weak coupling can promote improved accuracy of simulation results generated by the system coupled to the multimode readout device, thereby promoting improved processing accuracy, improved processing efficiency, and / or improved processing performance of the processing units associated with the system.

[0013] According to another embodiment, a system may include: a memory storing computer-executable components; and a processor executing the computer-executable components stored in the memory. The computer-executable components may include an analysis component capable of analyzing the response of a readout device coupled to a qubit. The computer-executable components may further include an allocation component capable of allocating a readout state of the qubit based on the response. The advantage of such a system is that it can provide improved qubit readout fidelity without inducing increased qubit decay (e.g., due to the Purcell effect) and / or increased phase shift, without the need for a Purcell filter.

[0014] In some embodiments, the readout device can be electrically coupled to at least one of a qubit or a qubit environment based on a defined electrical coupling value. The advantage of such a system is that it can weakly couple the readout device to the qubit and / or the qubit environment, which can facilitate improved accuracy of the simulation results generated by the system, and can promote improved processing accuracy, improved processing efficiency, and / or improved processing performance of the processing units associated with the system.

[0015] According to another embodiment, a computer-implemented method may include: analyzing the response of a readout device coupled to a qubit via a system operatively coupled to a processor. The computer-implemented method may further include assigning a readout state of the qubit by the system based on the response. An advantage of this computer-implemented method is that it can be used to provide improved qubit readout fidelity without inducing increased qubit decay (e.g., due to the Purcell effect) and / or increased phase shift, without the need for a Purcell filter.

[0016] In some embodiments, the analysis may include: analyzing the response of a readout device electrically coupled to at least one of the qubits or the qubit environment by the system based on defined electrical coupling values. The advantage of this computer-implemented method is that it can be used to weakly couple readout devices to qubits and / or the qubit environment, where such weak coupling can promote improved accuracy of simulation results generated by the system coupled to the readout device, thereby promoting improved processing accuracy, improved processing efficiency, and / or improved processing performance of the processing units associated with the system. Attached Figure Description

[0017] Figure 1 A block diagram of an example non-limiting system according to one or more embodiments described herein is shown, which can facilitate multi-mode qubit readout and state assignment components.

[0018] Figure 2 A block diagram of an example non-limiting system according to one or more embodiments described herein is shown, which can facilitate multi-mode qubit readout and state assignment components.

[0019] Figure 3 A top view of an example non-limiting system according to one or more embodiments described herein is shown, which can facilitate multi-mode qubit readout and state assignment components.

[0020] Figure 4 An electrical schematic diagram of an example non-limiting system according to one or more embodiments described herein is shown, which can facilitate multi-mode qubit readout and state assignment components.

[0021] Figure 5 Example non-limiting information is shown according to one or more embodiments described herein, which may facilitate multi-mode qubit readout and state assignment components.

[0022] Figure 6 Exemplary non-limiting information is shown according to one or more embodiments described herein, which may facilitate multi-mode qubit readout and state assignment components.

[0023] Figure 7 Example non-limiting information is shown according to one or more embodiments described herein, which may facilitate multi-mode qubit readout and state assignment components.

[0024] Figure 8 A flowchart of an example non-limiting computer implementation of a method according to one or more embodiments described herein is shown, which can facilitate multi-mode qubit readout and state assignment components.

[0025] Figure 9 A flowchart of an example non-limiting computer implementation of a method according to one or more embodiments described herein is shown, which can facilitate multi-mode qubit readout and state assignment components.

[0026] Figure 10 A block diagram illustrating one or more exemplary, non-limiting operating environments that facilitate the description herein is shown. Detailed Implementation

[0027] The following detailed description is illustrative only and is not intended to limit the embodiments and / or their application or use. Furthermore, there is no intention to be bound by any express or implied information presented in the preceding "Background" or "Summary" or "Detailed Description" sections.

[0028] One or more embodiments will now be described with reference to the accompanying drawings, wherein similar reference numerals are used throughout to refer to similar elements. In the following description, numerous specific details are set forth for purposes of explanation in order to provide a more thorough understanding of one or more embodiments. However, it will be apparent that one or more embodiments may be practiced without these specific details in various circumstances. Note that the accompanying drawings provided with this application are for illustrative purposes only and are therefore not drawn to scale.

[0029] In view of the aforementioned problems of qubit decay and / or qubit phase shift caused by probing and / or measuring the qubit state of such qubits, this disclosure can be implemented in the form of systems, computer-implemented methods, and / or computer program products to produce solutions to these problems. These systems, methods, and / or program products can facilitate the analysis of different individual mode responses of multi-mode readout devices coupled to qubits, and / or multiple single-mode readout devices coupled to qubits, and / or the allocation of qubit readout states based on these responses. The advantage of such systems, methods, and / or program products is that they can be used to provide improved qubit readout fidelity without inducing increased qubit decay (e.g., due to the Purcell effect) and / or enhanced phase shift, without employing Purcell filters.

[0030] Furthermore, in view of the aforementioned problems of qubit decay and / or qubit phase shifts caused by probing and / or measuring the qubit states of such qubits, this disclosure can be implemented in the form of systems, computer-implemented methods, and / or computer program products to generate solutions to these problems. In some embodiments, these systems, computer-implemented methods, and / or computer program products can facilitate the electrical coupling of multimode readout devices and / or multiple single-mode readout devices to at least one qubit or qubit environment based on defined electrical coupling values. The advantage of such systems, computer-implemented methods, and / or computer program products is that they can be used to weakly couple multimode readout devices and / or multiple single-mode readout devices to qubits and / or qubit environments. This weak coupling can facilitate improved accuracy of simulation results generated by systems coupled to such devices, and can facilitate improved processing accuracy, improved processing efficiency, and / or improved processing performance of processing units associated with the system.

[0031] Figure 1 A block diagram of an example non-limiting system 100 according to one or more embodiments described herein is shown, which can facilitate multi-mode qubit readout and state allocation components. According to some embodiments, system 100 may include a qubit state allocation system 102, a quantum system 114, and / or external electronics 124. In some embodiments, qubit state allocation system 102 may include a memory 104, a processor 106, an analysis component 108, an allocation component 110, and / or a bus 112. In some embodiments, quantum system 114 may include one or more readout devices 116 and / or one or more qubits 118. In some embodiments, components of quantum system 114 may be coupled to each other via circuitry 120 (e.g., electrical ground, communication ground, operative ground, etc.). In some embodiments, components of system 100, such as qubit state allocation system 102, quantum system 114, and / or external electronics 124, may be coupled via a linear passive microwave structure 122 (e.g., electrical ground, communication ground, operative ground, etc.).

[0032] It should be understood that the embodiments of this disclosure depicted in the various accompanying drawings are for illustrative purposes only, and therefore, the architecture of such embodiments is not limited to the systems, devices, and / or components depicted therein. For example, in some embodiments, system 100, qubit state allocation system 102, quantum system 114, and / or external electronic device 124 may further include the operating environment 1000 referenced herein and... Figure 10 Various computer- and / or computing-based elements are described. In some embodiments, they may be combined to implement [the following]. Figure 1The system, device, component, and / or computer-implemented operation shown and described in the other accompanying drawings may use one or more of such computer-based and / or computation-based elements.

[0033] According to some embodiments, memory 104 may store one or more computer and / or machine-readable, writable, and / or executable components and / or instructions that, when executed by processor 106, can facilitate the performance of operations defined by the executable components and / or instructions. For example, memory 104 may store computer and / or machine-readable, writable, and / or executable components and / or instructions that, when executed by processor 106, can facilitate the various functions described herein associated with qubit state allocation system 102, analysis component 108, allocation component 110, quantum system 114, readout device 116, qubit 118, external electronics 124, and / or another component associated with system 100 and / or qubit state allocation system 102, as described herein with or without reference to the various accompanying drawings of this disclosure.

[0034] In some embodiments, memory 104 may include volatile memory (e.g., random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), etc.) and / or non-volatile memory (e.g., read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), etc.) that may employ one or more memory architectures. Reference is made below to system memory 1016 and... Figure 10 Other examples of memory 104 are described below. Such instances of memory 104 can be used to implement any embodiment of the invention.

[0035] According to some embodiments, processor 106 may include one or more types of processors and / or electronic circuitry capable of implementing one or more computer- and / or machine-readable, writable, and / or executable components and / or instructions that may be stored in memory 104. For example, processor 106 may perform various operations that can be specified by these computer- and / or machine-readable, writable, and / or executable components and / or instructions, including but not limited to logic, control, input / output (I / O), arithmetic, etc. In some embodiments, processor 106 may include one or more central processing units, multi-core processors, microprocessors, dual microprocessors, microcontrollers, system-on-a-chip (SoC), array processors, vector processors, and / or another type of processor. Reference is made below to processing unit 1014 and... Figure 10 Other examples of processor 106 are described below. Such examples of processor 106 can be used to implement any embodiment of this disclosure.

[0036] In some embodiments, as described herein, the qubit state allocation system 102, memory 104, processor 106, analysis component 108, allocation component 110, and / or another component of the qubit state allocation system 102 may be communicatively, electrically, and / or operatively coupled to each other via bus 112 to perform the functions of system 100, qubit state allocation system 102, and / or any component coupled thereto. In some embodiments, bus 112 may include one or more memory buses, memory controllers, peripheral buses, external buses, local buses, and / or another type of bus that may employ various bus architectures. Other examples of bus 112 are referenced below to system bus 1018 and... Figure 10 The following description is provided. This example of bus 112 can be used to implement any embodiment of this disclosure.

[0037] In some embodiments, the qubit state allocation system 102, quantum system 114, and / or external electronic device 124 may include any type of component, machine, device, facility, apparatus, and / or instrument, including a processor and / or capable of effective and / or operable communication with wired and / or wireless networks. All such embodiments are contemplated. For example, the qubit state allocation system 102, quantum system 114, and / or external electronic device 124 may include server equipment, computing devices, general-purpose computers, special-purpose computers, quantum computing devices (e.g., quantum computers, quantum processors, etc.), tablet computing devices, handheld devices, server-class computers and / or databases, laptop computers, notebook computers, desktop computers, mobile phones, smartphones, home appliances and / or instruments, industrial and / or commercial equipment, digital assistants, telephones supporting multimedia Internet, multimedia players, and / or other types of devices.

[0038] In some embodiments, the qubit state allocation system 102, the quantum system 114, and / or the external electronic device 124 can be coupled (e.g., in a communicative, electrical, operational, or other manner) to one or more external systems, sources, and / or devices (e.g., computing devices, communication devices, etc.) via data cables (e.g., coaxial cables, high-definition multimedia interface (HDMI), RS-232, Ethernet cables, etc.). In some embodiments, the qubit state allocation system 102, the quantum system 114, and / or the external electronic device 124 can be coupled (e.g., in a communicative, electrical, operational, or other manner) to one or more external systems, sources, and / or devices (e.g., computing devices, communication devices, etc.).

[0039] According to some embodiments, such a network may include wired and wireless networks, including but not limited to cellular networks, wide area networks (WANs) (e.g., the Internet), or local area networks (LANs). For example, the quantum bit state allocation system 102, the quantum system 114, and / or the external electronic device 124 can communicate with one or more external systems, sources, and / or devices (e.g., computing devices) using virtually any desired wired or wireless technology (and vice versa), including but not limited to: Wi-Fi, Global System for Mobile Communications (GSM), Universal Mobile Telecommunications System (UMTS), Global Microwave Access Interoperability (WiMAX), Enhanced General Packet Radio Service (Enhanced GPRS), 3GPP Long Term Evolution (LTE), 3GPP2 Ultra Mobile Broadband (UMB), High-Speed ​​Packet Access (HSPA), Zigbee and other 802.XX wireless technologies and / or traditional telecommunications technologies. Session Initiation Protocol (SIP) RF4CE protocol, WirelessHART protocol, 6LoWPAN (IPv6 over low-power wireless LAN), Z-Wave, ANT, ultra-wideband (UWB) standard protocol, and / or other proprietary and non-proprietary communication protocols. In such an example, the qubit state allocation system 102, quantum system 114, and / or external electronic device 124 may therefore include hardware (e.g., central processing unit (CPU), transceiver, decoder), software (e.g., a set of threads, a set of processes, executing software), or a combination of hardware and software that facilitate communication between the qubit state allocation system 102, quantum system 114, and / or external electronic device 124 and external systems, sources, and / or devices (e.g., computing devices, communication devices, etc.) and external systems, sources, and / or devices.

[0040] According to some embodiments, the qubit state allocation system 102 may include one or more computer and / or machine-readable, writable, and / or executable components and / or instructions that, when executed by processor 106, can facilitate the performance of operations defined by such components and / or instructions. Furthermore, in numerous embodiments, any component associated with the qubit state allocation system 102, as described herein with or without reference to the various accompanying drawings, may include one or more computer and / or machine-readable, writable, and / or executable components and / or instructions that, when executed by processor 106, can facilitate the performance of operations defined by such components and / or instructions. For example, analysis component 108, allocation component 110, and / or any other component associated with the qubit state allocation system 102 disclosed herein (e.g., communicating with, electrically and / or operatively coupled to, and / or used by the qubit state allocation system 102) may include such computer and / or machine-readable, writable, and / or executable components and / or instructions. Therefore, according to many embodiments, as disclosed herein, the qubit state allocation system 102 and / or any components associated therewith can be executed using the processor 106 to perform such computer and / or machine-readable, writable and / or executable components and / or instructions in order to perform one or more operations described herein with reference to the qubit state allocation system 102 and / or any such components associated therewith.

[0041] In some embodiments, as described herein, in order to implement one or more qubit state allocation operations, the qubit state allocation system 102 may facilitate the execution of operations performed by and / or associated with the analysis component 108, the allocation component 110, the quantum system 114, the readout device 116, the qubit 118, the external electronic device 124, and / or another component associated with the qubit state allocation system 102. For example, as described in detail below, the qubit state allocation system 102 can facilitate: analyzing the response of a multi-mode readout device coupled to a qubit; analyzing the response of a readout device coupled to a qubit; allocating the readout state of the qubit according to the response; generating a response based on simultaneous multi-tone excitation; analyzing the response based on Boolean logic analysis, kernel integration of the response, time trajectory of the response, linear discriminant analysis, quadratic discriminant analysis, and / or support vector machine analysis; allocating the readout state according to the majority vote of the response; analyzing the response of a multi-mode readout device electrically coupled to at least one qubit or qubit environment based on a defined electrical coupling value; and / or allocating the readout state based on one or more parameters that facilitate a defined qubit readout fidelity, a defined qubit decay time protection, and / or a defined qubit phase shift protection.

[0042] According to various embodiments, quantum system 114 may include a superconducting system. For example, quantum system 114 may include a superconducting system including, but not limited to: quantum computing devices (e.g., quantum computers, quantum processors, quantum hardware, etc.), superconducting chips, superconducting qubit circuits fabricated on semiconductor substrates (e.g., silicon substrates), circuit quantum electrodynamics (circuit QED) systems, and / or other superconducting systems. In some embodiments, quantum system 114 may include a superconducting chip including one or more readout devices coupled to one or more qubits. For example, quantum system 114 may include a superconducting chip including one or more readout devices 116 coupled to each other and / or coupled to qubit 118 via circuit 120 (e.g., communicatively, electrically, operatively, mechanically, etc.).

[0043] According to many embodiments, the readout device 116 may include a qubit state measurement device capable of measuring the qubit state of a qubit. For example, the readout device 116 may include a qubit state measurement device, including but not limited to: a single-mode readout device, a multi-mode readout device, a superconducting resonator, a microwave resonator, a mechanical resonator, and / or another qubit state measurement device. In some embodiments, the readout device 116 may include a multi-mode readout device, such as a multi-mode microwave resonator, capable of simultaneously or sequentially measuring the qubit state using multiple modes (also referred to herein as channels, tones, harmonics, etc.). In some embodiments, the readout device 116 may include a multi-mode readout device, such as a multi-mode superconducting resonator (e.g., a microwave resonator) with multiple probe taps, capable of measuring the qubit state using multiple modes (e.g., simultaneously or sequentially), wherein the multiple modes may each correspond to multiple probe taps (e.g., each probe tap has a different mode). In some embodiments, the readout device 116 may include a single-mode readout device, such as a single-mode microwave resonator, which can use single-mode (e.g., as referred to below as readout devices 116a, 116b, 116n and...). Figure 2 The state of the qubit is measured.

[0044] In some embodiments, the readout device 116 may be coupled to the qubit based on one or more parameters that facilitate: defined qubit readout fidelity, defined qubit decay time protection, and / or defined qubit phase shift protection. For example, in some embodiments, where the readout device 116 includes a multimode readout device (e.g., a multimode microwave resonator), the readout device 116 may be electrically coupled (e.g., capacitively, inductively, etc.) to the qubit 118 based on one or more parameters that facilitate: defined qubit readout fidelity, defined qubit decay time protection, and / or defined qubit phase shift protection.

[0045] In some embodiments, such defined qubit readout fidelity, defined qubit decay time protection, and / or defined qubit phase shift protection can constitute optimal qubit readout fidelity, optimal qubit decay time protection, and / or optimal qubit phase shift protection. In some embodiments, such optimal qubit readout fidelity, optimal qubit decay time protection, and / or optimal qubit phase shift protection can be determined by using (e.g., via qubit state assignment system 102) a qubit fidelity function F (e.g., fidelity as measurement time t). m The functions of (e.g., the signal-to-noise ratio SNR, for example, in steady state) are shown in equations (1) and (2) below, respectively.

[0046] Equation ( 1 )

[0047]

[0048] in

[0049]

[0050] Equation ( 2 )

[0051]

[0052] In some embodiments, equation (1) and / or equation (2) may correspond to a single pattern. In some embodiments, This can represent the average number of photons in a single-mode measurement, or it can be a measure of the intensity at which each mode is excited. In some embodiments, It can be approximated as 10 In some embodiments, η can represent amplifier efficiency, indicating how much information (e.g., quantum information) is dissipated (e.g., lost) into the qubit (e.g., qubit 118) environment. In some embodiments, the amplifier efficiency η can be approximately equal to 0.1 (η ~ 0.1). In some embodiments, for example, as described below, the cavity attenuation rate κ can be approximately equal to 500 kHz (κ ~ 500 kHz). In some embodiments, for example, as described below, the cavity pull χ can be approximately equal to 500 kHz (χ ~ 500 kHz). In some embodiments, τ can represent the measurement time in units of qubit lifetime (T1). In some embodiments, τ final This can represent the total measurement time. In some embodiments, σ ​​can represent the standard deviation of the measurement signal. In some embodiments, ν th This can represent the temperature of the environment of qubit 118, where ν th=0 can indicate the absence of noise caused by finite temperature. In some embodiments, the qubit decay time T1 can be approximately equal to 50 microseconds (μs) (T1 ~ 50 μs).

[0053] In some embodiments, equation (1) can illustrate that information (e.g., quantum information) as a function of time can be obtained from the readout device 116, and as a function of time, fidelity (e.g., readout fidelity) can increase (e.g., the understanding of the qubit state can be improved) as more and more photons are obtained from the readout device 116. In these embodiments, at some point in time, the qubit (e.g., qubit 118) may begin to decay, which can lead to a decrease in readout fidelity. In these embodiments, for example, as... Figure 5 As shown, the graph of equation (1) illustrates how the allocation error decreases and then increases with consecutive measurements, suggesting the existence of an optimal time that minimizes the allocation error. In these embodiments, for that optimal time, the allocation error can be reduced by increasing the number of modes, and the measurement time can also be reduced. In some embodiments, equation (1) can show how information (e.g., quantum information) obtainable from a qubit (e.g., the qubit state of qubit 118) changes due to qubit decay and / or phase shift.

[0054] In some embodiments, optimal qubit readout fidelity, optimal qubit decay time protection, and / or optimal qubit phase shift protection can be determined (e.g., via qubit state allocation system 102) by changing one or more parameters of equations (1) and / or (2) above. For example, such optimal qubit readout fidelity, optimal qubit decay time protection, and / or optimal qubit phase shift protection can be determined (e.g., via qubit state allocation system 102) by changing one or more parameters of equations (1) and / or (2) above, including but not limited to cavity decay rate κ, cavity pull χ, and / or another parameter. For example, to avoid the loss of quantum information of a qubit (e.g., qubit 118) via qubit decay (e.g., the rate at which a qubit decays to its ground state) and / or via phase shift, an entity (e.g., a human user) may employ system 100 and / or qubit state allocation system 102 to select (e.g., via the graphical user interface (GUI) of qubit state allocation system 102) a cavity decay rate κ value and / or a cavity pull χ value for readout of readout device 116 that can promote protection of qubit decay time and / or phase shift. In some embodiments, for example, to avoid the loss of quantum information of a qubit (e.g., qubit 118) via qubit decay and / or via phase shift, an entity may employ system 100 and / or qubit state allocation system 102 to select a cavity decay rate κ value of approximately 500 kHz and / or a cavity pull χ value of approximately 500 kHz that respectively promote protection of qubit decay time and / or phase shift. In these embodiments, such cavity attenuation rate κ and / or cavity pull χ values ​​can promote optimal qubit readout fidelity, optimal qubit decay time protection, and / or optimal qubit phase shift protection.

[0055] In some embodiments, selecting certain parameters of Equations (1) and / or (2) above (e.g., cavity attenuation rate κ, cavity pull χ, etc.) can indicate how much the readout device 116 can be electrically coupled (e.g., capacitive, inductive, etc.) to the environment and / or electrically coupled (e.g., capacitive, inductive, etc.) to the qubit 118. As cited herein, a qubit environment can be defined as everything that is not part of a quantum system that includes such a qubit. For example, as cited herein, a qubit environment can include any location where there may be all possible leakage channels that are not part of a quantum system to the qubit information (e.g., quantum information). In another example, as cited herein, a qubit environment can include a noisy thermal background that can be a path of incoherent radiation.

[0056] In some embodiments, some parameters of Equations (1) and / or (2) above (e.g., cavity decay rate κ, cavity pull χ, etc.) can facilitate the acquisition of information from qubit 118 at a more favorable rate than the rate at which information might be lost (e.g., released, relaxed) in the environment of qubit 118 in a manner that might prevent (e.g., by readout device 116) such acquisition. For example, a qubit (e.g., qubit 118) may have an inherent qubit decay time T1, and thus, even without electrical coupling to a readout device (e.g., readout device 116), such a qubit may lose energy (e.g., quantum information). Therefore, in some embodiments, an entity (e.g., via a GUI of the qubit state allocation system 102 as described above) can select values ​​for some parameters of Equations (1) and / or (2) above (e.g., cavity decay rate κ, cavity pull χ, etc.) that can facilitate limiting additional energy loss and / or facilitate limiting phase shifts (e.g., quantum information). In these embodiments, such an entity may select values ​​of certain parameters of the above equations (1) and / or equation (2) that can facilitate a balance between the qubit decay rate T1 and the phase shift (e.g., optimal values ​​of certain parameters), since some parameters favor a finite qubit decay rate T1 while others favor a finite phase shift.

[0057] In some embodiments, the readout device 116 may be coupled to a qubit and / or such a qubit environment based on a defined electrical coupling value. For example, in embodiments where the readout device 116 includes a multimode readout device (e.g., a multimode microwave resonator), the readout device 116 may be electrically coupled (e.g., capacitively, inductively, etc.) to the qubit 118 and / or the environment of the qubit 118 based on a defined electrical coupling value. For example, the readout device 116 may be electrically coupled to the qubit 118 based on a cavity pull χ value of approximately 500 kHz, which may constitute a weak electrical coupling between the readout device 116 and the qubit 118. In another example, the readout device 116 may be electrically coupled to the qubit 118 based on a cavity decay rate κ value of approximately 500 kHz, which may constitute a weak electrical coupling between the readout device 116 and the environment of the qubit 118.

[0058] According to some embodiments, qubit 118 may include various types of qubits. For example, qubit 118 may include qubits including, but not limited to, superconducting qubits, charge qubits, flux qubits, phase qubits, and / or another type of qubit. In some embodiments, qubit 118 may include qubits having one or more Josephson junctions. As referenced herein, a Josephson junction may include a superconducting portion that exhibits a supercurrent Josephson effect, wherein current can flow indefinitely through the Josephson junction without an applied voltage. For example, a Josephson junction may be created by weakly coupling (e.g., communicative, electrical, operatively, etc.) two superconductors (e.g., capacitive pads) using a tunnel barrier (or tunnel layer) that may comprise a non-superconducting, non-conductive material (e.g., alumina (Al2O3)).

[0059] According to various embodiments, circuit 120 may include conductive components through which current and / or electrical signals can flow. For example, circuit 120 may include conductive components, including but not limited to wires, traces, capacitors, transistors, resistors, diodes, and / or other components through which current (e.g., alternating current and / or direct current) and / or electrical signals (e.g., microwave frequency signals) can flow. In another example, circuit 120 may include a bus, including but not limited to bus 112, a resonant bus, and / or another type of bus. In numerous embodiments, circuit 120 may facilitate various operations (e.g., transmission, storage, and / or modification of current, electrical signals, and / or electrical data) of quantum system 114, readout device 116, qubit 118, and / or components coupled thereto (e.g., qubit state allocation system 102, analysis component 108, allocation component 110, etc.).

[0060] According to numerous embodiments, the linear passive microwave structure 122 may include a linear passive microwave structure that can facilitate the transmission of microwave frequency signals. For example, the linear passive microwave structure 122 may include a coaxial cable (e.g., a 50-ohm (Ω) cable), a transmission line, a bus (e.g., a resonant bus), a waveguide, and / or other linear passive microwave structures.

[0061] According to various embodiments, external electronic device 124 may include any external electronic device capable of transmitting microwave signals at one or more frequencies (e.g., single-tone, multi-tone) and / or receiving reflected microwave signals at one or more such frequencies. For example, external electronic device 124 may include a vector network analyzer (VNA) capable of transmitting microwave signals of a single or multiple frequencies (e.g., via linear passive microwave structure 122) to quantum system 114, readout device 116, and / or qubit 118. In this example, qubit state allocation system 102 and / or external electronic device 124 may receive microwave signals of a single or multiple frequencies, wherein such microwave signals may be reflected by quantum system 114, readout device 116, and / or qubit 118. In this example, microwave signal transmission by external electronic device 124 at a single or multiple frequencies may constitute probe qubit 118. Although Figure 1 The external electronic device 124 is shown as a remote device (e.g., outside of the qubit state allocation system 102 and / or the quantum system 114), and it should be understood that this disclosure is not limited thereto. For example, in some embodiments, the qubit state allocation system 102 may include the external electronic device 124.

[0062] In some embodiments, as described above, the qubit state allocation system 102 may employ an external electronic device 124 to probe the qubit 118. This probe may be based on a defined qubit readout fidelity, a defined qubit decay time protection, a defined qubit phase shift protection, and / or a defined electrical coupling, which may be determined as described above. In these embodiments, based on this probe, the qubit state allocation system 102 and / or its components may receive reflected microwave signals from the quantum system 114, the readout device 116, and / or the qubit 118 in response to this probe. In these embodiments, the analysis component 108 may analyze the reflected microwave signals (e.g., by analyzing the response of the readout device 116, as described below). In these embodiments, the allocation component 110 may allocate the readout state (e.g., qubit state) of the qubit 118 based on this analysis performed by the analysis component 108. In these embodiments, this allocation of the readout state of the qubit 118 by the allocation component 110 may constitute an allocation of the readout state based on a defined qubit readout fidelity, a defined qubit decay time protection, and / or a defined qubit phase shift protection.

[0063] According to various embodiments, analysis component 108 can analyze the response of a multimode readout device coupled to a qubit. Such a response may include, but is not limited to: qubit response, qubit dispersion readout, qubit state information, quantum information, qubit logic state, qubit response function, microwave port response, admittance function (matrix), multiport admittance function (matrix), impedance function (matrix), and / or another response. In some embodiments, analysis component 108 can analyze the response of a multimode readout device that can facilitate the simultaneous or sequential use of multiple modes (e.g., different modes) to probe qubits in parallel, wherein such simultaneous and / or sequential parallel probing of qubits can provide a different readout response corresponding to each of the multiple modes. For example, analysis component 108 can analyze the response of readout device 116, wherein readout device 116 may include a multimode readout device (e.g., a multimode microwave resonator) that can facilitate the probe of qubit 118 (also referred to herein as simultaneous multitone excitation and / or sequential multitone excitation) based on simultaneous or sequential excitation of multiple modes of readout device 116.

[0064] In some embodiments, such as Figure 1 As shown, the readout device 116 may include a single multimode readout device (e.g., a multimode microwave resonator) and may include multiple harmonics (e.g., modes, tones, channels, etc.), wherein each such harmonic can be employed separately by stimulating the readout device 116 at multiple different frequencies. In these embodiments, such stimulation may occur simultaneously or sequentially. In some embodiments, to facilitate such stimulation of the readout device 116, system 100 and / or qubit state allocation system 102 may employ an external electronic device 124 (e.g., a VNA) to vector subsystem 114, readout device 116, and / or qubit 118 to transmit (e.g., via linear passive microwave structure 122) microwave signals at multiple frequencies. In these embodiments, such transmission of microwave signals at multiple frequencies by external electronic device 124 may constitute probe qubit 118.

[0065] In some embodiments, based on this probing of qubit 118 as described above, qubit state allocation system 102 and / or its components (e.g., analysis component 108) can receive reflected microwave signals at multiple frequencies, wherein such microwave signals can be reflected by quantum system 114, readout device 116, and / or qubit 118. In these embodiments, based on the qubit state allocation system 102 and / or analysis component 108 receiving such microwave signals at multiple frequencies, analysis component 108 can use one or more analysis techniques described below to analyze the multi-mode response individually and / or collectively.

[0066] In some embodiments, the analysis component 108 may analyze the responses of multiple modes individually to determine the qubit state decision corresponding to each individual mode response. In these embodiments, the allocation component 110 may allocate the readout state (e.g., qubit state) of a qubit based on the response and / or the analysis of such individual qubit state decisions. For example, the allocation component 110 may allocate the qubit state of qubit 118 by selecting one of such individual qubit state decisions as the qubit state of qubit 118. For example, the allocation component 110 may select an individual qubit state decision that includes one or more defined criteria. In this example, the allocation component 110 may select an individual qubit state decision that includes, for example, defined criteria including, but not limited to: defined Boolean values ​​(e.g., 0 or 1), defined fidelity (e.g., high fidelity and / or highest fidelity among all such individual qubit state decisions), another defined criterion, and / or any combination of such defined criteria.

[0067] In some embodiments, the allocation component 110 may allocate the readout state (e.g., qubit state) of a qubit based on a majority vote of the responses. For example, based on the qubit state decision corresponding to each individual mode response determined by the analysis component 108 as described above, the allocation component 110 may allocate the readout state (e.g., qubit state) of qubit 118 by applying a majority vote to such individual qubit state decisions. For example, when more than half (e.g., more than 50%) of the individual qubit state decisions contain a certain decision, thus constituting a majority vote, the allocation component 110 may allocate such decision as the readout state (e.g., qubit state) of qubit 118.

[0068] In some embodiments, the analysis component 108 can analyze a multimode response by collectively analyzing such responses. For example, instead of analyzing each individual mode response and / or the qubit state decisions corresponding to each individual mode as described above, the analysis component 108 can analyze the overall multimode response.

[0069] In some embodiments, the analysis component 108 can analyze the overall multimode response by analyzing the integrated response of all individual mode responses (e.g., kernel integrated response). For example, the analysis component 108 can analyze the entire multimode response by employing nonlinear discriminant analysis, where the kernel-weighted responses corresponding to the individual mode responses can be used as input for such analysis. For example, the analysis component 108 can analyze the overall multimode response by employing nonlinear discriminant analysis, including but not limited to: linear discriminant analysis (LDA), quadratic discriminant analysis (QDA), support vector machine (SVM, also known as state vector machine), and / or other nonlinear discriminant analyses.

[0070] In some embodiments, analysis component 108 can analyze the overall multimode response by analyzing the full-time trajectory of each individual mode response (e.g., the opposite of the integrated response described above). For example, analysis component 108 can analyze the entire multimode response by employing nonlinear discriminant analysis, where the full-time trajectories corresponding to the individual mode responses can be used as input to such analysis. For instance, analysis component 108 can analyze the overall multimode response by using one or more of the nonlinear discriminant analyses described above (e.g., LDA, QDA, SVM, etc.), using the full-time trajectories corresponding to the individual mode responses as input to such analysis.

[0071] In some embodiments, allocation component 110 may allocate the readout state of a qubit (e.g., qubit state) based on the output of a response and / or analysis process that can be used by analysis component 108 to analyze the overall multimode response. For example, allocation component 110 may allocate the readout state of a qubit based on the output of such nonlinear identification analysis that can be used by analysis component 108 to analyze the overall multimode response as described above (e.g., LDA, QDA, SVM). In this example, allocation component 110 may allocate the readout state of a qubit based on the kernel integrated response (e.g., a real number, such as a voltage value, integral voltage value, etc.) corresponding to each mode response and / or the full-time trajectory (e.g., a time function, such as f(t) or the change of voltage value with time V(t), etc.) corresponding to each mode response. For example, allocation component 110 may allocate the readout state of qubit 118 by selecting the output of such nonlinear identification analysis that includes one or more defined criteria (e.g., a defined voltage value, a defined voltage value with time V(t), etc.).

[0072] Figure 2 A block diagram of an exemplary non-limiting system 200 according to one or more embodiments described herein is shown, which can facilitate multi-mode qubit readout and state assignment components. For brevity, repeated descriptions of the same elements and / or processes employed in the various embodiments are omitted.

[0073] According to several embodiments, system 200 may include exemplary, non-limiting alternative embodiments of system 100. In such embodiments, the quantum system 114 of system 200 may include a plurality of readout devices 116a, 116b, 116n that may be electrically coupled (e.g., capacitively grounded, inductively grounded, etc.) to qubit 118, where n may represent the total number of readout devices 116 that may be coupled to qubit 118. In these embodiments, readout devices 116a, 116b, 116n may include single-mode readout devices, wherein each device may operate using a single mode (e.g., channel, harmonic, tone, etc.) different from the modes of all other readout devices 116a, 116b, 116n.

[0074] In some embodiments, analysis component 108 can analyze the response of such readout devices 116a, 116b, 116n electrically coupled to qubit 118. For example, based on probing qubit 118 (e.g., via external electronic device 124) and / or based on such probing receiving reflected microwave signals (e.g., reflected microwave signals received by qubit state allocation system 102 and / or its components), analysis component 108 can use the above references Figure 1 One or more analytical techniques are described to analyze, individually and / or collectively, the response of each mode corresponding to each readout device 116a, 116b, 116n (e.g., single qubit state selection decision, majority voting, LDA, QDA, SVM, etc.). In this example, allocation component 110 may allocate the readout state of qubit 118 based on such responses and / or the output of the analysis performed by analysis component 108 (e.g., as referenced above). Figure 1 (As described).

[0075] Figure 3 A top view of an example non-limiting system 300 according to one or more embodiments described herein is shown, which can facilitate multi-mode qubit readout and state assignment components. For brevity, repeated descriptions of the same elements and / or processes employed in the various embodiments are omitted.

[0076] According to several embodiments, system 300 may include the above-mentioned references. Figure 1An embodiment of the quantum system 114 is described. This embodiment of the quantum system 114 may include a superconducting chip 302. In some embodiments, the superconducting chip 302 may include a plurality of readout devices 116a, 116b, 116n, a qubit 118, and / or one or more ports 304a, 304b, 304n, wherein such readout devices 116a, 116b, 116n may be coupled to each other (e.g., electrical ground, communication ground, operative ground, mechanical ground, etc.) and / or coupled to the qubit 118 via circuitry 120. In some embodiments, ports 304a, 304b, 304n may be coupled (e.g., electrical ground, communication ground, operative ground, mechanical ground, etc.) to readout devices 116a, 116b, 116n, respectively. In some embodiments, ports 304a, 304b, 304n may also be coupled to a qubit state allocation system 102 and / or an external electronic device 124 (e.g., via a linear passive microwave structure 122). In some embodiments, ports 304a, 304b, and 304n can facilitate the detection of qubit 118 (e.g., as referenced above). Figure 1 The readout response of the external electronic device 124 and / or the readout device 116a, 116b, 116n based on such detection and capture (e.g., acquisition, measurement, analysis, etc.) (e.g., as referenced above) Figure 1 (as described, via the qubit state allocation system 102 and / or its components).

[0077] In some embodiments, the superconducting chip 302 may include superconducting circuits that can be implemented on a semiconductor substrate. For example, the superconducting chip 302 may include superconducting circuits (e.g., quantum circuits, integral quantum circuits, etc.) that can be implemented on a semiconductor substrate (e.g., a silicon substrate) using one or more semiconductor substrate fabrication techniques. For example, the superconducting chip 302 and / or its components can be manufactured using techniques including but not limited to: photolithography, microlithography, nanolithography, nanoimprint lithography, photomask technology, patterning technology, photoresist technology (e.g., positive photoresist, negative photoresist, hybrid photoresist, etc.), etching technology (e.g., reactive ion etching (RIE)), dry etching, wet etching, ion beam etching, plasma etching, laser ablation, etc.), evaporation technology, sputtering technology, plasma ashing technology, heat treatment (e.g., rapid thermal annealing, furnace annealing, thermal oxidation, etc.), physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced chemical vapor deposition (PECVD), chemical solution deposition, electroplating, molecular beam epitaxy (MBE), electrochemical deposition (ECD), lift-off technology, chemical mechanical planarization (CMP), back-side polishing technology and / or another technology for manufacturing integrated circuits.

[0078] In some embodiments, a variety of materials may be used to manufacture the superconducting chip 302 and / or its components. For example, one or more different material classes may be used to manufacture the superconducting chip 302 and / or its components, including but not limited to: conductive materials, semiconductor materials, superconducting materials, dielectric materials, polymer materials, organic materials, inorganic materials, non-conducting materials, and / or materials that can be used with one or more of the techniques described above for manufacturing integrated circuits.

[0079] Figure 4 Electrical schematic diagrams of an example non-limiting system 400 according to one or more embodiments described herein are shown, which can facilitate multi-mode qubit readout and state assignment components. For brevity, repeated descriptions of the same elements and / or processes employed in the various embodiments are omitted.

[0080] According to several embodiments, system 400 may include the above-mentioned references. Figure 3 The described embodiment of the superconducting chip 302, wherein Figure 4 An exemplary non-limiting electrical schematic topology may be included for this embodiment of the superconducting chip 302. In some embodiments, system 400 may include one or more environmental capacitors 402a, 402b, 402n and / or one or more qubit capacitors 404a, 404b, 404n, where n may represent the total number of such capacitors.

[0081] In some embodiments, ambient capacitors 402a, 402b, 402n may be coupled (e.g., electrical ground, communication ground, operational ground, mechanical ground, etc.) to ports 304a, 304b, 304n, respectively. In some embodiments, ambient capacitors 402a, 402b, 402n may also be coupled (e.g., electrical ground, communication ground, operational ground, mechanical ground, etc.) to readout devices 116a, 116b, 116n, respectively. In some embodiments, ambient capacitors 402a, 402b, 402n may facilitate the electrical coupling of readout devices 116a, 116b, 116n to the environment of qubit 118, respectively, wherein such electrical coupling may be based on cavity decay rate κ. In some embodiments, this electrical coupling between the readout devices 116a, 116b, 116n and the environment of the qubit 118 can be adjusted by (e.g., via an entity such as a human user, via the GUI of the qubit state allocation system 102) by adjusting the environmental capacitors 402a, 402b, 402n (e.g., by changing the value of the cavity attenuation rate κ).

[0082] In some embodiments, qubit capacitors 404a, 404b, 404n may be coupled (e.g., electrical ground, communication ground, operational ground, mechanical ground, etc.) to readout devices 116a, 116b, 116n, respectively. In some embodiments, qubit capacitors 404a, 404b, 404n may also be coupled (e.g., via circuit 120) to qubit 118 (e.g., electrical ground, communication ground, operational ground, mechanical ground, etc.). In some embodiments, qubit capacitors 404a, 404b, 404n may facilitate decoupling line resonances (e.g., line resonances of system 400 and / or readout devices 116a, 116b, 116n). In some embodiments, qubit capacitors 404a, 404b, 404n may facilitate defining (e.g., setting) electrical couplings from readout devices 116a, 116b, 116n to qubit 118, wherein such electrical couplings may be based on cavity pull χ. In some embodiments, this electrical coupling from the readout devices 116a, 116b, 116n to the qubit 118 can be adjusted by (e.g., via an entity such as a human user, via a GUI of the qubit state allocation system 102) by adjusting the qubit capacitors 404a, 404b, 404n (e.g., by changing the value of the cavity pull χ).

[0083] In some embodiments, system 400 may include an equivalent circuit that can be implemented using one or more readout devices (e.g., readout device 116 and / or readout devices 116a, 116b, 116n). In some embodiments, system 400 may illustrate how readout devices 116a, 116b, 116n can be coupled (e.g., electrically grounded) together and commonly coupled (e.g., electrically grounded) to a qubit (e.g., qubit 118), for example, using... Figure 4 The environmental capacitors 402a, 402b, 402n and / or qubit capacitors 404a, 404b, 404n are shown. In some embodiments, such as when system 400 includes an equivalent circuit, this circuit can be created after an electromagnetic simulation that can be used to determine the equivalent circuit is completed (e.g., via qubit state assignment system 102), which can facilitate the detection and / or measurement of qubit readout states, as described in one or more embodiments of this disclosure.

[0084] Figure 5 Example non-limiting information 500 according to one or more embodiments described herein is shown, which can facilitate multi-mode qubit readout and state assignment components. For brevity, repeated descriptions of the same elements and / or processes employed in the various embodiments are omitted.

[0085] According to several embodiments, information 500 may include the above references. Figure 1A graph of equation (1) described. In some embodiments, information 500 may illustrate how the assignment error decreases and subsequently increases with continued measurement of one or more patterns, which may indicate the existence of an optimal time that minimizes the assignment error. In these embodiments, for that optimal time, the assignment error can be reduced by increasing the number of patterns, and the measurement time can also be reduced. In these embodiments, line graph 502 may include one (1) pattern, line graph 504 may include three (3) patterns, line graph 506 may include five (5) patterns, line graph 508 may include seven (7) patterns, and / or line graph 510 may include nine (9) patterns.

[0086] Figure 6 Example non-limiting information 600 according to one or more embodiments described herein is illustrated, which can facilitate multi-mode qubit readout and state assignment components. For brevity, repeated descriptions of the same elements and / or processes employed in the various embodiments are omitted.

[0087] According to several embodiments, information 600 may include a logarithmic scale, wherein the x-axis may represent the number of modes n of the readout device 116, and the y-axis may include two (2) separate values ​​that overlap each other. For example, information y-axis 600 may include: a first value representing the logarithm of the distribution error (e.g., the logarithm of the readout error and / or the logarithm of the readout measurement), which may correspond to Figure 6 The black dot 602 is depicted in the middle; the second value represents time (e.g., seconds), which can correspond to the black dot 602 depicted in the middle. Figure 6 Gray dot 604 in the figure represents the qubit decay time and / or is caused by Figure 6 The white dot 606 in the diagram represents the phase shift time.

[0088] In some embodiments, information 600 may be based on the following assumptions, where Γ can represent a rate, Γ T1 The rate at which a qubit decays can be represented, φ can represent phase loss, and / or Γ. φ The rate of phase shift of a quantum bit can be represented. In some embodiments, information 600 can be based on a (1) mode. and / or Where m can represent the number of readout modes.

[0089] Assumption :

[0090]

[0091] Γ2=1 / 50μs

[0092] Γ1=1 / 50μs

[0093]

[0094] In some embodiments, information 600 may indicate how qubit decay and / or phase shift evolve according to the number of modes n of the readout device 116 (e.g., number of channels, tone, harmonics, etc.). For example, as shown in information 600, qubit decay and / or phase shift may increase at a slower rate (e.g., increase) than the rate at which readout fidelity (e.g., quantum information that can be obtained from the readout) can increase. For example, as shown in information 600, the slope of black dot 602 may be steeper than the slope of gray dot 604 and / or white dot 606, which may indicate that the allocation error decays in the readout (e.g., readout response) faster than the amount of error caused by qubit decay and / or phase shift resulting from the readout process.

[0095] In some embodiments, the time values ​​represented on the y-axis of information 600 (e.g., qubit decay time and / or phase shift time) may represent the total decay time applied to the qubit (e.g., qubit 118) due to the readout process. In these embodiments, as shown in information 600, such time values ​​may decrease as the number of modes n increases due to the introduction of additional modes (e.g., channels) for qubit relaxation.

[0096] In some embodiments, the decreasing slope of gray point 604 and / or white point 606 due to the increasingly shorter time can indicate an increase in qubit decay and / or phase shift. However, in these embodiments, the rate at which this increased qubit decay and / or phase shift occurs may be much slower than the rate at which the readout error decreases, as shown in information 600 (e.g., the slope of black point 602 compared to the slopes of gray point 604 and white point 606). In some embodiments, information 600 may show that the rate at which the slopes of gray point 604 and white point 606 decrease is slower than the rate at which the slope of black point 602 decreases. In some embodiments, as shown in information 600, by employing multiple modes n (e.g., such as... Figure 5 Of the nine (9) modes shown, black dot 602 can be reduced by about three (3) orders of magnitude, while gray dot 604 and white dot 606 can be reduced by about one (1) order of magnitude.

[0097] Figure 7 Example non-limiting information 700 according to one or more embodiments described herein is shown, which can facilitate multi-mode qubit readout and state assignment components. For brevity, repeated descriptions of the same elements and / or processes employed in the various embodiments are omitted.

[0098] According to several embodiments, information 700 illustrates, for example, three (3) individual modes of three (3) readout devices, in which each mode can produce a resonance at offset frequencies (e.g., 6.91 GHz, 6.989 GHz, and 7.07 GHz) that the readout devices can detect independently and / or simultaneously. In some embodiments, information 700 may represent each readout device (e.g., referenced above). Figure 2 , 3 The resonant and / or multi-mode readout devices (e.g., those described in reference 4) of the readout devices 116a, 116b, 116n Figure 1 Each mode of the described readout device 116 is illustrated as signal power (dB) along the y-axis and frequency (GHz) along the x-axis. In some embodiments, information 700 may illustrate that this disclosure (e.g., via qubit state allocation system 102, external electronic device 124, etc.) can approximately [begin to be specified]. Figure 7 Excite such a readout device at the frequency shown (e.g., simultaneously and / or independently) to obtain information about the qubit (e.g., quantum information) (e.g., the readout state of qubit 118).

[0099] In some embodiments, the qubit state allocation system 102 may be a multi-mode qubit readout and state allocation system and / or process associated with various technologies. For example, the qubit state allocation system 102 may be associated with superconducting quantum circuit technology, qubit technology, circuit quantum electrodynamics (circuit-QED) technology, quantum computing technology, scalable quantum computing architecture technology, surface code architecture technology, surface code error correction architecture technology, quantum hardware technology and / or other technologies.

[0100] In some embodiments, the qubit state allocation system 102 can provide technical improvements to systems, devices, components, operating steps, and / or processing steps associated with the various techniques identified above. For example, the qubit state allocation system 102 can facilitate improved qubit readout fidelity by using multiple modes of readout devices (e.g., readout device 116) and / or different individual modes of multiple readout devices (e.g., readout devices 116a, 116b, 116n), as well as the response analysis and / or qubit state allocation techniques described herein (e.g., performed by analysis component 108 and / or allocation component 110, respectively). In this example, the qubit state allocation system 102 can facilitate providing such improved qubit readout fidelity without incurring penalties associated with increased qubit readout performance, such as increased Purcell effects (e.g., increased qubit decay) and / or increased phase shift. In this example, the qubit state assignment system 102 can facilitate providing this improved qubit readout fidelity without incurring the penalty associated with increased qubit readout performance, and without the need for a bulky and / or strongly coupled (e.g., coupled to qubit 118) separate Purcell filter.

[0101] In some embodiments, the qubit state allocation system 102 can provide technical improvements to processing units (e.g., processor 106), circuit-QED systems, and / or superconducting quantum circuits associated with quantum computing devices (e.g., quantum processors, quantum hardware, etc.). For example, the qubit state allocation system 102 can be weakly coupled (e.g., as described above with reference to readout device 116 and...). Figure 1 The weakly coupled (as defined) connection is made to the qubit (e.g., qubit 118) and / or the qubit environment, where such weak coupling can contribute to improved accuracy of simulation results (e.g., simulations performed by the qubit state allocation system 102). In this example, such improved accuracy of the simulation results can contribute to improved processing accuracy, improved processing efficiency, and / or improved processing performance of the processing unit associated with the qubit state allocation system 102 (e.g., processor 106).

[0102] In some embodiments, the qubit state allocation system 102 can employ hardware and / or software to solve problems that are inherently highly technical, not abstract, and cannot be performed by humans as a set of intellectual actions. For example, the qubit state allocation system 102 can facilitate: analyzing the response of a multi-mode readout device coupled to the qubit; analyzing the response of the readout device coupled to the qubit; and / or allocating the readout state of the qubit based on the response. In such an example, the qubit state allocation system 102 can process microwave frequency signals and / or employ various complex mathematical functions and / or algorithms involving multiple variables (e.g., referenced above). Figure 1The equations (1) and / or (2) described herein are used to facilitate the execution of various operations of the qubit state allocation system 102 as described herein.

[0103] It should be understood that the qubit state allocation system 102 can utilize various combinations of electronic components, mechanical components, and circuits to perform multi-mode qubit readout and state allocation processes that cannot be replicated in the human mind or performed by a human. For example, the operation of qubits based on responses using various electrical connections, circuits, and microwave frequency signal analysis coupled to qubits and / or multiple single-mode readout devices coupled to qubits and / or allocation of readout states is greater than the computational capacity of human thought. For example, the amount of data processed by the qubit state allocation system 102 within a certain time period, the speed at which such data is processed, and / or the types of data processed can be greater than, faster than, and / or different from the amount, speed, and / or types of data that the human brain can process within the same time period.

[0104] According to some embodiments, the qubit state allocation system 102 can also be fully operational to perform one or more other functions (e.g., full power-on, full execution, etc.) while simultaneously performing the multi-mode qubit readout and state allocation processes described above. It should be understood that such simultaneous multi-operation execution exceeds the capabilities of the human brain. It should also be understood that the qubit state allocation system 102 may include information that is impossible for an entity such as a human user to obtain manually. For example, the type, quantity, and / or variety of information included in the analysis component 108 and / or allocation component 110 may be more complex than information that a human user could obtain manually.

[0105] Figure 8 A flowchart of an example non-limiting computer implementation of method 800 according to one or more embodiments described herein is shown. This example non-limiting method 800 can facilitate multi-mode qubit readout and state assignment components. For brevity, repeated descriptions of the same elements and / or processes employed in the various embodiments are omitted.

[0106] At 802, a system (e.g., via qubit state allocation system 102 and / or analysis component 108) operatively coupled to a processor (e.g., processor 106) analyzes the response (e.g., qubit response, qubit dispersion reading, qubit state information, quantum information, etc.) of a multi-mode readout device (e.g., readout device 116) coupled to a qubit (e.g., qubit 118). At 804, the system (e.g., qubit state allocation system 102 and / or allocation component 110) allocates the readout state (e.g., qubit state) of the qubit based on the response.

[0107] Figure 9A flowchart of an example non-limiting computer implementation of method 900 according to one or more embodiments described herein is shown. This example non-limiting method 900 can facilitate multi-mode qubit readout and state assignment components. For brevity, repeated descriptions of the same elements and / or processes employed in the various embodiments are omitted.

[0108] At 902, a system (e.g., via qubit state allocation system 102 and / or analysis component 108) operatively coupled to a processor (e.g., processor 106) analyzes the response (e.g., qubit response, qubit distributed readout, qubit state information, quantum information, etc.) of a readout device (e.g., readout device 116a, 116b, 116n) coupled to a qubit (e.g., qubit 118). At 904, the system (e.g., qubit state allocation system 102 and / or allocation component 110) allocates the readout state (e.g., qubit state) of the qubit based on the response.

[0109] For simplicity, the computer-implemented method is described as a series of actions. It should be understood and appreciated that the subject matter innovation is not limited to the actions shown and / or the order of the actions; for example, actions may occur in various orders and / or simultaneously, and may include other actions not presented or described herein. Furthermore, according to the disclosed subject matter, not all shown actions are required to implement the computer-implemented method. Additionally, those skilled in the art will understand and recognize that the computer-implemented method can alternatively be represented by a state diagram or events as a series of interrelated states. Furthermore, it should be further understood that the computer-implemented method disclosed below and throughout the specification can be stored on an article of art to facilitate the transfer and assignment of such computer-implemented method to a computer. The term "article of art" as used herein is intended to encompass a computer program accessible from any computer-readable device or storage medium.

[0110] In order to provide background on various aspects of the disclosed topic, Figure 10 The following discussion is intended to provide a general description of the suitable environments in which the various aspects of the topics disclosed herein can be implemented. Figure 10 A block diagram of an example non-limiting operating environment is shown, which may facilitate one or more embodiments described herein. For the sake of brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted.

[0111] refer to Figure 10The suitable operating environment 1000 for implementing various aspects of this disclosure may also include a computer 1012. The computer 1012 may also include a processing unit 1014, system memory 1016, and a system bus 1018. The system bus 1018 couples system components, including but not limited to system memory 1016, to the processing unit 1014. The processing unit 1014 may be any of a variety of available processors. Dual microprocessors and other multiprocessor architectures may also be used as the processing unit 1014. The system bus 1018 may be any of several types of bus architectures, including memory buses or memory controllers using any available bus architecture, peripheral buses or external buses, and / or local buses, including but not limited to Industry Standard Architecture (ISA), Micro Channel Architecture (MSA), Extended ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), Card Bus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), FireWire (IEEE 1394), and Small Computer System Interface (SCSI).

[0112] System memory 1016 may also include volatile memory 1020 and non-volatile memory 1022. The Basic Input / Output System (BIOS), containing basic routines such as those for transferring information between components within computer 1012 during startup, is stored in non-volatile memory 1022. Computer 1012 may also include removable / non-removable, volatile / non-volatile computer storage media. Figure 10 Disk storage 1024 is shown as an example. Disk storage 1024 may also include, but is not limited to, devices such as disk drives, floppy disk drives, tape drives, Jaz drives, Zip drives, LS-100 drives, flash memory, memory cards, or memory sticks. Disk storage 1024 may also include standalone storage media or storage media in combination with other storage media. To facilitate connection of disk storage 1024 to system bus 1018, a removable or non-removable interface, such as interface 1026, is typically used. Figure 10 Software that acts as an intermediary between the user and the basic computer resources described in the suitable operating environment 1000 is also described. Such software may also include, for example, an operating system 1028. The operating system 1028, which may be stored on disk storage 1024, is used to control and allocate the resources of computer 1012.

[0113] System application 1030 utilizes operating system 1028 to manage resources through program module 1032 and program data 1034 (e.g., program data stored in system memory 1016 or disk storage 1024). This disclosure can be implemented using various operating systems or combinations of operating systems. Users input commands or information to computer 1012 via input device 1036. Input device 1036 includes, but is not limited to, pointing devices such as mouse, trackball, stylus, touchpad, keyboard, microphone, joystick, gamepad, satellite dish, scanner, TV tuner card, digital camera, digital camcorder, webcam, etc. These and other input devices are connected to processing unit 1014 via system bus 1018 through interface port 1038. Interface port 1038 includes, for example, serial ports, parallel ports, game ports, and Universal Serial Bus (USB). Output device 1040 uses some of the same type of ports as input device 1036. Thus, for example, a USB port can be used to provide input to computer 1012 and to output information from computer 1012 to output. Output adapter 1042 is provided to illustrate the existence of output devices 1040, such as monitors, speakers, and printers, as well as other output devices 1040 that require special adapters. By way of illustration and not limitation, output adapter 1042 includes video and sound cards, providing a connection between output devices 1040 and the system bus 1018. It should be noted that other devices and / or device systems provide both input and output functionality, such as remote computer 1044.

[0114] Computer 1012 can operate in a networked environment using logical connections to one or more remote computers, such as remote computer 1044. Remote computer 1044 can be a computer, server, router, network PC, workstation, microprocessor-based device, peer-to-peer device, or other public network node, and typically may also include many or all of the elements described relative to computer 1012. For simplicity, only storage device 1046 is shown for remote computer 1044. Remote computer 1044 is logically connected to computer 1012 via network interface 1048 and then physically connected via communication connection 1050. Network interface 1048 includes local wired and / or wireless communication networks, local area networks (LANs), wide area networks (WANs), cellular networks, etc. LAN technologies include Fiber Distributed Data Interface (FDDI), Copper Distributed Data Interface (CDDI), Ethernet, Token Ring, etc. WAN technologies include, but are not limited to, point-to-point links, circuit-switched networks (such as Integrated Services Digital Network (ISDN)) and variations thereof, packet-switched networks, and Digital Subscriber Line (DSL). One or more communication connections 1050 refer to hardware / software for connecting network interface 1048 to system bus 1018. Although communication connection 1050 is shown inside computer 1012 for clarity, it can also be external to computer 1012. For illustrative purposes only, the software for connecting to network interface 1048 may also include internal and external technologies, such as modems including conventional telephone-grade modems, cable modems, and DSL modems, ISDN adapters, and Ethernet cards.

[0115] At any possible level of technical detail, the present invention can be a system, method, and / or computer program product. A computer program product may include a computer-readable storage medium having computer-readable program instructions loaded thereon for causing a processor to implement various aspects of the present invention. A computer-readable storage medium may be a tangible device capable of holding and storing instructions for use by an instruction execution device. A computer-readable storage medium may be, for example,—but not limited to—an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination thereof. The computer-readable storage medium used herein is not to be interpreted as a transient signal itself, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0116] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions to be stored in the computer-readable storage medium in each computing / processing device.

[0117] The computer program instructions used to perform the operations of this invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, integrated circuit configuration data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and procedural programming languages ​​such as the "C" language or similar programming languages. The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), is personalized by utilizing the status information of the computer-readable program instructions. This electronic circuitry can execute the computer-readable program instructions to implement various aspects of the invention.

[0118] Various aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions. These computer-readable program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operational steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more blocks in the flowchart and / or block diagram.

[0119] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to some embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction, which contains one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0120] Although the subject matter has been described above in the general context of computer-executable instructions for a computer program product running on one or more computers, those skilled in the art will recognize that this disclosure may also be implemented in combination with other program modules. Typically, program modules include routines, programs, components, data structures, etc., that perform specific tasks and / or implement specific abstract data types. Furthermore, those skilled in the art will understand that the computer implementation methods of this invention can be practiced with other computer system configurations, including single-processor or multi-processor computer systems, small computing devices, mainframe computers, and computers, handheld computing devices (e.g., PDAs, telephones), microprocessor-based or programmable consumer or industrial electronic products, etc. The described aspects can also be practiced in a distributed computing environment, where tasks are performed by remote processing devices linked via a communication network. However, some (if not all) aspects of this disclosure can be practiced on a standalone computer. In a distributed computing environment, program modules can reside in both local and remote storage devices.

[0121] As used herein, the terms “component,” “system,” “platform,” “interface,” etc., may refer to and / or include computer-related entities or entities associated with an operable machine computer having one or more specific functions. Entities disclosed herein may be hardware, a combination of hardware and software, software, or software in execution. For example, a component may be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. For illustration, an application running on a server and a server itself can both be components. One or more components may reside in an executing process and / or thread, and components may reside on a single computer and / or be distributed across two or more computers. In another example, individual components may be executable from various computer-readable media on which various data structures are stored. Components may communicate, for example, via local and / or remote processes based on signals having one or more data packets (e.g., data from one component interacts with another component in a local system, a distributed system, and / or interacts with other systems across a network (e.g., the Internet) via signals). As another example, a component may be a device having specific functions provided by a mechanical component operated by electrical or electronic circuitry, the mechanical component being operated by a software or firmware application executed by a processor. In this scenario, the processor can be internal or external to the device and can execute at least a portion of the software or firmware application. As yet another example, the component can be a device that provides specific functionality through electronic components that do not have mechanical components, wherein the electronic components can include a processor or other means to execute software or firmware that at least partially endows the electronic components with functionality. In one aspect, the component can be emulated, for example, via a virtual machine within a cloud computing system.

[0122] Furthermore, the term "or" is intended to indicate an inclusive "or" rather than an exclusive "or". That is, unless otherwise stated or clearly understood from the context, "X uses A or B" refers to any natural inclusive permutation. That is, if X uses A; X uses B; or X uses both A and B, then "X uses A or B" is satisfied in any case. Additionally, the articles "a" and "an" used in the subject matter specification and figures should generally be interpreted as meaning "one or more" unless otherwise stated or clearly indicated from the context as the singular form. The terms "example" and / or "exemplary" are used to indicate that something is used as an example, instance, or illustration. For the avoidance of doubt, the subject matter disclosed herein is not limited to such examples. Furthermore, any aspect or design described herein as "example" and / or "exemplary" is not necessarily to be construed as being more preferred or advantageous than other example aspects or designs, nor does it imply the exclusion of equivalent exemplary structures and techniques known to those skilled in the art.

[0123] As used herein, the term "processor" can refer substantially to any computing processing unit or device, including but not limited to a single-core processor, a single processor with software multithreading capabilities, a multi-core processor, a multi-core processor with software multithreading capabilities, a multi-core processor with hardware multithreading technology, a parallel platform, and a parallel platform with distributed shared memory. Additionally, a processor can refer to an integrated circuit, an application-specific integrated circuit (ASIC), a digital signal processor (DSP), a field-programmable gate array (FPGA), a programmable logic controller (PLC), a complex programmable logic device (CPLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Furthermore, processors can utilize nanoscale architectures, such as, but not limited to, molecular and quantum dot-based transistors, switches, and gates, to optimize space utilization or enhance the performance of user devices. Processors can also be implemented as a combination of computing processing units. In this disclosure, terms such as "storage," "data storage," "database," and substantially any other component relating to the operation and function of an information storage component are used to refer to a "memory component," an entity embodied in "memory," or a component that includes memory. It should be understood that the memory and / or memory components described herein may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. By way of illustration and not limitation, non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), flash memory, or non-volatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM)). Volatile memory may include RAM; for example, RAM may be used as an external cache. By way of illustration and not limitation, RAM comes in various forms, such as synchronous RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), direct Rambus RAM (DRRAM), direct Rambus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM). Furthermore, the memory components of the systems or computer-implemented methods disclosed herein are intended to include, but are not limited to, these and any other suitable types of memory.

[0124] The examples described above are merely examples of systems, computer program products, and computer-implemented methods. Of course, for the purposes of describing this disclosure, it is impossible to describe every possible combination of components, products, and / or computer-implemented methods; however, those skilled in the art will recognize that many further combinations and substitutions of this disclosure are possible. Where the terms “comprising,” “having,” etc., are used in the detailed description, claims, appendices, and drawings, these terms are intended to be interpreted similarly to how the term “comprising” is used as a transitional term in the claims.

[0125] Various embodiments have been described for illustrative purposes, but these descriptions are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, practical application of techniques found in the market or improvements to the technology, or to enable others skilled in the art to understand the patterns disclosed herein.

Claims

1. A computer-implemented system, comprising: Memory stores computer-executable components; A processor executes computer-executable components stored in memory, wherein the computer-executable components include: An analysis component analyzes the response of a multimode readout device weakly coupled to a superconducting qubit without employing a Purcell filter, wherein the multimode readout device generates the response based on simultaneous multitone excitation, and the multimode readout device is coupled to the qubit based on one or more parameters that facilitate at least one of the following: a defined qubit readout fidelity; a defined qubit decay time protection; or a defined qubit phase shift protection; and The allocation component allocates the readout state of the qubits based on the response.

2. The system according to claim 1, wherein, The multi-mode readout device includes a superconducting resonator with multiple probe taps.

3. The system according to claim 1, wherein, The analysis component analyzes the response based on at least one of the following: Boolean logic analysis; kernel integration of the response; temporal trajectory of the response; linear discriminant analysis; quadratic discriminant analysis; or support vector machine analysis.

4. The system according to claim 1, wherein, The allocation component allocates the readout state based on the majority vote of the response.

5. The system according to claim 1, wherein, Based on a defined electrical coupling value, the multi-mode readout device is electrically coupled to at least one of the qubits or the qubit environment, thereby facilitating improved processing accuracy associated with the processor.

6. A computer-implemented method, comprising: The response of a multimode readout device weakly coupled to a superconducting qubit is analyzed by a system operatively coupled to a processor without employing a Purcell filter, wherein the multimode readout device generates the response based on simultaneous multitone excitation, and the multimode readout device is coupled to the qubit based on one or more parameters that facilitate at least one of the following: a defined qubit readout fidelity; a defined qubit decay time protection; or a defined qubit phase shift protection; and The system assigns the readout state of the qubits based on the response.

7. The method according to claim 6, further comprising: The system generates a response based on simultaneous multi-tone excitation.

8. The method according to claim 6, wherein, The analysis includes the system analyzing the response based on at least one of the following: Boolean logic analysis; kernel integrated response; temporal trajectory of the response; linear discriminant analysis; quadratic discriminant analysis; or support vector machine analysis.

9. The method according to claim 6, wherein, The allocation includes the readout state being allocated by the system based on a majority vote of the response.

10. The method according to claim 6, wherein, The analysis includes a system analysis of the response of a multi-mode readout device electrically coupled to at least one qubit or qubit environment based on a defined electrical coupling value.

11. A computer program product that facilitates multi-mode qubit readout and state allocation processes, the computer program product comprising a computer-readable storage medium having program instructions embodied thereon, the program instructions being executed by a processor to cause the processor to: The response of a multimode readout device weakly coupled to a superconducting qubit is analyzed by a processor without employing a Purcell filter, wherein the multimode readout device generates the response based on simultaneous multitone excitation, and the multimode readout device is coupled to the qubit based on one or more parameters that facilitate at least one of the following: a defined qubit readout fidelity; a defined qubit decay time protection; or a defined qubit phase shift protection; and The processor assigns the readout state of the qubits based on the response.

12. The computer program product according to claim 11, wherein, This program instruction is executed by the processor, causing the processor to: The processor analyzes the response based on at least one of the following: Boolean logic analysis; kernel-integrated response; temporal trajectory of the response; linear discriminant analysis; quadratic discriminant analysis; or support vector machine analysis.

13. The computer program product according to claim 11, wherein, This program instruction is executed by the processor, causing the processor to: The processor assigns the readout state based on at least one of the following: a majority vote in response; the defined qubit readout fidelity; the defined qubit decay time protection; or the defined qubit phase shift protection.

14. The computer program product according to claim 11, wherein, The program instructions are executed by the processor, causing the processor to: The processor analyzes the response of a multi-mode readout device electrically coupled to at least one of the qubits or qubit environments based on a defined electrical coupling value.

15. A computer-implemented system, comprising: Memory stores computer-executable components; A processor executes computer-executable components stored in memory, wherein the computer-executable components include: An analysis component analyzes the response of a multimode readout device weakly coupled to a superconducting qubit without employing a Purcell filter, wherein the multimode readout device generates the response based on simultaneous multitone excitation, and the multimode readout device is coupled to the qubit based on one or more parameters that facilitate at least one of the following: a defined qubit readout fidelity; a defined qubit decay time protection; or a defined qubit phase shift protection; and The allocation component allocates the readout state of the qubits based on the response.

16. The system according to claim 15, wherein, The analysis component analyzes the response based on at least one of the following: Boolean logic analysis; kernel integration of the response; temporal trajectory of the response; linear discriminant analysis; quadratic discriminant analysis; or support vector machine analysis.

17. The system according to claim 15, wherein, The allocation component allocates the readout state based on at least one of the following: a majority vote in response; the defined qubit readout fidelity; the defined qubit decay time protection; or the defined qubit phase shift protection, thereby promoting the defined coherence time associated with the qubit.

18. The system according to claim 15, wherein, The multi-mode readout device is electrically coupled to at least one of the qubits or qubit environments based on a defined electrical coupling value.

19. A computer-implemented method, comprising: The response of a multimode readout device weakly coupled to a superconducting qubit is analyzed by a system operatively coupled to a processor without employing a Purcell filter, wherein the readout device generates the response based on simultaneous multitone excitation, and the multimode readout device is coupled to the qubit based on one or more parameters that facilitate at least one of the following: a defined qubit readout fidelity; a defined qubit decay time protection; or a defined qubit phase shift protection; and The system assigns the readout state of the qubits based on the response.

20. The computer-implemented method according to claim 19, wherein, The analysis includes the system analyzing the response based on at least one of the following: Boolean logic analysis; kernel-integrated response; time trajectory of the response; Linear discriminant analysis; quadratic discriminant analysis; or support vector machine analysis.

21. The computer-implemented method according to claim 19, wherein, The allocation includes the system allocating the readout state based on at least one of the following: a majority vote in response, the defined qubit readout fidelity; the defined qubit decay time protection; or the defined qubit phase shift protection.

22. The computer-implemented method according to claim 19, wherein, The analysis includes system analysis of the response of a multi-mode readout device electrically coupled to at least one qubit or qubit environment based on a defined electrical coupling value, thereby facilitating improved processing accuracy associated with the processor.

Images