FPGA-based resequencing analysis method and device

Abstract

The present disclosure proposes a resequencing analysis method and device based on FPGA, wherein the method includes: receiving genome resequencing data; using the resequencing data as the input of FPGA, determining the comparison results in the resequencing process according to the output of FPGA, and at the same time, sorting and de-duplicating the comparison results; correcting the base quality value of the comparison results after sorting and de-duplicating; and detecting the variation results according to the corrected comparison results. This method can save program running time, save computing costs, and improve resequencing efficiency.

Description

Technical Field

[0001] The present disclosure relates to the technical field of bioinformatics analysis, and in particular to a resequencing analysis method and device based on FPGA. Background Art

[0002] With the emergence of second-generation gene sequencing technology, the cost of gene sequencing has dropped rapidly, and the availability of sequencing data has increased. Detection and association studies of variations in the genome can promote the development of the medical field. However, the human genome consists of more than 3 billion base pairs, which is a large number. Therefore, when sequencing and analyzing the human genome, powerful computing power, storage capacity and network bandwidth are required.

[0003] In the related technology, resequencing analysis includes sequencing sequence comparison and variation detection, wherein the sequencing sequence comparison adopts a dynamic seed extension strategy for comparison. When the number of comparison positions obtained by the initial seed length exceeds a fixed value, the seed length is increased for comparison to obtain fewer comparison positions, and then the Smith-Waterman algorithm is used for comparison, and multi-threading is used for variation detection.

[0004] However, in the above method, since the steps are executed serially, there are problems of low execution efficiency and slow analysis rate. Summary of the invention

[0005] The present disclosure proposes a FPGA-based resequencing analysis method and device to save program running time, save computing costs, and improve resequencing efficiency, which is used to solve the technical problems of low execution efficiency and slow analysis rate in the prior art.

[0006] In one aspect, the present disclosure provides a resequencing analysis method based on FPGA, including:

[0007] receiving genome resequencing data;

[0008] The resequencing data is used as the input of the FPGA, and the alignment results in the resequencing process are determined according to the output of the FPGA, and at the same time, the alignment results are sorted and de-duplicated;

[0009] Correcting the base quality value of the comparison results after sorting and deduplication processing; and

[0010] The variation results are detected based on the corrected comparison results.

[0011] The FPGA-based resequencing analysis method of the disclosed embodiment receives genome resequencing data, and then uses the resequencing data as the input of the FPGA, determines the comparison results in the resequencing process according to the output of the FPGA, and at the same time, sorts and removes duplicates from the comparison results, then corrects the base quality value of the comparison results after sorting and de-duplication, and finally detects the variation results according to the corrected comparison results. In the disclosed embodiment, the comparison process, sorting process and de-duplication process can be executed synchronously, thereby saving program running time, saving computing costs, and improving resequencing efficiency.

[0012] In another aspect of the present disclosure, an FPGA-based resequencing analysis device is provided, comprising:

[0013] A receiving module, used for receiving genome resequencing data;

[0014] A processing module, used to use the resequencing data as an input of the FPGA, determine the comparison results in the resequencing process according to the output of the FPGA, and sort and remove duplicates from the comparison results;

[0015] A correction module, used to correct the base quality value of the comparison result after sorting and deduplication processing; and

[0016] The detection module is used to detect the variation results according to the corrected comparison results.

[0017] The FPGA-based resequencing analysis device of the disclosed embodiment receives genome resequencing data, and then uses the resequencing data as the input of the FPGA, determines the comparison results in the resequencing process according to the output of the FPGA, and at the same time, sorts and removes duplicates on the comparison results, then corrects the base quality value of the comparison results after sorting and de-duplication, and finally detects the variation results according to the corrected comparison results. In the disclosed embodiment, the comparison process, sorting process and de-duplication process can be executed synchronously, thereby saving program running time, saving computing costs, and improving resequencing efficiency.

[0018] Another aspect of the embodiments of the present disclosure provides a computer device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the FPGA-based resequencing analysis method as described in the foregoing embodiments of the present disclosure is implemented.

[0019] In yet another aspect of the embodiments of the present disclosure, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer-readable instructions, and the computer-readable instructions are used to enable a computer to execute the FPGA-based resequencing analysis method as described in the aforementioned embodiments of the present disclosure.

[0020] Additional aspects and advantages of the present disclosure will be given in part in the following description and in part will be obvious from the following description or learned through practice of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0022] Figure 1 A schematic diagram of the process of the FPGA-based resequencing analysis method provided in the first embodiment of the present disclosure;

[0023] Figure 2 A schematic diagram of the flow of the FPGA-based resequencing analysis method provided in the second embodiment of the present disclosure;

[0024] Figure 3 The structure of the FPGA-based resequencing analysis system of the present disclosure is shown in FIG. Figure 1 ;

[0025] Figure 4 A schematic diagram of a structure in which ping-pong cache technology is used for acceleration in an embodiment of the present disclosure;

[0026] Figure 5 The structure of the FPGA-based resequencing analysis system of the present disclosure is shown in FIG. Figure 2 ;

[0027] Figure 6 is a schematic diagram of the operating timing in the embodiment of the present disclosure;

[0028] Figure 7 The structure of the FPGA-based resequencing analysis system of the present disclosure is shown in FIG. Figure 3 ;

[0029] Figure 8 This is a flow chart of the FPGA-based resequencing analysis method provided in the third embodiment of the present disclosure;

[0030] Fig. 9 This is a schematic diagram of the structure of the FPGA-based resequencing analysis device provided in the fourth embodiment of the present disclosure;

[0031] Fig.10 This is a schematic diagram of the structure of the FPGA-based resequencing analysis device provided in Example 5 of the present disclosure. DETAILED DESCRIPTION

[0032] Embodiments of the present disclosure are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present disclosure, and should not be construed as limiting the present disclosure.

[0033] The following describes the FPGA-based resequencing analysis method and device of the embodiment of the present disclosure with reference to the accompanying drawings. Before describing the embodiment of the present invention in detail, for ease of understanding, the commonly used technical terms are first introduced:

[0034] FPGA, Field-Programmable Gate Array, is a configurable integrated circuit that contains a programmable wiring network that connects logic array modules, embedded memory modules, and digital signal processor (DSP) modules together, while the data paths and topologies of the central processing unit (CPU) and graphics processing unit (GPU) processing program instructions are fixed. In addition, FPGA resources can be configured and connected to establish customized instruction pipelines to process data. This architecture can solve many types of computing problems very efficiently. In addition, maturely developed and widely used applications can also rely on FPGAs to provide the basis and verification for the design of faster but less flexible application-specific integrated circuits (ASICs).

[0035] Resequencing refers to sequencing the genomes of different individuals of a species with a known genome sequence, and performing differential analysis on individuals or groups based on this. For individuals with genome sequencing, a large number of single nucleotide polymorphism sites and insertion and deletion sites can be determined through variation detection.

[0036] Figure 1 This is a schematic diagram of the flow of the FPGA-based resequencing analysis method provided in the first embodiment of the present disclosure.

[0037] The embodiment of the present disclosure takes the FPGA-based resequencing analysis method configured in an FPGA-based resequencing analysis apparatus as an example. The FPGA-based resequencing analysis apparatus can be configured in any computer device so that the computer device can perform the FPGA-based resequencing analysis function.

[0038] like Figure 1As shown, the FPGA-based resequencing analysis method includes the following steps:

[0039] Step 101, receiving genome resequencing data.

[0040] In the disclosed embodiment, the genome resequencing data includes: genome resequencing basic data and parameter information describing the basic data.

[0041] Optionally, the genome resequencing data may be written into a preset file in advance, and when the genome is resequenced, the preset file may be read, and the genome resequencing data may be obtained according to the preset file.

[0042] Furthermore, generally, the preset file is saved as a compressed file, for example, saved in a format such as gz, and therefore, before reading the preset file, the preset file may be decompressed.

[0043] Step 102, using the resequencing data as the input of the FPGA, determining the comparison results in the resequencing process according to the output of the FPGA, and at the same time, sorting and removing duplicates from the comparison results.

[0044] In the disclosed embodiment, the genome resequencing data can be compared and positioned on the reference genome to obtain the corresponding comparison position and other information, and then the obtained information is transmitted to the FPGA, and the FPGA calculates the comparison result to obtain the comparison result. As a possible implementation method, in order to improve the comparison efficiency, the genome resequencing data can be divided into multiple fixed-length genome resequencing sub-data according to the parallel processing characteristics of the FPGA, and then the multiple fixed-length genome resequencing sub-data are respectively compared with the reference genome at the same time to obtain multiple comparison sub-results, and finally the multiple comparison sub-results are combined to obtain the comparison result.

[0045] At the same time, when the comparison results are obtained, the comparison results can be sorted according to the comparison position on the reference genome, and the resequencing data of the same comparison position can be deduplicated. The reason is that repeated resequencing data will affect the comparison evaluation such as sequencing depth, and ultimately lead to false positives in gene mutation detection. Therefore, the resequencing data of the same comparison position can be deduplicated.

[0046] Optionally, bioinformatics software and alignment scripts can be called to align the resequencing data to determine the alignment results in the resequencing process, and then the alignment results are sorted and de-duplicated according to the bioinformatics software and sorting and de-duplication scripts to determine the alignment results after sorting and de-duplication. Among them, bioinformatics software includes: BuildAlignerIndex, Alignment, SortMarkDup, BuildBQSRIndex, BQSR and HaplotypeCaller, etc.

[0047] For example, the resequencing data can be compared based on high-performance DNA sequence comparison software accelerated by FPGA. This comparison software can support 33 to 160bp double-end short read comparison. Then, based on high-performance sorting and deduplication software accelerated by multi-threading, the results are sorted and deduplicated. This sorting and deduplication software supports pipeline input and output to improve the efficiency of sorting and deduplication.

[0048] In the disclosed embodiment, the comparison process, the sorting process and the de-duplication process can be executed synchronously, thereby saving program running time, saving computing costs and improving resequencing efficiency.

[0049] Step 103, calibrating the base quality value of the comparison result after sorting and deduplication processing.

[0050] In the disclosed embodiment, in order to make the base quality values ​​in the comparison results close to the truth and reduce the probability of mismatch with the reference genome, the base quality values ​​of the comparison results after sorting and deduplication processing can be corrected, that is, the base quality values ​​are calibrated internally in the data.

[0051] Optionally, bioinformatics software and base quality value correction scripts can be called to correct the base quality values ​​of the comparison results after sorting and deduplication processing to obtain a corrected comparison result. For example, high-performance base quality value correction software based on multi-threaded acceleration can be used to correct the base quality values ​​of the comparison results after sorting and deduplication processing. The correction software can support pipeline input and output to improve the efficiency of correction.

[0052] Step 104, detecting the variation results according to the corrected comparison results.

[0053] In the disclosed embodiment, the detection of the variation result includes: single nucleotide polymorphism site detection, insertion and deletion site detection. The variation result can be detected based on the corrected comparison result and related information.

[0054] Optionally, bioinformatics software and variation detection scripts may be called to detect variation results on the corrected comparison results to determine the detection results. For example, high-performance variation detection software accelerated by FPGA may be used to detect variation results on the corrected comparison results to obtain variation detection results, thereby improving the efficiency of variation detection.

[0055] The FPGA-based resequencing analysis of the disclosed embodiment receives genome resequencing data, and then uses the resequencing data as the input of the FPGA, determines the comparison results in the resequencing process according to the output of the FPGA, and at the same time, sorts and removes duplicates from the comparison results, then corrects the base quality value of the comparison results after sorting and de-duplication, and finally detects the variation results according to the corrected comparison results. In the disclosed embodiment, the comparison process, sorting process and de-duplication process can be executed synchronously, thereby saving program running time, saving computing costs, and improving resequencing efficiency.

[0056] As a possible implementation method, after receiving the genome resequencing data, the genome resequencing data can also be hashed based on a preset length sequence, and the genome resequencing data after the hashing operation can be used as the input of the FPGA. In this way, the comparison position of the genome can be quickly located, reducing random memory access and improving comparison efficiency.

[0057] In order to clearly illustrate the above embodiment, the present disclosure provides another FPGA-based resequencing analysis method.

[0058] Figure 2 This is a flow chart of the FPGA-based resequencing analysis method provided in the second embodiment of the present disclosure.

[0059] like Figure 2 As shown, the FPGA-based resequencing analysis method may include the following steps:

[0060] Step 201 : receiving genome resequencing data, wherein the genome resequencing data includes: genome resequencing basic data, and parameter information describing the basic data.

[0061] For example, see Figure 3 , Figure 3 The structure of the FPGA-based resequencing analysis system of the present disclosure is shown in FIG. Figure 1 The resequencing analysis system includes: a task scheduling unit 1, an analysis unit 2 and a result generation unit 3. The task scheduling unit 1 is used to receive genome resequencing basic data and parameter information describing the basic data.

[0062] Step 202, based on the basic data and parameter information describing the basic data, determine a first task for inputting the comparison result and determine a second task for performing sorting and deduplication processing.

[0063] In the disclosed embodiment, in order to improve the efficiency of resequencing, thereby saving program running time and computing costs, the comparison process, sorting process and deduplication process can be executed simultaneously. Therefore, after receiving the genome resequencing data, the first task for inputting the comparison result and the second task for performing sorting and deduplication processing can be determined based on the basic data and the parameter information describing the basic data.

[0064] For example, see Figure 3 The task scheduling unit 1 can determine the first task for inputting the comparison result and the second task for sorting and deduplication processing according to the basic data and the parameter information describing the basic data, and then send the first task and the second task to the analysis unit 2, and process the scheduling of the analysis unit 2. For example, the process scheduling of the analysis unit 2 can be realized through bioinformatics software and system scheduling scripts.

[0065] Step 203: allocate corresponding threads to the first task from the FPGA and allocate corresponding threads to the second task from the CPU.

[0066] In the embodiment of the present disclosure, after the first task and the second task are determined, a corresponding thread may be allocated to the first task from the FPGA and a corresponding thread may be allocated to the second task from the CPU.

[0067] Step 204 , start and execute the threads corresponding to the first task and the second task in parallel, and call the resequencing data via the corresponding threads.

[0068] In the embodiment of the present disclosure, after determining the threads corresponding to the first task and the second task, the threads corresponding to the first task and the second task can be started and executed simultaneously, and the resequencing data can be called through each corresponding thread to perform a comparison process, a sorting process and a deduplication process.

[0069] Step 205 , determining the comparison result in the resequencing process through the output result of the thread corresponding to the first task, and at the same time, sorting and deduplicating the comparison result through the output result of the thread corresponding to the second task.

[0070] In the disclosed embodiment, after the resequencing data is called by the thread corresponding to the first task, the alignment result in the resequencing process can be determined according to the output result of the thread corresponding to the first task. As a possible implementation method, the thread corresponding to the first task can be executed to determine the target alignment position, and then the alignment of repeated base pairs in the genome resequencing basic data is triggered according to the target alignment position, and finally the alignment result of the repeated base pairs is used as the alignment result in the resequencing process. For example, see Figure 3 The analysis unit 2 can analyze the genome resequencing data and determine the comparison result by calling the bioinformatics software and the comparison script in a process-oriented manner, and by accelerating the software and calling the thread corresponding to the first task in the FPGA.

[0071] In the embodiment of the present disclosure, the thread corresponding to the second task can call the comparison result, and sort and remove duplicates from the comparison result. Figure 3 The analysis unit 2 can call the bioinformatics software and the sorting and deduplication script in a process-oriented manner, and can perform sorting and deduplication processing on the comparison results by accelerating the software and calling the thread corresponding to the second task in the CPU.

[0072] Step 206, calibrating the base quality value of the comparison result after sorting and deduplication processing.

[0073] Step 207, detecting the variation results according to the corrected comparison results.

[0074] For example, see Figure 3 , the analysis unit 2 can process-call the bioinformatics software and the base quality value correction script to correct the base quality value of the comparison result after the sorting and deduplication processing. And, the analysis unit 2 process-calls the bioinformatics software and the variation detection script, and detects the variation result according to the corrected comparison result to obtain the variation detection result.

[0075] Further, see Figure 3 , the result generating unit 3 is used to send the variation detection result obtained by the analysis unit 2 to a designated location according to the parameter information describing the basic data transmitted by the task scheduling unit 1 after obtaining the variation detection result.

[0076] In the disclosed embodiment, the genome resequencing efficiency can be improved by calling bioinformatics software and personalized analysis scripts, accelerating the software, and calling resources in the FPGA to analyze the genome resequencing data.

[0077] As a possible implementation method, the target comparison position can be cached using ping-pong cache technology, for example, see Figure 4 , Figure 4This is a schematic diagram of the structure of using ping-pong cache technology for acceleration in the embodiment of the present disclosure. Ping-pong cache technology is used to cache the data in the FPGA global memory. The reason is that the CPU-side read / write operation of the FPGA global memory can be performed synchronously with the FPGA kernel module operation, thereby improving the operation efficiency.

[0078] If the traditional "write global memory → run kernel → read global memory" serial operation mode is used, the FPGA operation module will be in a waiting I / O state for a period of time, resulting in low operation efficiency. Therefore, the ping-pong cache technology is used to cache the data of the FPGA global memory, such as the target comparison position, so that the FPGA operation module is always in an efficient working state, and multiple subtasks of a single task can be executed in a pipelined manner to achieve parallel processing of tasks. For example, see Figure 4 ,In time slice C3, task T1 reads back from output cache 1, task T2 calculates using cache 2 data, and task T3 writes to input cache 1 can be performed simultaneously.

[0079] As an example, see Figure 5 , Figure 5 The structure of the FPGA-based resequencing analysis system of the present disclosure is shown in FIG. Figure 2 The resequencing analysis system includes: an alignment module 4 , a sorting and deduplication module 5 , a base quality value correction module 6 and a variation detection module 7 .

[0080] Among them, the comparison module 4 is used to compare the received genome resequencing data with the reference genome, and then transmit the compared data to the FPGA for calculation to obtain the comparison result, which can be stored in a SAM format file.

[0081] The sorting and deduplication module 5 is used to sort the data output by the comparison module 4 according to the comparison position, and then mark and filter the repeated data. The sorting and deduplication results can be stored in a file in BAM format.

[0082] The base quality value correction module 6 is used to correct the base quality value of the data output by the sorting and deduplication module 5. The correction result can be stored in a file in BAM format.

[0083] The variation detection module 7 is used to perform variation detection on the data output by the base quality value correction module 6 by calling bioinformatics software and analysis scripts, including single nucleotide polymorphism site detection and insertion and deletion site detection. The detection results can be stored in files in VCF or gVCF format.

[0084] As an example, see Figure 6 , Figure 6 Schematic diagram of the operating timing in the embodiment of the present disclosure. Figure 6 In the Fastq input file, the entire calculation process is optimized into a pipeline structure by adjusting the calculation mode of the data between adjacent steps and adding corresponding input and output buffers.

[0085] Specifically, the comparison module runs at the beginning of the program, compares the genome retest data in the input file to the reference genome, and outputs the comparison results to the sorting and deduplication module.

[0086] The sorting and deduplication module runs synchronously with the comparison module, sorts the output data of the comparison module according to the comparison position, and then marks and filters the duplicate data.

[0087] The base quality value correction module is run after the comparison module is completed. It runs synchronously with the sorting and deduplication module to correct the base quality values ​​of the sorted and deduplicated data.

[0088] The variation detection module is used to perform variation detection on the data output by the base quality value correction module by calling bioinformatics software and analysis scripts, including single nucleotide polymorphism site detection and insertion and deletion site detection.

[0089] In the disclosed embodiments, the genome resequencing analysis process is accelerated and the genome resequencing efficiency is improved by invoking bioinformatics software and analysis scripts in a streamlined manner.

[0090] As an example, see Figure 7 , Figure 7 The structure of the FPGA-based resequencing analysis system of the present disclosure is shown in FIG. Figure 3 .

[0091] The CPU reads the input file (Fastq), stores the data to be calculated in the memory, and transmits the data in the memory to the global memory of the FPGA through the bus and interface standards. The input data is processed, compared, and the results are recorded and output in the FPGA, and the results are stored in the global memory. After that, the FPGA transmits the processed data to the CPU memory through the bus and interface standards for subsequent processing, and outputs a file in SAM format.

[0092] In the disclosed embodiment, a heterogeneous CPU and FPGA are used to achieve high-speed comparison of genome retest data. The parallel preprocessing and subsequent processing of data can be achieved through CPU multi-threading technology. The FPGA uses multiple functional modules in a channel-connected manner to achieve fine-grained data pipeline operations.

[0093] As a possible implementation method, in FPGA, I / O read and write operations can be separated from compression / decompression operations. By using circular cache and multi-threading, compression / decompression operations can be performed in parallel, thereby improving the efficiency of genome resequencing.

[0094] As an example, see Figure 8 , Figure 8 This is a flow chart of the FPGA-based resequencing analysis method provided in the third embodiment of the present disclosure.

[0095] like Figure 8 As shown, the FPGA-based resequencing analysis method may include the following steps:

[0096] 300, the mission begins.

[0097] 301, program call, parameter setting and initialization. Specifically, after all parameters are initialized, task scheduling is started, and basic genome resequencing data and parameter information describing the basic data are received.

[0098] 302, determine whether to build a comparison index, if so, execute step 316.

[0099] 303, determine whether to construct a base quality value correction index, if so, execute step 313.

[0100] 304 or 317, determine whether to compare, if so, execute step 318.

[0101] 305, determine whether to sort and remove duplicates, if so, execute 319.

[0102] 306 , determining whether to calibrate the base quality value, if so, executing step 320 .

[0103] 307, determine whether to compare and sort to remove duplicates, if so, execute step 321.

[0104] 308, determine whether to copy the comparison result, if so, execute step 322.

[0105] 309 or 314, determine whether to calibrate the base quality value, if so, execute step 315.

[0106] 310 , determine whether to copy the base quality value correction result, if so, execute step 323 .

[0107] 311, determine whether to perform mutation detection, if so, execute step 324.

[0108] 312, wait for all processes to complete.

[0109] 313, construct base quality value correction index.

[0110] 315, call base quality value correction.

[0111] 316, build an alignment index for rapid alignment of genome resequencing data to a reference genome.

[0112] 318, call the comparison, compare the genome resequencing data to the reference genome on the CPU side, obtain the corresponding comparison position and other information, and transmit the obtained information to the FPGA for comparison calculation, and the FPGA sends the comparison result to the CPU side.

[0113] 319, call sorting and deduplication.

[0114] 320, calling base quality value correction to make the base quality value close to the truth and reduce the mismatch rate with the reference genome.

[0115] 321, call the alignment sorting to remove duplicates, and use the alignment position and other information to filter out repeated gene sequences in the alignment results. Repeated gene sequences are mainly generated by sequencing PCR, which will affect the comparison evaluation such as sequencing depth, and ultimately lead to false positives in gene mutation detection. The alignment results are generally stored in SAM / BAM format files.

[0116] 322, call the copy comparison result, which can be called in the background.

[0117] 323, call the copy base quality value correction result, which can be called in the background.

[0118] 324, call mutation detection.

[0119] 325, mission completed.

[0120] It should be noted that, in terms of hardware, FPGA acceleration cards can also be used to improve the resequencing efficiency, or GPUs can be used to improve the resequencing efficiency. In addition, the FPGA-based resequencing analysis system disclosed in the present invention is composed of multiple modules. The improvement, deformation, and replacement of any module method, for example, the use of the bwt algorithm to replace the comparison, all fall within the protection scope of the present disclosure. Therefore, whether hardware is used to accelerate the comparison of the bwt algorithm or the bwt algorithm is directly used to replace the comparison, the technical effect achieved by the present disclosure can be achieved.

[0121] As an example:

[0122] The following publicly available data was used for testing:

[0123] The data webpage path is as follows: http: / / gigadb.org / dataset / 100274

[0124] Data Path:

[0125] ftp: / / parrot.genomics.cn / gigadb / pub / 10.5524 / 100001_101000 / 100274 / CL100008589_L02_read_1.fq.gz

[0126] ftp: / / parrot.genomics.cn / gigadb / pub / 10.5524 / 100001_101000 / 100274 / CL100008589_L02_read_2.fq.gz

[0127] The process in the related technology is as follows BWA+GATK:

[0128] 1. Compare and sort to remove duplicates

[0129] Comparison and sorting:

[0130] . / BIN / bwa-0.7.13 / bwa mem-t 72-MY\

[0131] -R"@RG\tID:PE100\tPL:Illumina\tPU:PE100\tLB:NA12878\tSM:PE100\tCN:NIST"\

[0132] . / REF_hs37d5 / hs37d5 / hs37d5.fa\

[0133] . / read_1.fq.gz. / read_2.fq.gz\

[0134] |. / BIN / samtools-1.3 / bin / samtools view-buhS\

[0135] -t. / REF_hs37d5 / hs37d5 / hs37d5.fa.fai-\

[0136] |. / BIN / samtools-1.3 / bin / samtools sort-m 1000000000\

[0137] -T. / PE100.sort\

[0138] -o . / PE100.1.sorted.bam –

[0139] Deduplication:

[0140] . / BIN / jdk1.8.0_131 / bin / java-jar . / BIN / picard.jar MarkDuplicates\

[0141] I=. / PE100.1.sorted.bam\

[0142] O = . / PE100.2.rmdup.bam\

[0143] M = . / PE100.2.rmdup.mat\

[0144] REMOVE_DUPLICATES=false\

[0145] TMP_DIR=. / tmp

[0146] Create index:

[0147] . / BIN / samtools-1.3 / bin / samtools index\

[0148] . / PE100.2.rmdup.bam

[0149] 2. Base quality value correction

[0150] . / BIN / jdk1.8.0_131 / bin / java

[0151] -jar. / GATK_stat / lib / GenomeAnalysisTK.3.7-0 / GenomeAnalysisTK.jar\

[0152] --disable_auto_index_creation_and_locking_when_reading_rods\

[0153] -T BaseRecalibrator\

[0154] -nct 72\

[0155] -R REF_hs37d5 / hs37d5 / hs37d5.fa\

[0156] -I. / PE100.2.rmdup.bam\

[0157] -o . / PE100.4.bqsr.grp\

[0158] -knownSites. / REF_hs37d5 / GATK.b37 / Mills_and_1000G_gold_standard.indels.b37.vcf

[0159] -knownSites. / REF_hs37d5 / GATK.b37 / 1000G_phase1.indels.b37.vcf

[0160] -knownSites. / REF_hs37d5 / dbsnp_GRCh37_b149 / dbsnp-149.vcf

[0161] PrintReads:

[0162] . / BIN / jdk1.8.0_131 / bin / java

[0163] -jar. / GATK_stat / lib / GenomeAnalysisTK.3.7-0 / GenomeAnalysisTK.jar

[0164] --disable_auto_index_creation_and_locking_when_reading_rods

[0165] -T PrintReads

[0166] -nct 72

[0167] -R REF_hs37d5 / hs37d5 / hs37d5.fa

[0168] -I. / PE100.2.rmdup.bam

[0169] -BQSR. / PE100.4.bqsr.grp

[0170] -o. / PE100.4.bqsr.bam

[0171] -baqGOP 30

[0172] Build index:

[0173] . / BIN / samtools-1.3 / bin / samtools index

[0174] . / PE100.4.bqsr.bam

[0175] 3. Mutation detection

[0176] . / BIN / jdk1.8.0_131 / bin / java

[0177] -jar. / GATK_stat / lib / GenomeAnalysisTK.3.7-0 / GenomeAnalysisTK.jar\

[0178] --disable_auto_index_creation_and_locking_when_reading_rods\

[0179] -R REF_hs37d5 / hs37d5 / hs37d5.fa\

[0180] -T HaplotypeCaller\

[0181] -nct 72\

[0182] -I. / PE100.4.bqsr.bam\

[0183] --dbsnp. / REF_hs37d5 / dbsnp_GRCh37_b149 / dbsnp-149.vcf\

[0184] -stand_call_conf 10.0\

[0185] -o . / raw.snp_indel.vcf

[0186] The disclosure process is as follows:

[0187] MegaBOLT-type allwithindex-list. / my.list-scalafile. / my.scala

[0188] -ref. / REF_hs37d5 / hs37d5 / hs37d5.fa-alignerindex. / REF_hs37d5 / hs37d5 / hs37d5.fa

[0189] -bqsrindex. / REF_hs37d5 / hs37d5 / bqsrRef

[0190] -vcf. / REF_hs37d5 / dbsnp_GRCh37_b149 / dbsnp-149.vcf

[0191] Table 1, Process running time comparison

[0192] Dataset Number of bases (Gbp) process Running time (hours) Paired-end 100bp 114 MegaBOLT 2.4 BWA+GATK 59.0

[0193] Table 2. Comparison of mutation detection results evaluation

[0194]

[0195] From the above results, it can be seen that, as shown in Table 1, the running time of the present disclosure is about 20 times faster than that of the process in the related art; as shown in Table 2, compared with the process in the related art, the accuracy and sensitivity of SNP in the present disclosure are basically consistent, the accuracy of INDEL is slightly worse than that of the process in the related art, and the sensitivity remains basically the same, and the overall result is comparable to the process in the related art.

[0196] In order to implement the above embodiments, the present disclosure also proposes a resequencing analysis device based on FPGA.

[0197] Fig. 9 This is a schematic diagram of the structure of the FPGA-based resequencing analysis device provided in the fourth embodiment of the present disclosure.

[0198] like Fig. 9 As shown, the FPGA-based resequencing analysis device 100 includes: a receiving module 110 , a processing module 120 , a correction module 130 , and a detection module 140 .

[0199] The receiving module 110 is used to receive genome resequencing data.

[0200] The processing module 120 is used to use the resequencing data as the input of the FPGA, determine the comparison results in the resequencing process according to the output of the FPGA, and sort and remove duplicates from the comparison results.

[0201] The correction module 130 is used to correct the base quality value of the comparison result after the sorting and deduplication processing.

[0202] The detection module 140 is used to detect the variation result according to the corrected comparison result.

[0203] Further, in a possible implementation of the embodiment of the present disclosure, see Fig.10 ,exist Fig. 9 Based on the illustrated embodiment, the FPGA-based resequencing analysis device 100 may further include:

[0204] The operation module 150 is used to perform a hash operation on the genome resequencing data based on a sequence of a preset length after receiving the genome resequencing data.

[0205] Correspondingly, the processing module 120 is specifically used to: use the genome resequencing data after the hash operation as the input of the FPGA.

[0206] As a possible implementation manner, the genome resequencing data includes: genome resequencing basic data, and parameter information describing the basic data.

[0207] The determination module 160 is used to determine, after receiving the genome resequencing data, a first task for inputting the comparison result and a second task for performing sorting and deduplication processing based on the basic data and parameter information describing the basic data.

[0208] The allocation module 170 is used to allocate a corresponding thread to the first task from the FPGA and allocate a corresponding thread to the second task from the CPU.

[0209] The processing module 120 includes:

[0210] The start execution unit 121 is used to start and execute the threads corresponding to the first task and the second task in parallel, and call the resequencing data through each corresponding thread.

[0211] The determination processing unit 122 is used to determine the comparison result in the resequencing process through the output result of the thread corresponding to the first task, and at the same time, sort and remove duplicates from the comparison result through the output result of the thread corresponding to the second task.

[0212] As a possible implementation method, the processing unit 122 is determined to be specifically used for: executing the thread corresponding to the first task to determine the target comparison position; triggering the comparison of repeated base pairs in the genome resequencing basic data according to the target comparison position; and using the comparison result of the repeated base pairs as the comparison result in the resequencing process.

[0213] As another possible implementation, the determination processing unit 122 is further configured to: perform cache processing on the target comparison position by using a ping-pong cache technology.

[0214] It should be noted that the above explanation of the embodiment of the FPGA-based resequencing analysis method is also applicable to the FPGA-based resequencing analysis device 100 of this embodiment, and will not be repeated here.

[0215] The FPGA-based resequencing analysis device of the disclosed embodiment receives genome resequencing data, and then uses the resequencing data as the input of the FPGA, determines the comparison results in the resequencing process according to the output of the FPGA, and at the same time, sorts and removes duplicates on the comparison results, then corrects the base quality value of the comparison results after sorting and de-duplication, and finally detects the variation results according to the corrected comparison results. In the disclosed embodiment, the comparison process, sorting process and de-duplication process can be executed synchronously, thereby saving program running time, saving computing costs, and improving resequencing efficiency.

[0216] In order to implement the above embodiments, the present disclosure also proposes a computer device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, the FPGA-based resequencing analysis method proposed in the above embodiments of the present disclosure is implemented.

[0217] In order to implement the above embodiments, the present disclosure further proposes a computer-readable storage medium, which stores computer-readable instructions, and the computer-readable instructions are used to enable a computer to execute the FPGA-based resequencing analysis method proposed in the above embodiments of the present disclosure.

[0218] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0219] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of the present disclosure, "plurality" means at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0220] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code that includes one or more executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present disclosure includes additional implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present disclosure belong.

[0221] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute the instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purpose of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection with one or more wires (electronic device), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), a fiber optic device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing in other suitable ways if necessary, and then stored in a computer memory.

[0222] It should be understood that the various parts of the present disclosure can be implemented in hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, multiple steps or methods can be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof can be used to implement: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0223] A person skilled in the art may understand that all or part of the steps in the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiment.

[0224] In addition, each functional unit in each embodiment of the present disclosure may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0225] The storage medium mentioned above may be a read-only memory, a disk or an optical disk, etc. Although the embodiments of the present disclosure have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations of the present disclosure. A person of ordinary skill in the art may change, modify, replace and modify the above embodiments within the scope of the present disclosure.

Claims

1. A resequencing analysis method based on FPGA, characterized in that: The following steps are involved: Receiving genome resequencing data, including: genome resequencing basic data, and parameter information describing the basic data; after receiving the genome resequencing data, determining a first task for inputting a comparison result and a second task for performing a sorting and deduplication process according to the basic data and the parameter information describing the basic data; Allocating a corresponding thread for the first task from the FPGA and allocating a corresponding thread for the second task from the CPU; The resequencing data is used as an input of the FPGA, and the alignment result in the resequencing process is determined according to the output of the FPGA. Meanwhile, the alignment result is sorted and de-duplicated, including: Starting and executing the threads corresponding to the first task and the second task in parallel, and calling the resequencing data via the corresponding threads; Determine the comparison result in the resequencing process through the output result of the thread corresponding to the first task, and at the same time, sort and remove duplicates from the comparison result through the output result of the thread corresponding to the second task; Correcting the base quality value of the comparison results after sorting and deduplication processing; and The variation results are detected based on the corrected comparison results.

2. The FPGA-based resequencing analysis method according to claim 1, characterized in that: After receiving the genome resequencing data, the method further includes: Performing a hash operation on the genome resequencing data based on a sequence of a preset length; The using the resequencing data as an input of the FPGA comprises: The genome resequencing data after the hash operation is used as the input of the FPGA.

3. The FPGA-based resequencing analysis method according to claim 1, characterized in that: The determining the comparison result in the resequencing process through the output result of the thread corresponding to the first task includes: Execute the thread corresponding to the first task to determine the target comparison position; Triggering the alignment of repeated base pairs in the genome resequencing basic data according to the target alignment position; The alignment result of the repeated base pairs is used as the alignment result in the resequencing process.

4. The FPGA-based resequencing analysis method according to claim 3, characterized in that: After determining the target comparison position, the method further includes: The target comparison position is cached using ping-pong cache technology.

5. A resequencing analysis device based on FPGA, characterized in that: include: A receiving module, used to receive genome resequencing data, including: genome resequencing basic data, and parameter information describing the basic data; A determination module, configured to determine, after receiving the genome resequencing data, a first task for outputting an alignment result and a second task for performing a sorting and deduplication process based on the basic data and parameter information describing the basic data; An allocation module, configured to allocate a corresponding thread to the first task from the FPGA and allocate a corresponding thread to the second task from the CPU; A processing module is used to use the resequencing data as an input of the FPGA, determine the comparison results in the resequencing process according to the output of the FPGA, and sort and remove duplicates from the comparison results, including: A start execution unit is used to start and execute the threads corresponding to the first task and the second task in parallel, and call the resequencing data through each of the corresponding threads; a determination processing unit, configured to determine the comparison result in the resequencing process through the output result of the thread corresponding to the first task, and at the same time, to sort and remove duplicates from the comparison result through the output result of the thread corresponding to the second task; A correction module, used to correct the base quality value of the comparison result after sorting and deduplication processing; and The detection module is used to detect the variation results according to the corrected comparison results.

6. The FPGA-based resequencing analysis device according to claim 5, characterized in that: The device also includes: A calculation module, used for performing a hash operation on the genome resequencing data based on a sequence of a preset length after the genome resequencing data is received; The processing module is specifically used for: The genome resequencing data after the hash operation is used as the input of the FPGA.

7. The FPGA-based resequencing analysis device according to claim 5, characterized in that: The determination processing unit is specifically used for: Execute the thread corresponding to the first task to determine the target comparison position; Triggering the alignment of repeated base pairs in the genome resequencing basic data according to the target alignment position; The alignment result of the repeated base pairs is used as the alignment result in the resequencing process.

8. The FPGA-based resequencing analysis device according to claim 7, characterized in that: The determination processing unit is further used for: The target comparison position is cached using ping-pong cache technology.

9. A computer device, characterized in that: include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the FPGA-based resequencing analysis method as described in any one of claims 1 to 4 is implemented.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-readable instructions, and the computer-readable instructions are used to enable a computer to execute the FPGA-based resequencing analysis method described in any one of claims 1-4.

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