Wafer reassembly and die splicing

Abstract

A stitched die packaging technique and structure is described, wherein a reconstituted chip is formed using wafer reconstitution and die stitching techniques. In one embodiment, the chip includes a reconstituted back-end-of-line (BEOL) build-up structure (310) to connect a set of dies (110, 110) embedded in an inorganic gap filler material (130).

Description

[0001] Related patent applications

[0002] This patent application claims the benefit of priority to U.S. Provisional Patent Application Serial No. 62 / 773135, filed on November 29, 2018, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] Embodiments described herein relate to integrated circuit (IC) fabrication and the interconnection of multiple dies. Background Art

[0004] A multi-chip module (MCM) is typically an electronic component in which multiple dies are integrated on a substrate. Various embodiments of MCM include 2D, 2.5D, and 3D packaging. Generally speaking, a 2D package module includes multiple dies arranged side by side on a package substrate. In 2.5D packaging technology, multiple dies are bonded to an interposer using microbumps. The interposer is then bonded to the package substrate. The interposer may include wiring for interconnecting adjacent dies. Therefore, the dies in a 2.5D package can be directly connected to the interposer and connected to each other through wiring within the interposer. Generally speaking, a 3D package module includes multiple dies stacked vertically on top of each other. Therefore, the dies in a 3D package can be directly connected to each other, with the bottom die directly connected to the package substrate. The top die in a 3D package can be connected to the package substrate using various configurations, including wirebonds and through-silicon vias (TSVs) passing through the bottom die.

[0005] Chip-on-wafer (CoW) is a specific side-by-side packaging configuration that can be used to provide dense wiring, heterogeneous integration, and is scalable. In certain configurations, hybrid bonding between the die and the interposer can be used along with metal-to-metal bonding and oxide-to-oxide bonding to achieve high connection density by avoiding the use of solder bumps for the die-to-interposer connection. Summary of the Invention

[0006] A chip-type die packaging solution including wafer reassembly and die splicing technology is described. In one embodiment, a chip includes: a reassembled chip-level back-end-of-the-line (BEOL) build-up structure including a plurality of interconnected die sets on the reassembled chip-level BEOL build-up structure; and an inorganic gap filler material on the reassembled chip-level BEOL build-up structure and surrounding the die sets. The inorganic gap filler material can be made of, for example, oxides, oxynitrides (e.g., SiO x N y), multiple oxynitride or silicon matrices with variable ratios and thicknesses. In one embodiment, the reconstituted chip-level BEOL buildup structure includes intra-die interconnects for a first die in the die set, intra-die interconnects for a second die in the die set, and die-to-die interconnects between the first die and the second die. The wafer reconstitution sequence can be performed using both die face-up and face-down processing sequences. In one embodiment, a method for manufacturing a reconstituted wafer includes mounting a plurality of sets of die sets face-down on a first carrier substrate; depositing a gap fill material onto the first carrier substrate and laterally surrounding each die in the plurality of sets of die sets, bonding a second carrier substrate opposite to the first carrier substrate, and removing the first carrier substrate. For example, the gap fill material may include an inorganic matrix material, such as oxide or silicon. The reconstituted chip-level BEOL buildup structure can then be formed on the front side of the plurality of sets of die sets and the gap fill material. In one embodiment, the backside reconstituted chip-level BEOL buildup structure is formed on exposed through-silicon vias on the backside of the plurality of sets of die sets.

[0007] In one embodiment, a method for manufacturing a reconstituted wafer includes mounting a plurality of die assemblies face-up on a first carrier substrate, and depositing a gap filler material onto the first carrier substrate laterally surrounding each die in the plurality of die assemblies. For example, the gap filler material may include an inorganic matrix material such as an oxide or silicon. A reconstituted chip-level BEOL buildup structure may then be formed over the plurality of die assemblies and the gap filler material.

[0008] The wafer reconstitution sequence according to the embodiment can be extended to 3D packaging solutions, such as a stacked wafer (or wafer-to-wafer) process, which includes bonding a first reconstitution wafer of known good die to a second reconstitution wafer of known good die, and then singulating multiple 3D reconstituted chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 Schematic cross-sectional side view illustration of CoW packaging technology.

[0010] Figure 2 Schematic cross-sectional side view illustration of a die-to-interposer CoW interface.

[0011] Figure 3 is a schematic cross-sectional side view illustration of a chip fabricated using wafer reassembly and die bonding techniques according to one embodiment.

[0012] Figure 4 Back-end-of-the-line routing for contacting inner chip layers is shown according to one embodiment.

[0013] Figure 5Back-end-of-line routing for contacting the top metal layer is shown according to one embodiment.

[0014] Figure 6 Back-end process routing for vias and pads built into the original die is shown according to one embodiment.

[0015] 7A to 7C is a schematic cross-sectional side view illustration of a die-level BEOL build-up structure processing sequence according to one embodiment.

[0016] Figure 8 is a process flow diagram of a die face-down processing sequence before alignment for a wafer reassembly and die splicing technique according to one embodiment.

[0017] Figures 9A to 9E According to an embodiment Figure 8 Schematic cross-sectional side view illustration of a chip-level BEOL build-up structure with front-side reconstruction of the process flow shown.

[0018] Figures 9F to 9K According to an embodiment Figure 8 Schematic cross-sectional side view illustration of a chip-level BEOL build-up structure with backside reconstruction of the process flow shown.

[0019] Figure 10 is a process flow diagram of a die-face-up processing sequence before alignment for a wafer reassembly and die splicing technique according to one embodiment.

[0020] 11A to 11D According to an embodiment Figure 10 Schematic cross-sectional side view illustration of the process flow shown.

[0021] Figure 12A is a schematic cross-sectional side view illustration showing particles during the wafer reorganization and hybrid bonding stages of a CoW process.

[0022] Figure 12B is a schematic top view illustration showing particle sensitivity on a CoW hybrid bonding process.

[0023] Figure 13A is a schematic cross-sectional side view illustration showing lower particle sensitivity during a wafer reconstitution phase of a wafer reconstitution and die splicing technology process according to one embodiment.

[0024] Figure 13B is a schematic cross-sectional side view illustration showing particles during the interconnect phase of a wafer reassembly and die bonding technology process according to one embodiment.

[0025] Figure 13Cis a schematic top view illustration showing the impact of particles on wafer reassembly and die splicing technology processes according to one embodiment.

[0026] 14A to 14C is a schematic cross-sectional side view illustration of an aluminum dual damascene process according to one embodiment.

[0027] 15A to 15D is a schematic cross-sectional side view illustration of a gap fill deposition sequence according to one embodiment.

[0028] Figure 15E is a schematic cross-sectional side view illustration of a gap fill with an air gap according to one embodiment.

[0029] Figure 15F is a schematic cross-sectional side view illustration of a gap fill material between dies having tapered sidewalls according to one embodiment.

[0030] 16A to 16D is a schematic cross-sectional side view illustration of a gap fill deposition sequence including deposition of silicon ink or paste according to one embodiment.

[0031] 17A to 17E is a schematic cross-sectional side view illustration of a die face-up processing sequence before alignment with wafer reassembly and die splicing technique with mechanical leveling according to one embodiment.

[0032] Figure 18A is a schematic top view illustration of a dummy structure between die sets for maintaining aspect ratios around the die sets, according to one embodiment.

[0033] Figure 18B is a schematic top view illustration of a dummy structure around a set of dies for maintaining aspect ratio around the edge of a carrier substrate according to one embodiment.

[0034] Figure 19 is a flow chart of a wafer reassembly process according to one embodiment.

[0035] Figure 20 is a flow chart comparing yield considerations for a hybrid process flow of stacked wafer, chip-on-wafer, and wafer reassembly and die splicing technologies, according to one embodiment. DETAILED DESCRIPTION

[0036] The embodiment describes a 2.5D packaging solution in which a chip may include: a reorganized chip-level back-end-of-line (BEOL) build-up structure including multiple interconnects, a die set on the reorganized chip-level BEOL build-up structure, and an inorganic gap-fill material on and around the die set.

[0037] Some aspects of the embodiments may include reconstituted wafers with back-end-of-line (BEOL) interconnects to form side-by-side (SBS) heterojunctions. Reconstitution using inorganic materials (e.g., oxides, silicon) may allow for higher temperature processes and finer feature sets. The reconstituted wafers may be known good reconstituted wafers (KGRWs) for stacked wafer (WoW) processes, thereby improving yields.

[0038] In some aspects, the reconstituted chip-level BEOL interconnects can form (inter) die-to-die (D2D) interconnects, as well as (intra) on-chip interconnects (supports). In some embodiments, the reconstituted chip-level BEOL interconnects can include aluminum damascene interconnects. For example, these can be single damascene (two-step) or dual damascenes, such as using electrodeposition. The specific configuration of the die (active side up) with inorganic dielectrics in the reconstituted chip-level BEOL build-up structure can enable standard via and interconnect process paths.

[0039] In some aspects, packaging solutions can minimize or completely remove electrostatic discharge (ESD) protection on the die (thus moving bus-like components closer to the die). This can reduce capacitance and area.

[0040] In various embodiments, descriptions are made with reference to the accompanying drawings. However, certain embodiments may be implemented without one or more of these specific details or in combination with other known methods and configurations. In the following description, many specific details such as specific configurations, dimensions, and processes are shown to provide a thorough understanding of the embodiments. In other cases, well-known semiconductor processes and manufacturing techniques are not described in particular detail so as not to unnecessarily obscure the embodiments. References throughout the specification to "one embodiment" mean that the specific features, structures, configurations, or characteristics described in conjunction with the embodiments are included in at least one embodiment. Therefore, the phrase "in one embodiment" appearing in multiple places throughout the specification does not necessarily refer to the same embodiment. In addition, specific features, structures, configurations, or characteristics may be combined in one or more embodiments in any appropriate manner.

[0041] As used herein, the terms "on," "over," "to," "spanning," and "over" may refer to the relative position of one layer relative to other layers. A layer that is "on," "over," "spanning," or "on" relative to another layer, or bonded "to," or "in contact with" another layer may be directly in contact with the other layer or may have one or more intervening layers. A layer that is "between" multiple layers may be directly in contact with the multiple layers or may have one or more intervening layers.

[0042] In one aspect, embodiments describe a tiled die chip structure that can achieve the benefits of both CoW and BEOL interconnect technologies while avoiding many of the associated potential drawbacks. For example, several CoW beneficial characteristics include heterogeneity (using different substrates), dense I / O per unit area, dense routing per millimeter, scalability, redistribution and reintegration friendliness, and providing die placement accuracy. Some potential drawbacks of CoW include the cost of integrating hybrid bonding manufacturing lines into facilities, the maturity of the technology, particle sensitivity (especially during testing and dicing), and the high temperatures used for hybrid bonding.

[0043] Beneficial features of BEOL interconnect technology include being a mature process (which impacts yield and cost), providing dense I / O per unit area, dense routing per mm, scalability, lower particle sensitivity compared to CoW (especially during testing and dicing), and using moderate temperatures. Some potential disadvantages include being homogeneous (same substrate), and redistribution and reintegration can be more difficult (e.g., due to fixed placement, reconfiguration reticle costs, etc.).

[0044] Tiled die packaging techniques according to embodiments can achieve the best of both CoW and BEOL options. For example, embodiments can achieve the heterogeneity of CoW with reconstituted wafers. Furthermore, embodiments can achieve the dense I / O, die placement accuracy, and redistribution and reintegration friendliness of CoW. Embodiments can also achieve the beneficial characteristics of BEOL, including process maturity, dense I / O, dense routing, scalability, reduced particle sensitivity, and moderate temperatures.

[0045] Now see Figure 1 , provides a cross-sectional side view illustration of a CoW packaging technology in which a side-by-side (SBS) die 110 is hybrid bonded to an interposer 120 and secured with an oxide gap filler 130. As shown, a metal-to-metal bond 132 can be formed between the die pad 118 and the interposer pad 122. In addition, an oxide-to-oxide bond 134 can be formed between the die and the interposer and between the oxide gap filler and the interposer. It has been observed that such CoW technology can increase cost due to being very sensitive to particles and requiring strict environmental control to be maintained during hybrid bonding. In addition, hybrid bond wires can be a major non-recurring expense. Another disadvantage is that the oxide gap filler 130 has a thermal expansion CTE mismatch with silicon. In addition, forming the oxide gap filler is slow and expensive. This can also impose limitations on thin die 110 (e.g., less than 20 microns) and substrate size. See, for example Figure 2 Schematic cross-sectional side view illustration of a die-to-interposer CoW interface in , which shows the die 110 after hybrid bonding to the interposer 120 and bump 140 placement and before removal of the carrier substrate 200 . Figure 2Also shown is the wiring of a die-level BEOL build-up structure 115, which may include one or more metal layers and dielectric layers formed above the active devices 113 formed in the semiconductor substrate 111. Each die 110 includes both the semiconductor substrate 111 and the die-level BEOL build-up structure 115. The die-level BEOL build-up structure 115 may be formed using conventional BEOL processing techniques such as damascene. The die-level BEOL build-up structure 115 may include wiring layers, such as a lower wiring layer M. A , middle wiring layer M B 、M C and upper wiring layer M D As shown, the wiring layers may optionally have different thicknesses, where M D is the thickest, and M A is the thinnest (and best, for example, width). In addition, the preparation of the die 110 after testing (for example, testing of the Al test pad 112) can be a major recurring cost factor for CoW. In addition, as Figure 2 As shown, post-test die 110 preparation includes building up additional oxide 114 and copper vias 116 (minimum height required for bonding) before bonding to interposer 120 , and then building up metal pads 118 .

[0046] The packaging solution including wafer reassembly and die splicing technology according to the embodiment can maintain the best features of CoW and BEOL. This can be achieved by using high-yield wafers (known good reassembly wafers (KGRW)) with good oxide and integrated matrix reassembly. This supports accurate alignment, heterogeneous die integration and die allocation. BEOL interconnects can be used to connect dies with very high I / O surface density (e.g., 5μm-10μm pitch). A suitable number of coarse pitch metallization layers or even final metallization layers can be used to provide high wiring density. In addition, there is no need for hybrid bonding, which can reduce related costs and increase yield. This can further reduce risk and development time. Die periphery yield loss can be managed by the ratio of feature size to particle size. The reassembly sequence may be less sensitive to die (center) area yield loss.

[0047] The recombinant chip manufactured using wafer recombinant and die splicing technology according to the embodiment can achieve a density (design parallelism) of similar wires (or very close) on the chip. The wires can have improved T-line performance and can be used to span longer distances. In addition, the wiring can also be suitable for clock distribution, especially for larger spans. With high-density wiring, the number of layers can be tuned. The wires can also be used for conventional on-chip circuits (for example, routable on-chip buses). Repeaters can be formed in active silicon. There are also testing considerations for wiring, such as a portion of the bus can be set in the die (before integration). This enables testing. The complete bus can then be routed on top to provide complete functionality and bandwidth. Overall, the implementation of BEOL wiring can provide a look and feel and use that is closer to the on-chip environment.

[0048] The reassembled chips manufactured using wafer reassembly and die splicing techniques according to the embodiments can also minimize (or eliminate) electrostatic discharge (ESD) circuits in die-to-die connections, thereby requiring a smaller area and reducing parasitic capacitance. ESD can still be provided in the chip-level BEOL wiring for reassembly of chip external pads.

[0049] Figure 3 is a schematic cross-sectional side view illustration of a chip 300 fabricated using wafer reassembly and die stitching techniques according to one embodiment. As shown, chip 300 includes multiple side-by-side dies 110, which may be partitioned system-on-chip dies, heterogeneous dies from different wafers and from different process nodes, etc. The group of dies 110 is encapsulated in a gap filler 130 material, which may be, for example, an oxide (e.g., silicon oxide) or silicon. A reassembled chip-level BEOL buildup structure 310 is formed over the dies 110 and gap filler 130, including vias 312 between the dies 110 and one or more dielectric layers 318, on-chip (intra-chip) wiring 314, and die-to-die (D2D) interconnects (wiring) 316. In some embodiments, the reassembled chip-level BEOL buildup structure 310 may include, for example, a final metallization layer and / or a coarser pitch metallization layer. In one embodiment, the metallization layer may be a thicker layer, such as an upper wiring layer (eg, M) of the die-level BEOL build-up structure 115. D ) are equal to or thicker. According to some embodiments, conventional damascene or dual damascene through-hole connections between wiring layers may be utilized.

[0050] According to an embodiment, the reconstructed chip-level BEOL build-up structure 310 wiring is electrically connected to the die-level build-up structure 115 of the die 110. This can be achieved using Cu-Cu wiring, Al-Al wiring, and a combination of Cu-Al wiring methods. In one embodiment, the die-level BEOL build-up structure 115 can primarily include Cu wiring, wherein the upper wiring layer (e.g., MD ) includes a test pad formed of Al. In one embodiment, the reconstructed chip-level BEOL build-up structure 310 wiring includes an upper wiring layer (e.g., M) connected to the die-level build-up structure 115. D ) or the wiring layer in contact therewith (eg, M C ) wiring layer of equal or greater thickness (although finer wiring is possible). The reconstituted chip-level BEOL build-up structure 310 can be formed using a Cu or Al wiring process. In one embodiment, the reconstituted chip-level BEOL build-up structure 310 uses an Al wiring process, which may optionally use a (single) damascene via 312. However, depending on the embodiment, the via 312 used to contact the die-level BEOL build-up structure 115 can also be formed of Cu. In some embodiments, quality of service can be used to organize metal usage based on requirements such as latency, power, etc.

[0051] Exemplary methods for forming oxide gap fillers include chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), subatmospheric CVD (SA-CVD), and selective oxide deposition (SELOX). Such oxide deposition techniques are epitaxial techniques that are typically performed at high temperatures, are relatively slow, and are relatively expensive. Exemplary methods for forming silicon gap fillers include epitaxial techniques such as CVD, PECVD, low-pressure CVD (LPCVD), and hot-filament CVD, as well as sputtering, silicon ink, silicon paste, and electrodeposition. However, epitaxial techniques such as PECVD and LPCVD can be performed at lower temperatures, while hot-filament CVD can have significantly higher deposition rates. Electrodeposition can be performed at low temperatures using ionic liquids. In addition, silicon ink and paste can be deposited at low temperatures and then reflowed at low temperatures due to the lowering of the melting point of silicon nanoparticles. It is noteworthy that available techniques for forming silicon gap fillers can be performed at lower temperatures, shorter deposition times, and potentially cheaper equipment. This can affect both throughput and cost. In the case where silicon material is used to provide the gap fill 130 material and the integrated substrate, the silicon gap fill 130 material can be mechanically clean (i.e., good CTE matching). The silicon gap fill 130 material can also allow for the inclusion of thicker (active) dies 110 (e.g., 50 μm thick) compared to oxide gap fill 130 materials, which can be limited to a height of less than 20 μm. In addition, the silicon gap fill material can allow for the use of larger carrier substrate 200 options (such as 200mm, 300mm wafers or 500x500mm panels or larger) during manufacturing. Silicon can also be lower cost (e.g., silicon can be electrodeposited, sputtered, deposited using, for example, low temperature chemical vapor deposition, or using ink or paste), and can be made at low temperatures (e.g., less than 250°C, and less than 120°C is potentially feasible). With the silicon option, a "primer" can be applied after cleaning the wafer. Silicon processing can also reintroduce the process into a mature clean fab (eg, a mature larger production fab, such as a 90nm or 180nm process node, which can reduce non-recurrence costs).

[0052] Utilizing silicon material for the gap fill according to embodiments may allow for thicker die 110 options (improving thermal spreading of hot spots), as well as improving thermal contact from the die 110 (eg, silicon) to the gap fill 130 (silicon). Again, see briefly Figure 1 , shows such a comparison for a CoW thin oxide gap filler 130. As shown, in a CoW implementation, the die 110 may need to be less than 20 μm thick. Otherwise, the oxide gap filler 130 may crack due to stress. An oxide attachment film 211 may also be included (between the die 110 and the mechanically processed silicon substrate 200), but this is very thin and provides only a small increase in thermal resistance.

[0053] It is worth noting that silicon gap filling has nothing to do with wiring. The reconstituted wafer with silicon gap filling can also be used for CoW / hybrid bonding process.

[0054] Now see Figure 3 , the silicon gap fill 130 material can be made thicker and formed over the die 110 more feasible than the oxide gap fill material, and can also allow for a thicker die 110. Regardless of the gap fill 130 material selection, the die 110 can have at least some partial metal wiring. For example, this can include at least conventional fine pitch BEOL wiring (e.g., M A ). For example, these may include 12-18 metal layers in current technology, and possibly more in the future. These wires may include thin wires (e.g., M A ), and then into a BOEL-like (e.g., M B 、M C 、M D Each die 110 may include sufficient wiring and test pads 112 (e.g., aluminum pads, similar to Figure 2 ) to identify good known dies. Except for test requirements, the wiring does not need to be complete, or the circuit does not need to be complete. The final connection can be made in the reconstituted chip-level BEOL layer structure 310.

[0055] The reconstructed chip-level BEOL build-up structure (including the dielectric (oxide) layer 318 shown) can include similar or thicker wiring as the intra-die wiring. For example, without ESD protection, the intra-die wiring 314 in the reconstructed chip-level BEOL build-up structure 310 can include a tight I / O pitch of 2um-10um defined by the process. The die-to-die (D2D) interconnect (wiring) 316 can include a similar pitch with minimal or no ESD protection. The external chip pads 150 (e.g., which can be aluminum) can have an even looser I / O pitch defined by flip-chip bump pitch considerations, such as 60μm-130μm.

[0056] Figure 4 FIG2 shows a back-end process wiring sequence during the manufacture of a reconstituted chip-level BEOL build-up structure 310 for contacting the inner chip layer according to an embodiment. As shown, the reconstituted chip-level BEOL build-up structure may include one or more metal interconnect layers and may include damascene connections. In addition, deep vias 312 may be formed through the die-level BEOL layers to contact the die metallization. This may avoid the top metal layer (e.g., M-type) including the test pad 112. D). Thus, via 312 connections can be etched and formed into the die-level BEOL build-up structure 115 layer to connect to the die-level BEOL layer while bypassing the test pad 112. Additionally, the metal layers in the reconstituted chip-level BEOL build-up structure 310 can be used to fabricate D2D interconnects 316, which can also utilize the aforementioned via 312. External chip pads 150 can then be formed, followed by the application of (solder) bumps 140.

[0057] Figure 5 A back-end routing sequence for contacting the top metal layer is shown according to an embodiment. Figure 5 Similar to Figure 4 , one of the differences is that the via 312 contacts are connected to the top metal layer (e.g., M D ) pads 118. Thus, by comparison, the vias can be shallower vias, and the via pitch can be limited by the pitch of the die pads 118. In one embodiment, the pads 118 for the D2D interconnect 316 can have a finer pitch than the external chip pads 150 for the chip 300 (e.g., for a flip chip). This structure can also be beneficial for power delivery.

[0058] Now see Figure 6 , shows a back-end routing sequence for vias 116 and pads 118 built into the original die 110, according to an embodiment. In such an embodiment, after testing, the die 110 vias 116 and pads 118 can be fabricated in the original wafer format. Thus, after testing, a thin oxide 114 can be formed over the top metal layer test pads 112 shown. Die-level BEOL buildup structure 115 vias 116 and pads 118 are then formed after testing, after which the known good die 110 is sliced. A reconstituted wafer process is then performed, forming the reconstituted chip-level buildup structure 310 and intra-die interconnects 314, as well as D2D interconnects 316. In this case, shallower reconstituted chip-level vias 312 may be required in the reconstituted chip-level BEOL buildup structure 310 to contact the die 110 metal. This can be an option for very fine pitches where die placement accuracy is limited. For larger areas, reticle stitching can be performed. Finally, the outer bumps 140 are applied. Figure 6 Some physical characteristics of the embodiments include finer pitch shallower vias in a reconstituted chip-level BEOL process, and die-level vias 116 and pads 118 above probe pads 112 .

[0059] It should be understood that although described and shown separately Figures 4 to 6, but in some embodiments, the via descriptions may be combined. Furthermore, while a single metal or interconnect layer is shown in the reconstructed chip-level BEOL build-up structure 310, it should be understood that multiple metal or interconnect layers may be formed and may have different thicknesses (e.g., M C 、M D In some embodiments, quality of service can be used to organize metal usage based on requirements such as latency, power, etc.

[0060] 7A to 7C FIG. 1 shows a die-level BEOL build-up structure 115 processing sequence according to an embodiment. Figure 7A As shown, the process sequence begins with a semiconductor substrate 111 (e.g., a silicon wafer) including an active (device) layer including active devices 113 and a die-level BEOL build-up structure 115 including a very fine pitch metal layer (e.g., Mn) which may be, for example, aluminum. A ), coarser pitch metal layers (e.g., M B 、M C ) and the top metal layer (e.g., M D In one embodiment, the die-level BEOL layer includes damascene (e.g., single damascene or dual damascene) interconnects. The top metal layer (e.g., M D ) may include test pads 112. In one embodiment, the lower metallization layer is fabricated using standard copper processing, while the upper metal layer (e.g., M D and optional M C ).

[0061] Each individual die (still within the wafer) is then tested with a test probe, landing on the test pads 112 in the top metal layer. The wafer and test pads 112 may then be cleaned, followed by the application of an oxide layer 114. A thin oxide layer 114 may then optionally be formed on the top metal layer, followed by singulation of the die 110 along the dicing lines, as shown in FIG. Figure 7C At this stage, die 110 can be combined into known good die (KGD1). The process is repeated for the second wafer which will provide known good die (KDG2), and so on for additional wafers "2...n".

[0062] A carrier is then provided, and multiple groups of known good dies 110 are then mounted on the carrier substrate 205. This can be, for example, oxide bonding. In one embodiment, this can include bonding of groups of dies 110 (e.g., KGD1, KGD2, etc.). The process flow can differ depending on whether the dies 110 are mounted face-up or face-down on the carrier substrate.

[0063] Figure 8 is a process flow diagram of a die face-down processing sequence before alignment of a wafer reassembly and die splicing technique according to an embodiment. Figures 9A to 9E According to the implementation plan Figure 8 Cross-sectional side view illustration of a chip-level BEOL build-up structure with front-side reconstruction of the process flow shown. Figures 9F to 9K According to the implementation plan Figure 8 The process flow shown is a cross-sectional side view illustration of a chip-level BEOL build-up structure with backside reconstruction. It should be understood that Figures 9A to 9E and Figures 9F to 9K The processing sequence includes different gap fill matrix materials (e.g., oxide, silicon, oxynitride, etc.). In addition, several process variations are possible. For clarity and brevity, Figure 8 、 Figures 9A to 9E and Figures 9F to 9K The process sequence and variants are described together.

[0064] like Figure 9A and Figure 9F As shown, the processing sequence may begin at operation 810 where a plurality of die sets 110A, 110B, etc. (comprising at least two die 110) are mounted face down (active side down) onto a carrier substrate 205. Each die 110 may have varying heights. The die thickness may be 5 μm-100 μm (for ease of handling). The die 110 may be oxide bonded to the carrier substrate 205. For example, the oxide layer 114 may be bonded to the oxide layer on the carrier substrate 205. The incoming die may be cleaned individually (minimal test and scribe residue). Then, at operation 815, the thicker die members of the die set may be thinned, optionally by grinding or CMP polishing. This is done in Figure 9G shown in the Figure 9A This thickness reduction of the thicker die components can facilitate subsequent gap filling and die reduction to die height variations. Similarly, all die components can be thinned to provide equal thickness and remove steps between die component thicknesses in the die set.

[0065] In one embodiment, the die test pads 112 (e.g., aluminum pads from testing) may be repaired and cleaned prior to known good die placement (or even die dicing). An additional oxide layer 114 may then be deposited, and vias 116 and pads 118 may optionally be constructed, as described in detail in the accompanying drawings. Figure 6 As stated.

[0066] like Figure 9B and Figure 9HAs shown, at operation 820, gap filler 130 material is deposited on carrier substrate 205 such that it laterally surrounds each die in the plurality of die sets. Gap filler 130 can then be planarized as needed, which can optionally expose the backsides of one or more die sets 110A, 110B, etc. In some embodiments, gap filler 130 material is an oxide. In the case of silicon implementations (e.g., sputtering, LPCVD, hot-filament CVD, silicon ink, silicon paste, electrodeposition), this can allow CTE matching with die 110. In such silicon-silicon systems, better mechanical matching can be achieved. Additionally, thicker die 110 can potentially be used compared to oxide gap fills, where deposition can take longer.

[0067] The process sequence may then vary depending on whether front-side or back-side reconstruction of the chip-level BEOL build-up is to be performed. In the front-side approach, at operation 830, the second (back) carrier substrate 200 may then be bonded opposite the first (front) carrier substrate 205, followed by operation 840 and as Figure 9C The first carrier substrate 205 is shown removed. At this point, the die 110 face (active side) is on the exposed side. Figure 9D , the structure is flipped, and at operation 850, a reconstructed chip-level BEOL buildup structure 310 is constructed on multiple sets of die sets and gap fill 130 materials. This is different from the CoW sequence described above because the reconstructed chip-level BEOL buildup structure 310 does not require hybrid bonding, but can be formed in a layer-by-layer processing sequence, such as including polymer / metal or oxide / metal. Each reconstructed chip-level BEOL buildup structure wiring can be tested and then sliced ​​for chip singulation processing, such as Figure 9E shown. Figures 9A to 9E The processing sequence shown may allow for variations in the height of the die 110 because the active side faces outward for the processing sequence.

[0068] In the backside D2D interconnect method, at operation 835, through silicon vias (TSVs) 902 may then be formed in the plurality of die sets, or exposed (e.g., pre-formed TSVs are exposed). At this point, the die 110 face (active side) is still facing downward, and at operation 845, a reconstituted chip-level BEOL build-up structure 310 is constructed on the backsides of the plurality of die sets, the TSVs 902, and the gap fill 130 material, as shown. Figure 9I As previously described, the reconstructed chip-level BEOL build-up structure 310 may include D2D interconnects 316, on-chip (intra-chip) wiring 314, and one or more dielectric layers. Thus, the backside reconstructed chip-level BEOL build-up structure 310 includes D2D connections through TSVs 902. The second (rear) carrier substrate 200 may then be bonded opposite the first (front) carrier substrate 205, followed by operation 855 and as shown. Figure 9JThe first carrier substrate 205 is shown removed. At this point, the die 110 face (active side) is on the exposed side that can be used to connect to the package. Figure 9K , an additional front-side reconstituted chip-level BEOL build-up structure 910 may optionally be built on the plurality of die sets and gap fill 130 material, and more specifically on the die-level BEOL build-up structure 115. This structure may be followed by singulation and removal of the carrier substrate 200, application of bumps 140, additional WoW bonding, etc. The front-side reconstituted chip-level BEOL build-up structure 910 may be substantially similar to the previously described reconstituted chip-level BEOL build-up structures 120, 310 and include the same features.

[0069] Figure 10 is a process flow diagram of a die-face-up processing sequence before alignment of a wafer reassembly and die splicing technique according to an embodiment. 11A to 11D According to the implementation plan Figure 10 A cross-sectional side view illustration of the process flow is shown.

[0070] It should be understood that 11A to 11D The processing sequence includes different gap fill matrix materials (e.g., oxide, silicon). In addition, several process variations are possible. For clarity and brevity, Figure 10 as well as 11A to 11D The process sequence and variants are described together.

[0071] like Figure 11A As shown, the processing sequence may begin at operation 1010, where a plurality of sets of dies (including at least two dies 110) are mounted face-up (active side up) onto a carrier substrate 200. Each die 110 may have a small height variation. For example only, the variation may be + / - 1 μm, where the thickness of each die is 5 μm-20 μm. The thickness variation may be less than Figure 9A The die 110 may be, for example, oxide bonded to the carrier substrate 200. The incoming die may be cleaned individually (minimal test and scribe residue). Figure 11B As shown, at operation 1020, gap filler 130 material is deposited onto carrier substrate 205 such that it laterally surrounds each die in the plurality of groups of die sets. Gap filler 130 may then be planarized as desired. Figure 11CAt operation 1030, a reconstructed chip-level BEOL buildup structure 310 is constructed on the plurality of die sets 110A, 110B, etc. and the gapfill 130 material. This differs from the CoW sequence described above because the reconstructed chip-level BEOL buildup structure does not require hybrid bonding and can instead be formed in a layer-by-layer processing sequence, for example, including polymer / metal or oxide / metal. Formation of the reconstructed chip-level BEOL buildup structure 310 may include forming vias 312, which may extend through the gapfill 130 material. Because the active side faces upward, the height of the vias 312 from the die 110 needs to be sufficient to contact the die-level BEOL buildup structure 115. For example, this height may be greater than the height variation of the die 110. After planarization, the vias 312 may be exposed (at least on one of the dies, but not all if the thickness varies). The remainder of the reconstructed chip-level BEOL buildup structure 310 may then be formed. In some embodiments, the gapfill 130 material is an oxide. In the case of silicon implementations (eg, sputtering, CVD, PECVD, LPCVD, hot filament CVD, silicon ink, silicon paste, electrodeposition), this may allow for conformal, low temperature deposition, and CTE matching to the die, as previously described.

[0072] Each reassembled chip-level BEOL wiring can then be tested before being sliced ​​for chip 300 singulation processing, such as Figure 11D shown. 11A to 11D The processing sequence shown may be a less expensive processing sequence option. See also 17A to 17E Additional processing sequence variations are described and illustrated, which can further reduce processing costs.

[0073] Wafer reassembly and die splicing techniques according to embodiments may also provide reduced particle sensitivity compared to CoW hybrid bonding. Figure 12A is a schematic cross-sectional side view illustration of a particle 1200 during the wafer reassembly phase and hybrid bonding of a CoW process. Planarity requirements can be stringent (such as a root mean square (RMS) roughness of approximately 1 nm-5 nm), and even small particles (e.g., with a maximum particle size of 10 nm) can open a large number of pads 118, 122, potentially impacting yield. Thus, particle size and planarity requirements are closely related and require a very clean assembly environment, which can be expensive. As a corollary, 10 nm particle size control may require better technology node cleanliness than 20 nm, which implies setup and operating costs. Figure 12Bis a schematic top view diagram illustrating particle sensitivity on a CoW hybrid bonding process. As shown, the pads 118, 122 connections between the die 110 and the interposer 120 can be coarse features (e.g., power, ground pads, etc.) compared to the finer pads 118, 122 and features / routing in the die-to-die interconnect 125. As shown, particles 1200 can cause yield loss in any of these areas, and particle sensitivity exceeds 100% of the hybrid bonding area, even for fine features in smaller areas (e.g., 10% overall).

[0074] Figure 13A is a schematic cross-sectional side view illustration showing lower particle 1200 sensitivity during the wafer reconstitution phase of the wafer reconstitution and die splicing technology process, according to one embodiment. Figure 13B is a schematic cross-sectional side view illustration of a particle 1200 during the interconnect phase of a wafer reassembly and die bonding process according to one embodiment. 13A to 13B As shown, the through hole 312 is highly overetched to compensate for defects (particles). The exemplary pad 118 pitch of about 10 μm and the D2D interconnect 316 pitch of about 1 μm can be much larger than the particle (e.g., about 100 nm). This is 10X larger than the CoW case. Therefore, the wafer reassembly and die splicing technology according to the embodiment can reduce the particle size sensitivity by selecting physical / process dimensions. This can lead to more relaxed cleanliness and assembly options. As a corollary, 100nm particle size control requires better technology node cleanliness than 200nm (a very mature technology node). Figure 13C is a schematic top view illustration showing the effect of particles 1200 on wafer reassembly and die splicing technology processes according to one embodiment. Figure 12B The pads 118 connections between the die 110 and the reconstructed chip-level BEOL buildup structure 310 can be coarse features (e.g., power and ground pads), compared to the finer features / routing in pads 118, vias 312, and D2D interconnects 316. As shown, particle sensitivity is largely limited to the fine pitch area (e.g., 10% overall), which improves yield. Due to the coarser feature size, particles in other die areas have a much smaller impact on yield. Furthermore, by making the feature size in the D2D interconnect 316 area larger, the probability of failure can be further reduced.

[0075] The interconnects of the reconstituted chip-level BEOL buildup structure 310 for die bonding can be implemented with suitable conductive materials and BEOL processing techniques. In some embodiments, when forming the reconstituted chip-level BEOL buildup structure 310 using wafer reconstitution and die bonding techniques, copper wiring and / or aluminum wiring can be utilized. For example, aluminum wiring may be more suitable for highly mature BEOL production lines that do not support copper BEOL processes. Some highly mature processes and production lines only support aluminum. Aluminum processes can be sufficient for some applications and are less expensive than copper. In more traditional aluminum interconnects, aluminum wiring is combined with tungsten plugs for multi-layer fine pitch options (typically as an undermetal layer adjacent to silicon). Tungsten processing adds expense, as does the definition of the aluminum metal layer. In contrast, copper dual damascene processes can be expensive due to the cost of barrier and capping layers to prevent copper diffusion. In one embodiment, the BEOL interconnects include aluminum dual damascene connections. The aluminum dual damascene process may optionally include reflow for planarization and fill purposes, which may exceed 450°C. In some embodiments having such electrodeposited aluminum dual damascene embodiments, tungsten vias are not present and reflow is not performed. This enables fine metal pitch due to smoother topographic features.

[0076] 14A to 14C is a schematic cross-sectional side view illustration of an aluminum dual damascene process according to one embodiment. Figure 14A In the embodiment of the present invention, the sequence may include a first dielectric layer 1402 and a second dielectric layer 1406 separated by an etch stop layer 1204. The via 1210 opening and the trench 1412 opening may be formed using a via first or via last approach. Figure 14B As shown, a bulk aluminum layer 1420 is deposited to fill the via 1410 opening and the trench 1412 opening. This may be followed by a reflow process and planarization resulting in a dual damascene interconnect 1422, as shown. Figure 14C shown.

[0077] 15A to 15D is a schematic cross-sectional side view illustration of a gap fill deposition sequence according to an embodiment. In the particular sequence shown, the die 110 group is mounted face down on the carrier substrate 205 as previously described. Figure 9A As described and shown, however, the embodiments are not limited thereto, and the gap fill deposition sequence may utilize Figure 11A The first conformal layer 131 may then be formed, as shown. Figure 15B As shown. For example, this can be a thin oxide, nitride, silicon layer, etc. to provide good step coverage. In one embodiment, a higher quality and slower deposition method such as a high temperature CVD process that can result in epitaxial growth is used to form the first conformal layer 131. The bulk layer 133 can then be deposited, such as Figure 15CAs shown. The bulk layer 133 may be formed using a process that results in lower quality material (eg, more defects) and deposited at a higher rate. Figure 15D Gap filler 130 is shown planarized, which may optionally expose the backside of die 110 .

[0078] According to an embodiment, the gap fill 130 material may be formed of multiple layers and may include multiple layers of different materials. Figure 15D , but the gap filler 130 may include multiple conformal layers and other layer stacks. Figure 15E In the embodiment shown, the growth characteristics of the gap fill 130 layer can result in air gaps 1500 between groups of dies 110. For example, the air gaps can contribute dielectric properties to the resulting chip structure.

[0079] Selecting an appropriate gap fill 130 deposition technique may additionally consider the aspect ratio of the die height to the gap between the die sets. According to an embodiment, the gaps between adjacent die 110 in a die set are characterized by an aspect ratio of about 1 or higher (such as 1-2, or even up to 5), but higher aspect ratios are possible. For an exemplary aspect ratio of 5, the die 110 may have a minimum die height of 10 μm with a gap of 2 μm. However, lower aspect ratios may be easier to fill while reducing time requirements. Figure 15E In the embodiment shown, the sidewalls 199 of the die 110 may be tapered to facilitate gap filling.

[0080] 16A to 16D is a schematic cross-sectional side view illustration of a gap fill deposition sequence including deposition of silicon ink or paste according to an embodiment. As shown, the sequence may be similar to Figure 15A Initially, a first conformal layer 131 is optionally deposited. This can be, for example, a PECVD epitaxial deposition process of silicon. Alternatively, an oxide or nitride layer can be deposited. This first conformal layer 131 forms a high quality gap fill seal. See Figures 16B to 16C , a bulk layer 133 of silicon ink or paste may be deposited and then reflowed. For example, reflow may occur at a temperature below 350°C. The low reflow temperature may be a result of the size and shape of the silicon nanocrystals and the ink or paste. For example, the silicon nanocrystals may have a maximum width of less than 4 nm. The silicon nanocrystals may then be deposited as shown in FIG. Figure 16D Gap filler 130 is shown planarized, which may optionally expose the backside of die 110 .

[0081] Depending on the embodiment, the silicon ink or paste may additionally be used for mechanical die leveling. 17A to 17E is a schematic cross-sectional side view illustration of a die face-up processing sequence before alignment with wafer reassembly and die splicing techniques with mechanical leveling according to an embodiment. Specifically, 17A to 17EThe sequence shown in Figures 11A to 11C A modification of the face-up sequence shown in , wherein a moldable layer is deposited that is used to flatten the top surface topography of the die 110 prior to forming the gap fill 130 material. This allows for the formation of a reconstituted chip-level BEOL build-up structure 310 where the via 312 height does not need to be different for dies 110 of different heights. This sequence also allows for a single carrier substrate processing sequence, rather than Figures 9A to 9E A face-down processing sequence utilizing two carrier substrates.

[0082] As shown, the sequence may begin with the deposition of a moldable layer 1710. This may be, for example, a silicon ink or paste that may act as a silicon solder. The die 110 group is then placed on the moldable layer 1710, as shown in FIG. Figure 17B As shown, it is then flattened using a flat surface 1720. Figure 17C As shown, the top surface of the die 110 is now horizontal and the bottom surface is sunken into the moldable layer 1710. Heat can then be applied to set the moldable layer 1710, thereby causing the die to be attached to the carrier substrate through the moldable layer 1710. This can be followed by the formation of the gap fill 130 material, followed by the reconstituted chip-level BEOL build-up structure 310, as shown in FIG. Figures 17D to 17E shown.

[0083] Up to this point, the deposition of gap fill 130 material and the aspect ratios between groups of dies 110 have been described without regard to the carrier substrate (wafer) edge or the scribing of the die sets. Figure 18A In the embodiment shown in FIG, dummy structures 1810 are formed between the die sets to maintain the aspect ratio of the gaps around the die sets 110A, 110B, etc. This configuration can be utilized, for example, when the dicing lines (shown by the dashed lines) are wider than the gaps between the die 110 within the die sets 110A, 110B, etc. Figure 18B is an illustration of dummy structures 1810 formed around the edge of the carrier substrate (wafer) so that the gap fill and aspect ratio of the die 110 are maintained near the edge.

[0084] Now see Figure 19 , provides a high-level flow chart of a wafer reassembly flow according to an embodiment. As shown, at operation 1910, a plurality of wafers (1..n) are processed to determine known good die KGD1..KGDn, where qualified die 110 are indicated by check marks and defective die 110 are indicated by x marks. Then at operation 1920, the known good die set is reassembled onto a wafer (e.g., Figures 9A to 9C ; Figures 11A to 11B ; 17A to 17D). At operation 1930, the known good die can then be polished, cleaned, and primed. Mature fab processes can be used for this sequence, and no (or only very few) new lines are needed. The Fab sequence can also be reformatted into a 200mm or 300mm wafer line, or a larger panel line such as 500mm×500mm.

[0085] The known good reconstituted wafer (KGRW) may then be reintroduced into the fab at operation 1940 for reconstituted chip-level BEOL processing and D2D interconnect (e.g., Figure 9D ; Figure 11C ; Figure 17E ). This is followed by testing, dicing, and final packaging in operation 1950.

[0086] Alternatively, the KGRW with the reconstituted chip-level BEOL buildup structure can be bonded for 3D stacked wafer (WoW) packaging at this point, rather than tested and diced. In the illustrated case, for a 3D packaging solution, KGRW1 and KGRWn are bonded to the stacked wafer at operation 1945, followed by dicing and final packaging at operation 1955.

[0087] Figure 20 The present invention is a flowchart comparing yield considerations for a hybrid process flow of stacked wafers, chip-on-wafer, and wafer reassembly and die splicing technologies according to an embodiment. As shown in the figure, an x ​​mark indicates a defective die, while a check mark indicates a die that passed testing. As shown in the figure, in WoW technology, active dies are wasted. Both the bottom die and the top die must have yield. Process costs are wasted on the die with no yield. With CoW technology, active dies are preserved. Process costs are wasted on the non-yield portion of the base wafer. In a hybrid approach using a KGD1 bottom wafer and a KDG2 top wafer, the yield of both the base wafer and the top wafer is improved. Process costs are lower because both the top die and the bottom die have high-yield dies. Therefore, the reassembled wafers according to the embodiment can be used in stacked wafer technology (surface, alignment, TSV, bonding preparation) to manufacture 3D reassembled chips.

[0088] When utilizing various aspects of the embodiments, it will be apparent to those skilled in the art that combinations or variations of the above embodiments are possible for forming chips using wafer reassembly and die splicing techniques. Although the embodiments are described in language specific to structural features and / or methodological acts, it should be understood that the appended claims are not necessarily limited to the specific features or acts described. Instead, the specific features and acts disclosed should be understood as exemplary embodiments of the claims.

Claims

1. A chip, comprising: A reconstructed chip-level back-end-of-the-line (BEOL) stacked structure including multiple interconnects; A die set on the reconstructed chip-level BEOL build-up structure; as well as an inorganic gap-fill material on the reconstituted chip-level BEOL build-up structure and surrounding the die set, wherein the die set includes a first die and a second die, the first die includes a first die-level BEOL build-up structure, and the second die includes a second die-level BEOL build-up structure, wherein the reconstructed chip-level BEOL build-up structure includes intra-die interconnects for the first die, intra-die interconnects for the second die, and die-to-die interconnects between the first die and the second die, The reconstructed chip-level BEOL build-up structure includes a first deep via and a second deep via, wherein the first deep via connects the die-to-die interconnect to the first die-level BEOL build-up structure and extends under a first test pad in the first die-level BEOL build-up structure, and the second deep via connects the die-to-die interconnect to the second die-level BEOL build-up structure and extends under a second test pad in the second die-level BEOL build-up structure. 2 . The chip of claim 1 , wherein each of the first die-level BEOL build-up structure and the second die-level BEOL build-up structure comprises a damascene interconnect. 3 . The chip of claim 2 , wherein the reconstituted chip-level BEOL build-up structure comprises damascene interconnects. The chip of claim 3 , wherein the reconstituted chip-level BEOL build-up structure comprises aluminum damascene interconnects. The chip according to claim 3 , wherein the inorganic gap-filling material is an oxide or an oxynitride. The chip according to claim 3 , wherein the inorganic gap-filling material comprises a silicon matrix. 7 . The chip of claim 1 , wherein the die-to-die interconnect between a first die and a second die does not include ESD protection circuitry.

8. The chip of claim 7, wherein the reconstituted chip-level BEOL build-up structure includes an ESD protection circuit connected to external reconstituted chip-level contact pads.

9. A method for manufacturing a reconstituted wafer, comprising: mounting the plurality of die sets face down on a first carrier substrate; depositing a gap fill material onto the first carrier substrate and laterally surrounding each die in the plurality of sets of die; bonding a second carrier substrate opposite to the first carrier substrate; removing the first carrier substrate; as well as After depositing the gap-fill material and before bonding the second carrier substrate opposite the first carrier substrate, a reconstituted chip-level back-end-of-line (BEOL) build-up structure is constructed on the backside of the plurality of die sets and in contact with a plurality of through-silicon vias (TSVs) in the plurality of die sets.

10. The method of claim 9, wherein the gap-fill material is an oxide or an oxynitride material. The method of claim 9 , wherein the gap-fill material comprises a silicon matrix. 12 . The method of claim 9 , further comprising constructing a reconstituted chip-level back-end-of-the-line (BEOL) build-up structure on the plurality of die sets and the gap-fill material.

13. The method of claim 9, further comprising reducing a thickness of at least a thicker die member of the die set prior to depositing the gap fill material. 14 . The method of claim 13 , further comprising forming a plurality of TSVs in the plurality of groups of dies after depositing the gap fill material.

15. A method for manufacturing a reconstituted wafer, comprising: mounting a plurality of die sets face-up onto a first carrier substrate, wherein each die set comprises a first die comprising a first die-level back-end-of-the-line (BEOL) build-up structure including a damascene interconnect, and a second die comprising a second die-level BEOL build-up structure including a damascene interconnect; depositing a gap fill material onto the first carrier substrate and laterally surrounding each die in the plurality of sets of die, wherein the gap fill material comprises an inorganic matrix material selected from the group consisting of oxide, oxynitride, and silicon; as well as A reconstructed chip-level back-end-of-the-line (BEOL) layer structure is constructed on the plurality of die sets and the gap-filling material. wherein the reconstructed chip-level BEOL build-up structure includes intra-die interconnects for the first die, intra-die interconnects for the second die, and die-to-die interconnects between the first die and the second die, The reconstructed chip-level BEOL build-up structure includes a first deep via and a second deep via, wherein the first deep via connects the die-to-die interconnect to the first die-level BEOL build-up structure and extends under a first test pad in the first die-level BEOL build-up structure, and the second deep via connects the die-to-die interconnect to the second die-level BEOL build-up structure and extends under a second test pad in the second die-level BEOL build-up structure.

16. A wafer stacking process, comprising: bonding a first reconstituted wafer of known die to a second reconstituted wafer of known die; wherein the first reconstituted wafer of known dies comprises an array of dies embedded in a silicon matrix gap fill material, the die array comprising a first die and a second die, the first die comprising a first die-level BEOL build-up structure, and the second die comprising a second die-level BEOL build-up structure, wherein each of the first die-level BEOL build-up structure and the second die-level BEOL build-up structure comprises a damascene interconnect, The reorganized chip-level back-end BEOL build-up structure is on the die array and the gap filling material, the reorganized chip-level BEOL build-up structure includes intra-die interconnects for the die and die-to-die interconnects between the die, and the reorganized chip-level BEOL build-up structure includes a first deep through hole and a second deep through hole, the first deep through hole connects the die-to-die interconnect to the first die-level BEOL build-up structure and extends to under a first test pad in the first die-level BEOL build-up structure, the second deep through hole connects the die-to-die interconnect to the second die-level BEOL build-up structure and extends to under a second test pad in the second die-level BEOL build-up structure. 17 . The stacked wafer process according to claim 16 , further comprising singulating the plurality of 3D reconstructed chips.

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