Semiconductor package, method for manufacturing the same, and semiconductor device

Abstract

The purpose is to provide a technology that can achieve cost reduction or miniaturization of semiconductor packages. The wiring component includes: a second substrate; a plurality of first relay pads, which are arranged on the surface of the second substrate opposite to the conductor substrate and connected to the control pads of the plurality of semiconductor elements through wires; a plurality of second relay pads, which are arranged on the surface of the second substrate opposite to the conductor substrate, and the number of the second relay pads is less than or equal to the number of the first relay pads; and a plurality of wirings, which are arranged on the surface of the second substrate opposite to the conductor substrate and selectively connect the plurality of first relay pads and the plurality of second relay pads.

Description

Technical Field

[0001] The present invention relates to a semiconductor package, a manufacturing method thereof and a semiconductor device. Background Art

[0002] Various technologies have been proposed for power semiconductor devices. For example, Patent Document 1 proposes a semiconductor device in which a semiconductor element and a post electrode connected to the semiconductor element are packaged with a resin so that power controlled by the semiconductor element is obtained from the post electrode.

[0003] On the other hand, in power semiconductor devices such as MOSFET (Metal Oxide Semiconductor Field Effect Transistor) modules using silicon carbide (SiC), it is difficult to achieve a large area of ​​the MOSFET and even an increase in current capacity, and the technology of Patent Document 1 cannot be directly used. Therefore, a structure in which multiple semiconductor chips are connected in parallel in order to cope with the increase in current capacity is proposed. For example, Patent Document 2 proposes a structure in which signals are input from multiple semiconductor chips to a signal wiring pattern on an insulating substrate via a wire.

[0004] Patent Document 1: Japanese Patent Application Publication No. 2014-199955

[0005] Patent Document 2: International Publication No. 2014 / 046058 Summary of the invention

[0006] However, in the technology of Patent Document 2, the signal wiring pattern corresponding to the gate electrode and the main current circuit pattern corresponding to the source electrode are arranged on the same component. Therefore, when a relatively large current flows in the main current circuit pattern, for example, in order to ensure insulation between the signal wiring pattern and the main current circuit pattern, these patterns need to be sufficiently separated. As a result, there are problems such as an increase in the size of the semiconductor device and an increase in cost due to the complexity of the assembly method.

[0007] Therefore, the present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a technology capable of achieving cost reduction or miniaturization of a semiconductor package.

[0008] The semiconductor package of the present invention comprises: a conductor substrate; a plurality of semiconductor elements, which are bonded to the first main surface of the conductor substrate and have a switching function; and a wiring element, which is bonded to the first main surface of the conductor substrate, and each of the plurality of semiconductor elements comprises: a first substrate; a first main electrode portion, which is arranged on the surface of the first substrate on the opposite side of the conductor substrate; a second main electrode portion, which is arranged on the surface of the first substrate on the conductor substrate side and bonded to the conductor substrate; and a control pad, which is used to control the current flowing between the first main electrode portion and the second main electrode portion, and the wiring element comprises: a second substrate; a plurality of first relay pads, which are arranged on the surface of the second substrate on the opposite side of the conductor substrate and are connected to the control pads of the plurality of semiconductor elements through wires; a plurality of second relay pads, which are arranged on the surface of the second substrate on the opposite side of the conductor substrate, and the number of the second relay pads is less than or equal to the number of the plurality of first relay pads; and a plurality of wirings, which are arranged on the surface of the second substrate on the opposite side of the conductor substrate, selectively connecting the plurality of first relay pads and the plurality of second relay pads, the semiconductor package also comprises: a plurality of first conductor components, which are bonded to the first main electrode portions of the plurality of semiconductor elements; a plurality of second conductor components, which are bonded to the plurality of second relay pads of the wiring component; and a packaging material, which covers the plurality of semiconductor elements, the wiring component, at least a portion of the plurality of first conductor components, at least a portion of the plurality of second conductor components, and the first main surface of the conductor substrate in a state where the surfaces of the plurality of first conductor components on the opposite side of the conductor substrate, i.e., exposed surfaces, the surfaces of the plurality of second conductor components on the opposite side of the conductor substrate, i.e., exposed surfaces, and the second main surface of the conductor substrate on the opposite side of the first main surface are exposed.

[0009] Effects of the Invention

[0010] According to the present invention, the wiring element includes: a second substrate; a plurality of first relay pads connected to control pads of a plurality of semiconductor elements through wires; a plurality of second relay pads, the number of which is less than or equal to the number of the plurality of first relay pads; and a plurality of wirings selectively connecting the plurality of first relay pads and the plurality of second relay pads. Thus, the cost reduction or miniaturization of the semiconductor package can be achieved.

[0011] The objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a schematic plan view showing the structure of the semiconductor package according to the first embodiment.

[0013] Figure 2 It is a schematic cross-sectional view showing the structure of the semiconductor package according to the first embodiment.

[0014] Figure 3 It is a perspective schematic diagram showing the structure of the semiconductor device according to the first embodiment.

[0015] Figure 4 It is a schematic cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0016] Figure 5 It is a perspective schematic diagram showing the structure of the semiconductor device according to the first embodiment.

[0017] Figure 6 It is a schematic cross-sectional view showing the structure of a semiconductor package according to the second embodiment.

[0018] Figure 7 It is a schematic cross-sectional view showing the structure of a semiconductor package according to the third embodiment.

[0019] Figure 8 It is a perspective schematic diagram showing the structure of a semiconductor device according to a fourth embodiment.

[0020] Fig. 9 It is a schematic cross-sectional view showing the structure of a semiconductor device according to the fifth embodiment. DETAILED DESCRIPTION

[0021] <Implementation Method 1>

[0022] Figure 1 is a schematic plan view showing the structure of a semiconductor package 1 according to Embodiment 1 of the present invention. Figure 2 The structure of the semiconductor package 1 is shown in FIG. Figure 1 Schematic diagram of the cross section along the A-A' line.

[0023] like Figure 1 and Figure 2 As shown, the semiconductor package 1 includes a conductor substrate 2, a plurality of semiconductor elements 3, and a wiring element 4. Below, the description is made on the basis that the number of the plurality of semiconductor elements 3 is 5, but it can be any number as long as it is greater than or equal to 2. In addition, below, the description is made on the basis that the number of the wiring element 4 is 1, but it can be any number as long as it is less than the number of the plurality of semiconductor elements 3.

[0024] The plurality of semiconductor elements 3 are bonded to the first main surface 2S1 ( Figure 2 ), each of the plurality of semiconductor elements 3 has a switch function. The wiring element 4 is bonded to the first main surface 2S1 of the conductor substrate 2. Figure 1In the example, the wiring element 4 is surrounded by the plurality of semiconductor elements 3 in three directions (above, left, and right) except one direction (below) when viewed from above, and is close to the plurality of semiconductor elements 3.

[0025] Each of the plurality of semiconductor elements 3 includes a first substrate, namely a semiconductor substrate 31, a first main electrode portion, namely a surface electrode 32f, a second main electrode portion, namely a back electrode 33b, and greater than or equal to one control pad 34c. In addition, at least one of the plurality of semiconductor elements 3 may further include at least one of a current sensing element and a temperature sensing element (not shown).

[0026] The surface electrode 32f is disposed on the surface of the semiconductor substrate 31 opposite to the conductive substrate 2. The surface electrode 32f contains nickel as a main material, and gold or silver is contained on the outermost surface of the material. The surface electrode 32f corresponds to the source electrode.

[0027] The back electrode 33b is disposed on the surface of the semiconductor substrate 31 on the conductor substrate 2 side, that is, the back surface, and is bonded to the conductor substrate 2. As a result, the potentials of the back electrodes 33b of the plurality of semiconductor elements 3 are equal to each other. The back electrode 33b contains nickel as a main material, for example, and contains gold or silver on the outermost surface of the material. In addition, the back electrode 33b corresponds to the drain electrode.

[0028] The control pad 34c is a pad for controlling the current flowing between the front surface electrode 32f and the back surface electrode 33b. The control pad 34c corresponds to the gate electrode.

[0029] The wiring element 4 includes a wiring substrate 41 which is a second substrate, a plurality of first relay pads 42r, a plurality of second relay pads 43r, and a plurality of internal wirings 44i which are a plurality of wirings.

[0030] The plurality of first relay pads 42r, the plurality of second relay pads 43r, and the internal wiring 44i are arranged on the surface of the wiring substrate 41 opposite to the conductor substrate 2, and are insulated from the conductor substrate 2 by the wiring substrate 41 and the like.

[0031] The plurality of first relay pads 42r are connected to the plurality of control pads 34c of the semiconductor elements 3 via wires 5. The wires 5 have a wire diameter of, for example, 100 μmΦ or less and contain gold as a main material.

[0032] The number of the plurality of second relay pads 43r is less than or equal to the number of the plurality of first relay pads 42r. Figure 1 In the example, the plurality of second relay pads 43r are arranged along the edge portion of the wiring substrate 41 close to the outside of the semiconductor package 1, but the positions of the plurality of second relay pads 43r are not limited thereto.

[0033] The plurality of internal wirings 44i selectively connect the plurality of first relay pads 42r and the plurality of second relay pads 43r inside the wiring element 4. Figure 1 In the example, the width of the first relay pad 42r is larger than the width of the internal wiring 44i, and the width of the second relay pad 43r is larger than the width of the first relay pad 42r.

[0034] like Figure 1 and Figure 2 As shown, the semiconductor package 1 further includes a plurality of first conductor members, namely, a plurality of conductor plates 38 , a plurality of second conductor members, namely, a plurality of conductor pieces 48 , and a sealing material 6 .

[0035] The plurality of conductor plates 38 are joined to the surface electrodes 32f of the plurality of semiconductor elements 3, and the plurality of conductor pieces 48 are joined to the plurality of second relay pads 43r of the wiring element 4. The surface electrodes 32f and the second relay pads 43r each contain a metal capable of soldering, such as nickel, as a main material.

[0036] The packaging material 6 covers and substantially packages the plurality of semiconductor elements 3, the wiring element 4, at least a portion of the plurality of conductor plates 38, at least a portion of the plurality of conductor sheets 48, and the first main surface 2S1 of the conductor substrate 2. The packaging material 6 includes epoxy resin and is formed, for example, by transfer molding, compression molding, or casting.

[0037] In addition, the surfaces of the plurality of conductor plates 38 opposite to the conductor substrate 2, i.e., the exposed surfaces, the surfaces of the plurality of conductor pieces 48 opposite to the conductor substrate 2, i.e., the exposed surfaces, and the second main surface 2S2 of the conductor substrate 2 opposite to the first main surface 2S1 are exposed from the packaging material 6. Figure 2 As shown, the semiconductor package 1 has a first surface 1S1 and a second surface 1S2 facing in opposite directions. The second main surface 2S2 of the conductor substrate 2 corresponds to the first surface 1S1 of the semiconductor package, and the exposed surfaces of the plurality of conductor plates 38 and the exposed surfaces of the plurality of conductor pieces 48 correspond to the second surface 1S2 of the semiconductor package 1.

[0038] The structure in which a part of the plurality of conductor plates 38 and the plurality of conductor pieces 48 are exposed from the packaging material 6 is formed, for example, by a grinding process, in which a part of the metal parts that become the plurality of conductor plates 38 and the plurality of conductor pieces 48 is ground to expose the metal parts after covering them with the packaging parts that become the packaging material 6. At this time, the grinding is completed when the height of the packaging material 6 after grinding is sufficiently higher than the wire loop height h of the wire 5 and the wire 5 is not exposed from the packaging material 6.

[0039] In the first embodiment, the melting point of the bonding material 21 bonding the plurality of semiconductor elements 3 and the conductive substrate 2 is higher than the melting point of the solder. In addition, since the solder bonding step in the general semiconductor device manufacturing process is less than or equal to 450°C, the melting point of the bonding material 21 is preferably higher than 450°C.

[0040] Here, the plurality of semiconductor elements 3 and the conductor substrate 2 are sinter-bonded (fire-bonded) using, for example, a silver-based material or a copper-based material.

[0041] In the structure using the silver-based material for the bonding material 21, for example, after a paste to be the bonding material 21 is formed at a predetermined position of the conductor substrate 2 by printing or a dispenser, the semiconductor element 3 is placed on the paste so that the semiconductor element 3 and the conductor substrate 2 are closely bonded with each other without bubbles as much as possible. Thereafter, the paste is sintered at a temperature of 200° C. to 300° C. for several tens of minutes in a nitrogen atmosphere without applying pressure. As described above, in the structure using the silver-based material for the bonding material 21, sintering bonding of the plurality of semiconductor elements 3 and the conductor substrate 2 is performed without applying pressure.

[0042] In the structure using copper-based materials for the bonding material 21, for example, after the paste that will become the bonding material 21 is formed at a predetermined position of the conductor substrate 2 by printing or a dispenser, the semiconductor element 3 is placed on the paste, and pressure is applied by applying a load of 10 to 40 MPa, and at the same time, the paste is sintered in a nitrogen environment at a temperature of 200°C to 300°C for several tens of minutes. During this sintering, in order to prevent damage to the surface of the semiconductor element 3 caused by the application of the load, for example, a Teflon sheet is used. In addition, in the case of using a sheet molded product for the supply of sintering material, after the sintering material is temporarily attached to the back of the semiconductor element 3 in advance, the semiconductor element 3 is temporarily pressed to the predetermined position of the conductor substrate 2, and then pressure sintering is performed under the same conditions. As described above, in the structure using copper-based materials for the bonding material 21, the sintering bonding of the conductor substrate 2 and the plurality of semiconductor elements 3 is performed accompanied by pressure.

[0043] In addition, the conductor substrate 2 and the plurality of semiconductor elements 3 may also be diffused and bonded instead of being sintered. In addition, the bonding material 21 for bonding the conductor substrate 2 and the plurality of semiconductor elements 3 is described above, but the bonding material 22 for bonding the wiring element 4 and the conductor substrate 2 may also be the same as the bonding material 21.

[0044] The semiconductor package 1 according to the first embodiment further includes a protective film 36. The protective film 36 is a film that covers the end portions, i.e., the edges, of the plurality of semiconductor elements 3 and has a Young's modulus lower than that of the packaging material 6. The protective film 36 includes, for example, polyimide. In addition, for example, after the wiring element 4 and the plurality of semiconductor elements 3 are bonded to the conductor substrate 2, a precursor solution of the protective film 36 is drawn using a dispenser, and the precursor solution is fired to form the protective film 36.

[0045] The conductor substrate 2 mainly includes copper, for example. A recessed portion, namely a groove 2d, is provided in a region other than the region bonded to the wiring element 4 and the plurality of semiconductor elements 3 on the first main surface 2S1 of the conductor substrate 2. The recessed portion may be a recessed hole or the like instead of the groove 2d.

[0046] The plurality of conductor plates 38 and the plurality of conductor sheets 48 include copper as a main material, for example. Figure 2 As shown, the plurality of conductor plates 38 and the surface electrodes 32f of the plurality of semiconductor elements 3 are joined, for example, by solder 37, and the plurality of conductor pieces 48 and the plurality of second relay pads 43r of the wiring element 4 are joined, for example, by solder 47. The thickness of the plurality of conductor plates 38 and the plurality of conductor pieces 48, i.e., the thickness d of the plurality of conductor plates 38 and the thickness of the plurality of conductor pieces 48 after the above-mentioned grinding process, is sufficiently larger than the wire loop height h of the wire 5.

[0047] In the first embodiment, the plurality of semiconductor elements 3 include compound semiconductors. For example, the plurality of semiconductor elements 3 include silicon carbide (SiC) as a main material of the compound semiconductor. Each of the plurality of semiconductor elements 3 includes, for example, a MOSFET (not shown) for performing a switching operation and a body diode (not shown) for performing a freewheeling operation. Furthermore, the MOSFET and the body diode can be bidirectionally energized.

[0048] In the first embodiment, after forming a plurality of conductor plates 38, a semiconductor package 1 is further formed, and then a screening test is performed to detect defects in a plurality of semiconductor elements 3. Thus, it is possible to suppress the degradation of the characteristics of elements such as electrodes caused by the body diode energization in the screening test. In addition, in a structure in which the body diode energization is not used for the main freewheeling path, the semiconductor element 3 may also include a freewheeling SBD (Schottky barrier diode) instead of a body diode.

[0049] The wiring substrate 41 of the wiring element 4 may be, for example, a silicon substrate containing silicon (Si) as a main material. In this case, an oxide film is formed on the silicon substrate, and a plurality of first relay pads 42r, a plurality of second relay pads 43r, and a plurality of internal wirings 44i are formed on the oxide film. The patterns of these pads and wirings can be formed using a common wafer process method such as patterning achieved by photolithography after sputtering. These pads and wirings are covered, for example, by a cover film 46, which contains, for example, polyimide as the protective film 36.

[0050] The wiring substrate 41 of the wiring element 4 is not limited to the above-mentioned substrate, and may be, for example, a resin substrate containing resin. In this case, for example, before the wiring substrate 41 is bonded to the conductor substrate 2, a first relay pad 42r and a second relay pad 43r are formed in advance on the surface of the resin substrate by a copper material. Then, the conductor sheet 48 is bonded to the second relay pad 43r electrically connected to the outside by sintering bonding. Thereafter, the wiring substrate 41 is bonded to the conductor substrate 2. In addition, at least one of a bonding film, i.e., a thin film of copper, etc., a connecting film, i.e., a thin film of nickel, silver, copper, etc., and an anti-oxidation film, i.e., a thin film of gold, etc., is selectively formed on the back of the resin substrate. In addition, in the case where a nickel thin film is used for the connecting film, in order to ensure the bonding property of the sintering bonding using silver, it is preferred to provide a gold thin film on the outermost surface of the connecting film.

[0051] The semiconductor substrate 31 of the semiconductor element 3 is, for example, ground to a thickness of about 100 μm. On the other hand, the wiring element 4 is, for example, ground to a thickness of about 400 μm, about 250 μm, and is ground to about 150 μm as needed. When a silicon substrate is used for the wiring substrate 41 and the wiring element 4 is thinned to about 150 μm, it is difficult to cause problems in the wafer process. In this way, if there is a height difference between the semiconductor element 3 and the wiring substrate 4, the effect of facilitating the wire bonding of the wire 5 is produced. In addition, the outer periphery of the semiconductor element 3 has a pressure-resistant retaining structure such as a guard ring. Since it becomes a high electric field, it is preferred to keep the wire loop portion of the wire 5 above the outer periphery of the semiconductor element 3 in the cross-section as far away from the surface of the semiconductor element 3 as possible. In the case where the semiconductor element 3 is thinner than the wiring substrate 4, since the wire loop portion of the wire 5 can be kept away from the surface of the semiconductor element 3, it is preferred that the semiconductor element 3 is thinner than the wiring element 4.

[0052] Figure 3 FIG. 1 is a perspective schematic diagram showing the structure of a semiconductor device 7 using the semiconductor package 1 according to the first embodiment. Figure 4 It is a cross-sectional schematic diagram showing a part thereof.

[0053] like Figure 3 and Figure 4As shown, the semiconductor device 7 has more than or equal to one semiconductor package 1. Figure 3 and Figure 4 As shown, the semiconductor device 7 further includes a resin case 71, an insulating substrate 72, a first circuit pattern, i.e., a first main current circuit pattern 73, an external electrode 74, a circuit pattern 75, a wire 76, a main terminal, i.e., an external electrode 77, a wire 78, and a control terminal, i.e., a signal terminal 79. Figure 4 As shown, the semiconductor device 7 further includes a packaging material 80, a cover 81, and a metal layer 82. Furthermore, one or more semiconductor packages 1 may include six semiconductor packages constituting a full-bridge circuit as a unit.

[0054] The resin case 71 and the insulating substrate 72 constitute a container having a space opened at the top. The first main current circuit pattern 73 is disposed in a portion of the insulating substrate 72 that forms the space of the container. The first main current circuit pattern 73 is connected to the second main surface 2S2 ( Figure 2 ) are bonded. In the semiconductor device 7 thus constructed, the first main current circuit pattern 73 is used as a drain electrode. The first main current circuit pattern 73 is connected to an external electrode 74.

[0055] The circuit pattern 75 is connected to the exposed surface ( Figure 2 ) is connected. In addition, the circuit pattern 75 is connected to an external electrode 77. In this way, the external electrode 77 is electrically connected to the exposed surface of the conductor plate 38 through the wire 76. The wire 76 that electrically connects the exposed surface of the conductor plate 38 and the external electrode 77 can be, for example, a wire having a wire diameter greater than or equal to 400 μmΦ and containing aluminum as a main material, or a wire containing copper or the like as a main material. In addition, when the wire 76 is a wire containing copper as a main material, the electrical conductivity can be improved.

[0056] The signal terminal 79 is connected to the exposed surface ( Figure 2 The wire 78 electrically connecting the exposed surface of the conductor piece 48 and the signal terminal 79 may be, for example, a wire having a wire diameter of 200 μmΦ or more and containing aluminum as a main material.

[0057] As described above, the semiconductor package 1 is electrically connected to the external electrodes 74, 77, and the signal terminals 79. In the first embodiment, the resin case 71, the external electrodes 74, 77, and the signal terminals 79 are formed integrally, but the present invention is not limited thereto. After the semiconductor package 1 is connected to the external electrodes 74, etc., as shown in FIG. Figure 4As shown, by encapsulating the packaging material 80 in the space of the container body, the semiconductor package 1 is encapsulated by the packaging material 80. The packaging material 80 includes, for example, silicone gel. Figure 4 and Figure 5 As shown, by attaching a cover 81 to the resin case 71 , the outside of the semiconductor device 7 is isolated from the inside of the semiconductor device 7 including the semiconductor package 1 and the bonding structure around the semiconductor package 1 .

[0058] exist Figure 4 In the example of FIG. 1 , a metal layer 82 such as a conductor plate is disposed on the surface of the insulating substrate 72 on the opposite side to the semiconductor package 1 and is connected to a cooling fin (not shown). The metal layer 82 is connected to the cooling fin using, for example, a common bonding material and method such as brazing material, solder, or thermal grease. The heat generated from the semiconductor element 3 is dissipated by cooling the cooling fin. In addition, the metal layer 82 and even the semiconductor element 3 may be cooled by directly contacting the metal layer 82 with cooling water instead of connecting the metal layer 82 to the cooling fin.

[0059] <Summary of Implementation Method 1>

[0060] According to the semiconductor package 1 involved in the present embodiment 1, by using a wiring element 4 containing Si, for example, to perform signal wiring for a plurality of semiconductor elements 3 such as MOSFET containing SiC, it is possible to use the conductor piece 48 as a control pad (for example, a gate electrode, a source Kelvin electrode, a current sensing source electrode, a temperature sensing element electrode, etc.), the conductor plate 38 as a source electrode, and the conductor substrate 2 as a drain electrode. As a result, the plurality of semiconductor elements 3 can be used like a single semiconductor element or even a single semiconductor chip. Therefore, for example, cost reduction and miniaturization of the semiconductor device 7 can be achieved by improving the assemblability of the semiconductor device 7 in the wire bonding and chip welding processes. In addition, since the main current circuit pattern corresponding to the source electrode is not provided in the wiring element 4, cost reduction and miniaturization of the semiconductor package 1 can be achieved by improving the assemblability of the semiconductor package 1.

[0061] In addition, by providing the wiring element 4, the length of the wire 78 can be shortened as much as possible, and the diameter of the wire 78 can be reduced. Therefore, the size of the control pad 34c of the semiconductor element 3 can be reduced as much as possible. As a result, the effective area of ​​the semiconductor element 3 can be expanded. In particular, when an expensive material such as SiC is used for the base material of the semiconductor element 3, it is effective to reduce the product cost by expanding the effective area of ​​the semiconductor element 3.

[0062] In addition, in the first embodiment, each of the plurality of semiconductor elements 3 includes, for example, a MOSFET (not shown) for switching on and off and a body diode (not shown) for freewheeling. According to such a structure, since semiconductor elements such as SBDs can be omitted, the semiconductor package 1 can be miniaturized and the cost can be reduced.

[0063] In addition, when there are crystal defects in the MOSFET including SiC, if the body diode is energized, the defect sometimes grows and the characteristics are deteriorated. However, by performing a screening test, it is possible to avoid mounting a semiconductor package 1 containing defects on the semiconductor device 7. In this screening test, since a relatively large current needs to flow, there is a concern that if a large current flows to the thin surface electrode 32f, the surface electrode 32f will be damaged. In addition, there is a concern that the heat generated by the energization is not efficiently dissipated and accumulates in the semiconductor element 3, so that the semiconductor element 3 becomes high temperature. For example, there is also a concern that the current and heat are concentrated at the position where the test tool such as the probe contacts. However, as shown in the first embodiment, after forming a plurality of conductor plates 38, the semiconductor package 1 is further formed, and then the screening test is performed, so that such electrode damage can be suppressed. In addition, since a material with a large heat capacity such as copper is directly bonded to perform electrical and thermal connection, it is possible to effectively dissipate heat from the semiconductor element 3 compared to the case where the heat generated during the screening test is tested with the semiconductor element 3 alone. In addition, since the test tool such as the probe is once in contact with the conductor plate 38, the current can be distributed, and the current of the screening test can be uniformly passed to the semiconductor element 3. That is, it is preferable to apply a material such as copper having a large heat capacity and high electrical conductivity to the conductor plate 38. In addition, as shown in the first embodiment, in a structure in which the semiconductor package 1 is the minimum unit (1 in 1) in the circuit structure, the defect rate can be reduced compared with the case where the screening test is performed on a semiconductor device with a larger circuit scale such as 2 in 1 or 6 in 1.

[0064] In a structure in which the wiring substrate 41 of the wiring element 4 includes Si as a main material, the wiring element 4 can be easily formed by an existing wafer process. Therefore, if a back electrode that is the same as or similar to the semiconductor element 3 is also formed on the wiring element 4, the wiring element 4 can be formed by the same method as the semiconductor element 3, so the manufacturing cost can be reduced.

[0065] In the structure in which the wiring substrate 41 of the wiring element 4 includes resin, since the resin substrate to which the conductor sheet 48 is previously bonded can be bonded to the conductor substrate 2, the assemblability of the semiconductor package 1 can be improved. In addition, for example, in the case where the plurality of first relay pads 42r and the plurality of second relay pads 43r disposed on the surface of the resin substrate include copper material, the wiring substrate 41 can be bonded to the conductor substrate 2 after the conductor sheet 48 is bonded to the second relay pads 43r by sintering. In addition, by selectively forming at least one of, for example, a bonding film, i.e., a thin film of copper or the like, a connection film, i.e., a thin film of nickel, silver, copper or the like, and an anti-oxidation film, i.e., a thin film of gold or the like, on the back surface of the resin substrate, solder bonding properties and sintering bonding properties using silver or copper can be improved, thereby improving manufacturability. Furthermore, according to the wiring substrate 41 formed of a resin substrate, the processing time for joining the conductor sheet 48 to the second relay pad 43r can be shortened compared to the wiring substrate 41 formed of a silicon substrate, so that the manufacturing cost can be suppressed.

[0066] In addition, in the present first embodiment, the bonding material 21 that bonds the conductor substrate 2 and the plurality of semiconductor elements 3 uses a bonding material having a melting point higher than that of the solder. Thus, when the semiconductor package 1 is solder-bonded to, for example, the first main current circuit pattern 73 on the insulating substrate 72, the remelting of the bonding material 21 below the semiconductor element 3 can be suppressed. As a result, the degradation of the yield and the heat dissipation performance can be suppressed. Moreover, since the degradation of the bonding material 21 can be suppressed when the semiconductor element 3 is operated at a high junction temperature, the reliability of the semiconductor package 1 can be improved.

[0067] In addition, in the present embodiment 1, the sintering bonding of the conductor substrate 2 and the plurality of semiconductor elements 3 is performed without pressurization using a silver-based material. Thus, since positional displacement during pressurization can be avoided and dimensional tolerance can be reduced, the semiconductor package 1 can be miniaturized. In addition, since consumable parts such as Teflon sheets used in pressurization can be reduced, manufacturing costs can be reduced. In addition, in the case of using a copper-based material to perform the sintering bonding of the conductor substrate 2 and the plurality of semiconductor elements 3, compared with the case of using a gold-based material to perform the sintering bonding, since the bonding is high-strength, it is expected that the reliability of the semiconductor package 1 will be improved.

[0068] In addition, in the first embodiment, the end of the semiconductor element 3 is covered by the protective film 36. This can improve the adhesion between the semiconductor element 3 and the packaging material 6, and also improve the reliability of the semiconductor package 1 by providing stress buffering. In the structure in which the protective film 36 includes polyimide, the compatibility of the structural material on the surface of the semiconductor element 3 and the packaging material 6 is good, so the reliability of the semiconductor package 1 can be improved.

[0069] In addition, in the first embodiment, after the wiring element 4 and the plurality of semiconductor elements 3 are bonded to the conductor substrate 2, a precursor solution of the protective film 36 is drawn using a dispenser, and the precursor solution is fired to form the protective film 36. Thus, it is possible to suppress the bonding material 21 below the semiconductor element 3 from melting during the step of firing the protective film 36.

[0070] In addition, in the present embodiment 1, the conductor substrate 2 includes copper as a main material. As a result, the semiconductor package 1 can be easily soldered to the circuit pattern (for example, the first main current circuit pattern 73) outside the semiconductor package 1. In addition, according to such a structure, the heat of the semiconductor element 3 can be efficiently diffused, so the thermal resistance can be reduced. Generally, since the loss deteriorates if the temperature of the MOSFET containing SiC rises, it is preferred to efficiently cool the MOSFET, but there are problems such as difficulty in large-scale production due to the influence of the yield rate and high thermal resistance. In contrast, in the present embodiment 1, the conductor substrate 2 that is sintered and bonded using silver directly below the semiconductor element 3 includes a copper material with high thermal conductivity. Therefore, heat diffusion can be promoted. Specifically, efficient heat diffusion can be performed through an area that is substantially equal to or larger than the area of ​​the semiconductor element 3, so the thermal resistance can be reduced.

[0071] In addition, in the first embodiment, a recessed portion, that is, a groove 2d, is provided in an area other than the area bonded to the wiring element 4 and the plurality of semiconductor elements 3 in the first main surface 2S1 of the conductor substrate 2. As a result, the adhesion between the packaging material 6 and the conductor substrate 2 is improved, thereby improving the reliability of the semiconductor package 1. In addition, since the tensile stress on the surface of the conductor substrate 2 can be dispersed, the warping of the semiconductor package 1 can be suppressed.

[0072] In the first embodiment, the main material of the conductor plate 38 and the conductor piece 48 includes copper. This allows the conductor plate 38 and the conductor piece 48 to be formed at low cost, and they can be easily joined by soldering.

[0073] In addition, in the first embodiment, various bonding methods such as wire bonding and solder bonding are used for the external electrodes 74 and 77 and the signal terminals 79. As a result, the semiconductor package 1 can be easily mounted and bonded to the semiconductor device 7, and the conventional semiconductor devices and manufacturing equipment can be made common, thereby reducing the manufacturing cost of the semiconductor device 7 and the investment in the manufacturing equipment.

[0074] <Implementation Method 2>

[0075] Figure 6 FIG. 1 is a diagram showing the structure of a semiconductor package 1 according to a second embodiment of the present invention. Figure 2 Hereinafter, among the components according to the second embodiment, the components that are the same as or similar to the above components are denoted by the same reference numerals, and the different components will be mainly described.

[0076] like Figure 6 As shown, the conductor substrate 2 of the semiconductor package 1 according to the second embodiment includes a laminate 2e containing carbon fibers 2cf. The carbon fibers 2cf are arranged along the plane direction of the semiconductor substrate 31 of the plurality of semiconductor elements 3. By adjusting the parameters such as the content, diameter and length of the carbon fibers 2cf, the lateral thermal conductivity and linear expansion coefficient of the semiconductor element 3 can be adjusted arbitrarily. The laminate 2e includes aluminum as a main material.

[0077] In addition, in the second embodiment, the conductor substrate 2 includes: a laminated plate 2f, which is arranged on the first main surface 2S1 side and does not include the carbon fiber 2cf; and a laminated plate 2g, which is arranged on the second main surface 2S2 side and does not include the carbon fiber 2cf. The laminated plate 2f, 2g may each include a connection film arranged on the outermost surface of the laminate 2e, for example, including nickel or copper as a main material. In addition, the laminated plate 2f, 2g may each include an anti-oxidation film arranged on the outermost surface of the connection film, for example, including gold as a main material. The connection film and the anti-oxidation film can be formed by plating treatment, for example. In addition, even if the connection film is oxidized, the oxidation film can be relatively easily removed by performing a process such as solder bonding in a reducing environment, so the anti-oxidation film is not necessary.

[0078] <Summary of Implementation Method 2>

[0079] In the second embodiment, the conductor substrate 2 includes a laminate 2e containing carbon fibers 2cf. With such a structure, the linear expansion coefficient of the conductor substrate 2 is adjusted to suppress warping of the semiconductor package 1, thereby improving assemblability and reliability of the semiconductor package 1.

[0080] In the second embodiment, the carbon fibers 2cf are arranged along the plane direction of the semiconductor substrate 31 of the plurality of semiconductor elements 3. Thus, the heat generated by the semiconductor elements 3 can be efficiently diffused, and thus the semiconductor elements 3 can be efficiently cooled in a range greater than or equal to the effective area.

[0081] In addition, as shown in the second embodiment, in a structure in which the laminated plate 2e includes aluminum as a main material, the Young's modulus can be reduced compared to a structure in which the laminated plate 2e includes copper as a main material. By utilizing this point and adjusting the linear expansion coefficient of the conductor substrate 2 by including the carbon fibers 2cf, the stress generated in the semiconductor element 3 and the packaging material 6 can be reduced. As a result, the warping of the semiconductor package 1 can be suppressed, and the peeling of the packaging material 6 from the conductor substrate 2 can be suppressed, so that the assemblability and reliability of the semiconductor package 1 can be improved.

[0082] In addition, when the laminated plate materials 2f and 2g are each composed of a connection film containing nickel or copper as a main material disposed on the outermost surface of the laminated plate 2e containing aluminum, and an anti-oxidation film containing gold as a main material disposed on the outermost surface of the connection film, the manufacturability can be improved because the solder bonding property and the sintering bonding property using silver can be improved. In addition, when nickel is used for the connection film, it is preferable to provide gold on the outermost surface in order to ensure the sintering bonding property using silver.

[0083] <Implementation Method 3>

[0084] Figure 7 FIG. 1 is a diagram showing the structure of a semiconductor package 1 according to a third embodiment of the present invention. Figure 2 Hereinafter, among the components according to the third embodiment, the components that are the same as or similar to the above components are denoted by the same reference numerals, and the different components will be mainly described.

[0085] like Figure 7 As shown, the conductor substrate 2 of the semiconductor package 1 according to the third embodiment includes a stacked metal film having three or more metal films. Figure 7In the example, more than or equal to three metal films are the first metal film located on the inner side in the stacking direction, that is, the inner metal film 2j, and the second metal film and the third metal film located on the outer side in the stacking direction, that is, the surface metal film 2k and the surface metal film 2l. The surface metal film 2k is arranged on one surface of the inner metal film 2j, and the surface metal film 2l is arranged on the other surface of the inner metal film 2j. The linear expansion coefficient of the inner metal film 2j is lower than the linear expansion coefficient of the surface metal films 2k and 2l. The surface metal films 2k and 2l contain copper as the main material, and the inner metal film 2j contains nickel and iron as the main material. In addition, more than or equal to three metal films are not limited to the inner metal film 2j and the surface metal films 2k and 2l.

[0086] <Summary of Implementation Method 3>

[0087] In the third embodiment, since the linear expansion coefficient of the conductor substrate 2 can be adjusted by the inner metal film 2 j and the surface metal films 2 k and 2 l , warping of the semiconductor package 1 can be suppressed, resulting in improved assemblability and reliability of the semiconductor package 1 .

[0088] In addition, in the third embodiment, since the surface metal film 2k contains copper as a main material, the heat generated by the semiconductor element 3 can be easily diffused. In addition, since the surface metal film 2l contains copper as a main material, solder bonding can be easily performed. Moreover, by sandwiching the inner metal film 2j containing nickel having a lower linear expansion coefficient than copper by the surface metal films 2k and 2l containing copper, the warping of the semiconductor package 1 can be suppressed. In addition, since the bonding property of copper and nickel is relatively good, the bonding property of the inner metal film 2j and the surface metal films 2k and 2l can be ensured, and as a result, the above-mentioned warping can be suppressed, and the manufacturability and reliability of the semiconductor package 1 can be ensured.

[0089] <Implementation Method 4>

[0090] Figure 8 1 is a perspective view schematically showing the structure of a semiconductor device 7 according to Embodiment 4. Hereinafter, components according to Embodiment 4 that are identical or similar to the above components are denoted by the same reference numerals, and different components will be mainly described.

[0091] like Figure 8 As shown, in the semiconductor device 7 according to the fourth embodiment, instead of Figure 3The conductor frame 83 is used instead of the conductor 76 of the semiconductor package 1. Specifically, the circuit pattern 75 is connected to the exposed surface of the conductor plate 38 in the second surface 1S2 of the semiconductor package 1 through the conductor frame 83, and the circuit pattern 75 is connected to the external electrode 77. That is, the external electrode 77 is electrically connected to the exposed surface of the conductor plate 38 through the conductor frame 83. In addition, the conductor frame 83 and the external electrode 77 may be formed integrally. The exposed surface of the conductor plate 38 and the conductor frame 83 may be joined, for example, by solder, or may be joined, for example, by ultrasonic bonding.

[0092] <Summary of Implementation Method 4>

[0093] In the fourth embodiment, the external electrode 77 is electrically connected to the exposed surface of the conductor plate 38 via the conductor frame 83. Figure 3 Compared with the semiconductor device 7 of FIG. 1 , the resistance can be lowered and the bonding can be easily performed. In addition, compared with the wire bonding, the processing time can be shortened and the manufacturing cost can be suppressed.

[0094] <Implementation method 5>

[0095] Fig. 9 1 is a schematic cross-sectional view showing the structure of a semiconductor device 7 according to Embodiment 5. Hereinafter, components according to Embodiment 5 that are identical or similar to the above components are denoted by the same reference numerals, and different components are mainly described.

[0096] like Fig. 9 As shown, the semiconductor device 7 according to the fifth embodiment and Figure 4 The semiconductor device 7 of the embodiment 1 includes a semiconductor package 1, an insulating substrate 72, a first main current circuit pattern 73, and a metal layer 82. The first main current circuit pattern 73 is bonded to the second main surface 2S2 of the conductive substrate 2 in the first surface 1S1 of the semiconductor package 1 by, for example, solder. The first main current circuit pattern 73 is bonded to the second main surface 2S2 of the conductive substrate 2 in the first surface 1S1 of the semiconductor package 1 by, for example, solder. Figure 3 The first main electrode 87 of the external electrode 74 is connected.

[0097] The semiconductor device 7 according to the fifth embodiment further includes an insulating substrate 84, a second main current circuit pattern 85 as a second circuit pattern, and a control terminal pattern 86 as a third circuit pattern. The insulating substrate 84 is disposed opposite to the exposed surfaces of the conductor plate 38 and the conductor sheet 48.

[0098] The second main current circuit pattern 85 is disposed on the insulating substrate 84 and is bonded to the exposed surface of the conductor plate 38 on the second surface 1S2 of the semiconductor package 1. The exposed surface of the conductor plate 38 and the second main current circuit pattern 85 are bonded to each other, for example, by solder. Figure 3 The second main electrode 88 of the external electrode 77 is connected.

[0099] The control terminal pattern 86 is disposed on the insulating substrate 84 and is bonded to the exposed surface of the conductor piece 48 on the second surface 1S2 of the semiconductor package 1. The exposed surface of the conductor piece 48 and the control terminal pattern 86 are bonded to each other, for example, by solder. Figure 3 The control terminal 89 of the semiconductor device 7 is connected to the signal terminal 79. Thus, a control signal from outside the semiconductor device 7 is input to the semiconductor element 3 in the semiconductor package 1 via the signal terminal 79 and the like.

[0100] A cooling metal layer 82 is provided on the surface of the insulating substrate 72 opposite to the surface on which the first main current circuit pattern 73 is provided, and a cooling metal layer 90 is provided on the surface of the insulating substrate 84 opposite to the surface on which the second main current circuit pattern 85 is provided. Moreover, by cooling the cooling metal layers 82 and 90 directly or indirectly, the semiconductor package 1 is cooled from both sides. In a structure for direct cooling, cooling is performed by directly bringing cooling water into contact with the cooling portion of the metal layers 82 and 90 by making a part of the cooling metal layers 82 and 90 a watertight area. In a structure for indirect cooling, the cooling metal layers 82 and 90 are connected to cooling fins using common bonding materials and methods such as brazing material, solder, and thermal grease. By cooling the cooling fins, the heat generated from the semiconductor element 3 is dissipated.

[0101] <Summary of Implementation Method 5>

[0102] In the fifth embodiment, the semiconductor package 1 can be efficiently cooled by a double-sided cooling structure for cooling both sides of the semiconductor device 7. In addition, according to the structure of the fifth embodiment in which the semiconductor package 1 is sandwiched between two insulating substrates 72 and 84, the semiconductor device can be easily assembled compared to the case where a plurality of SiC MOSFETs having relatively small chip sizes are individually arranged in parallel and assembled.

[0103] In addition, since the area of ​​the semiconductor package 1 is larger than that of the single semiconductor element 3, the tilting accuracy can be easily improved compared to the case where the semiconductor element 3 is directly mounted on the double-sided cooling structure, and as a result, the thermal resistance of the double-sided cooling structure can be stabilized. Furthermore, since the tilting accuracy and position accuracy are improved, it is possible to suppress damage to the semiconductor element caused by pressurization or fixation by a tool.

[0104] Furthermore, the present invention can freely combine the various embodiments within the scope of the invention, and can appropriately modify or omit the various embodiments.

[0105] Although the present invention has been described in detail, the above description is in all aspects illustrative and the present invention is not limited thereto. It should be understood that numerous modifications not shown here are conceivable without departing from the scope of the present invention.

[0106] Description of the label

[0107] 1 semiconductor package, 2 conductor substrate, 2cf carbon fiber, 2d groove, 2e laminated board, 2j inner metal film, 2k, 2l surface metal film, 2S1 first main surface, 2S2 second main surface, 3 semiconductor element, 4 wiring element, 5, 76, 78 wire, 6 packaging material, 7 semiconductor device, 31 semiconductor substrate, 32f surface electrode, 33b back electrode, 34c control pad, 36 protective film, 37 solder, 38 conductor plate, 41 wiring substrate, 42r first relay pad, 43r second relay pad, 44i internal wiring, 47 solder, 48 conductor sheet, 73 first main current circuit pattern, 77 external electrode, 79 signal terminal, 83 conductor frame, 84 insulating substrate, 85 second main current circuit pattern, 86 control terminal pattern.

Claims

1. A semiconductor package, comprising: Conductor substrate; a plurality of semiconductor elements bonded to the first main surface of the conductor substrate and having a switching function; and a wiring element bonded to the first main surface of the conductor substrate, Each of the plurality of semiconductor elements comprises: 1st substrate; a first main electrode portion disposed on a surface of the first substrate opposite to the conductive substrate; a second main electrode portion disposed on a surface of the first substrate on the conductive substrate side and bonded to the conductive substrate; as well as a control pad for controlling a current flowing between the first main electrode portion and the second main electrode portion, The wiring component includes: 2nd substrate; a plurality of first relay pads disposed on a surface of the second substrate opposite to the conductive substrate and connected to the control pads of the plurality of semiconductor elements via conductive wires; a plurality of second relay pads disposed on the surface of the second substrate opposite to the conductive substrate, the number of which is less than or equal to the number of the plurality of first relay pads; and a plurality of wirings disposed on the surface of the second substrate opposite to the conductive substrate, and selectively connecting the plurality of first relay pads and the plurality of second relay pads; The semiconductor package also has: a plurality of first conductor members joined to the first main electrode portions of the plurality of semiconductor elements; a plurality of second conductor members joined to the plurality of second relay pads of the wiring element; as well as A packaging material that covers the multiple semiconductor elements, the wiring elements, at least a portion of the multiple first conductor components, at least a portion of the multiple second conductor components, and the first main surface of the conductor substrate in a state where the surfaces of the multiple first conductor components on the opposite side to the conductor substrate, i.e., the exposed surfaces, the surfaces of the multiple second conductor components on the opposite side to the conductor substrate, and the second main surface of the conductor substrate on the opposite side to the first main surface are exposed.

2. The semiconductor package according to claim 1, wherein: The melting point of the bonding material bonding the plurality of semiconductor elements and the conductor substrate is higher than the melting point of the solder.

3. The semiconductor package according to claim 1, wherein: The plurality of semiconductor elements and the conductor substrate are sintered and bonded using a silver-based material or a copper-based material.

4. The semiconductor package according to claim 2, wherein: The plurality of semiconductor elements and the conductor substrate are sintered and bonded using a silver-based material or a copper-based material.

5. The semiconductor package according to claim 1, wherein: The plurality of semiconductor elements and the conductor substrate are diffusion-bonded.

6. The semiconductor package according to claim 2, wherein: The plurality of semiconductor elements and the conductor substrate are diffusion-bonded.

7. The semiconductor package according to any one of claims 1 to 6, wherein: A protective film is also provided, which covers the end portions of the plurality of semiconductor elements and has a Young's modulus lower than that of the packaging material.

8. The semiconductor package according to claim 7, wherein: The protective film includes polyimide.

9. The semiconductor package according to any one of claims 1 to 6, wherein: The conductor substrate includes copper as a main material.

10. The semiconductor package according to any one of claims 1 to 6, wherein: A recessed portion is provided in a region of the first main surface of the conductor substrate excluding a region bonded to the plurality of semiconductor elements and the wiring element.

11. The semiconductor package according to any one of claims 1 to 6, wherein: The conductor substrate includes a laminated plate containing carbon fibers.

12. The semiconductor package according to claim 11, wherein The carbon fibers are arranged along a plane direction of the first substrate of the plurality of semiconductor elements.

13. The semiconductor package according to claim 11, wherein: The laminated plate contains aluminum as a main material.

14. The semiconductor package according to claim 12, wherein: The laminated plate contains aluminum as a main material.

15. The semiconductor package according to any one of claims 1 to 6, wherein: The conductor substrate includes a stacked metal film having three or more metal films, Among the three or more metal films, a metal film located on the inner side in the stacking direction has a lower linear expansion coefficient than a metal film located on the outer side in the stacking direction.

16. The semiconductor package according to claim 15, wherein: The stacked metal film comprises: a first metal film; and a second metal film and a third metal film, which are disposed on one surface and the other surface of the first metal film, respectively; The second metal film and the third metal film include copper as a main material.

17. The semiconductor package according to claim 16, wherein: The first metal film includes nickel and iron as main materials.

18. The semiconductor package according to any one of claims 1 to 6, wherein: The plurality of first conductor members and the plurality of second conductor members include copper as a main material.

19. The semiconductor package according to any one of claims 1 to 6, wherein: The plurality of first conductor members and the first main electrode portions of the plurality of semiconductor elements are joined by solder.

20. The semiconductor package according to any one of claims 1 to 6, wherein: The plurality of semiconductor elements include compound semiconductors.

21. The semiconductor package according to claim 20, wherein: The plurality of semiconductor elements include silicon carbide as a main material of the compound semiconductor.

22. The semiconductor package according to any one of claims 1 to 6, wherein: The second substrate of the wiring element includes silicon as a main material.

23. The semiconductor package according to any one of claims 1 to 6, wherein: The second substrate of the wiring element includes resin.

24. The semiconductor package according to any one of claims 1 to 6, wherein: The semiconductor element is thinner than the wiring element.

25. The semiconductor package according to any one of claims 1 to 6, wherein: Each of the plurality of semiconductor elements includes a MOSFET for performing switching operations and a body diode for performing freewheeling operations. Bidirectional current flow between the MOSFET and the body diode is possible.

26. A method for manufacturing a semiconductor package, which is the method for manufacturing a semiconductor package according to claim 3 or 4, in which: The sintering bonding of the plurality of semiconductor elements and the conductor substrate is performed using a silver-based material without applying pressure.

27. A method for manufacturing a semiconductor package, which is the method for manufacturing a semiconductor package according to claim 7, in which: After the plurality of semiconductor elements and the wiring element are bonded to the conductor substrate, a precursor solution of the protective film is drawn using a dispenser and the precursor solution is fired to form the protective film.

28. A method for manufacturing a semiconductor package, which is the method for manufacturing a semiconductor package according to claim 8, in which: After the plurality of semiconductor elements and the wiring element are bonded to the conductor substrate, a precursor solution of the protective film is drawn using a dispenser and the precursor solution is fired to form the protective film.

29. A method for manufacturing a semiconductor package, which is the method for manufacturing a semiconductor package according to any one of claims 1 to 25, in which: After forming the plurality of first conductor members, a screening test is performed to detect defects in the plurality of semiconductor elements. 30 . A semiconductor device comprising at least one semiconductor package according to claim 1 .

31. The semiconductor device according to claim 30, wherein: At least one of the semiconductor packages is configured to include six semiconductor packages constituting a full-bridge circuit as a unit.

32. The semiconductor device according to claim 30 or 31, wherein: The device further includes a first circuit pattern joined to the second main surface of the conductive substrate exposed from the packaging material by solder.

33. The semiconductor device according to claim 32, wherein: The first circuit pattern is used as a drain electrode.

34. The semiconductor device according to claim 30 or 31, wherein: A control terminal is further provided, and the control terminal is connected to the exposed surface of the second conductor member through a wire.

35. The semiconductor device according to claim 30 or 31, wherein: A main terminal is further provided, and the main terminal is electrically connected to the exposed surface of the first conductive member through a wire.

36. The semiconductor device according to claim 35, wherein: The conductive wire electrically connecting the exposed surface of the first conductive member and the main terminal includes copper as a main material.

37. The semiconductor device according to claim 30 or 31, wherein: A main terminal is further provided, and the main terminal is electrically connected to the exposed surface of the first conductive member through a conductive frame.

38. The semiconductor device according to claim 37, wherein: The exposed surface of the first conductive member and the conductive frame are joined by solder.

39. The semiconductor device according to claim 37, wherein: The exposed surface of the first conductor member and the conductor frame are ultrasonically bonded.

40. The semiconductor device according to claim 30, wherein Also features: an insulating substrate disposed opposite to the exposed surface of the first conductor component and the exposed surface of the second conductor component; a second circuit pattern disposed on the insulating substrate and bonded to the exposed surface of the first conductor member; as well as A third circuit pattern is disposed on the insulating substrate and is bonded to the exposed surface of the second conductive member.

41. The semiconductor device according to claim 40, wherein The exposed surface of the first conductor member and the second circuit pattern are joined by solder. The exposed surface of the second conductor member and the third circuit pattern are joined by solder.

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