Transistor characteristics, simulation method of electronic circuit characteristics, non-transitory recording medium

Abstract

Provided are a method for simulating transistor characteristics and electronic circuit characteristics, and a non-transitory recording medium. The transistor includes a semiconductor layer and a gate. The semiconductor layer includes a source and a drain separated from each other, and a channel located between the source and the drain. The gate faces the channel of the semiconductor layer. The method includes calculating a thermal equilibrium trapped charge density Q' based on the Poisson equation and the charge neutrality law. T Calculating the transient trapped charge density q after applying a voltage between the gate and the semiconductor layer T process (b); based on the transient trap charge density q T Calculate the free carrier charge density q I process (c); based on the free carrier charge density q I Calculate the drain current I flowing between the source and the drain d process (d).

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Japanese Patent Application No. 2020-009620, filed on January 24, 2020, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The present disclosure generally relates to a method for simulating transistor characteristics, a method for simulating characteristics of an electronic circuit including a transistor, and a non-transitory recording medium storing a simulation program for transistor characteristics. Background Art

[0004] Typically, liquid crystal displays, organic electroluminescent (EL) displays, and similar display devices are manufactured by forming a semiconductor layer on a glass substrate, a plastic film substrate, or the like, and forming various types of electronic circuits including transistors in or on the semiconductor layer. It is difficult to form a single-crystal semiconductor layer on a glass substrate, a plastic film substrate, or the like. Therefore, typically, a non-single-crystal (polycrystalline, amorphous, or the like) semiconductor layer containing many crystal defects is formed on a glass substrate, a plastic film substrate, or the like. Typically, a plurality of thin-film transistors (TFTs) formed from the non-single-crystal semiconductor layer are installed in the display device.

[0005] Simulation software called Simulation Program with Integrated Circuit Emphasis (SPICE) is widely used to design electronic circuits. A simulation model called a compact model for a transistor is required to simulate the characteristics of the electronic circuit including the transistor using a circuit simulator.

[0006] Examples of compact models for metal oxide semiconductor field effect transistors (MOSFETs) formed from single crystal semiconductor layers include the Berkeley short-channel IGFET model (BSIM), the Hiroshima University Semiconductor Science and Technology Research Center (STARC) IGFET model (HiSIM), etc. Meanwhile, examples of known compact models for thin film transistors formed from non-single crystal semiconductor layers include the model disclosed in Japanese Patent Application No. 2010-062441, Japanese Patent Application No. 2013-080847, and Non-Patent Document 1 (IEEE Trans. Electron Devices, vol. 36, No. 12, pp. 2764-2769, 1989).

[0007] However, these compact models for thin-film transistors do not reflect the non-quasistatic effect (NQS) of trapped charge in a trapped state caused by structural defects. The NQS effect is defined as the time delay for the charge distribution in the channel to reach its thermal equilibrium value after changing the terminal voltage. The time required for the trapped charge distribution to reach thermal equilibrium is significantly longer than the time required for the free carrier charge to reach thermal equilibrium. For example, the time delay for the trapped charge distribution to reach thermal equilibrium can range from a few seconds to tens of seconds.

[0008] Japanese Patent Application Publication No. 2010-171384 discloses a compact MOSFET model that reflects the NQS effect of free-carrier charge. In Japanese Patent Application Publication No. 2010-171384, a model is constructed that assumes that the free-carrier charge density changes exponentially with time (with a time dependence of a first-order delayed response) until the free-carrier charge density reaches equilibrium after voltage is applied to the MOSFET.

[0009] Non-patent document 2 (IEEE Trans. Electron Devices, vol. 62, No. 3, pp. 862-868, 2015) discloses a compact model of a thin film transistor that reflects the NQS effect of trapped charge. In Non-patent document 2, the NQS effect of trapped charge is incorporated into the compact model for a thin film transistor by applying the model disclosed in Japanese Patent Application Publication No. 2010-171384.

[0010] However, these compact models of thin-film transistors that reflect the NQS effect of trapped charges cannot satisfactorily reproduce the measured results. This is because the simple first-order delay function is not suitable for describing the NQS effect in trapped charges.

[0011] The present disclosure has been made in view of the above-described situation, and an object of the present disclosure is to provide a simulation method of transistor characteristics that more closely reproduces measurement results. Summary of the Invention

[0012] A method for simulating transistor characteristics, the transistor comprising a semiconductor layer and a gate, the transistor comprising a source and a drain separated from each other and a channel located between the source and the drain, the gate facing the channel of the semiconductor layer, the method comprising: calculating a thermal equilibrium trapped charge density Q' based on the Poisson equation and the charge neutrality law T The process (a) is as follows: the Poisson equation represents the relationship between the electrostatic potential and the charge in the channel, the charge including the free carrier charge and the trapped charge in the trap state in the channel, the charge neutrality law is applicable to the charge accumulated on the gate and the channel; the transient trapped charge density q is calculated after applying a voltage between the gate and the semiconductor layer. TProcess (b), where it is assumed that the transient trapped charge density q T The time variation of is represented by a function obtained by superimposing multiple exponential functions with different time constants; based on the transient trap charge density q T Calculate the free carrier charge density q I process (c); and based on the free carrier charge density q I Calculate the drain current I flowing between the source and drain d process (d).

[0013] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the disclosure.

[0014] According to the present disclosure, a simulation method is provided that more closely reproduces transistor characteristics of measurement results. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] A more complete understanding of the present application may be obtained when the following detailed description is considered in conjunction with the following drawings, in which:

[0016] Figure 1 is a block diagram showing a typical computer configuration;

[0017] Figure 2 is a flowchart showing the processing flow of the circuit simulator;

[0018] Figure 3A is a cross-sectional view showing a transistor as a simulation model;

[0019] Figure 3B is a schematic diagram showing electrostatic potential distribution and charge distribution in a semiconductor layer constituting a transistor;

[0020] Figure 4 is a flow chart of a method for simulating transistor characteristics according to this embodiment;

[0021] Figure 5 is a cross-sectional view showing the fabrication of a transistor;

[0022] Figure 6 is a diagram showing measurement results and simulation results related to transient response current characteristics of a transistor;

[0023] Figure 7 The figure shows the relationship between the drain current I and the channel length of the transistor when it is set to 4 μm. d -Gate voltage V g Plots of characteristic-related measurement and simulation results;

[0024] Figure 8The figure shows the relationship between the drain current I and the channel length of the transistor when it is set to 100 μm. d -Gate voltage V g Plots of characteristic-related measurement and simulation results;

[0025] Figure 9 The figure shows the relationship between the drain current I and the channel length of the transistor when it is set to 4 μm. d -Drain voltage V d Plots of characteristic-related measurement and simulation results;

[0026] Figure 10 The figure shows the relationship between the drain current I and the channel length of the transistor when it is set to 100 μm. d -Drain voltage V d Plots of characteristic-related measurement and simulation results;

[0027] Figure 11 is a diagram showing measurement results and simulation results related to hysteresis characteristics of a transistor;

[0028] Figure 12 is a diagram showing measurement results and simulation results related to overshoot characteristics and undershoot characteristics of a transistor;

[0029] Figure 13A is a diagram showing a voltage waveform to be applied to a transistor;

[0030] Figure 13B is a diagram showing measurement results related to historical characteristics of a transistor;

[0031] Figure 13C is a diagram showing simulation results related to historical characteristics of a transistor;

[0032] Figure 14 It is the equivalent circuit corresponding to the display device;

[0033] Figure 15A and Figure 15B are diagrams showing voltage waveforms of Vscan and Vdata input to an equivalent circuit representing a display device, respectively;

[0034] Figure 16A is a diagram showing measurement results related to electrical characteristics of an equivalent circuit of a display device and simulation results according to a simulation method using a plurality of time constants;

[0035] Figure 16B It is through magnification Figure 16A A diagram obtained by taking a portion of a diagram of;

[0036] Figure 17Ais a diagram showing measurement results related to electrical characteristics of an equivalent circuit of a display device and simulation results according to a simulation method using a single time constant; and

[0037] Figure 17B It is through magnification Figure 17A A diagram obtained by taking a portion of a diagram of FIG. DETAILED DESCRIPTION

[0038] The following describes a method for simulating transistor characteristics according to an embodiment. It should be noted that, in general, the following simulation method is written as a program so that it can be read by an ordinary computer such as a workstation or a personal computer. In particular, the simulation method is written so that it can be used as a compact model in a circuit simulator SPICE. In addition, the desired characteristics of the transistor and the characteristics of the electronic circuit including the transistor are simulated by causing a computer (particularly a circuit simulator SPICE incorporated into the computer) to execute the written program.

[0039] Figure 1 The configuration of a typical computer is shown in a simplified manner. Computer 90 includes an input device 91, a storage device (memory) 92, a central processing device (CPU or central processing unit) 93, and an output device 94. These devices are generally connected to a bus (signal transmission path).

[0040] The input device 91 includes, for example, a keyboard, an operation panel, a voice input device, various data reading devices, etc. Basic information required for simulation, a circuit diagram (network topology) to be simulated, a compact model (mathematical model equation), etc. are inputted via the input device 91 .

[0041] The storage device 92 includes non-transitory recording media such as flash memory and a hard disk. Various types of information inputted from the input device 91, programs related to the circuit simulator and programs corresponding to the simulation method described below, simulation results calculated according to the programs, etc. are stored in the storage device 92.

[0042] The central processing device 93 performs arithmetic processing according to various programs stored in the storage device 92. The central processing device 93 controls various devices based on the results of the arithmetic processing.

[0043] The output device 94 includes, for example, a monitor, a printer, an external storage device, etc. In one example, the output device 94 outputs (displays) the result of arithmetic processing performed by the central processing device 93 (simulation result).

[0044] Figure 2 The process flow of a circuit simulator (SPICE) is shown in a simplified manner. Figure 1 A circuit simulator 95 is started on the computer 90 shown.

[0045] Information 96 about the network topology including various circuit elements (e.g., the equivalent circuit of the organic EL display described later) is stored in the circuit simulator 95. This information is also called a "net list." The circuit simulator 95 solves the network equation (nonlinear multidimensional simultaneous equations) corresponding to the network topology based on Kirchhoff's Law. Specifically, the circuit simulator 95 calculates the voltage and current values ​​of all terminals (nodes) of the circuit elements in the network.

[0046] When simulating the characteristics of an electronic circuit including transistors, a compact model (mathematical model equation) 97 representing the relationship between the terminal voltage and terminal current of the transistor is incorporated into the network equations. The model parameters included in compact model 97 are predetermined based on the measurement results of the transistors. The circuit simulator 95 solves the network equations incorporated into the compact model to output the characteristics 98 (current waveform, voltage waveform, etc.) of the electronic circuit including the transistors.

[0047] Figure 3A and Figure 3B A simulation model of a transistor assumed in this embodiment is shown. Figure 3A is a cross-sectional view schematically showing the structure of a transistor. Figure 3B is a schematic diagram showing the electrostatic potential distribution and charge distribution in the semiconductor layer (channel) when a gate voltage is applied to the transistor.

[0048] like Figure 3A As shown in FIG. 5 , a gate-insulated TFT in which a semiconductor layer 30, a gate insulating film 20, and a gate electrode 10 are laminated is assumed as a transistor 50 to be simulated. The semiconductor layer 30 has a structure in which a channel 31 is sandwiched between a low-resistance source electrode 32 and a drain electrode 33. The gate electrode 10 is arranged opposite the channel 31 of the semiconductor layer 30. The gate insulating film 20 is arranged between the semiconductor layer 30 (channel 31) and the gate electrode 10.

[0049] Semiconductor layer 30 is formed of a non-single-crystal semiconductor material containing many crystal defects (trap states). In one example, transistor 50 constitutes an n-channel TFT. It should be noted that when assuming a p-channel, the following voltage and charge polarity can be simply reversed.

[0050] The thickness direction of the semiconductor layer 30 is defined as the x-direction (x-axis), and the interface position between the semiconductor layer 30 and the gate insulating film 20 is set as the origin of the x-axis. The direction in which the source electrode 32, the channel 31, and the drain electrode 33 are arranged is defined as the y-direction (y-axis), and the boundary position between the source electrode 32 and the channel 31 is set as the origin. The x-axis and the y-axis are orthogonal to each other, and the direction orthogonal to the x-axis and the y-axis is defined as the z-direction (z-axis, not shown). The length of the channel 31 along the y-axis is defined as L, and the width along the z-axis is defined as W.

[0051] like Figure 3B As shown, when a voltage V is applied between the gate 10 and the semiconductor layer 30 g When the voltage applied to the gate insulating film 20 is defined as V ox , and the voltage applied to the semiconductor layer 30 (channel 31) (also referred to as the electrostatic potential in the semiconductor layer) is defined as Φ. It should be noted that the electrostatic potential on the surface of the semiconductor layer 30 (the interface with the gate insulating film 20) is defined as the surface potential Φ s .

[0052] Here, the charge density (charge amount per unit volume) of the gate charge charged on the gate 10 is defined as Q G , the charge density of the induced free carrier charge in the semiconductor layer is defined as Q I , and the charge density of the trapped charges is defined as Q T The capacitance (per unit area) of the gate insulating film 20 is defined as C g .

[0053] Generally, the semiconductor layer 30 has a band structure including a valence band and a conduction band and an energy gap therebetween. The energy of the valence band peak is defined as E v , and the energy of the conduction band valley is defined as E c .

[0054] The electrical characteristics of the above transistor are simulated, especially the current flowing between the source and the drain (in the channel) (called "drain current I d ”).

[0055] Figure 4 The simulation method according to this embodiment mainly includes the process of preparing information required for simulation (S110), using the prepared information to calculate the charge density Q' of the trapped charge under thermal equilibrium, and T The process (thermal equilibrium trap charge density) (S120), calculates the transient charge density q of the trapped charge T process (S130), and using the charge density q T Calculate the charge density Q'I of the free carrier charge and the drain current I d Each of the processes S110 to S170 will be described in detail below.

[0056] In process S110, information required for simulation is prepared. Examples of this information include model parameters, TFT element information, terminal voltage information, etc. Model parameters are information such as free carrier charge mobility (surface carrier mobility μ d), parameters related to the energy distribution of the trap state, T0, NTC, etc. The model parameters are pre-modeled based on the TFT measurement results. TFT element information includes information such as channel length L, channel width W, thickness of the gate insulating film, etc. The terminal voltage information includes the voltage values ​​of the gate, source, and drain (gate voltage V g , source voltage V s and drain voltage V d In addition, parameters related to simulation time are also given, such as the time step (t i –t i-1 ) and the end of the time step (the final time step t max ) between the two.

[0057] Next, we describe the charge density used to calculate the trapped charge in thermal equilibrium (thermal equilibrium trapped charge density) Q' T Process S120.

[0058] In process S120, the charge density of the trapped charges in thermal equilibrium (thermal equilibrium trapped charge density) is calculated mainly based on the basic information. Specifically, the thermal equilibrium trapped charge density is calculated as the surface charge density Q' of the trapped charges. T It should be noted that the thermal equilibrium trapped charge density can be calculated as the total trapped charge density of all regions of the channel.

[0059] For thermal equilibrium trap charge density (surface charge density Q' T The calculation process of ) is as follows. The calculation process includes the process of calculating the surface potential of the semiconductor layer and the process of calculating the thermal equilibrium trap charge density (surface charge density Q') based on the surface potential. T It should be noted that in this calculation process, the surface charge density of the free carrier charge under thermal equilibrium, the drain current, etc. can be calculated simultaneously.

[0060] Calculation of surface potential

[0061] First, calculate the surface potential of the semiconductor layer (channel). In short, the surface potential Φ s It is calculated based on the Poisson equation and the charge neutrality law. The Poisson equation expresses the relationship between free carrier charge, trapped charge, and electrostatic potential induced in the channel, and in this case, this relationship can be expressed as the following equation (1).

[0062] Equation 1

[0063]

[0064] Here, φ(x) is the electrostatic potential in the thickness direction (x direction) of the semiconductor layer, and Q T (x) and QI (x) is the charge density of trapped charges and free carrier charges in the thickness direction (x direction) of the semiconductor layer. In addition, ε is the dielectric constant of the semiconductor layer.

[0065] The charge neutrality law is a physical law that states that when the gate, gate insulating film, and semiconductor layer are regarded as a capacitor, the charge charged to the capacitor remains electrically neutral (equal amounts of positive and negative charges are charged), and can be expressed as the following equation (2).

[0066] Equation 2

[0067]

[0068] Here, C g is the capacitance of the gate insulating film, V g is the gate voltage, V fb is the flat band voltage of the semiconductor layer, and (dΦ s / dx) is the electric field intensity at the interface between the gate insulating film and the semiconductor layer on the semiconductor layer side.

[0069] Q in Equation 1 T (x) and Q I (x) are given by the following equations (3) and (4), respectively.

[0070] Equation 3

[0071]

[0072] Equation 4

[0073]

[0074] Here, q is the charge, k B is the Boltzmann constant, n i is the intrinsic carrier density of the semiconductor layer, and T is the temperature. T0 and NTC are model parameters related to the energy distribution of the trap states. It should be noted that the charge density Q representing the trapped charge T The equation of (x) is not limited to equation (3). For example, the charge density Q of the trapped charge T (x) can be expressed using an analytical function represented by the sum of two exponential functions with different NTC and T0 values, a constant function that does not depend on the electrostatic potential φ(x), etc.

[0075] Integrating Equation 1 (Equations (3) and (4) are substituted) yields (dΦ s / dx) into equation (2), and the following equation (5) is obtained.

[0076] Equation 5

[0077] Cg φ s +F(φ s )-C g (V g -V fb )=0 (5)

[0078] Here, F(Φ s ) is given by the following equation (6).

[0079] Equation 6

[0080]

[0081] Equations (5) and (6) represent the external given gate voltage V g and surface potential Φ s These equations are nonlinear and cannot be solved analytically. Therefore, they are solved numerically using, for example, the Newton-Raphson method.

[0082] For example, the surface potential Φ on the source and drain sides s0 and Φ sL By respectively on the source side of the channel (y = 0, gate voltage = V g , source voltage = 0V) and drain side (y = L, gate voltage = V g , drain voltage = V d )Solve these equations to calculate.

[0083] Calculation of thermal equilibrium trap charge density

[0084] First, the procedure for deriving the charge density of trapped charges (and free carrier charges) in thermal equilibrium is described.

[0085] The drain current of an insulated gate FET including a TFT and a single crystal MOSFET is given by the following equation (7).

[0086] Equation 7

[0087]

[0088] Here, V c is the electrostatic potential of the channel and is a function of position y. In addition, Q'I(V c ) is the surface charge density of the free carrier charge, which is determined by the free charge density Q of the free carrier charge in the depth direction of the semiconductor layer (channel). I (x) is integrated and given by the following equation (8).

[0089] Equation 8

[0090]

[0091] Drain current I d It is expressed by the following equation (9) using equations (7) and (8).

[0092] Equation 9

[0093]

[0094] Equation (9) includes double integrals in the x-direction and the y-direction and cannot be solved analytically. Equation (10) is obtained by approximating that the amount of free carrier charge (charge density) is small compared to the amount of trapped charge (charge density) and can be ignored.

[0095] Equation 10

[0096]

[0097] Surface charge densities Q'I and Q' of free carrier charge and trapped charge T It is expressed by the following equations (11) and (12) by substituting equation (10) into equation (8).

[0098] Equation 11

[0099]

[0100] Equation 12

[0101]

[0102] The surface potential Φ calculated in the previous process s Substitute the value of into equation (12) to calculate the thermal equilibrium trap charge density Q' T .

[0103] Calculation of drain current

[0104] For convenience, the drain current I is described here as d calculation process.

[0105] By dividing the surface potential Φ on the source and drain sides calculated in the previous process s0 and Φ sL Substituting into equation (11), the surface charge density Q'I of the free carrier charge on the source and drain sides is S and Q'I d They are expressed by equations (13) and (14) respectively.

[0106] Equation 13

[0107]

[0108] Equation 14

[0109]

[0110] Drain current I d The y-direction integral of can be solved using the so-called unified charge control model (UCCM) method (for details, see C. Galup Montoro and MC Schneider, “MOSFET MODELING FOR CIRCUITAN ALYSIS AND DESIGN”, Singapore, World Scientific, 2007). This results in equation (15).

[0111] Equation 15

[0112]

[0113] Here, n is called the "slope factor" and is given by the following equation (16).

[0114] Equation 16

[0115]

[0116] Here, C T is the surface charge density Q' of the trapped charges T Relative to the surface potential Φ s It is calculated by differentiation and is given by the following equation (17).

[0117] Equation 17

[0118]

[0119] The relationship expressions related to the various parameters described above vary depending on, for example, the approximation method, and the relationship expressions related to the various parameters can be derived using other approximation methods. In addition, other physical factors can be considered when deriving the relationship expressions related to the various parameters.

[0120] Next, the process S130 is described, that is, calculating the transient charge density q of the trapped charge T (transient trapped charge density) process.

[0121] In process S130, based on the calculated thermal equilibrium trap charge density (surface charge density) Q' T The transient charge density of the trapped charges (transient trapped charge density) is calculated. Specifically, the transient trapped charge density is calculated as the surface charge density Q by the following equations (18) to (20): T .

[0122] Equation 18

[0123]

[0124] Equation 19

[0125]

[0126] Equation 20

[0127]

[0128] Next, equation (18) is described.

[0129] Assume that the trapped charge q T (t i ) partial charge q T j (t i ) each with a different delay constant τ NQS j . Delay constant τ NQS j It is a parameter that represents the time required to fill a trap state with partial charge (or the time required to release from a trap state) after voltage is applied to the transistor.

[0130] Assume that the delay constant τ of the partial charges constituting the trapped charge is NQS The probability distribution of accords with the log-normal distribution represented by the following equation (21), for example.

[0131] Equation 21

[0132]

[0133] Here, N T is the partial charge that constitutes the trapped charge, u is the logarithm of the delay constant log(τ NQS ). In addition, μ is the mean of the distribution and σ is the standard deviation. It should be noted that the preferred assumption is that the partial charges constituting the trapped charges are proportional to the delay constant τ NQS The partial charges constituting the trapped charges are widely distributed, and it can be assumed that the partial charges constituting the trapped charges conform to a long-tail distribution in addition to the log-normal distribution, such as the power law distribution, the Levy distribution, the Pareto distribution, and the like.

[0134] It should be noted that since each of the partial charges constituting the trapped charge has a charge amount corresponding to the quantum amount of electricity, this distribution can be regarded as the charge amount distribution of the trapped charge with respect to the delay constant τ. The entire charge amount distribution of the trapped charge with respect to the delay constant τ (total area) corresponds to the thermal equilibrium trapped charge density Q'T .

[0135] The probability distribution function given by equation (21) is τ NQS In order to reduce the computational cost, the probability function is approximated as a set of n (where n is an integer equal to or greater than 2) delay constants τ NQS 1 to τ NQS n Here, there is a delay constant τ NQS 1 to τ NQS n The partial charges are defined as N T 1 to N T n Alternatively, with a delay constant τ NQS 1 to τ NQS n The proportion (weight) of the partial charge relative to the whole can be set as P 1 to P n .

[0136] will have a delay constant τ NQS 1 to τ NQS n The total charge density of the partial charges is defined as Q T 1 to Q T n . Charge density Q T 1 to Q T n Corresponding to the basic charge q×partial charge N T 1 to N T n , and further corresponds to the thermal equilibrium trapped charge density Q' T ×weight P 1 to P n The expression (18), where the delay constants τ are respectively NQS 1 to τ NQS n The total charge density Q of the partial charges T 1 to Q T n The sum is equal to the thermal equilibrium trap charge density Q' T .

[0137] Next, equation (19) is described. iand t i-1 Respectively represent the i-th time (where i is an integer greater than or equal to 1) and time t i The time before. In addition, τ NQS j is the delay constant τ NQS 1 to τ NQS n The j-th delay constant of (where j is an integer greater than or equal to 1 and less than or equal to n).

[0138] Q T j is a time delay constant τ NQS j The total charge density of the partial charges (the portion of the charge density of the trapped charges in thermal equilibrium). In addition, q T j (t i ) and q T j (t i-1 ) are respectively at time t i and t ii-1 The transient charge density of the trapped charges when θ is 0.05 V (the part of the transient charge density of the trapped charges reflecting the NQS effect).

[0139] This relational expression is obtained from the model disclosed in Japanese Patent Application Publication No. 2010-171384. This relational expression represents the transient charge density q of the trapped charge. T j The charge density Q when it converges to the thermal equilibrium of the trapped charge T j , whose delay corresponds to the delay constant τ NQS j .

[0140] It should be noted that when the charge density q at time t0 T j (t0) is 0, and time t ∞ The charge density q T j (t ∞ ) is Q T j Integrating equation (19) under the boundary conditions, we get the following equation (22). According to this relationship, the transient charge density q of the trapped charge is T j Decays exponentially with time (has time dependence on first-order delayed response).

[0141] Equation 22

[0142]

[0143] Next, we describe Equation (20). The transient trapped charge density q T is the first to nth transient charge density q of the trapped charge T 1 to q T n sum.

[0144] From equation (22), we know that the jth transient charge density q of the trapped charge is T j The time variation of can be expressed by an exponential function with a single time constant. Therefore, the first to nth transient charge density q of the trapped charge is T 1 to q T n The transient trapped charge density q T The temporal variation of the superposition with a time constant τ NQS 1 to τ NQS n By superimposing multiple exponential functions in this way, the actual NQS effect (non-quasi-static effect) can be calculated more accurately.

[0145] Q T j and τ NQS j The model parameters for μ and σ, as well as the distribution parameters for μ and σ, are pre-modeled based on measurement results of TFT elements. Furthermore, if the number of n partitions for trapped charge is too small, the difference between simulation and measurement results increases. If n is too large, the computational cost increases, and simulation results require more time. According to the inventors' research, an appropriate value for n is approximately 5 to 10.

[0146] Next, the process S140 is described, which is to calculate the free carrier charge (transient free carrier charge density) q I The process of transient charge density.

[0147] In process S140, based on the thermal equilibrium trap charge density (surface charge density) Q' T and transient trapped charge density (surface charge density) q T Calculate the charge density of free carriers (surface charge density) q I The trapped charge does not directly affect the drain current. Therefore, another equation is needed to relate the transient trapped charge to the free carrier charge and the drain current.

[0148] It is assumed that the NQS effect of trapped charge affects the increase / decrease of free carrier charge. Specifically, it is assumed that the charge increase / decrease amount of trapped charge (by the trapped charge density Q' from the thermal equilibrium) T Subtract the transient trap charge density q T The transient free carrier charge density (surface charge density) q, which reflects the NQS effect, is obtained. I1 The free carrier charge can be increased or decreased by the amount q I NQS (expressed by the following equation (23)) is added to the free carrier charge density Q'I (expressed in equation (11)) in the thermal equilibrium state to calculate.

[0149] Equation 23

[0150]

[0151] Alternatively, it can be assumed that the NQS effect of the trapped charge affects the increase / decrease of the gate charge (charge charged on the gate). Specifically, it can be assumed that the increase / decrease amount of the trapped charge (by the trapped charge density Q' from the thermal equilibrium) T Subtract the transient trap charge density q T In this case, assuming that an effective gate voltage V is applied to the gate, G +ΔV g (The gate voltage change ΔV is expressed by the following equation (24) g Added to the actual gate voltage V G ).

[0152] Equation 24

[0153]

[0154] Assuming that an effective gate voltage V is applied to the gate G +ΔV g In the case of , the charge density (surface charge density) q of the free carrier charge reflecting the NQS effect can be calculated by solving equations (1) to (11) I2 According to the research of the present inventors, it can be understood that the charge density q of the free carrier charge is used. I2 The simulation results are better than those obtained using the charge density q of the free carrier charge. I1 The obtained simulation results are closer to the measured results.

[0155] Next, the process S150 is described, which is to calculate the drain current I d process.

[0156] In process S150, based on the transient free carrier charge density q I (The charge density q of the free carrier charge reflecting the NQS effect I1 and q I2 ) Calculate the drain current I d Specifically, the charge density q based on the free carrier charge at the source and drain terminals is IS and q ID , use equation (15) to calculate the drain current I d .

[0157] In process S160, it is determined whether the elapsed time reaches the end of the simulation time given in the simulation input card. Specifically, if the time step t i The last time step t has been reached max , the simulation ends. If the time step t i The final time step t is not reached max , then the time step is sent to the next time step t i+1 (Process S170), and repeat processes S130 to S150.

[0158] Therefore, the electrical characteristics of the transistor are simulated by the simulation method according to this embodiment. Next, the measurement results are compared with the simulation results obtained by the simulation method according to this embodiment. First, the basic structure and manufacturing method of the measured p-channel TFT are described.

[0159] Figure 5 A schematic cross-sectional view of a measured TFT is shown.

[0160] A glass substrate or a resin film is prepared as the substrate 42. An electrically insulating undercoat film 44 is formed on the prepared substrate 42. The undercoat film 44 has a structure in which a silicon oxide film SiO2 and a silicon nitride film SiN are laminated.

[0161] Semiconductor layer 30 made of polycrystalline silicon (poly-Si) is formed in a desired pattern on undercoat film 44. First, an amorphous silicon thin film is deposited on undercoat film 44 by plasma chemical vapor deposition (CVD). The amorphous silicon thin film is irradiated with excimer laser light to crystallize the amorphous silicon thin film. As a result, a polycrystalline silicon layer having a thickness of, for example, approximately 50 nm is formed. Thereafter, the polycrystalline layer is molded into a desired pattern by known photolithography or etching processes to obtain semiconductor layer 30.

[0162] A gate insulating film 20 formed of SiO2 is formed by a plasma CVD method on the surface of the semiconductor layer 30. The thickness of the gate insulating film 20 is about 100 nm.

[0163] The gate 10 is formed on the gate insulating film 20 so as to face the channel 31. First, a molybdenum film is deposited on the gate insulating film 20 by a sputtering method. Thereafter, the molybdenum film is molded into a desired pattern by a known photolithography or etching process to obtain the gate 10. The thickness of the gate 10 is about 100 nm.

[0164] Using the gate 10 as a mask, an ion implantation method is used to implant about 1×10 15 cm -2 Boron elements of 100 nm are implanted into the semiconductor layer 30. Thereafter, heat treatment (activation) at about 500° is performed, and low-resistance p-silicon regions (source 32 and drain 33) are formed.

[0165] Semiconductor layer 30 includes a source electrode 32 and a drain electrode 33 that are arranged separately from each other, and a channel 31 between source electrode 32 and drain electrode 33. Channel 31 is not doped with impurities and has I-type conductivity.

[0166] An interlayer insulating film 21 is formed by a plasma CVD method so as to cover the gate electrode 10. The interlayer insulating film 21 is formed of SiO2, and has a thickness of about 300 nm.

[0167] The source electrode 11 and the drain electrode 12, which are connected to the source electrode 32 and the drain electrode 33, respectively, are formed so as to penetrate the gate insulating film 20 and the interlayer insulating film 21. First, openings are formed in the gate insulating film 20 and the interlayer insulating film 21 by a known photolithography or etching process. Thereafter, a laminate film is formed by a sputtering method to fill the openings in the gate insulating film 20 and the interlayer insulating film 21. This laminate film has a molybdenum layer / aluminum layer / molybdenum layer structure. The laminate film is molded into a predetermined pattern by a known photolithography or etching process to obtain the source electrode 11 and the drain electrode 12.

[0168] The protective insulating film 22 covering the source electrode 11 and the drain electrode 12 is deposited by a plasma CVD method. The protective insulating film 22 is formed of a silicon nitride film (SiN) and has a thickness of about 250 nm.

[0169] Thus, the p-channel TFT is completed. It should be noted that in products such as displays, electrodes for displaying images, insulating films, light-emitting elements, etc. are further formed on the protective insulating film 22. However, in this case, the description of these components is omitted.

[0170] The present inventors compared the measurement results with the simulation results obtained using the simulation method according to the present embodiment for transient response current characteristics ( Figure 6 )、DC characteristics( Figures 7 to 10 ), hysteresis characteristics ( Figure 11 ), overshoot characteristics and undershoot characteristics ( Figure 12) and historical characteristics (Figure 13). The comparison results show that for all characteristics, the simulation results are generally consistent with the measurement results. The following describes the comparison / investigation of the simulation and measurement results.

[0171] Figure 6 shows the transient response current characteristics of a p-channel TFT. Figure 6 The vertical axis of the diagram shown corresponds to the drain current I d The horizontal axis corresponds to the logarithm of time t.

[0172] In the diagram, the measurement results (represented by the group of points marked "measurement") and the simulation results (a) (represented by the dotted lines) and (b) (represented by the solid lines) are shown. The simulation result (a) is a simulation using a single delay constant τ NQS 1 Calculate the drain current I d The simulation results (b) are obtained by using multiple delay constants τ NQS 1 to ττ NQS 7 Calculate the drain current I d These results show that the drain voltage V d Fixed at -10V and gate voltage V g After changing from 0V to -2V, the drain current I d time changes.

[0173] According to the measurement results, the drain current I d With respect to time t, it has a power dependence (I d ∝I d (0)t -α ). The simulation result (a) has a very poor fit with the measurement results. Simulation result (b) also matches the measurement results over a longer timeframe than simulation result (a). Comparing simulation results (a) and (b), it's clear that the simulation results using multiple delay constants more accurately capture the actual NQS effect (delay phenomenon). It should be noted that by adjusting parameters other than the delay constant τ, the simulation results can be made closer to the measurement results.

[0174] Figures 7 to 10 The direct current (DC) characteristics of a p-channel TFT are shown. Figure 7 shows that when the channel length L is set to 4 μm and the drain voltage V d The drain current I changes when d -Gate voltage V g characteristic. Figure 8 It shows that when the channel length L is set to 100 μm and the drain voltage V d The drain current I changes when d-Gate voltage V g characteristic. Figure 9 shows that when the channel length L is set to 4 μm and the gate voltage V g The drain current I changes when d -Drain voltage V d characteristic. Figure 10 shows that when the channel length L is set to 100 μm and the gate voltage V g The drain current I changes when d -Drain voltage V d characteristic. Figures 7 to 10 Each of shows a measurement result (indicated by a solid line) and a simulation result (indicated by a dotted line), respectively.

[0175] These figures confirm that the simulation results are consistent with the measurement results over a wide range of channel lengths. In particular, the drain current versus gate voltage V g The exponentially increasing subthreshold region allows for good reproduction of the measured results.

[0176] It should be noted that for the subthreshold region, the drain current I d (especially its rising slope) and the drain current I d The numerical settings of NTC and T0 in equation (3) and Vfb in equation (5) are particularly important for making the simulation results close to the measured results. In this simulation, NTC is set to 4.3×10 15 , T0 is set to 1660, and V fb Set to -0.2.

[0177] Figure 11 shows the hysteresis characteristics of a p-channel TFT. Figure 11 The vertical axis of the graph corresponds to the drain current I d , and the horizontal axis corresponds to the gate voltage V g In the diagram, the measurement results (the group of points marked as “measurement”) and the simulation results (solid line) are shown. These results show that when the drain voltage V d is set to -10V and the gate voltage V g The gate voltage V g Furthermore, the hysteresis characteristic changes from -6.0V to +2.0V at a rising rate of 0.1V / second.

[0178] Reduce the gate voltage V g The process is defined as forward scanning, and increasing the gate voltage V g The process is defined as reverse scanning. The characteristic curve of reverse scanning is relative to the characteristic curve of forward scanning along the gate voltage V gThis phenomenon is common in TFTs made of polycrystalline silicon or amorphous silicon.

[0179] The figure confirms that the simulation results closely reproduce the measured results. It should be noted that for the hysteresis characteristics, the numerical settings of μ and σ in Equation (21) are particularly important for making the simulation results close to the measured results. In the current simulation, μ is set to 3.7 and σ is set to 1.0.

[0180] Figure 12 The overshoot and undershoot characteristics of a p-channel TFT are shown. Figure 12 The vertical axis in the graph shown in corresponds to the drain current I d , and the horizontal axis corresponds to time t. The graph shows the measurement results (solid line) and simulation results (the group of points marked as "Simulation"). These results show that when the drain voltage V d is fixed at -10V, and the gate voltage V g When the voltage changes from 0V to -2.0V, -2.3V and -2.0V, the drain current I d time changes.

[0181] According to the measurement results, when the gate voltage V g When the drain voltage I changes from 0V (cut-off potential) to -2.0V (intermediate potential), d In addition, when the gate voltage V g When the drain voltage I changes from -2.3V (on-state potential) to -2.0V (intermediate potential), confirm that d The figure confirms that the simulation results are close to the measured results.

[0182] It should be noted that for the overshoot and undershoot characteristics, the numerical settings of μ and σ in equation (21) are particularly important to make the simulation results close to the measurement results. Figure 11 As shown in the simulation of , in the current simulation, μ is set to 3.7 and σ is set to 1.0.

[0183] Figures 13A to 13C The historical characteristics of a p-channel TFT are shown. The historical characteristics are characteristics in which the magnitude of the TFT overshoot depends on the off-time of the gate voltage.

[0184] Figure 13A The temporal change of the gate voltage (the waveform of the voltage applied to the gate) is shown. Figure 13B Shown is the temporal change of the drain current according to the measurement results. Figure 13C Shown is the temporal variation of the drain current according to the simulation results.

[0185] like Figure 13AAs shown in Figure 2, in case (a), a voltage of -3.0 V is applied to the gate for 1 second, and then the gate voltage (0 V) is cut off for 1 second. In case (b), a voltage of -3.0 V is applied to the gate for 1 second, and then the gate voltage is cut off for 0.1 second. In case (c), a voltage of -3.0 V is applied to the gate for 1 second, and then the gate voltage is cut off for 0.01 second.

[0186] Figure 13B The measurement results for cases (a) to (c) are shown. Figure 13B It is confirmed that the overshoot characteristic of the drain current increases as the off-time of the gate voltage increases. That is, Figure 13B The historical characteristics of TFT were confirmed.

[0187] Figure 13C The simulation results for cases (a) to (c) are shown. The overshoot history characteristic of the drain current is reproduced as the gate voltage cut-off time increases. Physically, when the cut-off time is not long enough, the trapped charge cannot recover to the thermal equilibrium defined as the cut-off voltage (gate voltage = 0V), so it can be interpreted as Q'Tq in equations (23) and (24). T (t i ) will decrease, and the current overshoot range will decrease.

[0188] As described above, it can be understood that since the transient behavior of trapped charges is taken into account in the simulation method according to this embodiment, the transient response characteristics of TFTs can be reproduced with high accuracy. These characteristics are very useful for simulating the transient characteristics of electronic circuits including TFTs.

[0189] For example, in an organic EL device, TFTs are generally used to drive pixels constituting a display surface. Figure 12 The overshoot and undershoot characteristics of TFTs shown in FIG significantly affect the image quality (afterimage, etc.) of these displays. Due to the simulation method according to this embodiment, the overshoot and undershoot characteristics of TFTs can be accurately predicted, and thus the image quality of displays can be evaluated and studied in advance (at the design stage) with higher accuracy.

[0190] Next, a simulation of characteristics of an electronic circuit including an organic light emitting diode (organic EL element) is described. In this case, the simulation method (compact model of transistor) according to this embodiment is used.

[0191] Figure 14The equivalent circuit of an organic EL display including TFTs is shown in a simplified manner. The equivalent circuit includes two p-channel thin film transistors M1 and M2, a capacitor Cst, and an organic light emitting diode element OLED. The data voltage Vdata is input to the drain of transistor M1, and the scan voltage Vscan is input to the gate. When transistor M1 is turned on, a charge is maintained on capacitor Cst connected to the source of transistor M1. The gate of transistor M2 is also connected to the source of transistor M1, and controls the current I flowing through the organic light emitting diode element OLED according to the voltage state of transistor M2. OLED . VDD is set to +5V, and VEE is set to -5V.

[0192] Figure 15A and 15B The signal waveforms of voltage Vscan and voltage Vdata are shown. Vscan has a pulse waveform with a period of 16.7 milliseconds. Vdata has a step voltage waveform in which the voltage changes from 6V to 2V in a time of 40 seconds. The current I flowing through the organic light emitting diode element OLED is OLED Basically, there is no flow from time 0 to 40 seconds, and it gradually starts to flow from time 40 seconds.

[0193] Figure 16A and 16B ,as well as Figure 17A and 17B Shown Figure 14 The electrical characteristics of the equivalent circuit are shown.

[0194] Figure 16A shows the current I flowing over a wide time range OLED time changes, and Figure 16B The current I around 40 seconds is shown in an enlarged manner. OLED Time changes, Figure 16A and Figure 16B The calculated transient trap charge density q is shown in Figure 2. T Simulation results (shown by dotted lines) and measurement results (shown by solid lines) obtained by using multiple delay constants.

[0195] same, Figure 17A shows the current I flowing over a wide time range OLED time changes, and Figure 17B It is shown in an enlarged manner that the current I OLED time changes. Figure 17A and Figure 17B The calculated transient trap charge density q is shown in Figure 2. T The simulation results (shown by the dotted line) and the measurement results (shown by the solid line) obtained by using a single delay constant are shown.

[0196] based on Figure 16A and Figure 16B , it can be said that the simulation results are very close to the measurement results in both wide and narrow time ranges. Figure 17A and Figure 17B While it can be said that the simulation results are close to the measured results within a narrow time range, it cannot be said that the simulation results are close enough to the measured results within a wider time range. Considering these results, it is obvious that simulations using multiple delay constants more accurately capture the actual NQS effect (delay phenomenon).

[0197] An embodiment according to the present disclosure is described above, but the present disclosure is not limited to this embodiment. In the embodiment, a method for simulating a p-channel TFT using a polycrystalline silicon thin film as a semiconductor layer is described. However, the present simulation method can also be applied to an n-channel TFT. Additionally, the semiconductor layer is not limited to polycrystalline silicon. For example, the present simulation method can be applied to a semiconductor layer having a trap state in the semiconductor layer (in the channel), such as amorphous silicon, microcrystalline silicon, a metal oxide semiconductor (such as InGaZnO), and an organic semiconductor. In addition, it is obvious to those skilled in the art that various other changes, modifications, combinations, etc. are possible.

[0198] Some example embodiments have been described above for illustrative purposes. Although the above discussion has presented specific embodiments, those skilled in the art will recognize that changes can be made in form and detail without departing from the broader spirit and scope of the present invention. Therefore, the description and drawings are to be regarded in an illustrative rather than a restrictive sense. Therefore, this detailed description should not be read in a limiting sense, and the scope of the present disclosure is limited only by the claims included therein and the full scope of equivalents to which such claims are entitled.

Claims

1. A method for simulating transistor characteristics, The transistor includes a semiconductor layer and a gate, wherein the semiconductor layer includes: A source electrode and a drain electrode are separated from each other, and a channel is located between the source electrode and the drain electrode, the gate electrode faces the channel of the semiconductor layer, and the method includes: Calculation of thermal equilibrium trap charge density Q' based on Poisson's equation and the charge neutrality law T Process (a), wherein the Poisson equation represents the relationship between the electrostatic potential and the charge in the channel, the charge including the free carrier charge and the trapped charge in the trap state in the channel, and the charge neutrality law is applicable to the charge accumulated on the gate and the channel; Calculate the transient trapped charge density q after applying a voltage between the gate and the semiconductor layer T Process (b), where it is assumed that the transient trapped charge density q T The time variation of is represented by a function obtained by superimposing multiple exponential functions with different time constants; Based on the transient trapped charge density q T Calculate the free carrier charge density q I process (c); and Based on the free carrier charge density q I Calculate the drain current I flowing between the source and the drain d process (d), wherein the process (b) comprises: Based on the probability distribution of the partial charges constituting the trapped charges, n delay constants τ corresponding to the time constants included in the exponential function are determined. NQS 1 to τ NQS n and respectively have the delay constant τ NQS 1 to τ NQS n The partial charge density Q of the trapped charge T 1 to Q T n Sub-process (b1), wherein n is an integer greater than or equal to 2, and the probability variable thereof is a delay constant corresponding to the time required for the partial charges constituting the trapped charges to fall into the trapped state, and The delay constant τ based on the trapped charge NQS 1 to τ NQS n and the charge density Q T 1 to Q T n Calculate the transient trapped charge density q T Sub-process (b2).

2. The method for simulating transistor characteristics according to claim 1, wherein When the i-th time is t i When i is an integer greater than or equal to 1, at the time t i The previous time is t i-1 , the delay constant τ NQS 1 to τ NQS n The jth delay constant is τ NQS j , where j is an integer greater than or equal to 1 and less than or equal to n, and the charge density of the trapped charge Q T 1 to Q T n The jth charge density is Q T j , The time t is calculated by the equation in the following sub-process (b2): i The charge density q of the trapped charge at T (t i ) Equation 1 Equation 2 Equation 3 3. The method for simulating transistor characteristics according to claim 1, wherein in sub-process (b1), the probability distribution conforms to any one of lognormal distribution, power law distribution, Levy distribution and Pareto distribution.

4. The method for simulating transistor characteristics according to claim 1 , wherein in process (c), it is assumed that the heat equilibrium trapped charge density Q′ T Subtract the transient trapped charge density q from T The increase / decrease in the trapped charge obtained corresponds to the increase / decrease in the gate charge charged on the gate, and the free carrier charge density q is calculated as I .

5. A method for simulating characteristics of an electronic circuit including a transistor, The transistor includes a semiconductor layer and a gate, the semiconductor layer includes a source and a drain separated from each other and a channel located between the source and the drain, the gate facing the channel of the semiconductor layer, and the method including: Calculation of thermal equilibrium trap charge density Q' based on Poisson's equation and charge neutrality law T process (a), wherein the Poisson equation represents the relationship between the electrostatic potential and the charge in the channel, the charge including the free carrier charge and the trapped charge in the trap state in the channel, and the charge neutrality law is applicable to the charge accumulated on the gate and the channel; Calculate the transient trapped charge density q after applying a voltage between the gate and the semiconductor layer T Process (b), where it is assumed that the transient trapped charge density q T The time variation of is represented by a function obtained by superimposing multiple exponential functions with different time constants; Based on the transient trapped charge density q T Calculate the free carrier charge density q I process (c); as well as Based on the free carrier charge density q I Calculate the drain current I flowing between the source and the drain d process (d), wherein the process (b) comprises: Based on the probability distribution of the partial charges constituting the trapped charges, n delay constants τ corresponding to the time constants included in the exponential function are determined. NQS 1 to τ NQS n and respectively have the delay constant τ NQS 1 to τ NQS n The partial charge density Q of the trapped charge T 1 to Q T n Sub-process (b1), wherein n is an integer greater than or equal to 2, and the probability variable thereof is a delay constant corresponding to the time required for the partial charges constituting the trapped charges to fall into the trapped state, and The delay constant τ based on the trapped charge NQS 1 to τ NQS n and the charge density Q T 1 to Q T n Calculate the transient trapped charge density q T Sub-process (b2), The electronic circuit further includes an organic EL element driven by the transistor.

6. A non-transitory recording medium storing a simulation program for transistor characteristics, The transistor includes a semiconductor layer and a gate, wherein the semiconductor layer includes a source and a drain separated from each other and a channel located between the source and the drain, and the gate faces the channel of the semiconductor layer. The simulation program causes the computer to perform the following operations: Calculation of thermal equilibrium trap charge density Q' based on Poisson's equation and charge neutrality law T In step (a), the Poisson equation represents the relationship between the electrostatic potential and the charge in the channel, the charge including the free carrier charge and the trapped charge in the trap state in the channel, and the charge neutrality law is applicable to the charge accumulated on the gate and the channel; Calculate the transient trapped charge density q after applying a voltage between the gate and the semiconductor layer T Step (b), wherein it is assumed that the transient trapped charge density q T The time variation of is represented by a function obtained by superimposing multiple exponential functions with different time constants; Based on the transient trapped charge density q T Calculate the free carrier charge density q I step (c); and Based on the free carrier charge density q I Calculate the drain current I flowing between the source and the drain d step (d), wherein said step (b) comprises: Based on the probability distribution of the partial charges constituting the trapped charges, n delay constants τ corresponding to the time constants included in the exponential function are determined. NQS 1 to τ NQS n and respectively have the delay constant τ NQS 1 to τ NQS n The partial charge density Q of the trapped charge T 1 to Q T n Sub-step (b1), wherein n is an integer greater than or equal to 2, and the probability variable is a delay constant corresponding to the time required for the partial charges constituting the trapped charges to fall into the trapped state, and The delay constant τ based on the trapped charge NQS 1 to τ NQS n and the charge density Q T 1 to Q T n Calculate the transient trapped charge density q T Sub-step (b2).

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