Semiconductor structure and method for forming the same

Abstract

A semiconductor structure includes a first substrate having a front side and a back side and a second substrate having a front side and a back side, wherein the back side of the second substrate is connected to the back side of the first substrate. The structure also includes a device layer located above the front side of the second substrate; a first conductor passing through the semiconductor layer in the second substrate; and a conductive connection connecting the first conductor to a conductive component in the device layer. Embodiments of the present application also relate to methods of forming semiconductor structures.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor structure and a method for forming the same. Background Art

[0002] Conventionally, integrated circuits are manufactured in a stacked fashion with transistors at the lowest level and interconnects (vias and wires) on top of the transistors to provide connectivity to the transistors. Power rails (e.g., metal lines for voltage sources and ground planes) are also located above the transistors and may be part of the interconnects. As integrated circuits continue to shrink, the power rails also shrink. This inevitably leads to an increase in the voltage drop across the power rails, and increased power consumption of the integrated circuit. Summary of the invention

[0003] According to one aspect of the present invention, a semiconductor structure is provided, comprising: a first substrate having a front side and a back side; a second substrate having a front side and a back side, wherein the back side of the second substrate is connected to the back side of the first substrate; a device layer located above the front side of the second substrate; a first conductor passing through the semiconductor layer in the second substrate; and a conductive connection connecting the first conductor to a conductive component in the device layer.

[0004] According to another aspect of the present invention, a semiconductor structure is provided, comprising: a first substrate having a front side and a back side; a second substrate having a front side and a back side, wherein the back side of the second substrate is bonded to the back side of the first substrate; a metal component extending from the back side of the first substrate to the front side of the second substrate; a device layer located above the front side of the second substrate and above the metal component; and a multi-layer interconnection located above the device layer.

[0005] According to another aspect of the present invention, a method for forming a semiconductor structure is provided, comprising: receiving a first substrate having a front side and a back side, the front side of the first substrate having a semiconductor material, and the back side of the first substrate having a passivation layer; receiving a second substrate having a front side and a back side, the back side of the second substrate having an insulator; connecting the back side of the first substrate to the back side of the second substrate; etching a groove through the second substrate and through the passivation layer; and forming a conductor in the groove. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0007] Figure 1 A top view of a semiconductor device according to an embodiment of the present invention is shown;

[0008] Figure 2 , Figure 3 , Figure 4 ,and Figure 5 shows cross-sectional views of semiconductor devices according to various embodiments of the present invention;

[0009] Figure 6 , Figure 7 ,and Figure 8 shows cross-sectional views of semiconductor devices according to various embodiments of the present invention;

[0010] Fig. 9 A flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown;

[0011] Fig.10a , 10b , and 10c show the Fig. 9 a cross-sectional view of a semiconductor device during fabrication of an embodiment of the illustrated method;

[0012] Fig.11 A flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown;

[0013] Fig.12a , Figure 12b , Fig.12c , Fig.12d , Fig.12e ,and Fig.12f Shown according to Fig.11 a cross-sectional view of a semiconductor device during fabrication of an embodiment of the illustrated method;

[0014] Fig.13 A flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown;

[0015] Fig.14a , Fig.14b , Fig.14c ,and Fig.14d Shown according to Fig.13 a cross-sectional view of a semiconductor device during fabrication of an embodiment of the illustrated method;

[0016] Fig.15 A flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown;

[0017] Fig.16a , Fig.16b , Fig.16c , Fig.16d , Fig.16e , Fig.16f ,and Figure 16g Shown according to Fig.15 a cross-sectional view of a semiconductor device during fabrication of an embodiment of the illustrated method;

[0018] Fig.17 A flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown;

[0019] Fig.18a , Fig.18b , Fig.18c , Fig.18d , Fig.18e , Fig.18f ,and Figure 18g Shown according to Fig.17 A cross-sectional view of a semiconductor device during fabrication illustrating an embodiment of the method. DETAILED DESCRIPTION

[0020] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or structures discussed.

[0021] Moreover, for ease of description, spatially relative terms such as "under," "beneath," "lower," "above," "upper," etc. may be used herein to easily describe the relationship of one element or component to another (or other) elements or components as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. Furthermore, when "approximately," "approximately," etc. are used to describe a number or a range of numbers, the term is intended to cover numbers within + / - 10% of the described number, unless otherwise specified. For example, the term "about 5 nm" covers a size range from 4.5 nm to 5.5 nm.

[0022] Various embodiments of the present invention generally relate to the integration of semiconductor devices, and more specifically to semiconductor devices having conductors passing through substrates. These conductors are located below the transistors of the semiconductor device or at the same level as the transistors of the semiconductor device. Therefore, in some cases in the present invention, they are also referred to as "embedded conductors". These conductors supplement existing multi-layer interconnections and provide additional wiring resources for semiconductor devices. For example, they can be used as power rails or other types of interconnections (such as signal lines) for semiconductor devices. In particular, they are manufactured using large sizes to reduce voltage drops and power consumption. In the following description, specific embodiments are provided as examples to teach broader inventive concepts, and those of ordinary skill in the art can easily apply the teachings of the present invention to other semiconductor devices and methods for manufacturing the same.

[0023] Figure 1 A top view of a portion of a semiconductor device 100 according to various aspects of the present invention is shown. The semiconductor device 100 includes an embedded conductor 230 adjacent to an active area 310, in which or on which the source, drain, and channel of various transistors are formed. In the present embodiment, the embedded conductor 230 and the active area 310 are oriented with their lengths along the same X direction. In the Y direction perpendicular to the X direction, the embedded conductor 230 is wider than the active area 310. The semiconductor device 100 also includes a gate line 316 overlapping the active area 310 and providing a gate electrode (or terminal) for the transistor. The gate line 316 is oriented with its length along the Y direction. In the present embodiment, the active area 310 is a fin-shaped active area, that is, having a fin-shaped shape, and the transistor is a FinFET. In alternative embodiments, the active area 310 may be a planar active area, a nanosheet active area, or a nanowire active area. Semiconductor device 100 also includes local interconnects 330 and 340, which connect embedded conductor 230 to some conductive features of the transistor (e.g., source, drain, and / or gate electrodes). The length direction of local interconnect 330 is oriented along the Y direction. Local interconnect 340 is oriented along a length direction perpendicular to the X direction and the Y direction (i.e., Figure 1 The Z direction (see Figure 2 ). The semiconductor device 100 also includes a multi-layer interconnect 304 that provides conductors and vias (or via plugs) for routing signals and / or power rails (voltage supply and ground) of the semiconductor device 100. Figure 2 The spatial relationship of the above various components and other components of the semiconductor device 100 is further shown in FIG.

[0024] refer to Figure 2, which shows a cross-sectional view of a portion of a semiconductor device 100 in the YZ plane, the semiconductor device 100 comprising a first substrate 110 and a second substrate 200 connected together. The substrate 110 has a front side (where the semiconductor material layer 116 is located) and a back side (where the redistribution layer 120 and the insulator 130 are located). The substrate 200 has a front side (where the semiconductor material layer 220 is located) and a back side (where the insulator 210 is located). In the present embodiment, the back side of the substrate 110 is connected to the back side of the substrate 200, for example, by a bonding structure (such as direct bonding or hybrid bonding), using an adhesive, or using other connection structures.

[0025] The semiconductor device 100 includes embedded conductors 230, one of which is Figure 2 As shown. In this embodiment, the embedded conductor 230 starts from the back side of the substrate 110, passes completely through the substrate 200, and extends above the front side of the substrate 200. In another embodiment, the embedded conductor 230 passes through the substrate 200, but does not appear above the substrate 200 (i.e., its top surface is at the same level as the front side of the substrate 200). In yet another embodiment, the embedded conductor 230 does not pass through the substrate 200, i.e., its top surface is located below the top surface of the substrate 200. For further this embodiment, the local interconnect 340 extends into the substrate 200 to contact the embedded conductor 230. The (some) conductive materials used for the embedded conductor 230 can vary depending on the manufacturing sequence between the formation of the embedded conductor 230 and any high temperature manufacturing stages. For example, manufacturing stages such as the formation of wells and the formation of source / drain electrodes may involve high temperature anneals of several hundred degrees Celsius or more than one thousand degrees Celsius. In some embodiments in which the embedded conductor 230 is formed before such a high temperature process is performed, the material used for the embedded conductor 230 is selected to be able to withstand such high temperatures. Therefore, materials with high melting points and low resistivity are suitable for embedded conductor 230. Such suitable materials may include tungsten, ruthenium, rhodium, iridium, molybdenum, chromium, or combinations thereof. In some embodiments where embedded conductor 230 is formed after such a high temperature process is performed, or in some embodiments where the manufacturing process does not involve high temperatures at all, other conductive materials may be used in addition to the materials listed above. For example, copper, gold, silver, palladium, osmium, platinum, tungsten, ruthenium, rhodium, iridium, molybdenum, chromium, other materials, or combinations thereof may be used as the material(s) for embedded conductor 230 in these embodiments. Embedded conductor 230 may include other suitable conductive material(s).

[0026] In the present embodiment, semiconductor device 100 includes liner 232 between embedded conductor 230 and substrates 110 and 200. In some embodiments, liner 232 may also be interposed between embedded conductor 230 and dielectric material 320 above the front surface of substrate 200. In some embodiments, liner 232 is optional. The inclusion of liner 232 and its material depends on the material of embedded conductor 230. For example, when the material of embedded conductor 230 is relatively active (e.g., copper), liner 232 having an oxide or nitride is included as a barrier layer to prevent the metal material in embedded conductor 230 from diffusing into the surrounding silicon or dielectric material. On the other hand, when the material of embedded conductor 230 is relatively inactive, liner 232 may be omitted. When liner 232 is interposed between embedded conductor 230 and conductor 124 (as shown in the present embodiment), liner 232 uses a conductive material, such as conductive titanium nitride. Otherwise, liner 232 may be conductive or non-conductive.

[0027] Each of the semiconductor layers 116 and 220 may include silicon or other suitable semiconductor material(s), such as germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, silicon germanium, gallium arsenide phosphide, aluminum indium phosphide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, or indium gallium arsenide phosphide. The semiconductor layers 116 and 220 may include the same or different materials.

[0028] Although not shown, the semiconductor layer 116 may include active devices, such as transistors including metal oxide silicon field effect transistors (MOSFETs), FinFETs, gate-all-around (GAA) devices, nanowire devices, nanosheet devices, high-frequency transistors, high-voltage transistors, high-power transistors, low-power transistors, or other types of active devices. The semiconductor layer 116 may also include passive devices, such as inductors, capacitors, and resistors, and may also include isolation structures, metal lines, and other structures.

[0029] The redistribution layer 120 includes a conductor 124 embedded in one or more dielectric layers 122. Likewise, the material(s) used for the conductor 124 may vary depending on the manufacturing sequence between the formation of the conductor 124 and any high temperature manufacturing stages, similar to what is discussed above with respect to the embedded conductor 230. In some embodiments where the conductor 124 is formed before such a high temperature process is performed, the material used for the conductor 124 is selected to be able to withstand high temperatures, such as tungsten, ruthenium, rhodium, iridium, molybdenum, chromium, or a combination thereof. In some embodiments where the conductor 124 is formed after such a high temperature process is performed, or in some embodiments where the manufacturing process does not involve high temperatures at all, other conductive materials may be used in addition to the materials listed above. For example, copper, gold, silver, aluminum, palladium, osmium, platinum, tungsten, ruthenium, rhodium, iridium, molybdenum, chromium, other materials, or a combination thereof may be used as the material(s) used for the conductor 124 in these embodiments. The dielectric layer 122 may include an oxide material, such as silicon dioxide. The embedded conductor 230 electrically contacts some of the conductors 124 directly or indirectly through the pad 232. In one embodiment, the redistribution layer 120 is provided to the package pads (e.g., Figure 5 100 , some of which are for voltage sources or grounds of device 100. For further embodiments, some of embedded conductors 230 are for power rails or ground planes of device 100 and are connected to power or ground package pads. Due to the large size of embedded conductors 230 and conductors 124, device 100 has the advantage of low voltage drop across its power rails and ground planes. In various embodiments, embedded conductors 230 can be used to route other signals in addition to or in place of power rails or ground planes.

[0030] The insulator 130 is located above the redistribution layer 120. The insulator 130 may include an oxide such as silicon dioxide, or a nitride such as silicon nitride (Si3N4). On the back side of the substrate 200, the insulator 210 may include an oxide such as silicon dioxide.

[0031] There is a device layer 300 above the front side of the substrate 200, which includes a semiconductor active region (e.g., a semiconductor fin) and various active devices (e.g., transistors) fabricated in or on the semiconductor active region. The device layer 300 may also include passive devices such as capacitors, resistors, and inductors. The device layer 300 also includes local interconnects, isolation structures, and other structures. Figure 2In the illustrated embodiment, the device layer 300 includes a semiconductor fin 310 extending upward from the substrate 200, an epitaxial component 312 located above the semiconductor fin 310, and a dielectric isolation component 320 located between the semiconductor active regions including the semiconductor fin 310. The epitaxial component 312 can be a source or drain electrode of a transistor. The semiconductor fin 310 can include silicon or other suitable semiconductor materials, such as silicon germanium. The top surface of the semiconductor fin 310 is located above the top surface of the embedded conductor 230. The device layer 300 also includes local interconnects 330 and 340, which provide connectivity to the source and / or drain electrodes of the transistor, and to the dielectric isolation components 320, although not shown in this figure (see FIG. 1 ). Figure 1 316 in the device layer 300). In particular, some local interconnects 330 and 340 connect some source, drain, or gate electrodes to the embedded conductor 230. The local interconnect 340 extends along a Z direction that is substantially perpendicular to the upper surface of the substrate 200, while the local interconnect 330 extends along a direction that is substantially parallel to the upper surface of the substrate 200. The device layer 300 also includes a contact plug 350 that connects the source, drain, and gate electrodes of the transistor to the multilayer interconnect 400. The contact plug 350 may include copper, tungsten, ruthenium, or other suitable materials.

[0032] The multilayer interconnect 400 is located above the device layer 300 and includes a conductor 410 (e.g., a wire and a via) embedded in one or more dielectric materials 420. The conductor 410 provides connectivity to the source, drain, and gate electrodes of the transistors in the device layer 300. The conductor 410 can also provide power rails and ground planes for the device 100. However, in general, the size of the conductor 410 is much smaller than the embedded conductor 230. The conductor 410 may include copper, aluminum, or other suitable materials and may be formed using a single damascene process, a dual damascene process, or other suitable processes. The dielectric material 420 may include silicon nitride, silicon oxynitride, silicon nitride with oxygen (O) or carbon (C) elements, tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), boro-doped silicon glass (BSG), and / or other suitable dielectric materials.

[0033] Figure 3 1 shows a cross-sectional view of a portion of a semiconductor device 100 according to an embodiment. The semiconductor device 100 includes substrates 110 and 200, a device layer 300, and a multi-layer interconnect 400. These structures have been described with reference to Figure 24. The semiconductor device 100 is described in detail, and for the sake of brevity, its detailed description is omitted here. The semiconductor device 100 also includes a metallization layer (or package layer) 500 located above the multilayer interconnect 400. In one embodiment, the metallization layer 500 includes pads for connecting the input, output, power supply, grounding, and other interface signals of the semiconductor device 100 to the package pins. Some of these pads are electrically connected to the transistors in the device layer 300 through the multilayer interconnect 400, the plug 350, and / or other connectors. Some of these pads are electrically connected to the embedded conductor 230 through the multilayer interconnect 400, the plug 350, the local interconnect 333 and 340, and / or other connectors. The metallization layer 500 may also include a power rail, a ground plane, a passivation layer, and other suitable components.

[0034] Figure 4 1 shows a cross-sectional view of a portion of a semiconductor device 100 according to another embodiment. The semiconductor device 100 includes substrates 110 and 200, a device layer 300, and a multi-layer interconnect 400. These structures have been described with reference to Figure 2 1. The semiconductor device 100 is described in detail, and its detailed description is omitted here for the sake of brevity. The semiconductor device 100 also includes a redistribution layer 112 located above the front side of the substrate 110. In the present embodiment, the redistribution layer 112 includes a pad 113, which is used to connect to the package pins of the device 100, one or more dielectric layers 114, and a conductor 115 (one shown in the figure) embedded in the dielectric layer 114. In the present embodiment, the substrate 110 also includes a through silicon via (TSV) 118, which passes through the semiconductor layer 116 and electrically connects some conductors 124 in the redistribution layer 122 to some conductors 115 in the redistribution layer 112. Each of the conductors 124 and 115 has a larger footprint than the TSV 118. The redistribution layer 112, the TSV 118, and the redistribution layer 120 provide electrical connections from the package pins to the embedded conductors 230, and the embedded conductors 230 provide electrical connections to the transistors in the device layer 300.

[0035] Figure 5 1 is a cross-sectional view of a portion of a semiconductor device 100 according to yet another embodiment. The semiconductor device 100 includes substrates 110 and 200, a device layer 300, and a multi-layer interconnection 400. The substrate 110, the device layer 300, and the multi-layer interconnection 400 have been described with reference to FIG. Figure 2 For the sake of brevity, the detailed description is omitted here. The substrate 200 in this embodiment is Figure 2A variation of the substrate 200 in the illustrated embodiment. In particular, in this embodiment, the substrate 200 includes an insulator 210 extending from the front side of the substrate 200 to the back side of the substrate 200, and does not include a semiconductor layer 220. The insulator 210 may include one or more layers of an insulating material such as silicon dioxide. The semiconductor fins 310 are fabricated directly on the upper surface of the insulator 210. Effectively, the semiconductor layer from which the semiconductor fins 310 are generated and the insulator 210 may collectively be part of a silicon-on-insulator (SOI) substrate. In contrast, in Figure 2 In the embodiment, the semiconductor layer from which the semiconductor fin 310 is generated and the semiconductor layer 220 may be collectively part of the bulk silicon substrate. It is worth noting that Figure 2 The thickness of the substrate is greater than Figure 5 The thickness of the substrate 200 in this embodiment is Figure 2 Another difference between the illustrated embodiments is the aspect ratio of the embedded conductor 230 , which is defined as the ratio of the height to the width of the embedded conductor 230 . Figure 2 In the embodiment, the aspect ratio of the embedded conductor 230 is greater than Figure 5 The aspect ratio of the embedded conductor 230 in the embodiment of FIG.

[0036] Figure 6 , Figure 7 ,and Figure 8 Various embodiments of a semiconductor device 100 are shown. Figure 6 , semiconductor device 100 includes substrates 110 and 200, and device layer 300. Semiconductor device 100 may include other components or layers, such as multi-layer interconnect 400, metallization layer 500, or redistribution layer 112. Embedded conductor 230 passes through substrate 200 and connects conductive features (not shown) in substrate 110 to conductive features (not shown) in device layer 300. Substrate 200 may be formed using a Figure 2 (ie, having a semiconductor layer 220 above an insulator 210) or as Figure 5 The embedded conductor 230 may be in the form of a semiconductor layer 220 (i.e., having an insulator 210 without a semiconductor layer 220). The embedded conductor 230 may rise above the top surface of the substrate 200. In another embodiment, the top surface of the embedded conductor 230 may be flush with the top surface of the substrate 200. In yet another embodiment, the top surface of the embedded conductor 230 may be lower than the top surface of the substrate 200. The substrate 110 may include a redistribution layer 120 on its back side, such as Figure 2-Figure 5As shown. In particular, substrate 110 includes input / output (I / O) devices for device 100, while device layer 300 includes core devices (including logic devices and memory devices) for device 100. Embedded conductors 230 provide connections between the I / O devices and the core devices. Substrate 200 provides reasonable isolation between the I / O devices and the core devices (e.g., for shielding noise). In some applications that require high drive current, embedded conductors 230 can achieve such high drive current with relatively low IR drop and power consumption. Figure 6 In the embodiment of the present invention, a flexible design for integrating multiple devices is provided. In particular, the device layer 300 can provide transistors with high density, while the substrate 110 can provide large-sized transistors for I / O functions. The transistors in the device layer 300 and in the substrate 110 can have different feature sizes or be manufactured by different processes. This gives the designer the freedom to optimize each type of device (I / O device or core device) separately.

[0037] refer to Figure 7 , the semiconductor device 100 includes substrates 110 and 200, a device layer 300, and an embedded conductor 230. The semiconductor device 100 may include other components or layers, such as a multi-layer interconnect 400, a metallization layer 500, or a redistribution layer 112. Figure 6 Therefore, for the sake of brevity, many details of this embodiment are omitted. Figure 7 , the substrate 110 includes a semiconductor material doped with a first type of dopant, and the device layer 300 includes a semiconductor material doped with a second type of dopant, wherein the first type and the second type of dopant have opposite conductivity (for example, one is N-type and the other is P-type). Figure 2 , the doped semiconductor material of substrate 110 may include semiconductor layer 116, and the doped semiconductor material of device layer 300 may include semiconductor fins 310. In one embodiment, substrate 110 includes an N-type doped semiconductor material (i.e., doped with an N-type dopant, such as phosphorus or arsenic); and device layer 300 includes a P-type doped semiconductor material (i.e., doped with a P-type dopant, such as boron or indium). In another embodiment, substrate 110 includes a P-type doped semiconductor material (i.e., doped with a P-type dopant, such as boron or indium); and device layer 300 includes an N-type doped semiconductor material (i.e., doped with an N-type dopant, such as phosphorus or arsenic). In one embodiment, the semiconductor material in substrate 110 is the same as the semiconductor material in device layer 300 (e.g., both are silicon), except for the difference in dopants therein. In another embodiment, the semiconductor material in substrate 110 is different from the semiconductor material in device layer 300, for example, one is primarily silicon and the other is primarily silicon germanium. In Figure 7 In the embodiments of the present invention, a flexible design for integrating multiple devices is provided. In particular, since only one type of dopant is present in the substrate 110 (or the device layer 300), the manufacturing process for the substrate 110 (or for the device layer 300) is simplified compared to other designs that require different types of dopants in a single substrate (e.g., creating an N-well in a P-type substrate).

[0038] refer to Figure 8 , the semiconductor device 100 includes substrates 110 and 200, a device layer 300, and an embedded conductor 230. The semiconductor device 100 may include other components or layers, such as a multi-layer interconnect 400, a metallization layer 500, or a redistribution layer 112. The embodiment of the device 100 in this figure is similar to Figure 6 Therefore, for the sake of brevity, many details of this embodiment are omitted. Figure 8 In this embodiment, the substrate 110 includes a memory device and the device layer 300 includes a logic device. In another embodiment, the substrate 110 includes a logic device and the device layer 300 includes a memory device. Each of the logic device and the memory device may include a FinFET or other types of transistors. Figure 8 In an embodiment of the present invention, a flexible design for integrating multiple devices is provided. In particular, logic devices and memory devices may have different optimization goals. For example, logic devices may be optimized for speed, while memory devices are typically optimized for circuit density and / or low power consumption. Therefore, logic devices and memory devices may have different feature sizes. In addition, it is sometimes not ideal to place these two types of devices on one substrate. Figure 8 In the illustrated embodiment, the substrate 110 and the device layer 300 can be optimized independently, while the embedded conductors 230 can provide the desired connections between the logic devices and the memory devices.

[0039] Fig. 9 , Fig.11 , Fig.13 , Fig.15 ,and Fig.17 Flowcharts of methods 900, 1100, 1300, 1500, and 1700 for fabricating semiconductor device 100 in various embodiments discussed above are shown. Methods 900, 1100, 1300, 1500, and 1700 are merely examples and are not intended to limit the invention beyond the scope expressly recited in the claims. Additional operations may be provided before, during, and after methods 900, 1100, 1300, 1500, and 1700, and some of the operations described may be replaced, omitted, or relocated for additional embodiments of the methods. Fig.10a , Fig.10b ,and Fig.10c To describe method 900. Fig.12a , Figure 12b , Fig.12c , Fig.12d , Fig.12e ,and Fig.12f To describe method 1100. Fig.14a , Fig.14b , Fig.14c ,and Fig.14d To describe method 1300. Fig.16a , Fig.16b , Fig.16c , Fig.16d , Fig.16e , Fig.16f ,and Figure 16g To describe method 1500. Fig.18a , Fig.18b , Fig.18c , Fig.18d , Fig.18e , Fig.18f ,and Figure 18g To describe method 1700. Figure 10a-Figure 10c , Figure 12a-12f , Figure 14a-14d , Figure 16a-16g ,and Figure 18a-18g Various cross-sectional views of the semiconductor device 100 are shown during manufacturing steps according to the described method.

[0040] refer to Fig. 9 At operation 902, method 900 prepares a substrate A to be incorporated into semiconductor device 100. For example, substrate A may be Figure 2-Figure 8 The embodiment of the substrate 110 shown in FIG. The following description also refers to the substrate A as the substrate 110. Fig.10a , the substrate 110 has a front side (indicated by reference numeral 102) and a back side (indicated by reference numeral 104). A semiconductor layer 116 is located on the front side of the substrate 110. A redistribution layer 120 and an insulator 130 are located on the back side of the substrate 110. In one embodiment, the semiconductor layer 116 can be a silicon wafer. The redistribution layer 120 can be formed by depositing one or more dielectric layers 122 over the surface of the semiconductor layer 116, etching the dielectric layer 122 to form trenches, and forming conductors 124 in the trenches. The insulator 130 (e.g., oxide or nitride) can be deposited over the redistribution layer 120 using any suitable method such as chemical vapor deposition (CVD). The insulator 130 is also referred to as a passivation layer 130.

[0041] At operation 904, method 900 prepares a substrate B to be incorporated into semiconductor device 100. For example, substrate B may be Figure 2-Figure 8The embodiment of the substrate 200 shown in FIG. 1 is shown in FIG. 1 . The substrate B is also referred to as the substrate 200 in the following description. Fig.10a , the substrate 200 has a front side (indicated by reference numeral 202) and a back side (indicated by reference numeral 204). A semiconductor layer 220 is located on the front side of the substrate 200. In one embodiment, the semiconductor layer 220 may be a silicon wafer. An insulator 210 (e.g., an oxide) is located on the back side of the substrate 200. The insulator 210 may be formed by oxidizing the surface of the semiconductor layer 220 using thermal oxidation or other types of oxidation. In the present embodiment, the substrate 200 further includes a hydrogen-rich layer (or region) 212, which may be formed by implanting hydrogen into the semiconductor layer 220.

[0042] At operation 906, method 900 ( Fig. 9 ) connects substrates A and B together. Fig.10b In this embodiment, method 900 turns substrate B upside down and bonds the back side of substrate B to the back side of substrate A. Operation 906 may use any suitable bonding process, such as direct bonding or hybrid bonding. Operation 906 may include rinsing, alignment, and / or other processes.

[0043] At operation 908, method 900 ( Fig. 9 ) removes a portion of substrate B. Fig.10c In this embodiment, method 900 implements an annealing process, which creates a gap in the hydrogen-rich region 212, thereby disconnecting a portion of the semiconductor layer 220. The portion of the semiconductor layer 220 between the hydrogen-rich region 212 and the insulator 210 remains in the device 100 and becomes the front side of the substrate 200. In an alternative embodiment, a portion of the substrate B can be removed by grinding or other methods.

[0044] refer to Fig.11 At operation 1102 , method 1100 continues the fabrication process by epitaxially growing semiconductor material over the front side of substrate B. Fig.12a 1 shows the structure of device 100 after performing operation 1102 according to one embodiment. Fig.12a , using the semiconductor material of layer 220 as a seed crystal to epitaxially grow semiconductor layer 222 on semiconductor layer 220. Semiconductor layers 220 and 222 may include the same material or different materials. In one embodiment, semiconductor layers 220 and 222 both include silicon crystals, such as single crystal silicon. In another embodiment, semiconductor layer 220 includes silicon crystals, and semiconductor layer 222 includes a silicon germanium alloy (Si x Ge 1-x In the present embodiment, the semiconductor layer 222 is a part of the device layer 300 .

[0045] refer to Fig.11 At operation 1104 , the method 1100 etches one or more trenches 224 to expose the conductor 124 on the back side of the substrate 110 . Figure 12b 1 shows the structure of device 100 after performing operation 1104 according to one embodiment. Figure 12b , trench 224 passes through semiconductor layer 222, substrate 200, and insulator 130, and exposes conductor 124 in substrate 110. Operation 1104 may include several steps. For example, it may form a hard mask layer above semiconductor layer 222, form a photoresist layer above the hard mask layer, and pattern the photoresist layer using any photolithography process including a double patterning process. The photoresist layer is patterned to provide an opening corresponding to trench 224. Subsequently, the hard mask layer and various layers 222, 220, 210, and 130 are etched through the opening to form trench 224. Then, the photoresist layer and the hard mask layer are removed. In an alternative embodiment, a photoresist layer may be formed directly on semiconductor layer 222 without using a hard mask layer. Various other methods of implementing operation 1104 are possible and contemplated.

[0046] refer to Fig.11 At operation 1106, method 1100 forms a liner (or barrier) layer 232 on the surface of the trench and forms an embedded conductor 230 over liner layer 232. Liner layer 232 is optional, and in an alternative embodiment, method 1100 forms embedded conductor 230 directly on the surface of the trench. Fig.12c 1 shows the structure of device 100 after performing operation 1106 according to one embodiment. Fig.12c The liner layer 232 is formed on the exposed groove 224 (see Figure 12b ) on the surface of various layers 222, 220, 210, and 130 in the trench 224. The embedded conductor 230 is formed over the liner layer 232 and fills the remaining space of the trench 224. In the present embodiment, the liner layer 232 is removed from the surface of the conductor 124, and the embedded conductor 230 directly contacts the conductor 124. In alternative embodiments (e.g. Figure 2 ), liner layer 232 remains on the surface of conductor 124 and is interposed between embedded conductor 230 and conductor 124. Liner layer 232 may be formed using any (some) processes suitable for depositing its (some) dielectric material(s), such as atomic layer deposition (ALD) and chemical vapor deposition (CVD). Embedded conductor 230 may be formed using any (some) processes suitable for depositing its (some) metallic material(s), such as CVD, physical vapor deposition (PVD), and plating.

[0047] refer to Fig.11At operation 1108, method 1100 partially etches back embedded conductor 230 and liner 232 to form recess 226, as shown in FIG. Fig.12d As shown. From a top view, the recess 226 can have the same size as the trench 224, or can be slightly larger than the trench 224. Operation 1108 can use an etching process that is selectively adjusted to etch the embedded conductor 230 and the liner layer 232 without etching the semiconductor material 222. At operation 1110, the method 1100 ( Fig.11 ) A dielectric material 234 is deposited in the recess 226, such as Fig.12e The dielectric material 234 may include silicon dioxide or other suitable dielectric material(s), and serves as a capping layer to protect the embedded conductor 230 from subsequent processes.

[0048] At operation 1112, method 1100 ( Fig.11 ) to form an active region such as a semiconductor fin 310 in the semiconductor layer 222, such as Fig.12f As shown. Fig.12f As shown, method 1100 forms a patterned hard mask layer 314 over the fin 310, and forms a liner layer 318 on the sidewalls of the fin 310 and the upper surface of the semiconductor layer 220. The patterned mask 314 can be formed using one or more photolithography processes, including double patterning or multi-patterning processes. Typically, the double patterning or multi-patterning process combines photolithography and self-alignment processes, thereby allowing the creation of patterns having, for example, a pitch smaller than other pitches obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over the semiconductor layer 222 and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels become the patterned mask 314. In various embodiments, the patterned mask 314 may include silicon oxide, silicon nitride, photoresist, or other suitable materials. Operation 1112 includes etching the semiconductor layer 222 using the patterned mask 314 as an etch mask to form the fin 310, and then forming a liner layer 318. The liner layer 318 may include silicon nitride (e.g., Si3N4) and may be deposited using chemical vapor deposition (CVD) such as low pressure CVD (LPCVD) or plasma enhanced CVD (PECVD), atomic layer deposition (ALD), or other suitable methods.

[0049] At operation 1114, method 1100 ( Fig.11) to form device 100. For example, method 1100 may deposit isolation material 320 between fins 310, form transistors in or on semiconductor fins 310, form contacts, local interconnects, and upper interconnect layers. In particular, method 1100 forms local interconnects 330 and 340 (e.g., local interconnects 330 and 340) that connect embedded conductors 230 to some of the source, drain, and gate electrodes of the transistors. Figure 2 ). Method 1100 demonstrates that conductor 230 may be formed prior to forming semiconductor fins (or other types of active regions) in the same device.

[0050] Fig.13 A flow chart of method 1300 is shown, which is a variation of method 1100. Fig.13 , method 1300 includes respectively and reference Fig.11 Described operations 1102, 1104, 1106, 1108, 1112, and 1114 are similar to operations 1302, 1304, 1306, 1308, 1312, and 1314. One difference is that method 1300 performs operation 1312 (forming fins) before operation 1304 (etching trenches for embedded conductors). Method 1300 is briefly discussed below.

[0051] At operation 1302 , method 1300 epitaxially grows semiconductor material over the front side of substrate B. This operation is similar or identical to operation 1102 , and the resulting structure of device 100 is shown in 12 a .

[0052] At operation 1312 , method 1300 forms fins 310 , patterned hard mask layer 314 , and liner layer 318 , such as Fig.14a This operation is similar to or the same as operation 1112.

[0053] At operation 1304, method 1300 forms trenches 224 to expose conductors 124 on the back side of substrate 110. This operation is similar to operation 1104, except that fins 310 exist before operation 1304. In particular, trenches 224 are formed between fins 310. Operation 1304 includes photolithography and etching processes as discussed with reference to operation 1104. Trench 224 is adjacent to fin 310, as in this embodiment. Fig.14b Alternatively, the groove 224 may be spaced apart from the fin 310, as shown in FIG. Figure 1 As shown, the space occupied by the embedded conductor 230 corresponds to the trench 224 .

[0054] In operation 1306, method 1300 performs a step of forming a groove 224 (eg, Fig.14cAn optional liner (or barrier) layer 232 is formed on the surface of the substrate, and an embedded conductor 230 (eg, Fig.14d 1106. At operation 1308, method 1300 partially etches back embedded conductor 230 and liner 232. Operation 1308 may use an etching process that is selectively tuned to etch embedded conductor 230 and liner 232 without etching liner layer 318.

[0055] At operation 1314, method 1300 ( Fig.13 ) to form device 100. For example, method 1300 may deposit isolation material 320 between fins 310, form transistors in or on semiconductor fins 310, form contacts, local interconnects, and upper interconnect layers. In particular, method 1300 forms local interconnects 330 and 340 (e.g., local interconnects 330 and 340) that connect embedded conductors 230 to some of the source, drain, and gate electrodes of the transistors. Figure 2 shown).

[0056] Fig.15 A flow chart of method 1500 is shown. Fig.15 , method 1500 includes operations 1502, 1504, 1506, 1508, 1510, 1512, 1514, and 1516. Method 1500 is briefly discussed below.

[0057] refer to Fig.15 At operation 1502, method 1500 prepares a substrate A to be incorporated into semiconductor device 100. This is similar to operation 902 discussed above. For example, substrate A may be Figure 2-Figure 8 The embodiment of the substrate 110 shown in FIG. The following description also refers to the substrate A as the substrate 110. Fig.16a The substrate 110 has a front side (indicated by reference numeral 102) and a back side (indicated by reference numeral 104). The substrate 110 includes a semiconductor layer 116, a redistribution layer 120, and an insulator 130. The redistribution layer 120 includes one or more dielectric layers 122 and a conductor 124. The portion 103 of the conductor 124 is used to connect to an embedded conductor 230 (see FIG. 1 ) described later. Fig.16f and Figure 16g ) to connect.

[0058] At operation 1504, method 1500 ( Fig.15 ) Prepare a substrate B to be incorporated into the semiconductor device 100. For example, the substrate B may be Figure 2-Figure 8 The embodiment of the substrate 200 shown in FIG. 1 is shown in FIG. 1 . The substrate B is also referred to as the substrate 200 in the following description. Fig.16bAs shown, the substrate 200 has a front side (indicated by reference numeral 202) and a back side (indicated by reference numeral 204). The substrate 200 includes a semiconductor layer 220 and an insulator 210 (eg, oxide).

[0059] At operation 1506, similar to operation 1102 described above, method 1500 ( Fig.15 ) grows semiconductor material over the front side of substrate 200. Fig.16c , using the semiconductor material of layer 220 as a seed to epitaxially grow semiconductor layer 222 on semiconductor layer 220. Semiconductor layers 220 and 222 may include the same material or different materials, as described above with respect to Fig.12a discussed.

[0060] In operation 1508, method 1500 ( Fig.15 ) A semiconductor device or a portion thereof is formed over the front surface of the substrate 200. Fig.16d In this embodiment, operation 1508 forms fin 310, epitaxial component 312 that may be a source or drain electrode of a transistor, and isolation material 320. Operation 1508 may also form a gate electrode (e.g., a high-k metal gate). Operation 1508 may also form a nanowire and / or nanosheet structure instead of fin 310, or, operation 1508 may also form a nanowire and / or nanosheet structure in addition to fin 310. In one embodiment, operation 1508 completes the embedded conductor 230 ( Fig.16f and Figure 16g ) any and all high temperature processes that would adversely affect

[0061] At operation 1510, method 1500 ( Fig.15 ) One or more trenches 224 are etched from the back side of the substrate 200. Fig.16e , trench 224 is etched through insulator 210, semiconductor layer 220, and into device layer 300. This is similar to operation 1104, except that operation 1510 etches trench 224 from the back side of the substrate. Figure 2 The conductors 330 and 340 in FIG. Fig.16e In an embodiment where the conductor 230 (shown in FIG. 1 ) has been formed in the device layer 300, the trench 224 may expose the conductor so that the embedded conductor 230 ( Fig.16f ) can be formed to electrically contact the conductor.

[0062] At operation 1512, method 1500 ( Fig.15 ) An optional liner (or barrier) layer 232 is formed on the surface of the trench 224, and an embedded conductor 230 is formed over the liner layer 232. This is similar to operation 1106. Fig.16f The structure of device 100 is shown after performing operation 1512 according to one embodiment.

[0063] At operation 1514, method 1500 ( Fig.15 ) connects substrates A and B together. Figure 16g In this embodiment, method 1500 connects the back side of substrate B to the back side of substrate A. In particular, embedded conductors 230 are bonded to electrical contact conductors 124. Operation 1514 may use any suitable bonding process, such as direct bonding or hybrid bonding.

[0064] At operation 1516, method 1500 ( Fig.15 ) Additional processes are performed to form the device 100. For example, the method 1500 can form contacts, local interconnects, and upper interconnect layers.

[0065] Fig.17 A flow chart of method 1700 is shown. Fig.17 , method 1700 includes operations 1702, 1704, 1706, 1708, 1710, 1712, 1714, and 1716. Operations 1702, 1704, 1706, and 1708 are similar to operations 1502, 1504, 1506, and 1508, respectively. The structures obtained by operations 1702, 1704, 1706, and 1708 are respectively Fig.18a , Fig.18b , Fig.18c ,and Fig.18d and are similar to Fig.16a , Fig.16b , Fig.16c ,and Fig.16d For the sake of brevity, the description thereof is omitted.

[0066] At operation 1710, method 1700 ( Fig.17 ) connects substrates A and B together. Fig.18e In this embodiment, method 1700 connects the back side of substrate B to the back side of substrate A. Operation 1710 may use any suitable bonding process, such as direct bonding or hybrid bonding.

[0067] At operation 1712, method 1700 ( Fig.17 ) One or more trenches 224 are etched from the front side of the substrate 200. Fig.18f , trench 224 is etched through device layer 300 , semiconductor layer 220 , and insulator 210 , exposing conductor 124 . This is similar to operation 1104 .

[0068] At operation 1714, method 1700 ( Fig.17) An optional liner (or barrier) layer 232 is formed on the surface of the trench 224, and an embedded conductor 230 is formed over the liner layer 232. This is similar to operation 1106. Fig.16f The structure of device 100 is shown after performing operation 1714 according to one embodiment. Embedded conductor 230 electrically contacts conductor 124.

[0069] At operation 1716, method 1700 ( Fig.17 ) Additional processes are performed to form the device 100. For example, the method 1700 can form contacts, local interconnects, and upper interconnect layers. In particular, the method 1700 forms a connection to the embedded conductor 230.

[0070] Although not intended to be limiting, one or more embodiments of the present invention provide many benefits to semiconductor devices and their formation. For example, an embodiment of the present invention provides a device having an embedded conductor passing through a substrate, which can be a bulk substrate or an SOI substrate. In particular, the embedded conductor is located below the transistor of the device or at the same level as the transistor. The embedded conductor provides additional routing resources for the device, reduces IR drop on the power rail, reduces power consumption, and enables further device expansion and integration. In some embodiments, the embedded conductor minimizes temperature and / or mechanical stress and improves yield.

[0071] In one exemplary aspect, the invention is directed to a structure comprising a first substrate and a second substrate. The first substrate has a front side and a back side. The second substrate has a front side and a back side. The back side of the second substrate is connected to the back side of the first substrate. The structure also includes: a device layer located above the front side of the second substrate; a first conductor passing through a semiconductor layer in the second substrate; and a conductive connection connecting the first conductor to a conductive component in the device layer.

[0072] In one embodiment of the structure, the first substrate includes a redistribution layer located on the back side of the first substrate. The redistribution layer includes a second conductor embedded in the dielectric layer. The first conductor contacts the second conductor.

[0073] In one embodiment of the structure, the first conductor is connected to a power rail or a ground plane of the structure. In another embodiment of the structure, the first conductor extends over the front side of the second substrate.

[0074] In one embodiment, the structure further includes a semiconductor fin extending over the front side of the second substrate, wherein a top surface of the first conductor is lower than a top surface of the semiconductor fin.

[0075] In one embodiment of the structure, the first conductor comprises tungsten, ruthenium, rhodium, iridium, molybdenum, chromium, or a combination thereof. In another embodiment of the structure, the first conductor comprises copper, gold, silver, palladium, osmium, platinum, or a combination thereof.

[0076] In one embodiment, the structure further comprises a liner layer between the first conductor and the second substrate. In another embodiment, the structure further comprises an interconnect layer over the front side of the second substrate and over the device layer. In yet another embodiment, the structure further comprises a redistribution layer over the front side of the first substrate, wherein one of the first conductors is electrically connected to the redistribution layer.

[0077] In another exemplary aspect, the present invention is directed to a structure comprising: a first substrate having a front side and a back side; a second substrate having a front side and a back side; wherein the back side of the second substrate is bonded to the back side of the first substrate. The structure also comprises: a metal feature extending from the back side of the first substrate to the front side of the second substrate; a device layer located above the front side of the second substrate and above the metal feature; and a multi-layer interconnect located above the device layer.

[0078] In one embodiment of the structure, the first substrate includes a redistribution layer located on a back side of the first substrate, and the metal feature is electrically connected to the redistribution layer.

[0079] In one embodiment, the structure further includes: a connector electrically connecting the metal component to a source, a drain, or a gate electrode in the device layer.

[0080] In one embodiment of the structure, the second substrate includes a layer of semiconductor material located on a front side of the second substrate, and the metal feature extends through the layer of semiconductor material.

[0081] In another embodiment of the structure, the second substrate includes one or more layers of insulator extending from a front side of the second substrate to a back side of the second substrate.

[0082] In yet another exemplary aspect, the invention is directed to a method comprising: receiving a first substrate having a front side and a back side, the front side of the first substrate having a semiconductor material, the back side of the first substrate having a passivation layer; receiving a second substrate having a front side and a back side, the back side of the second substrate having an insulator; connecting the back side of the first substrate to the back side of the second substrate; etching a trench through the second substrate and through the passivation layer; and forming a conductor in the trench.

[0083] In one embodiment, the method further comprises removing a portion of the second substrate after the connection and before the etching of the trench. In another embodiment, the method further comprises forming a semiconductor fin over the front side of the second substrate after the connection. In another embodiment, the formation of the semiconductor fin is performed after the formation of the conductor. In another embodiment, the formation of the semiconductor fin is performed before the etching of the trench.

[0084] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as the present disclosure. Those skilled in the art should also be aware that such equivalent structures do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and modifications can be made without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure comprising: A first substrate having a front side and a back side; a second substrate having a front side and a back side, wherein the back side of the second substrate is connected to the back side of the first substrate; a device layer, located above the front surface of the second substrate; A first conductor passing through the semiconductor layer in the second substrate; and Conductively connecting the first conductor to a conductive component in the device layer; A semiconductor fin extends above the front surface of the second substrate, wherein a top surface of the first conductor is lower than a top surface of the semiconductor fin.

2. The semiconductor structure according to claim 1, wherein: The first substrate includes a redistribution layer located on the back side of the first substrate, and the redistribution layer includes a second conductor embedded in a dielectric layer, wherein the first conductor contacts the second conductor.

3. The semiconductor structure according to claim 1, wherein: The first conductor is connected to a power rail or a ground plane of the semiconductor structure.

4. The semiconductor structure according to claim 1, wherein: The first conductor extends over the front side of the second substrate.

5. The semiconductor structure according to claim 1, wherein: The first conductor has a T-shaped cross-sectional profile.

6. The semiconductor structure according to claim 1, wherein: The first conductor includes tungsten, ruthenium, rhodium, iridium, molybdenum, chromium, or a combination thereof.

7. The semiconductor structure according to claim 1, wherein: The first conductor includes copper, gold, silver, palladium, osmium, platinum, or a combination thereof.

8. The semiconductor structure of claim 1, further comprising a liner layer between the first conductor and the second substrate.

9. The semiconductor structure of claim 1 further comprising an interconnect layer over the front side of the second substrate and over the device layer.

10. The semiconductor structure of claim 1, further comprising a redistribution layer located above the front side of the first substrate, wherein: One of the first conductors is electrically connected to the redistribution layer.

11. A semiconductor structure comprising: A first substrate having a front side and a back side; A second substrate having a front side and a back side, wherein the back side of the second substrate is bonded to the back side of the first substrate, and the second substrate comprises a semiconductor material layer located on the front side of the second substrate; a metal component extending from the back surface of the first substrate to the front surface of the second substrate; a liner layer surrounding the metal component, wherein the semiconductor material layer is in direct contact with left and right sides of the liner layer; a device layer located over the front side of the second substrate and over the metal features; and A multi-layer interconnect is located above the device layer.

12. The semiconductor structure according to claim 11, wherein: The first substrate includes a redistribution layer located on the back side of the first substrate, and the metal feature is electrically connected to the redistribution layer.

13. The semiconductor structure of claim 11, further comprising: A connector electrically connects the metal component to a source, a drain, or a gate electrode in the device layer.

14. The semiconductor structure according to claim 11, wherein: The metal feature extends through the layer of semiconductor material.

15. The semiconductor structure according to claim 11, wherein: The second substrate includes one or more layers of insulator extending from the front surface of the second substrate to the back surface of the second substrate.

16. A method of forming a semiconductor structure, comprising: receiving a first substrate having a front side and a back side, the front side of the first substrate having a semiconductor material, the back side of the first substrate having a passivation layer; receiving a second substrate having a front side and a back side, the back side of the second substrate having an insulator; connecting the back surface of the first substrate to the back surface of the second substrate; After said connecting, forming a semiconductor fin over said front surface of said second substrate; etching a trench through the second substrate and through the passivation layer; as well as A conductor is formed in the trench.

17. The method according to claim 16, further comprising: After said connecting and before said etching of said trenches, a portion of said second substrate is removed.

18. The method according to claim 16, wherein: A top surface of the conductor is lower than a top surface of the semiconductor fin.

19. The method according to claim 18, wherein: The forming of the semiconductor fin is performed after the forming of the conductor.

20. The method according to claim 18, wherein: The forming of the semiconductor fin is performed prior to the etching of the trench.

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