An energy efficient relaxation oscillator

Abstract

The present invention relates to an energy-efficient relaxation oscillator, which adjusts the threshold voltage of the comparator I1 by adjusting the high and low threshold voltages (VA, VB), thereby realizing the programmable oscillator frequency. And the lower plate of the capacitor C1 and the upper plate of the capacitor C2 are charged by the reference voltages VREFP and VREFN respectively, and the overdrive voltages of M2 and M3 are adjusted. Since the power consumption of the circuit is related to g m / I d The higher the value, the lower the power consumption. Therefore, by adjusting the values ​​of the reference voltages VREFP and VREFN, the overall power consumption of the oscillator circuit is reduced, and the energy efficiency of the oscillator circuit is improved. The present invention further improves the energy efficiency utilization rate and reduces power consumption.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic equipment, and in particular to an energy-efficient relaxation oscillator capable of further improving energy efficiency and reducing power consumption. Background Art

[0002] The 21st century is a brand new information age. The development of the information technology industry has changed the world and people's lives to a great extent. For example, low-power systems such as wireless sensor nodes have been widely used in portable wearable devices, biomedicine and other fields. In addition, in the applications in these fields, the hardware system is required to maintain a long working time, that is, the hardware system needs to have low power consumption. Wireless sensors usually enter idle mode after working for a period of time, and the clock source is the only circuit working in idle mode, which plays a "wake-up" function. In low-power applications, relaxation oscillators are usually used as clock sources to wake up other circuit modules in sleep mode. Therefore, the design of high-precision, low-power relaxation oscillators has always been the research focus of scholars at home and abroad.

[0003] An energy-efficient relaxation oscillator is needed that can further improve energy efficiency and reduce power consumption. Summary of the invention

[0004] The object of the present invention is to provide an energy efficient relaxation oscillator which can further improve energy efficiency and reduce power consumption.

[0005] An energy efficient relaxation oscillator, comprising:

[0006] An oscillator, wherein the oscillator is respectively provided with a high threshold voltage interface VA, a low threshold voltage interface VB, a first reference voltage interface VREFP, a second reference voltage interface VREFN, and an output signal interface VO;

[0007] The first reference voltage interface VREFP is connected to the source of the transistor M1, the gate of the transistor M1 is connected to the V2 interface, the drain of the transistor M1 is connected to the capacitor C1, and is connected to the source of the transistor M2, the gate of the M2 is connected to the V1 interface, and is connected to the gate of the M3, the source of the M3 is connected to the capacitor C2, and is connected to the drain of the transistor M4, the capacitor C2 is grounded, the gate of the transistor M4 is connected to the V2 interface, the source of the transistor M4 is connected to the second reference voltage interface VREFN, after the drain of the M2 is connected to the drain of the M3, it is connected to the capacitor C3, and is connected to the INP interface of the comparator I1, the capacitor C3 is grounded, the INN interface of the comparator I1 is connected to the OUT interface of the transmission gate I4, and is connected to the OUT interface of the transmission gate I5, the interface V1 of the comparator I1 is connected to the inverter I2, and is connected to the V1 interface, the inverter I2 is connected to the inverter I3, and is connected to the V2 interface, and the inverter I3 is connected to the output signal interface VO;

[0008] The IN interface of the transmission gate I4 is connected to the high threshold voltage interface VA, the VP interface of the transmission gate I4 is connected to the output signal interface VO, the VN interface of the transmission gate I4 is connected to the V2 interface, the IN interface of the transmission gate I5 is connected to the low threshold voltage interface VB, the VN interface of the transmission gate I5 is connected to the output signal interface VO, and the VP interface of the transmission gate I5 is connected to the V2 interface.

[0009] The transmission gate I5 has the same structure as the transmission gate I4, and is a transmission gate TG respectively.

[0010] The VN interface of the transmission gate TG is connected to the gate of the transistor M5, the source of the transistor M5 is connected to the source of the transistor M6 and then to the OUT interface, the drain of the transistor M5 is connected to the drain of the transistor M6 and then to the IN interface, and the gate of the transistor M6 is connected to the VP interface.

[0011] One end of the capacitor C1 is connected.

[0012] The comparator I1 , the inverter I2 , and the inverter I3 are directed toward the output signal interface VO.

[0013] The transistor M5 is a PMOS transistor, and the transistor M6 is an NMOS transistor.

[0014] The voltages of the first reference voltage interface VREFP and the second reference voltage interface VREFN are adjustable.

[0015] The oscillator of the present invention is respectively provided with a high threshold voltage interface VA, a low threshold voltage interface VB, a first reference voltage interface VREFP, a second reference voltage interface VREFN, and an output signal interface VO; the first reference voltage interface VREFP is connected to the source of a transistor M1, the gate of the transistor M1 is connected to the V2 interface, the drain of the transistor M1 is connected to the capacitor C1 one way, connected to the source of the transistor M2 one way, the gate of M2 is connected to the V1 interface one way, connected to the gate of M3 one way, the source of M3 is connected to the capacitor C2 one way, connected to the drain of the transistor M4 one way, the capacitor C2 is grounded, the gate of the transistor M4 is connected to the V2 interface, the source of the transistor M4 is connected to the second reference voltage interface VREFN, the drain of M2 is connected to the drain of M3, and then connected to the capacitor C 3, one way is connected to the INP interface of the comparator I1, the capacitor C3 is grounded, the INN interface of the comparator I1 is connected to the OUT interface of the transmission gate I4, one way is connected to the OUT interface of the transmission gate I5, the interface V1 of the comparator I1 is connected to the inverter I2, one way is connected to the V1 interface, the inverter I2 is connected to the inverter I3, one way is connected to the V2 interface, the inverter I3 is connected to the output signal interface VO; the IN interface of the transmission gate I4 is connected to the high threshold voltage interface VA, the VP interface of the transmission gate I4 is connected to the output signal interface VO, the VN interface of the transmission gate I4 is connected to the V2 interface, the IN interface of the transmission gate I5 is connected to the low threshold voltage interface VB, the VN interface of the transmission gate I5 is connected to the output signal interface VO, and the VP interface of the transmission gate I5 is connected to the V2 interface. The present invention further improves the energy efficiency and reduces power consumption.

[0016] The present invention adjusts the threshold voltage of the comparator I1 by adjusting the high and low threshold voltages (VA, VB), thereby realizing the programmable oscillator frequency. And the lower plate of the capacitor C1 and the upper plate of the capacitor C2 are charged by the reference voltages VREFP and VREFN respectively, and the overdrive voltages of M2 and M3 are adjusted. m / I d The higher the value, the lower the power consumption. Therefore, by adjusting the values ​​of the reference voltages VREFP and VREFN, the overall power consumption of the oscillator circuit can be reduced and the energy efficiency of the oscillator circuit can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is an overall block diagram of the present invention;

[0018] Figure 2 is a first internal circuit diagram of the present invention;

[0019] Figure 3 is a second internal circuit diagram of the present invention;

[0020] Figure 4 is a circuit diagram of a transmission gate TG of the present invention;

[0021] In the figure: 1. Oscillator. DETAILED DESCRIPTION

[0022] The present invention is further described below in conjunction with the accompanying drawings and specific embodiments.

[0023] An energy-efficient relaxation oscillator comprises: an oscillator 1, wherein the oscillator 1 is respectively provided with a high threshold voltage interface VA, a low threshold voltage interface VB, a first reference voltage interface VREFP, a second reference voltage interface VREFN, and an output signal interface VO; the first reference voltage interface VREFP is connected to the source of a transistor M1, the gate of the transistor M1 is connected to the V2 interface, the drain of the transistor M1 is connected to a capacitor C1 one way, and to the source of a transistor M2 one way, the gate of M2 is connected to the V1 interface one way, and to the gate of M3 one way, the source of M3 is connected to a capacitor C2 one way, and to the drain of a transistor M4 one way, the capacitor C2 is grounded, the gate of the transistor M4 is connected to the V2 interface, the source of the transistor M4 is connected to the second reference voltage interface VREFN, the drain of M2 and the drain of M3 are connected to the back , one way is connected to capacitor C3, one way is connected to the INP interface of comparator I1, capacitor C3 is grounded, the INN interface of comparator I1 is connected to the OUT interface of transmission gate I4, one way is connected to the OUT interface of transmission gate I5, interface V1 of comparator I1 is connected to inverter I2, one way is connected to V1 interface, inverter I2 is connected to inverter I3, one way is connected to V2 interface, inverter I3 is connected to output signal interface VO; IN interface of transmission gate I4 is connected to high threshold voltage interface VA, VP interface of transmission gate I4 is connected to output signal interface VO, VN interface of transmission gate I4 is connected to V2 interface, IN interface of transmission gate I5 is connected to low threshold voltage interface VB, VN interface of transmission gate I5 is connected to output signal interface VO, VP interface of transmission gate I5 is connected to V2 interface.

[0024] The transmission gate I5 and the transmission gate I4 have the same structure, which are transmission gates TG. The VN interface of the transmission gate TG is connected to the gate of the transistor M5, the source of the transistor M5 is connected to the source of the transistor M6, and then connected to the OUT interface, the drain of the transistor M5 is connected to the drain of the transistor M6, and then connected to the IN interface, and the gate of the transistor M6 is connected to the VP interface. One end of the capacitor C1 is connected. The comparator I1, the inverter I2, and the inverter I3 are directed toward the output signal interface VO. The transistor M5 is a PMOS transistor, and the transistor M6 is an NMOS transistor. The voltages of the first reference voltage interface VREFP and the second reference voltage interface VREFN are adjustable.

[0025] An energy-efficient relaxation oscillator, oscillator 1 (Comparator) includes two voltage references (VREFP, VREFN), two high and low threshold voltage input terminals (VA, VB), and an output signal (VO). It is composed of a transistor M1, a transistor M2, a transistor M3, a transistor M4, a capacitor C1, a capacitor C2, a capacitor C3, a comparator I1, an inverter I2, an inverter I3, and a transmission gate I4, a transmission gate I5. The specific structure of the transmission gate TG is composed of a PMOS transistor M5 and an NMOS transistor M6.

[0026] The working process is as follows. If the output voltage V1 of the comparator I1 is high, the output of the inverter I2 is low, the output of the inverter I3 is high, the transmission gate I4 is turned off, and the transmission gate I5 is turned on, resulting in the low threshold voltage VB being input to the input terminal INN of the comparator I1. At the same time, the transistor M1, the transistor M3 are turned on, the transistor M2, and the transistor M4 are turned off, the lower plate of the capacitor C1 is charged to the first reference voltage VREFP, and the capacitor C3 begins to discharge, resulting in the potential of the comparator input terminal INP starting to decrease. When the voltage of the input terminal INP of the comparator drops to a voltage lower than the input terminal INN voltage of the comparator I1 (i.e., the low threshold voltage VB), the output voltage V1 of the comparator I1 is low. When the output voltage V1 of the comparator I1 is low, the output of the inverter I2 is high, the output of the inverter I3 is low, the transmission gate I5 is turned off, and the transmission gate I4 is turned on, resulting in the high threshold voltage VA being input to the input terminal INN of the comparator I1. At the same time, transistors M2 and M4 are turned on, transistors M1 and M3 are turned off, the upper plate of capacitor C2 is charged to the second reference voltage VREFN, and capacitor C3 starts to charge, causing the potential of the input terminal INP of comparator I1 to start to rise. When the voltage of the input terminal INP of comparator I1 rises to a voltage higher than the input terminal INN voltage of comparator I1 (i.e., the high threshold voltage VA), the output voltage V1 of comparator I1 is high. Through such repeated cycles, a stable oscillation waveform can be obtained at the output of the comparator.

[0027] In the present invention, the threshold voltage of the comparator I1 can be adjusted by adjusting the high and low threshold voltages (VA, VB), thereby realizing the programmable oscillator frequency. And the lower plate of the capacitor C1 and the upper plate of the capacitor C2 are charged by the reference voltages VREFP and VREFN respectively, and the overdrive voltages of M2 and M3 are adjusted. m / I d The higher the value, the lower the power consumption. Therefore, by adjusting the values ​​of the reference voltages VREFP and VREFN, the overall power consumption of the oscillator circuit can be reduced and the energy efficiency of the oscillator circuit can be improved.

[0028] The present invention is an energy-efficient relaxation oscillator design, which is composed of a transistor M1, a transistor M2, a transistor M3, a transistor M4, a capacitor C1, a capacitor C2, a capacitor C3, a comparator I1, an inverter I2, an inverter I3, a transmission gate I4, and a transmission gate I5. By adjusting the high and low threshold voltages (VA, VB), the threshold voltage of the comparator I1 is adjusted, so that the oscillator frequency can be programmable. And the lower plate of the capacitor C1 and the upper plate of the capacitor C2 are charged respectively by the reference voltages VREFP and VREFN, and the overdrive voltages of the transistors M2 and M3 are adjusted. Since the power consumption of the circuit is related to g m / I d The higher the value, the lower the power consumption. Therefore, by adjusting the values ​​of the reference voltages VREFP and VREFN, the overall power consumption of the oscillator circuit can be reduced and the energy efficiency of the oscillator circuit can be improved.

[0029] The above shows and describes the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The above embodiments and descriptions are only for explaining the principles of the present invention. The present invention may be subject to various changes and improvements without departing from the spirit and scope of the present invention. These changes and improvements fall within the scope of the present invention to be protected. The scope of protection of the present invention is defined by the attached claims and their equivalents.

Claims

1. An energy efficient relaxation oscillator, characterized in that include: An oscillator (1), wherein the oscillator (1) is respectively provided with a high threshold voltage interface VA, a low threshold voltage interface VB, a first reference voltage interface VREFP, a second reference voltage interface VREFN, and an output signal interface VO; The first reference voltage interface VREFP is connected to the source of the transistor M1, the gate of the transistor M1 is connected to the V2 interface, the drain of the transistor M1 is connected to the capacitor C1, and is connected to the source of the transistor M2, the gate of the M2 is connected to the V1 interface, and is connected to the gate of the M3, the source of the M3 is connected to the capacitor C2, and is connected to the drain of the transistor M4, the capacitor C2 is grounded, the gate of the transistor M4 is connected to the V2 interface, the source of the transistor M4 is connected to the second reference voltage interface VREFN, after the drain of the M2 is connected to the drain of the M3, it is connected to the capacitor C3, and is connected to the INP interface of the comparator I1, the capacitor C3 is grounded, the INN interface of the comparator I1 is connected to the OUT interface of the transmission gate I4, and is connected to the OUT interface of the transmission gate I5, the interface V1 of the comparator I1 is connected to the inverter I2, and is connected to the V1 interface, the inverter I2 is connected to the inverter I3, and is connected to the V2 interface, and the inverter I3 is connected to the output signal interface VO; The IN interface of the transmission gate I4 is connected to the high threshold voltage interface VA, the VP interface of the transmission gate I4 is connected to the output signal interface VO, the VN interface of the transmission gate I4 is connected to the V2 interface, the IN interface of the transmission gate I5 is connected to the low threshold voltage interface VB, the VN interface of the transmission gate I5 is connected to the output signal interface VO, and the VP interface of the transmission gate I5 is connected to the V2 interface.

2. An energy efficient relaxation oscillator according to claim 1, characterized in that: The transmission gate I5 has the same structure as the transmission gate I4, and is a transmission gate TG respectively.

3. An energy efficient relaxation oscillator according to claim 1, characterized in that: The VN interface of the transmission gate TG is connected to the gate of the transistor M5, the source of the transistor M5 is connected to the source of the transistor M6 and then to the OUT interface, the drain of the transistor M5 is connected to the drain of the transistor M6 and then to the IN interface, and the gate of the transistor M6 is connected to the VP interface.

4. An energy efficient relaxation oscillator according to claim 1, characterized in that: One end of the capacitor C1 is connected.

5. The energy efficient relaxation oscillator according to claim 1, characterized in that: The comparator I1 , the inverter I2 , and the inverter I3 are directed toward the output signal interface VO.

6. The energy efficient relaxation oscillator according to claim 1, characterized in that: The transistor M5 is a PMOS transistor, and the transistor M6 is an NMOS transistor.

7. The energy efficient relaxation oscillator according to claim 1, characterized in that: The voltages of the first reference voltage interface VREFP and the second reference voltage interface VREFN are adjustable.

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