Phase-locked detection device and phase-locked detection method, phase-locked loop

Abstract

The present invention provides a phase-locked detection device and a phase-locked detection method, a phase-locked loop, including a reference pulse generating circuit, a feedback pulse generating circuit, a reset circuit, a reset signal generating circuit, a pulse acquisition circuit, and a phase-locked judgment circuit; a reference clock inputs a reference pulse generating circuit to generate a reference pulse, the reference pulse inputs a pulse acquisition circuit and a reset signal generating circuit; a feedback clock inputs a feedback pulse generating circuit, the feedback pulse generating circuit outputs a feedback pulse, the feedback pulse inputs a pulse acquisition circuit; the pulse acquisition circuit uses the feedback pulse as a clock input, the reference pulse as a counting input, and outputs a phase-locked enable signal; the phase-locked enable signal is output to the phase-locked judgment circuit, and the phase-locked judgment circuit outputs a locking signal after the count reaches a preset value. This scheme provides a detection device with both precision and simple structure.

Description

Technical Field

[0001] The present invention relates to the technical field of phase-locked loops, and in particular to a lock detection circuit. Background Art

[0002] PLL (Phase Locked Loop) is a phase-locked loop or phase-locked loop, which is used to unify and integrate clock signals to make high-frequency devices work normally. PLL is used as feedback technology in oscillators. For many electronic devices to work properly, they usually need the external input signal to be synchronized with the internal oscillation signal. Due to process and cost reasons, ordinary crystal oscillators cannot achieve very high frequencies. When high-frequency applications are required, the corresponding device VCO can be used to convert high frequencies, but it is not stable. Therefore, a phase-locked loop can be used to achieve a stable and high-frequency clock signal. Whether PLL can lock the clock frequency determines whether the subsequent circuit module can start working, and also affects the performance of the subsequent circuit operation.

[0003] In current applications, there are two detection methods for phase-locked loops: analog and digital. One is the simplest digital detection scheme, which uses continuous result clock cycles to detect that the pulse width of the phase detector is less than a certain threshold as an effective lock judgment rule.

[0004] Another solution is to use an analog circuit solution for lock detection, also known as N-channel drain open detection. Its implementation principle is to perform an XOR operation on the leading and lagging pulses output by the PFD and directly output the result. Since the result of XOR is a series of high and low pulses, an external circuit is required for filtering to obtain a level value, and since it is a drain open logic, a pull-up resistor is required on the output.

[0005] The current digital detection method will make the results less reliable if the reference clock is lost, if a relatively accurate VCXO needs to be driven, and if phase detection is required at a high frequency. It is also unable to identify short-term loss of lock, has a relatively low sensitivity, and cannot detect short pulses.

[0006] The problem with the current analog detection method is that, although it has advantages in high-frequency frequency discrimination compared to digital detection, the design method is more complicated and requires calculation of filter capacitors, pull-up and series capacitors. Summary of the invention

[0007] In view of the above problems, the present invention provides a detection device with both high accuracy and simple structure.

[0008] In order to solve the above technical problems, the present invention is solved by the following technical solutions:

[0009] A phase-lock detection device comprises a reference pulse generating circuit, a feedback pulse generating circuit, a pulse acquisition circuit and a phase-lock judgment circuit;

[0010] The reference clock is input into a reference pulse generating circuit to generate a reference pulse, and the reference pulse is input into a pulse acquisition circuit and a reset signal generating circuit;

[0011] The feedback clock is input into the feedback pulse generating circuit, the feedback pulse generating circuit outputs the feedback pulse, and the feedback pulse is input into the pulse collecting circuit;

[0012] The pulse acquisition circuit uses the feedback pulse as the clock input, the reference pulse as the counting input, and outputs a phase-locked enable signal;

[0013] The phase lock enable signal is output to the phase lock judgment circuit, and the phase lock judgment circuit outputs a lock signal after the count reaches a preset value.

[0014] Optionally, a reset circuit is also included, which is respectively connected to the reference pulse generating circuit, the feedback pulse generating circuit, the reset signal generating circuit, the pulse acquisition circuit and the phase-locked judgment circuit.

[0015] Optionally, the pulse acquisition circuit includes a D flip-flop, a feedback pulse is input to a clock input terminal of the D flip-flop, and a reference pulse is input as a data terminal of the D flip-flop to output a phase-locked enable signal.

[0016] Optionally, the reference pulse generating circuit includes a reference frequency dividing circuit, which is used to obtain eight frequency dividing signals of positive value REF_1~REF_8 and eight frequency dividing signals of negative value REF_N1~REF_N8, and the REF_1~REF_8 are positive signals corresponding one-to-one to the REF_N1~REF_N8.

[0017] Optionally, the reference pulse generating circuit further includes an AND gate logic circuit,

[0018] The AND gate logic circuit includes four first AND gates, two second AND gates, and one first AND gate, and the first AND gate inputs REF_N1 to REF_N7 and REF_8 output by the feedback frequency division circuit;

[0019] Two second AND gates, used for receiving the first logic signals output by the four first AND gates;

[0020] a third AND gate, used for receiving the second logic signals output by the two second AND gates;

[0021] The third AND gate outputs a third logic signal.

[0022] Optionally, a reset signal generating circuit is further included, wherein the reset signal generating circuit outputs a frequency division reset signal which is input into the feedback pulse circuit to reset the frequency division of the feedback pulse circuit.

[0023] Optionally, the reset signal generating circuit includes four first AND gates, two second AND gates, and one first AND gate, and the first AND gate inputs REF_N1 to REF_N8 output by the reference frequency dividing circuit;

[0024] Two second AND gates, used for receiving the first logic signals output by the four first AND gates;

[0025] a third AND gate, used for receiving the second logic signals output by the two second AND gates;

[0026] The third AND gate outputs a third logic signal.

[0027] Optionally, the feedback pulse generating circuit includes a feedback frequency dividing circuit, which is used to obtain eight frequency dividing signals of positive value REF_1~REF_8 and eight frequency dividing signals of negative value FB_N1~FB_N8, and the FB_1~FB_8 are positive signals corresponding to the FB_N1~FB_N8 one by one.

[0028] Optionally, the feedback pulse generating circuit further includes an AND gate logic circuit,

[0029] The AND gate logic circuit includes four first AND gates, two second AND gates, and one first AND gate, wherein the first AND gate inputs FB_N1 to FB_N7 and FB_8 output by the feedback frequency dividing circuit;

[0030] Two second AND gates, used for receiving the first logic signals output by the four first AND gates;

[0031] a third AND gate, used for receiving the second logic signals output by the two second AND gates;

[0032] The third AND gate outputs a third logic signal.

[0033] Optionally, it also includes a D flip-flop, wherein the clock input terminal of the D flip-flop is used to receive the third logic signal, the data terminal of the D flip-flop is used to receive the VDD signal, and output a feedback control signal, the feedback control signal is inverted and input into a fourth AND gate together with the third logic signal, and the fourth AND gate outputs a feedback pulse signal.

[0034] Optionally, the reset circuit includes a bypass mode input signal and a Power down mode input signal, and the bypass mode input signal and the Power down mode input signal are respectively input into an AND gate through a NOT gate, and the logic signal output by the AND gate is input into another AND gate together with the Power down mode input signal to output a reset signal.

[0035] The present invention also provides a phase-locked detection method, comprising the following steps:

[0036] Obtain the divided-by-two frequency signals of the reference clock and feedback clock of the phase-locked loop;

[0037] Performing a multi-bit logic operation on the binary frequency-divided signal to obtain a reference pulse and a feedback pulse;

[0038] Collect feedback pulses with reference pulses to obtain phase-locked enable signals;

[0039] The phase lock enable signal is executed by a counter, and a locking result is output.

[0040] Optionally, a multi-bit logic operation is performed on the binary frequency-divided signal to obtain a periodic reset signal, and the feedback pulse is controlled by the periodic reset signal.

[0041] The present invention also provides a phase-locked loop, for which effective locking detection is performed.

[0042] Beneficial effects of the present invention:

[0043] The present invention is aimed at the application of PLL inside DDR. In DDR, the working clock is relatively high and both edges are used, so the PLL needs to be more stable and sensitive and have phase detection mode requirements. This solution provides a detection device and monitoring method with both accuracy and simple structure.

[0044] Specifically, 1) the phase-locked method is used to collect reference pulses using feedback pulses, thereby reducing the steps of determining the width of the region.

[0045] 2) By adding a dynamic reset circuit, the circuit's response speed to changes in the clock input state is increased, and it also has a certain adaptability to short-term clock changes.

[0046] 3) After the logic operation and frequency division processing of the reference and feedback clocks, the comparison method of the relative positions of the reference pulse and the feedback pulse is relatively simple, but the accuracy and response speed are not reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0048] Figure 1 It is the overall structural block diagram of the phase-locked detection device;

[0049] Figure 2 It is the circuit diagram of the reference pulse generating circuit;

[0050] Figure 3 It is the circuit diagram of the feedback pulse generating circuit;

[0051] Figure 4 is a circuit diagram of a reset signal generating circuit;

[0052] Figure 5 Reset circuit diagram;

[0053] Figure 6 It is the circuit diagram of the pulse acquisition circuit;

[0054] Figure 7 It is the circuit diagram of the phase-locked judgment circuit. DETAILED DESCRIPTION

[0055] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings. It should be understood that these descriptions are only exemplary and are not intended to limit the scope of the present invention. In addition, in the following description, the description of well-known structures and technologies is omitted to avoid unnecessary confusion of the concept of the present invention.

[0056] A phase-locked detection device, such as Figure 1 As shown, it includes a reference pulse generating circuit, a feedback pulse generating circuit, a reset circuit, a reset signal generating circuit, a pulse acquisition circuit and a phase-locked judgment circuit;

[0057] The reference clock (REF_CLK) is input into the reference pulse generating circuit to generate a reference pulse, and the reference pulse is input into the pulse acquisition circuit and the reset signal generating circuit; the feedback clock (FB_CLK) is input into the feedback pulse generating circuit, and the feedback pulse generating circuit outputs a feedback pulse, and the feedback pulse is input into the pulse acquisition circuit; the pulse acquisition circuit uses the feedback pulse as the clock input and the reference pulse as the counting input, and outputs a phase-lock enable signal; the phase-lock enable signal is output to the phase-lock judgment circuit, and the phase-lock judgment circuit outputs a lock signal (LOCK) after the count reaches a preset value.

[0058] The reset circuit is respectively connected to the reference pulse generating circuit, the feedback pulse generating circuit, the reset signal generating circuit, the pulse collecting circuit and the phase-locked judging circuit.

[0059] The reset signal generating circuit outputs a frequency division reset signal which is input into the feedback pulse circuit to reset the frequency division of the feedback pulse circuit.

[0060] like Figure 2The reference pulse generating circuit includes a reference frequency dividing circuit, which is used to obtain eight-way frequency dividing signal positive values ​​REF_1~REF_8 and eight-way frequency dividing signal negative values ​​REF_N1~REF_N8, and the REF_1~REF_8 are positive signals corresponding to the REF_N1~REF_N8 one by one.

[0061] The reference pulse generating circuit further includes an AND gate logic circuit, the AND gate logic circuit includes four first AND gates, two second AND gates, and one first AND gate, the first AND gate inputting REF_N1 to REF_N7 and REF_8 output by the feedback frequency dividing circuit;

[0062] Two second AND gates, used for receiving the first logic signals output by the four first AND gates;

[0063] a third AND gate, used for receiving the second logic signals output by the two second AND gates;

[0064] The third AND gate outputs a third logic signal (REF_PULSE).

[0065] Then the reference pulse (REF_PULSE): REF_PULSE = REF_8 & REF_N7 & REF_N6 & REF_N5 & REF_N4 & REF_N3 & REF_N2 & REF_N1

[0066] After the frequency division circuit, REF_8 is at the last high level interval of REF_N1 in the high level interval. This position is at the very end of the last level of frequency division. REF_PULSE is obtained, and its pulse width is half a cycle of the reference clock.

[0067] After passing through the AND gate logic circuit, a pulse with a width of the REF_CLK cycle is obtained at the middle position of one cycle of REF_8. The pulse widths of all pulses used mentioned in this embodiment correspond to one cycle of REF_CLK and FB_CLK.

[0068] like Figure 3 As shown, the feedback frequency division circuit is used to obtain eight-way frequency division signal positive values ​​REF_1 to REF_8 and eight-way frequency division signal negative values ​​FB_N1 to FB_N8, and the FB_1 to FB_8 are positive signals corresponding to the FB_N1 to FB_N8 one by one.

[0069] The feedback pulse generating circuit also includes an AND gate logic circuit,

[0070] The AND gate logic circuit includes four first AND gates, two second AND gates, and one first AND gate, wherein the first AND gate inputs FB_N1 to FB_N7 and FB_8 output by the feedback frequency dividing circuit;

[0071] Two second AND gates, used for receiving the first logic signals output by the four first AND gates;

[0072] a third AND gate, used for receiving the second logic signals output by the two second AND gates;

[0073] The third AND gate outputs a third logic signal (FB_OUT_ORG).

[0074] The third logic signal (FB_OUT_ORG): FB_OUT_ORG=FB_8&FB_N7&FB_N6&FB_N5&FB_N4&FB_N3&FB_N2&FB_N1

[0075] FB_OUT_ORG is the feedback pulse obtained by preliminary calculation, in order to increase the response speed of the system and avoid accidental waveform intersection with the reference pulse to cause misjudgment.

[0076] This embodiment further adds a feedback control pulse FB_CONTROL signal to control the feedback pulse generating circuit. The feedback control pulse FB_CONTROL signal generating circuit is as follows: Figure 3 shown.

[0077] The feedback control pulse FB_CONTROL signal is generated by a D flip-flop, the clock input terminal of the D flip-flop is used to receive the third logic signal, the data terminal of the D flip-flop is used to receive the VDD signal, and the Q terminal outputs a feedback control pulse, which is inverted and input into the fourth AND gate together with the third logic signal (FB_OUT_ORG), and the fourth AND gate outputs a feedback pulse signal (FB_PULSE). FB_PULSE = FB_OUT_ORG & FB_CONTROL.

[0078] Furthermore, the D flip-flop in the feedback frequency division circuit is controlled by the reset of REF_RES. The design idea can be specifically expressed as follows: the DFF flip-flop is controlled by the reset of REF_RES. When the phase relationship changes and is no longer locked, REF_RES will quickly pull down the reset, so that the loss of lock can be quickly determined. At the same time, it can avoid misjudgment that may be caused when FB_CLK and REF_CLK are different or even have a large frequency difference.

[0079] Figure 1 and Figure 4 As shown, the reset signal generating circuit outputs a frequency division reset signal to generate a REF_RES signal, which is input into the feedback pulse circuit. The purpose of this signal is to reset the frequency division of the feedback clock to achieve dynamic monitoring, which will make the lock and unlock detection response faster and ensure that accidental frequency overlap will not affect normal judgment.

[0080] The reset signal generating circuit comprises four first AND gates, two second AND gates, and one first AND gate, wherein the first AND gate inputs REF_1 to REF_8 output by the reference frequency dividing circuit;

[0081] Two second AND gates, used for receiving the first logic signals output by the four first AND gates;

[0082] a third AND gate, used for receiving the second logic signals output by the two second AND gates;

[0083] The third AND gate outputs a third logic signal (REF_RES).

[0084] (REF_N1&REF_N2&REF_N3&REF_N4&REF_N5&REF_N6&REF_N7&REF_N8).

[0085] First, changes in the reference clock will affect the generation of the REF_RES signal. This signal will reset the frequency division of the feedback clock. Under normal circumstances, the REF_RES signal will reset the feedback frequency division at the end of each judgment cycle. At this time, the divided clock generated by the feedback clock will correspond to the reference clock again to ensure the judgment of the relative position.

[0086] Secondly, when there is a problem with the clock, the REF_RES signal will affect the clock end of the pulse acquisition circuit and speed up the loss of lock judgment.

[0087] like Figure 6 As shown, the pulse acquisition circuit includes a D flip-flop, the feedback pulse is input to the clock input terminal of the D flip-flop, and the reference pulse is input as the data terminal of the D flip-flop to output a phase lock enable signal LOCK_EN. The phase lock enable signal LOCK_EN is output to the phase lock judgment circuit, and the phase lock judgment circuit outputs a lock signal after the count reaches a preset value.

[0088] The phase-lock judgment circuit includes an 8 / 16 selectable counter and a condition judgment unit. The phase-lock judgment circuit mainly consists of an 8 / 16 selectable counter and a condition judgment. After the locking condition is met, counting is performed, and a LOCK signal is output after the counting cycle requirement is met.

[0089] The optional 8 / 16 counter is added to correspond to two application situations, one is the high frequency conversion range, the other is the low frequency conversion range, in order to adapt to different response speeds. When the current reference clock and the feedback clock are of the same frequency and phase, the result collected by the pulse acquisition circuit will be LOCK_EN is 1. For specific timing, see Figure 7 .

[0090] In the lock judgment, the unlock judgment responds quickly. The lock judgment is the same as the conventional scheme. When the counter reaches the maximum value (the counter is configurable), the LOCK signal is output. The structural design described in this embodiment is aimed at DDR applications, and only a counter with a fixed value is set. There are two options. One is 8 counts and the other is 16 counts. The mode is optional, the maximum value of 8 counts is 7; the maximum value of 16 counts is 15. When the counter reaches this value, it is judged to be locked.

[0091] like Figure 5 As shown, the reset circuit includes a bypass mode input signal and a Power down mode input signal. The bypass mode input signal and the Power down mode input signal are respectively input into an AND gate after passing through a NOT gate. The logic signal output by the AND gate is input into another AND gate together with the Sys_reset mode input signal to output a reset signal (RES_INT).

[0092] like Figure 2 As shown, the reset signal RES_INT controls the reference pulse generating circuit, the pulse acquisition circuit and the phase-locked judgment circuit. Generally, the reset is valid at a low level. However, the signals of several modes in this embodiment are valid at a high level. If the bypass mode input signal, the power down mode input signal and the sys_reset mode input signal are high, it means that these modes are valid, then the entire circuit needs to be in a non-working state, and the reset signal naturally needs to be kept at a low level. As long as one of these signals is high, the reset is low.

[0093] The above-mentioned frequency division circuits all include eight binary frequency dividers.

[0094] Embodiment 2:

[0095] This embodiment provides a phase lock detection method, comprising the following steps:

[0096] Obtain the divided-by-two frequency signals of the reference clock and feedback clock of the phase-locked loop;

[0097] Performing a multi-bit logic operation on the binary frequency-divided signal to obtain a reference pulse and a feedback pulse;

[0098] The reference pulse is collected with the feedback pulse as the trigger condition to obtain the phase-locked enable signal;

[0099] The phase lock enable signal is executed by a counter, and a locking result is output.

[0100] A multi-bit logic operation is performed on the binary frequency-divided signal to obtain a period reset signal, and the feedback pulse is controlled by the period reset signal.

[0101] In addition, it should be noted that in Example 1, Figure 2-5The descriptions of the first AND gate, the second AND gate, the first logic signal, the second logic signal, etc. do not represent the same components in actual physical space positions and are only used for the convenience of description.

[0102] As for the specific embodiments described in this specification, the shapes and names of the parts and components may be different. Any equivalent or simple changes made according to the structure, features and principles described in the patent concept of the present invention are included in the protection scope of the patent of the present invention. The technicians in the technical field of the present invention can make various modifications or supplements to the specific embodiments described or replace them in a similar way, as long as they do not deviate from the structure of the present invention or exceed the scope defined by the claims, they should all fall within the protection scope of the present invention.

Claims

1. A phase-locked detection device, characterized in that: It includes a reference pulse generating circuit, a feedback pulse generating circuit, a pulse collecting circuit and a phase-locked judging circuit; The reference clock is input into a reference pulse generating circuit to generate a reference pulse, and the reference pulse is input into a pulse acquisition circuit and a reset signal generating circuit; The feedback clock is input into the feedback pulse generating circuit, the feedback pulse generating circuit outputs the feedback pulse, and the feedback pulse is input into the pulse collecting circuit; The pulse acquisition circuit uses the feedback pulse as the clock input, the reference pulse as the counting input, and outputs a phase-locked enable signal; The phase lock enable signal is output to the phase lock judgment circuit, and the phase lock judgment circuit outputs a lock signal after the count reaches a preset value; The reference pulse generating circuit includes a reference frequency dividing circuit, the reference frequency dividing circuit is used to obtain eight-way frequency dividing signal positive values ​​REF_1 to REF_8 and eight-way frequency dividing signal negative values ​​REF_N1 to REF_N8, the REF_1 to REF_8 are positive signals corresponding to the REF_N1 to REF_N8 one by one, and the reference frequency dividing circuit includes eight binary frequency dividers; The feedback pulse generating circuit includes a feedback frequency dividing circuit, the feedback frequency dividing circuit is used to obtain eight-way frequency division signal positive values ​​FB_1 to FB_8 and eight-way frequency division signal negative values ​​FB_N1 to FB_N8, the FB_1 to FB_8 are positive signals corresponding to the FB_N1 to FB_N8 one by one, and the feedback frequency dividing circuit includes eight binary frequency dividers; Among them, the reference pulse REF_PULSE=REF_8&REF_N7&REF_N6&REF_N5&REF_N4&REF_N3&REF_N2&REF_N1 input pulse acquisition circuit and reset signal generation circuit; Among them, the feedback pulse FB_OUT_ORG=FB_8&FB_N7&FB_N6&FB_N5&FB_N4&FB_N3&FB_N2&FB_N1 is input to the pulse acquisition circuit; The reset signal generating circuit outputs a frequency division reset signal, and the frequency division reset signal is input into the feedback pulse circuit to reset the frequency division of the feedback pulse circuit; the frequency division reset signal REF_RES=~(REF_N1&REF_N2&REF_N3&REF_N4&REF_N5&REF_N6&REF_N7&REF_N8).

2. The phase-locked detection device according to claim 1 further comprises a reset circuit, wherein the reset circuit is respectively connected to the reference pulse generating circuit, the feedback pulse generating circuit, the reset signal generating circuit, the pulse acquisition circuit and the phase-locked judgment circuit.

3. According to the phase-locked detection device of claim 1, the pulse acquisition circuit includes a D flip-flop, the feedback pulse is input to the clock input terminal of the D flip-flop, and the reference pulse is input as the data terminal of the D flip-flop to output a phase-locked enable signal.

4. The phase-lock detection device according to claim 1, wherein the reference pulse generating circuit further comprises an AND gate logic circuit. The AND gate logic circuit includes four first AND gates, two second AND gates, and one first AND gate, wherein the first AND gate inputs REF_N1 to REF_N7 and REF_8 output by the reference frequency dividing circuit; Two second AND gates, used for receiving the first logic signals output by the four first AND gates; a third AND gate, used for receiving the second logic signals output by the two second AND gates; The third AND gate outputs a third logic signal.

5. The phase-lock detection device according to claim 1, wherein the reset signal generating circuit comprises four first AND gates, two second AND gates, and one first AND gate, wherein the first AND gate inputs REF_N1 to REF_N8 output by the reference frequency dividing circuit; Two second AND gates, used for receiving the first logic signals output by the four first AND gates; a third AND gate, used for receiving the second logic signals output by the two second AND gates; The third AND gate outputs a third logic signal.

6. The phase-lock detection device according to claim 1, wherein the feedback pulse generating circuit further comprises an AND gate logic circuit, wherein the AND gate logic circuit comprises four first AND gates, two second AND gates, and one first AND gate, wherein the first AND gate inputs FB_N1 to FB_N7 and FB_8 output by the feedback frequency dividing circuit; Two second AND gates, used for receiving the first logic signals output by the four first AND gates; a third AND gate, used for receiving the second logic signals output by the two second AND gates; The third AND gate outputs a third logic signal.

7. According to the phase-locked detection device of claim 6, the feedback pulse generating circuit also includes a D flip-flop, the clock input end of the D flip-flop is used to receive the third logic signal, the data end of the D flip-flop is used to receive the VDD signal, and output a feedback control signal, the feedback control signal is inverted and input into a fourth AND gate together with the third logic signal, and the fourth AND gate outputs a feedback pulse signal.

8. According to the phase-lock detection device according to claim 2, the reset circuit includes a bypass mode input signal and a power down mode input signal, the bypass mode input signal and the power down mode input signal are respectively input into an AND gate after passing through a NOT gate, and the logic signal output by the AND gate is input into another AND gate together with the power down mode input signal to output a reset signal.

9. A phase-locked detection method, characterized in that: The phase-locked detection device according to any one of claims 1 to 8 comprises the following steps: Obtain the divided-by-two frequency signals of the reference clock and feedback clock of the phase-locked loop; Performing a multi-bit logic operation on the binary frequency-divided signal to obtain a reference pulse and a feedback pulse; The reference pulse is collected with the feedback pulse as the trigger condition to obtain the phase-locked enable signal; The phase lock enable signal is executed by a counter, and a locking result is output. 10 . The phase-locked detection method according to claim 9 , wherein a multi-bit logic operation is performed on the binary frequency-divided signal to obtain a period reset signal, and the feedback pulse is controlled by the period reset signal.

11. A phase-locked loop, characterized in that: The phase-lock detection device described in any one of claims 1 to 8 is used to perform lock detection.

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